ABSTRACT. High resolution observation of density of interface states (Dit) at SiO2/4H-SiC interfaces was performed by time-resolved scanning nonlinear dielectric microscopy (tr-SNDM). The sizes of the non-uniform contrasts observed in the map of Dit were in the order of several tens of nanometres, which is smaller than the value reported in the previous study (>100 nm). The simulation of the tr-SNDM measurement suggested that the spatial resolution of tr-SNDM is down to the tip radius of the cantilever used for the measurement and can be smaller than the lateral spread of the depletion layer width.

ABSTRACT. Scanning Acoustic Microscopy (SAM) is a widely used technology for non-destructive failure analysis in electronics samples. The primary information generated by SAM is a grey scale image, which is the basis for the interpretation by the failure analysis engineer. The quality of this primary image depends, amongst others, on the system setup by the operator and on the selected transducer. Therefore, if SAM analyses of a given sample are performed by several engineers using different types of SAM systems, then in general the obtained images differ. In the present study we introduce specifically manufactured golden samples with single or stacked dice including known defects for assessing the image quality and reproducibility of SAM images. These golden samples represent a robust measurement standard. They are particularly suited for studying and then minimizing differences in SAM image quality obtained by different operators and/or different types of SAM measurement equipment. Ultimately, they will allow to homogenize the SAM image quality on different kinds of typical standard samples on a high level, and thus contribute to reliable failure identification independently of the specific operator or measurement system.

ABSTRACT. With the density increase of today’s printed circuit board assemblies (PCBA), the electronic fault detection methods reached their limits, in the same time the requirements of high reliability and robustness are greater. Industrials are obliged to find better-adapted test methods. Current test methods must be rethought to include a large panel of physical phenomena that can be used to detect electrical defects of components, absence, wrong value, and shorts at component level on the board under test (BUT). We will present the possibility of using electromagnetic signature to diagnose faulty components contactlessly. The technic consists in using small diameter near electromagnetic field probes which detect the field distribution over powered sensitive components. The biasing of the BUT is specifically chosen to enhance the sensitivity of the EM measurements. Reference EM signatures are extracted from a fault-free circuit, which will be compared to those extracted from a sample PCBA in which we introduced a component level defect by shorting, removing or changing the value of critical components. As a result, we will show that the amplitude of a specific harmonic acts as a sensing parameter, which is accurately related to the variation of the component value.

ABSTRACT. Quiescent current (IDDQ) test demonstrated over years its effectiveness in identifying the ICs failure root causes. In this paper three cases study are presented, all based on the use of IDDQ test during Emission Microscopy (EMMI). The DUTs analyzed, implemented in different technological solutions (BCD and BiCMOS), belong to the automotive market segment. In the cases here described the emission microscopy approach from both front and backside has been considered. Different physical analysis techniques have been used in order to characterize morphological marginalities or abnormalities. Results from the three cases should be good examples to prove how this kind of approach - fault isolation driven by IDDQ - is a powerful technique able to identify quickly and precisely failure root causes in high complexity ICs, independently of design and technology, and even when Automatic Test Pattern Generation (ATPG) is not available.

ABSTRACT. In the context of More than Moore 3D integration concepts, the µm to nm sized failure detection and failure analysis present highly demanding tasks. In this work, micron sized (about 10 µm) artificially induced metallization defects are detected by scanning acoustic microscopy (SAM), high resolution µ-Xray tomography (XCT) and scanning electron microscopy (SEM). Notably, the SAM results detected the failure mode at a different position from the XCT and the SEM. In order to interpret these controversial analyses, elastodynamic finite integration technique (EFIT) simulations have been performed that suggest an increased capability of the SAM concerning defect detection, if additional wave modes in the sample are present. The simulation efforts show that interference effects might cause the defect to appear at a different position in the SAM analyses. Simulation and understanding of such effects can be highly beneficial for the progress of state of the art failure detection and analyses.

ABSTRACT. In the present work the reliability assessment of capacitive MEMS accelerometers of 3 different suppliers for their use in space applications was performed. The applied reliability assessment testing programme addressed specific severities typical for space missions, such as mechanical shocks and vibrations during take-off and stage separation flight segments, high temperature gradients and radiation endurance during in-orbit operation, etc… The main aim of the testing was to evaluate the robustness and reliability limits of MEMS devices by overstressing their specific properties and parameters with dedicated tests. Typical failures of the tested MEMS devices were analysed and failure root causes were identified taking into account the device design consisting of: MEMS structure, ASIC, interconnecting wires, and package. Overall results of the performed reliability assessment tests and failure mode analyses suggest that the most specific MEMS components, namely the MEMS structures, themselves do not constitute the failure causes. Usually, other device components, e.g. interconnects, ASIC or packaging, exhibit lower reliability limits to the specific stresses of the space harsh conditions.

ABSTRACT. Reliability and integration of Lead Zirconate Titanate (PZT) is still a strong concern regarding its commercialization. In this work we present an approach to include reliability on wafer-level for integration and process development. Long-term leakage current development with high statistics of integrated low-temperature PVD PZT capacitors at different temperature, voltage and polarity are presented. We find strong similarities to the behaviour of pulsed laser deposition (PLD), sol-gel and ceramic PZT [1,5,6,7]. We suggest to use the current evolution after first breakdown as possible indication of remaining useful life. Breakdown times (tBD) under DC stress were found to show a distinct and strong profile over wafer position. Consistent profiles were found for various temperatures and voltages. They are repeatable for wafers of at least one lot, which enables investigation of the underlying physical mechanisms. Position dependence of tBD influences analysis of failure statistics. Assuming that sample composition is similar between measurements and influences of the profile are initially small, comparison over temperature and voltage were possible. For negative polarity we found changes of Weibull slope above a temperature of 150°C and gradual change over voltage acceleration in the range of 100kV/cm to 200kV/cm.

ABSTRACT. The stress distribution and the failure of CMOS-MEMS microphone under shock loading was investigated by finite element method. The results show that corners of spring, the anchors connecting spring and fix end and the connection of the spring and diaphragm had higher stresses for MEMS microphone under shock loading. Four parameters, the width of anchor, the width of spring, the radius of diaphragm and the thickness of diaphragm, were chosen in stress analysis of MEMS Microphone by Taguchi method. Each parameter has lower, middle and higher levels. The case with higher width of anchor, width of spring, thickness of diaphragm and lower radius of diaphragm has smaller stress, 50% less than that of the original design; the case with middle width of anchor, lower width of spring, higher radius of diaphragm and thickness of diaphragm has 7.16 times of microphone capacitive sensitivity than that in the original design. Drop test experiment was performed to verify the simulation results according to the JEDEC standards, JESD22-B111 and JESD22-B110B. The results obtained in this study can give useful suggestions for improving the design and reliability of MEMS microphone.

ABSTRACT. The reliability as well as performance of micro electronic devices strongly depends on the resistance to their thermal degradation induced during operation. In present work, a process flow is developed to fabricate Micro-Electro-Mechanical systems (MEMS) structures, which provide a reliable platform to study thermomechanical aspects of silicon-thin metal interface at different temperatures. Here different submicron structures such as cantilever, beams, plus sign, theta and curved cantilevers of varying dimensions are fabricated. The process demonstrates flexibility to manufacture different structures, where the thickness of silicon and of copper can be varied independent to each other. Features based on Si with thickness of 4 or 11µm coated with Cu of 0.5-3µm in thickness are manufactured and used as plus signs and curved cantilevers to study deformation over the temperature range of -50 to 400°C. Deflections from 3µm tensile to -8µm compressive are observed. This study gives an experimental evidence of behavior of copper over thermal cycling using MEMS structure. Moreover, Si-Cu based structures are subjected to high temperature cycling to induce degradation and microstructure of their interface is studied. This methodology offers flexibility to characterize different kinds of thin films of different dimensions under individual process conditions.

ABSTRACT. The potential application of Yttrium Oxide (Y2O3) in capacitive Micro-Electro-Mechanical Switches (MEMS) dielectric films is investigated. The electrical properties and impact of electrical stress of capacitive switches have been investigated with the aid of Metal-Insulator-Metal (MIM) capacitors and MEMS capacitive switches in order to determine the suitability of this material for such application. The assessment consisted of current-voltage characteristics and the current transients were recorded in MIMs in order to determine the transport mechanisms and the charge injection and collection by injecting electrodes. MEMS were employed to monitor the charge injection through the bridge during pull-in state and collection during pull-up state. The process was performed under different stress conditions in order to determine the impact of stressing electric field intensity.

ABSTRACT. For nanometer technologies, SET is increasingly growing in importance in circuit design. Accordingly, different hardening techniques were developed to reduce the Soft-Error Rate. Considering selective node hardening technique based on standard cells, this work evaluates the SET response of logic gates from a Standard-Cell library under heavy ions. The MC-Oracle, a Monte-Carlo predictive simulation tool, is used to account for the particle interaction in the device and to determine the transient pulses. With the results gathered in this work, circuit designers can implement reliability-aware synthesis algorithms with selective hardening more efficiently to tackle the threat of SET in combinational circuits.

ABSTRACT. The paper presents an experimental characterization of the damages induced by heavy ion irradiation in commercial 1200V - 24A SiC power MOSFET. The used experiment setup permits to measure the time evolution of both drain and gate leakage currents during the irradiation and then to distinguish between the formation of damages at drain and gate structures. It is shown that, for drain bias between ⁓100V and ⁓330V only the gate structure is damaged. From ⁓330V up to the SEB critical voltage (⁓500V), differently from Si counterparts, the drain structure is progressively damaged by the irradiation. The increase of the drain leakage current corresponds to an hyperbolic decrease of the drain resistance and then can be modelled by a cumulative increase of the parallel tiny conductive paths associated with micro-damages which progressively form across the body junction.

ABSTRACT. TID and SEE induced errors in 1Mb HfO2-based resistive-random-access memory (RRAM) with 1T1R storage cell structure are investigated. TID-induced leakage current in the access transistors on the same bit-lines causes a read decision failure and bit errors observed. SELs in the CMOS peripheral circuits have been found, while RRAM memory array is immune to SEU. These are useful for developing radiation-hard RRAM aiming at space applications.

ABSTRACT. This paper presents a study of High Power Electromagnetics (HPEM) stress effects on a GaAs (Gallium Arsenide) low-noise amplifier (LNA). This work aims to evaluate such electrical stress effect from circuit to component scale in relation to more general Intentional electromagnetic interference (IEMI) studies. Conducted susceptibility measurements were made on a specifically designed device under test (DUT). Those experiments yielded interesting results concerning exposition of the DUT to destructive values of interference power, as well as its response to non-destructive but significant powers. Additional measurements and analysis are provided to get a better understanding of the observed phenomena.

ABSTRACT. This paper presents a single-event-upset tolerant latch design based on a redundant structure featuring four storage nodes (i.e. Quatro). The reference structure manifests single node upset issues when either of the two internal nodes is hit and observes a positive transient afterwards. Two OFF-state resistors are added to those two internal pull-up paths, suppressing positive transient. Simulation and experimental data demonstrate that the proposed design has smaller cross section and higher upset threshold than the reference design.

ABSTRACT. The given project is to benchmark typical preparation methods under the aspect of the influence of initial intrinsic stresses inside electronic components. Micro drilling - and laser-decapsulation in combination with plasma etching were chosen as preparation methods. Raman spectroscopy has been applied as well as the piezo resistive readout on a specifically designed model stress monitoring chip. The results of the analysis at each manufacturing step of the model chip and the first investigations of partial decapsulation will be presented.

ABSTRACT. This paper identifies failure mechanisms of axial lead fuses subjected to real field ambient thermal profiles by finite element simulations and experimental testing. Experimental observation of failed fuses attributes fatigue failure of fuses to breakage of the fuse element. The fuse elements consistently fail at the notches adjacent to the end caps accompanied by a localized out-of-plane bend. Identification of the failure mechanism motivates a comprehensive thermo-mechanical study of the fuse deformation response prior to failure, which is rather involved due to complex interactions of the fuse components, and residual effects of manufacturing processes. An investigation on the pre-operational state of fuses evaluates damage introduced during manufacturing of the fuse. In specific, the work simulates soldering induced residual stresses and addresses their impact on the fatigue damage and lifetime of the fuse. In the paper, a lifetime model of the fuse is proposed and tested.

ABSTRACT. Integrated circuit (IC) reliability failure at field presents significant cost to both manufacturer and consumer. This paper targets reliability issue due to design weakness, presenting a case of 28nm Input/Output (I/O) circuit reliability failure, and shows a complete work flow, starting from root cause identification using failure analysis, and ending with design retrofit to solve the issue. The work flow identifies design weak spot in the I/O issue successfully, and is applicable to solve general design related reliability problem.

ABSTRACT. Open defects in power pins are often invisible during manufacturing process and can remain as potential risks in case of stressful device operations. The difficulties of testing power-opens are largely due to both no direct visibility of power pins and the design practices of over-designing the number of power pins. In this work, power noises were electrically probed and analysed, to better understand electrical signatures induced by power-opens. When power-open faults were injected into the system, current was redistributed; the distribution of impedance among power pins greatly affected this current distribution. The power network inside the DDR3 SDRAMs used for the experiments was discovered to be asymmetrical. An asymmetric power network was demonstrated using the power pin disconnection method with a custom-built platform for studying open power pins. Power-open defects produced a wide range of power noises (0 to 45 mV) on power pins depending on these pin’s locations. The Spice Simulation was also conducted to recreate and validate observations from test platform experiments. The Spice Simulation also showed that when power distribution is not well-designed, the effect of power-opens could be more widely varying depending on impedance dependency among power pins.

ABSTRACT. We have systematically studied the origin of high gate leakage current in AlGaN/GaN high electron mobility transistors (HEMTs). Devices that initially have a low gate-leakage current (good devices) are compared with ones that have a high gate-leakage current (bad devices). The Schottky barrier height of bad devices (0.4 < Barrier Height < 0.62 eV) was found to be lower than that of the good devices (Barrier Height = 0.79 eV). From transmission electron microscopy (TEM) and electron energy loss spectroscopy (EELS) analysis, we found that this difference is due to the presence of carbon impurities in the Nickel layer in the gate region.

ABSTRACT. The effect of gate technology and semiconductor passivation on the switching speed and device reliability has been investigated. By reducing the parasitic capacitances and reducing the passivation induced surface charge density a median life time of 106h at a channel temperature of 125 °C and a current-gain cut-off frequency of 74 GHz for a T-gate technology has been achieved. By electroluminescence and TEM cross-sectioning of a stressed device a local inhomogeneous pit formation was found as the major degradation mechanism for the decrease of the saturation current.

ABSTRACT. Room temperature photoluminescence (PL) was carried out on a pre-processed GaN/AlGaN/GaN/SiC wafer. The yellow luminescence (YL) band, peaking at 2.2 eV, intensity was much higher in the wafer’s edge. A large number of AlGaN/GaN high electron mobility transistors were characterized by DC, double pulse and drain current transients (DCT) to investigate YL intensity correlation with electrical characteristics. A good correlation was found between YL intensity and maximum drain current IDSS and threshold voltage. DCT spectra exhibit two prominent trap centers for three representative devices from different part of the wafer. E2 (Ea = 0.6 eV) trap features the same activation energy and electron capture cross section for the three samples, which means if it contributes to the yellow band, it is not the responsible of the high YL intensity of about 15% in the edge compared to the center of the wafer. The significantly high YL intensity would be more likely related to deep level traps (E1) with an activation energy between 0.7 eV and 0.9 eV. This is assumed as the E1 capture cross section is higher for the edge devices.

ABSTRACT. Due to the intrinsic piezoelectric nature of Gallium Nitride (GaN), devices manufactured with such technology are in principle prone to experience electro-mechanically induced resonance phenomena under operating conditions. In this paper, we present the thorough approach combining simulation and experiment to study the occurrence and implications of such electro-mechanical resonances. A simple GaN-on-Si capacitor test structure was fabricated and electrically excited in order to activate the mechanical eigenmodes of the assembly which are measured by a Laser-Doppler-Scanning-Vibrometer. A multiphysics Finite Element (FE) model of the tested structures was built in order to perform harmonic analysis and to quantitatively study the effects of damping on displacement, stress and strain. Comparison of measured and simulated eigenmodes shows good agreement.

ABSTRACT. This paper describes the methodology and results obtained from performing a rigorous ESCC qualification of European microwave GaN technology for the European Space Agency (ESA) Biomass mission. This is the first time European GaN technology has been qualified for an ESA mission and represents a major breakthrough in the maturity and application readiness of this technology. The work has involved developing hermetic packaging solutions and performing extensive mechanical, assembly, endurance and space operating environmental tests to ensure the components are capable of satisfying the Biomass mission requirements.

A summary of the key qualification results obtained shall be presented.

ABSTRACT. This paper evaluates the reliability of a GPU pipeline upset by SEU faults and the impacts of software-based and hardware-based fault tolerance techniques. The approach entails first assessing the vulnerability of the GPU pipeline to SEU through a fault injection campaign at register transfer level. Second, this assessment applies three low-level software-based fault tolerance techniques to protect the register files intending to indirectly protect the pipeline and evaluates impacts on performance degradation. Thirdly, it evaluates the costs of applying selective double modular redundancy and its impacts on area overhead. Experiments are performed using a GPU based on the NVIDIA G80 architecture running four case-study applications. Results show fault detection rates of 35% with performance costs of 78%, and up to 100% with less than 60% area overhead.

ABSTRACT. Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial replication. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristic. The algorithm initially defines the gates to be approximated using testability and observability measures. Experiments compare our new approach with a state of the art technique that uses genetic algorithm showing a good trade-off between the ATMR schemes quality and the computational effort needed to generate them.

ABSTRACT. This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessors behaviour. The proposed approach is suitable for COTS because it does not modify the microprocessor architecture and hardens it thanks to the reuse of its trace subsystem. Proton irradiation campaign has been performed with Cortex A9 microprocessor. Experimental results demonstrate the high detection capabilities of the proposed approach that are accomplished without microprocessor architecture modification.

ABSTRACT. Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. This paper presents a methodology for accurate characterization of radiation-induced Single Event Transients (SETs) effects in SRAM-based Field Programmable Gate Arrays (FPGAs). A technique based on internal electrical pulse injection is proposed for emulating SET within logic resources of SRAM-based FPGAs. Experimental results provide detailed characterization of basic logic gates.

ABSTRACT. This paper presents a metric to the efficient application of selective hardening using software-based techniques. It offers a method for selecting the resources to be protected obtaining maximum fault coverage with the minimum overhead. Common approaches are based on exhaustive exploration of the solution space or time-consuming fault injection campaigns. Contrarily, our Software based HARdening Criticality metric (SHARC) relies on early estimations of the impact that protection techniques will have on the global reliability of the application. SHARC estimations rely on features extracted from the dynamic analysis of source code and produce a prioritization of the resources implied accordingly. For assessing our approach two case studies were carried out using low-cost embedded microprocessors. Results were compared to traditional approaches like brute-force exploration and the Architectural Vulnerability Factor (AVF) metric. Experiments show that SHARC improves the results between 5% and 21% reducing the effort by several orders of magnitude.