ABSTRACT. The preliminary characterization study and analysis of the short-circuit capability of SiC MOSFET has been reported in recent years. However, the failure modes of the SiC MOSFET under various short-circuit conditions and their physical mechanisms are unclear. The purpose of this paper is to extensively investigate the shortcircuit ruggedness, failure modes and internal physical mechanisms of the SiC MOSFET. The influence of major limiting factors on the SiC MOSFET is experimentally studied, including gate drive voltage, DC bus voltage, and die sizing. Two short-circuit failure mechanisms, the thermal runaway and gate interlayer dielectric breakdown of the SiC MOSFET are identified as the root causes of failure by means of microscopic failure analysis techniques.

ABSTRACT. The aim of this paper is to investigate the role of the etching of the sidewalls of p-GaN on the dynamic performance of normally-off GaN HEMTs with p-type gate. We analyze two wafers having identical epitaxy but with different recipes for the sidewall etching, referred to as “Etch A” (non-optimized) and “Etch B” (optimized). We demonstrate the following relevant results: (i) the devices with non-optimized etching (Etch A), when submitted to positive gate bias, show a negative threshold voltage shift and a decrease in Ron, which are ascribed to hole injection under the gate and/or in the access regions; (ii) transient characterization indicates the existence of two trap states, with activation energies of 0.84 eV (CN defects) and 0.30 eV. The latter (with time-constants in the ms range) is indicative of the hole de-trapping process, possibly related to trap states in the AlGaN barrier or at the passivation/AlGaN interface; (iii) the threshold voltage shift increases at higher temperatures, indicating a thermally-activated hole trapping mechanism; (iv) by optimizing the p-GaN sidewall etching (for the same epitaxy) it is possible to completely eliminate the threshold voltage shift. This indicates that hole injection mostly takes place on the sidewalls.

ABSTRACT. In order to distinguish die-attach solder layer and bond wire degradation during power cycling tests, a simultaneous on-line measurement method is proposed in this paper. To measure accurately solder layer voltage drop, the intrinsic diode is used as a heating source in place of the MOSFET switch. In this way, the measurement method becomes intrinsically insensitive to possible threshold voltage shifts, typical of the accelerated test of SiC power MOSFETs. Finally, the experimental results are presented to verify the feasibility of the proposed test method. It is revealed that the solder layer resistance increases linearly with the number of cycles in good approximation.

ABSTRACT. We present an extensive analysis of the degradation of GaN-on-GaN fin-vertical transistors submitted to stress under positive gate voltage and off-state conditions. By analysing the degradation kinetics we demonstrate the existence of different processes: (i) trapping of electrons in the gate insulator under positive gate bias, (ii) time-dependent breakdown of the gate MOS structure under forward gate voltage; (iii) catastrophic failure for off-state voltages higher than 280 V. 2D simulations are used to identify the physical location of the failed region, and to investigate the dependence of electric field on fin width (values between 70 nm and 195 nm).

ABSTRACT. The hot electron injection model presently available in the TCAD tools has been investigated against experiments on new test devices to the purpose of gaining an insight on its predictability in the context of the new-generation technologies. The study has been carried out on electron emission in extremely high electric fields, as expected in power LDMOS devices at the onset of avalanche breakdown, reaching for the first time injection probabilities as high as 0.01. The numerical analysis clearly showed that the new Si/SiO2 interfaces experience different features with respect to the old ones. The TCAD method based on the deterministic solution of the Boltzmann equation can accurately capture such effects.

ABSTRACT. The most relevant transport features of doped diamond-like carbon (DLC) films have been implemented in a TCAD setup to provide a theoretical tool to assess the reliability expectations for high-voltage device passivation. Starting from the band structure and boundary conditions of a metal-insulator-semiconductor (MIS) device, trap states in the bandgap have been used to determine the characteristics of differently doped DLC layers against experiments. The role of the DLC as a passivation layer on top of the bevel termination of a high-voltage diode has been studied and compared with experiments. The breakdown voltage is significantly influenced by the properties of the DLC as nicely explained by the TCAD simulation results.

ABSTRACT. Electrostatic discharge (ESD) protection devices in advanced state-of-the-art CMOS technologies need to be optimized towards minimizing size and capacitive loading of the core circuitry without loss of ESD performance. In this work, a layout study of diode-trigged SCR (DTSCR) by means of calibrated 3D TCAD is presented. The focus lies on layout dependent uniformity of operation, and transient turn-on behaviour under very-fast (vf)-TLP stress, for which a 3D approach is mandatory. In this context, we employ a novel TCAD methodology that allows to reliably perform 3D process simulations in a fast, and yet accurate way. We can generate very large device structures with a mesh node count in the order of millions, such as the DTSCRs under investigation. Using rigorous 3D process simulation would be too expensive, or simply not feasible. Process simulation turnaround time (TAT) reduction from weeks to days or hours opens for the possibility of using the 3D TCAD simulation deck for guiding the layout optimization process.

ABSTRACT. The significance of transistor degradation due to aging mechanisms such as BTI or HCI has increased significantly with the continuous scaling down of CMOS technologies and their presence in safety-critical systems. In order to deliver the reliable systems that the industry currently demands, it is necessary to apply aging simulations in IC design projects. However, the capabilities that are available strongly depend on the EDA environment and tools. In this paper we present the work done in a case study to characterize and model NBTI and HCI degradation for X-FAB’s XU035 technology, and we discuss a methodology developed to implement and integrate user-defined aging models for circuit level simulation with consistent results across different design environments.

ABSTRACT. An integrated health indicator is developed for lithium-ion batteries to predict remaining useful life. The indicators are correlated to aging mechanisms, and then the integrated health indicator is developed by incorporating capacitance, resistance, and constant current charge time. Remaining useful life is predicted using a particle filter algorithm based on a three-order polynomial degradation model. A case study is employed to validate the developed method, and a threshold 0.85 is recommended to be the end-of-life criterion.

ABSTRACT. State of Health (SOH) plays a pivotal role in the reliability and safety of the Lithium-ion (Li-ion) battery. Utilizing the features from voltage response of the Li-ion battery under current pulse test, a novel SOH estimation method is proposed by using the Support Vector Machine (SVM). Since the terminal voltage of the battery measured at the same test point varies with the battery aging process, the features for SOH estimation are extracted from voltage response under specify current pulse in this paper. After an optimal feature selection process, SVM is able to establish the relationship between the new features and the battery State of Health (SOH). A LiFePO4 battery is tested in the battery test station for 37 weeks to verify the validation of the proposed method.

ABSTRACT. Discharge voltage is an important indicator to alarm end-of-discharge of lithium-ion batteries. Therefore, prediction of the discharge voltage when the battery is in use is helpful in preventing issues caused by running out of power. For many real applications, the battery is working under unknown and dynamic loads, which makes the prediction difficult. In this paper, we propose a novel method to predict the discharge voltage under unknown future loads. This method firstly establishes the relationship between the discharge voltage and the loads, then predicts future loads based on a framework consisted of wavelet analysis and polynomial neutral network with group method of data handling. Finally, the discharge voltage is predicted using the relationship model with particle filter-based updating scheme and the predicted future loads. The effectiveness of this method is demonstrated by a real flight dataset coming from experiments conducted on a plant protection UAV. The results show that our method is able to achieve good prediction accuracy and outperforms some other benchmark methods.

ABSTRACT. An accurate state of health (SOH) estimation for Li-ion batteries is essential to provide the electrical performance evolution over time and with operation for users. In this context, an efficient method based on Incremental Capacity Analysis (ICA) is proposed to estimate the SOH for Nickel Manganese Cobalt oxide (NMC)/Graphite battery. We focused on the qualitative and quantitative ICA according to different ageing modes under aeronautic conditions: calendar ageing at 55°C and -20°C, power cycling at 45°C and 0°C. A logarithmic and linear regression are observed between SOH and normalized parameter. With proposed method, the SOH estimation for NMC/Graphite battery can reach 97% accuracy.

ABSTRACT. The robustness margins for automotive electronics are getting smaller due to growing complexity in technology and increasingly challenging use cases. Formal qualification based on electrical testing without microstructure analysis and without EOL testing for deeper understanding of failure risks increases the probability of field returns. Failure root causes include complex interactions between chip, package and system in combination with specific details of the mission profile. In this talk illustrative examples of complex defect mechanisms will be presented demonstrating the need for robustness validation-oriented physics of failure approaches. It will be shown that robustness validation can benefit from precompetitive research on physics of failure concepts prior to reliability investigation of products.

ABSTRACT. As the minimum feature size continues to shrink, a host of vulnerabilities influence the resiliency of VLSI circuits, such as increased process variation as well as workload-dependent runtime variations due to voltage and thermal fluctuations together with various device and interconnect aging effects. Current approaches for variation-aware resilient circuit design consider only a small subset of these factors and typically address each of them in isolation. As a result, an over-pessimistic additive design margin, resulting from these sources, is eroding gains from technology scaling. In this talk I will discuss cross-layer approaches for holistic modeling of various variation effects in the design stack, by taking into account netlist, layout and workload to capture all spatial and temporal information, and also consider the interplay of various process and runtime variation effects. In addition, I will cover cross-layer variation-aware design optimization schemes.

ABSTRACT. In this study, we have revealed that the possibility of using Ag SMB technology for applications of large area die-attachment. We observed how hillock growth changed on the Ag layer over various bonding conditions, how it varied in large area, and how it related to the bond strength. The large bonded area (20 x 20 mm2) was achieved by using SMB process, resulting in average flexural strength of 40.5 MPa at 300 °C. The hillock growth was significantly scarce at the edge and its area was about 700 μm from the edge, which is expected to seldom affect in large area chip bonding. The bonding technology can be an attractive technology for large area bonding in the power device electronic applications and its reliability issue.

ABSTRACT. In the packaging and evaluation of power electronic components non-destructive test methods (NDT) such as scan- ning acoustic microscopy (SAM) are valuable tools in packaging and failure analysis. As power modules become more compact and power devices thinner, echo overlap and interference can hamper the imaging capability and analysis of the conventional SAM time domain-based imaging techniques. Frequency domain analysis offers increased resolution and contrast but the interpretation and feature identification of waveforms is less obvious and interpretation guidelines have received little attention. In this paper a physics-based analysis of the frequency domain response is presented in a power module case study. The analysis is used to demonstrate physics-based feature selective contrast in such systems and offers guidelines for feature prediction. The approach is verified on full scan datasets from an acoustic scans of a hybrid multi- layer stack. Distinct features in the echo frequency domain are identified as resonances associated with multiple internal reflections in the layer structure. Where such features may hamper analysis in the conventional approach these can, if properly assigned, be exploited to yield selective and improved contrasts.

ABSTRACT. Thermal aging effect on the electrical resistivity and mechanical properties as well as microstructure of sintered porous silver paste was examined under high temperature exposure. Silver paste was printed in a shape of a test specimen on a Cu substrate, and was sintered at 250 °C for 1 h in air with no pressure and then which were exposed for 0, 50, 500, and 1000 h at 250 °C. Electrical resistivity and tensile strength was obtained at each ageing stage . The evolution of microstructure including sintered silver grains, porous structure and fracture surface were characterized by SEM and EBSD. The relationship between aging microstructure and mechanical/electrical properties was discussed in detail.

ABSTRACT. One of the most critical aspects of long-term reliability for electronic applications is corrosion. However, this aspect does not take place in most accelerated tests. In particular, power electronics applications, for example in offshore wind turbines, include some of the harshest environmental conditions for electrical components. For these applications a reliable die attach technology is necessary. One of the most promising technologies is the sinter silver technology. This paper gives an overview of corrosion behavior of sintered silver under harsh environmental conditions. The paper deals with the investigation of the influence of different sintering pressures on the corrosion behavior. To characterize the corrosion issues of sintered silver, various electrochemical and analytical methods are used.

ABSTRACT. Wire bond resistance increase due to thermal stress can be modelled by the Arrhenius equation, permitting prediction of wire bond reliability in a product prior to qualification if sufficient experimental data is collected and statistically analysed. Activation energies for various experiment “legs” are determined by stressing a number of wire bonds at 3 different temperatures, then, using survival analysis techniques for accelerated failure time models, extrapolating results to use conditions. Example lifetime predictions for Cu and PCC wire bonds on Al pads are shown to illustrate the method, using a small number of test die that incorporate four-wire resistance measurements of wire bond pairs, with two ball bond sizes and two different wire types, stressed at precise temperatures with in-situ resistance monitoring in the University of Waterloo’s “mini-oven” reliability test systems. These results show that typical Cu wire bonds on Al bond pads can be highly reliable up to 163 °C without encapsulation or 155 °C with encapsulation, with estimated lifetimes of 12000 h with less than 1 ppm failure rate.

ABSTRACT. During the last years more and more results of investigations on the visco-plastic behavior of sintered silver interconnections were published. To classify the meaning of the rate-dependency of porous silver films a good model description is necessary. Since different formulations are available and already used this work focusses on different modeling strategies for describing the experimental results. Creep tests on sintered silver films at different load and temperature levels were conducted. Two approaches to model the rate dependency were used. After parameterization of the models different load scenarios were compared. Showing a good accordance of simulation and experiments for monotonic loading, large differences between the predicted stresses and strains for multiple-hardening-relaxation scenario was observed. The knowledge gathered will be used to give suggestions for each modeling strategy for sintered silver with respect to specific applications in the field of electronics packaging.

ABSTRACT. Various reference printed circuit board (PCB) thermal designs have been provided by semiconductor manufacturers and researchers. However, the recommendations are not optimal, and there are some discrepancies among them, which may confuse electrical engineers. This paper aims to develop an analytical thermal model for PCB vias, and further to find the optimal design for thermal resistance minimization. Firstly, the vertical thermal resistance of a PCB via array is analytically modelled. Then the dependence of the thermal resistance on multiple design parameters is analysed, and the optimal via diameter is found for different PCB specifications. Finally, the developed thermal model and optimal trajectory are verified by computational fluid dynamics (CFD) simulations and experiments.

ABSTRACT. Manufacturers of electronic components and systems are currently undergoing profound changes. For foundry manufacturers, Moore's law is fast approaching and they must find technological solutions to further densify their electronic circuits. For PCB manufacturers, the change is even more important as they have to bury components inside their circuitry. In this paper we present physics analysis and simulations (FEM) of copper VIAs to study the impact of this kind of assembly process on the reliability of these new electronic circuits. First we present analysis made with the IMS SAM (scanning acoustic microscope) using shear wave’s generation to extract information about strain induced by the copper VIA. Finite element analysis shows the correlation between the two studies. Secondly, we present finite element analysis made on embedded active components inside PCB. TDM (Topography and Deformation Measurements) are made to calibrate the model generated by finite elements. A discussion is then conducted to determine the weaknesses and strengths of each of these technologies in order to determine their long-term robustness.

ABSTRACT. The lifetime of power module in motor drive is closely related to its thermal cycling. Especially in low speed and high output power condition, the thermal performance can be even worse. In this paper, a fundamental region-based thermal control strategy is presented. Firstly, the model for high power drive thermal cycling calculation is established. Then, with the lifetime model, the junction temperatures and number of power cycles can be mapped with fundamental frequency. Thus the fundamental frequency region is divided. Finally, the switching frequency is selected in the obtained fundamental frequency region to control the thermal fluctuation and reliability. The techniques developed can actively extend the lifetime of driver.

ABSTRACT. The battery is the most sensitive part in the powertrain of full electric vehicles because of its cost and weight. The full electric vehicle range and prize are highly determined by the battery performances. During its lifespan, the battery performances are degraded because of ageing mechanisms. Typically, there are two types of ageing: calendar and cycling ageing. In the electric vehicle application, both types of ageing coexist and interact. In this paper, we report the results of accelerated ageing tests and present a methodology to separate calendar from cycling ageing. With this analysis method, we demonstrate the interaction between calendar and cycling ageing when battery is cycled following representative current profiles of the electric vehicle application.

ABSTRACT. High power insulated gate bipolar transistor(IGBT) modules in new energy power generation, electric vehicles and high-voltage direct current transmission is widely used in fields, its system reliability is more and more attention, power device junction temperature is an important factor that influence the reliability. In view of electric vehicle applications, this paper presents a method of temperature prediction and over temperature protection for electric vehicle power devices. According to the thermal impedance model of modules and relationship between power module internal thermistor NTC temperature and junction temperature, two junction temperature estimation can be gained, under different conditions to adjust two estimated junction temperature’s proportion to get an optimal estimation. On the basis of junction temperature estimation add a threshold temperature, when it reachs this temperature, implementing effective over temperature protection using motor control to prevent junction temperature is too high and the electric vehicle motor driver is failed.

ABSTRACT. In this paper, a comparison between the performance of a Lithium-ion battery at beginning-of-life (BOL) and at end-of-life (EOL) is presented. The capacity, internal resistance, and open circuit voltage of a 13Ah Lithium-ion battery had been measured at BOL for different temperatures, C-rates, and state-of-charge (SOC) levels. Then, the battery was aged, losing 60% of its initial capacity, and the aforementioned measurements were also repeated at battery’s EOL. The obtained results have shown that besides the expected capacity fade and internal resistance increase, there is a dramatic change, from BOL to EOL, in the variation of the battery performance parameters with the temperature, C-rate, and/or SOC.

ABSTRACT. Electronic control units, power modules, and consumer electronics are used today in a wide variety of varying climatic conditions. Varying external climatic conditions of temperature and humidity can cause an uncontrolled local climate inside the device enclosure. Uncontrolled humidity together with number of other factors including the presence of hygroscopic contamination resulting from the PCBA manufacturing process can introduce deviation from desired functionality or even intermittent or permanent failure of the device. Additional factors are the miniaturization and high density packing combined with the use of several materials, which can undergo electrochemical corrosion in presence of water film formed due to humidity exposure and bias conditions on the PCBA surface. Aim of this paper is to show how the interplay between humidity (also transient changes in climate) and electrical functionality occurs, which cause several reliability issues on electronics due to electrochemical failure mechanisms.

ABSTRACT. Technology Computer Aided Design (TCAD) tools can be used to effectively study and analyze a multitude of reliability issues in semiconductor devices. In the following article, we first describe Negative-Bias Temperature Instability (NBTI), which is one of the most severe reliability issues. Using the Reaction-Diffusion (RD) model for simulating the NBTI effect, we show that the simulated threshold voltage degradation agrees well with measured data. Based on the simulation results, we propose an on-chip heater to enhance recovery and revert the NBTI degradation. Next, we discuss how to apply the Hot-Carrier Stress (HCS) model to analyze hot carrier degradation in FinFET. We show that the threshold voltage shift agrees well with experiment and use the HCS model for the simulation of breakdown voltage walkout in a LDMOS transistor. Then, we apply process emulation to better understand modern DRAM structures and illustrate the row hammering reliability issue. Finally, we demonstrate a multi-level sub-modeling methodology for chip to package interaction (CPI) and apply the method to study the effect of wafer bending on the reliability of re-distribution layers (RDL).

ABSTRACT. Development of advanced electronic packages can be drastically affected by implementation of new materials. The ever increasing demands for high performance and reliable power electronics, raise the need for rapid robustness evaluation of interconnects. In this study the lifetime of heavy wire bonded interconnects, fabricated with different wire material types Al, AlMg, Cu and Al coated Cu (CucorAl) bonded onto direct copper bonded ceramic substrates was investigated. The tests were performed using an accelerated mechanical fatigue testing system, which allows to determine the lifetime of the interconnects with regard to wire bond lift-off failure, hence comparing the performance of different material combinations, the influence of ultrasonic power variation and impact of aging in a short period of time. Cu wire bonds showed clearly the best fatigue performance as well as static shear strength followed by AlMg and Al bonds. Increasing the ultrasonic power for CucorAl elevates its fatigue life higher than pure Al wires. In certain cases the results of fatigue experiments and static shear tests were found to be contradictory. The presented results suggest that accelerated mechanical fatigue testing can be used as an additional fast method for qualification of interconnects and assessment to determine the influence of wire material, bond parameter and aging.

ABSTRACT. A PCB-embedding process using pressed metal foam to connect the top-side pads of a power die is considered; its reliability is experimentally investigated. The manufacturing process, simple and highly cost-effective, is described in detail; samples of embedded diodes are manufactured and aged through passive thermal cycling and high-amplitude current surges. It is shown that prototypes cycled between -40 °C and 150 °C exhibit reliability close to that of Direct Bounded Copper (BDC) substrates. Samples submitted to 150 A-surges have highly dispersed reliability, failing after 7,000 to more than 13 million pulses. A discussion on the development of reliability-assessment-methods, especially suited for PCB-embedding processes, is proposed.

ABSTRACT. Shear testing of microelectronic wirebonds is important in bonding process qualification, but the actual mechanism of shearing Cu bonds from Al pads is not thoroughly understood. In this study, experiments and finite element analysis (FEA) are employed to develop a deeper understanding of shear testing and its ability to predict wirebond reliability. Thermosonic ball bonding on Al pads causes Al deformation, including thinning beneath the bond and Al “splash” to the sides, while forming the weld through intermetallic (IMC) formation. Pad Al thickness and IMC area are both important factors for shear force of as-bonded circuits, explained by simulations calibrated to experimental data of both destructive and non-destructive shear testing. Shear test results after encapsulation and reflow, and after reliability stress testing, are compared with shear force of as-bonded.

ABSTRACT. The effects of moisture on the electrical properties of epoxy molding compounds containing high quantities of silica filler microparticles have been investigated by means of dielectric spectroscopy, steady-state conductivity and pulsed electro-acoustic space charge measurements. It has been shown that the presence of water at the filler/epoxy interfacial areas affects the low-frequency dielectric response of the materials and significantly increases their electrical conductivity, especially at higher temperatures. In addition, in presence of moisture, space charge measurements have shown the accumulation of heterocharges which significantly increase the electric field at the electrodes. These aspects are of primary importance, as the properties of the encapsulation materials strongly influence the reliability of high voltage devices.

ABSTRACT. The increasing number of thin film interfaces in modern microelectronic components makes determining fatigue delamination properties and understanding the underlying mechanisms a necessity to ensure the reliability of such components. In this work an advanced four-point bending setup for cyclic delamination investigations of multi-layered thin film samples has been developed. The static and cyclic delamination behaviour of two types of Si/SiN/TiW/Cu/Polyimide thin film stacks have been investigated. By calculating delamination growth rate da/dN related to the cyclic energy release rate ΔG it is shown that the cyclic delamination occurs at energy release rates lower than under static loading. Surface analysis of the delaminated interfaces furthermore revealed that the fatigue delamination may occur along a different interface compared to static growth.

ABSTRACT. Insulated Gate Bipolar Transistor (IGBT) is a key component in the power electronics application. Active thermal associated model predictive control is an effective way to reduce the thermal stress of power device with a lower average switching frequency and prolonged lifetime. However, the reduction of switching frequency will impair the power quality of the system. This paper represents a model predictive control method with two thermal state for three-phase inverter. The two thermal states are “reliability critical state” and “reliability non-critical state”, which are of lower and higher switching frequency respectively. The transition of the two thermal states is achieved by changing the coefficients of the cost function in the model predictive control. The criterion of the state shifting is derived from B10 lifetime provided by manufacturer. The method is verified by simulation and will be further analysed by experiment in the final paper.

ABSTRACT. In this work, we report on the development of a methodology for the long term reliability analysis of digital circuits implemented in FPGA. For this, a simulation environment for FPGA has been extended using Python to introduce aging. The aging laws for Look-Up Tables have been integrated by introducing additional variables and equations. The aging laws accurately describe the drifts in the propagation time caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms. An analytical model of the failure time of the digital circuit as a function of the clock frequency has been proposed based on the aging law parameters. Moreover, the developed methodology has been applied to a CORDIC circuit implemented in FPGA.

ABSTRACT. The internal temperature distribution considerably influences the reliability of power modules. Therefore, in order to assess the power module reliability and performance, it is vital to have more accurate models to estimate the thermal behavior. In conventional thermal approaches, thermal heat is considered, but its correlation with the electrical parameters is often neglected. Also, interactions between non-uniform temperature and electrical characteristics of components are rarely taken into account in the literature. In this paper, a Si IGBT die and a SiC MOSFET die are modeled including bond wires and both temperature-dependent thermal and electrical characteristics of the materials. Also, the active area of the die is defined by extracting the area corresponding to the gate pad, gate runners, and termination ring. The results obtained in this work show that if all above items are investigated in the electro-thermal model, then temperatures are increased for the Si die by 4% and for the SiC die by 28% in comparison to a conventional approach (Case I). Furthermore, the uneven current distribution caused by non-uniform temperature distributions among the paralleled bond wires attached to the surface of the chip metalization is considered.

ABSTRACT. The key of ADT (accelerated degradation testing) data processing method based on the pseudo-failure lifetime lies in modelling the degradation path. However, the traditional regression method can only illustrate the average changing trend of the degradation, which may lose much information of the actual degradation process. Therefore, we propose a new processing method for ADT data based on the QR (quantile regression). The different quantiles of the degradation path under different stresses can be obtained by using QR, which offers a more comprehensive explanation for ADT data and allows us to use the alpha quantile of the degradation to represent the system state. Besides, the proposed method can overcome the problems of the heteroscedasticity and outliers in data. Finally, we use double-stress ADT of the seal ring as an example to illustrate the availability of the proposed method.

ABSTRACT. The failure of the traction power supply system may lead to delay or outage of high-speed trains, which will directly affect the entire operation schedule and cause incalculable losses. Therefore, the reliability assessment of the traction power supply system can guarantee the transportation quality of high-speed trains and improve the economy, which is significant for the safe and stable operation of high-speed trains. This paper presents a reliability evaluation method for traction power supply system based on quantification of margins and uncertainties (QMU). According to the basic idea of QMU, by combining with the characteristics of traction power supply equipment and system, we establish the watch list and determine the performance channel for the equipment and system. By the quantification of the performance margins and uncertainties, the confidence ratio is calculated and the reliability of equipment and system is quantified. Practical operation data from a China traction power supply system are applied for method implementation. The simulation results show that the proposed reliability assessment method can account for the uncertainty and quantify reliability index. The reliability of the traction power supply system can be effectively evaluated, and the method is of good applicability for traction power supply system.

ABSTRACT. This paper proposed a new fault-tolerant control strategy for the short-fault occurring in the Switched Reluctance Motor (SRM) electric drive system, which can not only suppress severe torque ripples in short faults, but also can adjust the total torque and torque ripples in different conditions to ensure the safety of the SRM system and drivers. The proposed strategy is to select the derating states according to the operation requirements when the switch short faults occur, then alter the conduction angle of the faulty phase and adjust the duty cycle of the all switches of three phases according to the proposed fault-tolerance rule. Furthermore, the fault-tolerant strategy was applied to a three-phase 12/8 SRM drive. Simulation results in MATLAB/Simulink and experiments on the RT-LAB validate the effectiveness of the proposed strategy, which may be significant in reliability of electric vehicles.

ABSTRACT. The quasi-Z source inverter (qZSI) is one of the most promising power electronics converter topologies suitable for traction applications. The thermal stress of power modules is one of the most important causes of their failure, which is not considered during the control of qZSI drive. For this purpose, this paper introduces the thermal-based control to the qZSI drive controller for the first time. A thermal stress reduction scheme of qZSI drive, which utilizes finite control set model predictive control (FCS-MPC), is proposed. With the help of the cost function, which includes terms for switching counts, number of cycles to failure and inverter constraints in addition to the currents and capacitor voltage, the overall performance of qZSI drive can be improved. The proposed scheme is able to actively regulate the losses and to reduce the thermal stress as well as extend the lifetime of power module. The approach is applied and validated in simulation. Details of the proposed method will be provided in the final paper with experimental tests.

ABSTRACT. Power switch failures have great influence for electronic converter. Prompt detection of power switch’s failure and fault-tolerant operation of multilevel converters have extremely vital significance for high reliability electronic systemss. The paper presents a new technique of detecting, identifying, and locating faults of switching devices in a N-Level Flying Capacitor Buck-Boost Converter(FCBBC). The characteristics of inductor current and flying capacitor voltage of FCBBC with different kinds of failure are analyzed. A new fault diagnosis algorithm is proposed to detect and identify the fault on basis of these information. Then the fault-tolerant operation method of the FCBBC is also discussed. The vadility of the new control method is demonstrated in the control hardware in the loop (CHIL) experiment.

ABSTRACT. In DC power system, reliability and security are essential concerns. However, the reliability cannot be guaranteed because the fast increasing fault current cannot be reliably interrupted due to the limited ultimate capacity of DC circuit breaker (DCCB). This paper proposes a novel current-limiting circuit based on resistive-type superconducting fault current limiter (R-SFCL) to suppress fault current, where arrester in parallel with the breaker is removed. The operation procedure of the proposed current-limiting circuit is presented in details. Then, a mathematical model of opening process is established to estimate the interruption time. Finally, the simulation results verify the effectiveness of this circuit. It is observed that this proposal can limit fault current without applying a big inductor, thus the reliability of DC system can be improved. Furthermore, overvoltage on DCCB is also prevented and the fault isolation time is almost halved.

ABSTRACT. Deprocessing of ICs historically employs a variety of mechanical and chemical process tools in combination with one or more imaging modalities to reconstruct the IC architecture. In this work, we explore the development of an extensible programmatic workflow which can take advantage of evolving technologies in 2D/3D imaging, distributed instrument control, image processing, as well as automated mechanical/chemical deprocessing technology. Initial studies involve automated backside mechanical ultra-thinning of 65nm node 3.0 cm2 Opteron IC processor chips in combination with automated montage SEM imaging and lab-based x-ray tomography and microanalysis. Areas as large as 800umX800um were deprocessed using gas-assisted plasma FIB delayering. Ultrathinning the silicon substrate in the packaged device within 1-2 um of the IC device significantly reduces the amount of time required for deprocessing. The computer aided backside ultrathinning approach not only improves the success rate, as compared to manual techniques, it also allows the dense lower layers with smallest feature size to be imaged via high resolution SEM first, while the sample layers are the most uniform. Backside deprocessing has the additional advantage that it can be possible to access the device while keeping it “alive” for in-situ electrical testing. Ongoing work involves enhancing the deprocessing workflow with “intelligent automation” by bridging FIB-SEM instrument control and near real-time data analysis to establish a computationally guided microscopy suite. As described in the text, a common python scripting API architecture between the FIB-SEM platform and the image processing and microanalysis platforms permit rapid development of customized programmatic instrument control with data process integration and feedback. Current studies use smartcards as an archetype to develop automated workflows. Smartcards represent a good architecture to discuss and develop these methods because they are as much as sixteen times smaller area than a 1 cm2 processor and typically containing far few layers. Yet these small form factor embedded integrated circuits have rapidly become a widespread element of modern society and their security architecture represents an important problem. We demonstrate for the first time; tomographic reconstruction based upon automated back-side ultra-thinning coupled to automated gas-assisted plasma FIB delayering.