ABSTRACT. During semiconductor manufacturing an electrical function test, called wafer test, is performed before further processing. The I/O pads of the chip, which are placed on top of brittle Si-oxide layers, are connected by small elastic probes to supply power and test patterns. During contact a mechanical load is applied on the pads, which increases the risk of oxide cracks. Cracks, however, can cause an electrical failure of the device and affect the quality and reliability. We present a concept and experimental verification data of a new method, based on the established acoustic emission testing, to activate and to detect oxide layer cracks during contacting in real-time. The high sensitivity and resolution of this method offers new opportunities for thin layer characterization at lower time and cost.

ABSTRACT. Our recent research shows that hot-carrier photon emission spectra can deliver several important voltage-dependent device parameters of modern FinFET devices including electron and hole energy distributions, maximum electric field strength in the FET channel, free mean path length and temperature approximations for the hot carrier gas in the channel. These device parameters can be used to continuously monitor device degradation and to obtain estimates for carrier energies and scattering processes within the FET. Furthermore, the gate current function over voltage can be derived from the data using a suitable theoretical model, which can support reliability forecasts. The data presented here is almost impossible to obtain with other methods for an active device. PEM holds the further advantage of being non-invasive and only collects photons emitted by regular FET operation, leaving transistor functionality and the whole chip unaltered.

ABSTRACT. Non destructive failure analysis and defect characterization are necessary steps for every component that is destined to space project. The Infrared Thermography is a non-invasive, contactless technique providing information in defect localization as well as in thermal characterization. The system use in CNES Expertise Laboratory is a DCG ELITE system equipped with an InSb camera that detect IR between 3-5µm. The defect localization could be done in steady state observation, where the Device Under Test (DUT) is observed in nominal condition for hot spot localization. The spatial resolution for the defect heat source localization could be improved with a lock-in mode, also known as phase sensitive modulation thermography. Defected or not, the component can be thermally characterized by time related heat propagation, to visualize the heat origin, and perform real temperature measurement for a thermal map of the DUT. Both defect localization and thermal characterization are possible at board and component level, and their utilization will be illustrated by study case analyses

ABSTRACT. Supercapacitors are used nowadays in an extensive range of battery-powered devices such as GPS/GPRS transceivers, active RFID tags, industrial PDAs, electronic locks, micro medical pumps, digital cameras, mobile phones and others. They are also used in vehicle’s and machine’s sub-systems requiring short but robust powerful current pulses. This covers back-up, delivery and leveling of high peak power as well as storing harvested energy. They are designed to meet high power requirements that cannot be fulfilled by standard batteries. Furthermore, their size and cost is very attractive for industries. However, selecting the right supercapacitor for a specific application remains a real challenge to industry. The specifications of these components only provide limited information about their lifetime for specific stress values. This information is not enough for industries to design a robust product and avoid high field returns. In this paper, we apply the Physics-of-Failure (PoF) methodology for qualification and lifetime assessment of electronic systems [1], to derive PoF models for supercapacitors at different stresses relevant for some industrial applications. It is expected from these models to better understand the performance of supercapacitors at different stresses and to predict accurate lifetime of supercapacitors allowing industry to robustly design their products and avoid high field returns. The PoF methodology is updated using the accelerated life testing based method for qualification of supercapacitors. This method includes a review of the ESR (equivalent serial resistance) and capacitance estimation methods for supercapacitors and their comparison, PoF models and their sensitivities to failure criteria based on ESR and / or capacitance degradation, accuracy of the developed PoF models for predicting the supercapacitors lifetime at the use stress condition. Furthermore, a critical comparison with regards to Electrolytic capacitors PoF models developed in [1], seen the similarities between these models, is carried-out.

ABSTRACT. Accelerated lifetime testing of power semiconductors is time consuming and expensive due to the destructive nature of the tests. Therefore, it makes sense to extract as much data as possible during each test to provide the maximum value from each consumed component. However, traditional power cycling methods typically only monitor a single parameter and stop the test after this parameter reaches a predefined threshold. This leaves little data available for analysis of the aging process, which instead must take place post-failure. In this paper we present a power cycling test setup for SiC MOSFETs that enables real-time measurement and logging of the Semiconductor Die Resistance, Bondwire Resistance, Threshold Voltage, Junction Temperature and Thermal Resistance. This provides ample data in order to view the aging process of the module in real-time and in greater detail, which will hopefully lead to more intelligent design of power cycling tests.

ABSTRACT. This paper presents an experimental technique to characterize the damage evolution of the topside interconnections of power semi-conductor devices during power cycling tests. DC power cycling tests are done on SKIM 63 power modules from Semikron, a solder-free module with silver sintered chips, ensuring the degradations to appear in the top layers only. The cycled substrates are then extracted from the test bench at different steps of the aging for analyse. Four-probe measurements are implemented on the metallization chips of the same cycled substrates so that the evolution of physical parameters representative of the degradation can be obtained. As well, specific measurements and analysis of the bond wire contacts are done to characterize the electrical contacts and to correlate them with physical degradations.

ABSTRACT. The occurrence of critical spots, where carriers’ multiplication occurs due to the local high-electric field can be very detrimental for the robustness and the reliability of power devices, since at these locations catastrophic failure mechanisms like Single Event Burnout can be initiated. Traditional analytical techniques like DC analysis, photoemission microscopy, electron, and optical probing are not the first choice to detect the presence and in particular to locate such critical spots because they either lack in sensitivity, or they suffer from relevant penalties due to the thick metallization layers at the surface of the devices. In recent years, successful attempts have been made by finely focused high-energy ion beams. However, such nuclear probing techniques require advanced complex facilities like particle accelerators, operate under high vacuum conditions, and are not immune to radiation damage effects.

In this paper, we propose the use of planar and collimated alpha sources to assess the presence and to locate critical high-field spots in power semiconductors. It is shown, that the proposed technique just requires basic spectrometry equipment and provides sufficient sensitivity and space resolution to fulfill all analytical requirements

ABSTRACT. We have proposed a failure analysis based on a real-time monitoring of poser devices under acceleration test. The real-time monitoring enables to visualize the mechanism that leads to a failure by obtaining the change of structure inside the device in time domain with high spatial resolution. In this paper, we presented a new analytical instrument based on the proposed failure analysis concept. The essential functions of this instrument are (1) power stress control, (2) non-destructive inspection and (3) water circulation. An original design power-stress control system and a customized scanning acoustic microscopy system enable us a non-destructive inspection inside the device under power cycling test.

ABSTRACT. High voltage IGBT modules are used in high power applications including traction, industrial drives, Grid systems and Renewables such as in wind-power generation and conversion. Many of these applications are subject to harsh environmental conditions and in particular when the inverter cabinets do not shield the power electronics, including the IGBT modules from such conditions. As an example, IGBT modules can be for instance subject to increased humidity levels. Also when the inverter is not always running under full load conditions and can be in idle or running in partial load which means that the temperature can rise or drop relatively fast. Due to that, moisture can penetrate into the IGBT modules during long idle periods of time and there is no high temperature levels to drive out moisture from the modules. Another aspect is that condensation can appear while having a temperature drop during operation, which can lead to drastic changes in the material properties (e.g. dielectric properties of chip passivation and module encapsulation materials such as Si-gel). These undesirable modifications can have a negative impact on the electric field at the periphery of the semiconductor device and therefore cause an increased localized stress at the chip junction termination region. Therefore, it is crucial that the materials used for the IGBT module and the design of the power semiconductor including chip termination and passivation can cope with the increased stress levels.

ABSTRACT. With shrinking feature dimensions in semiconductor devices, the signals measured during device investigation become weaker all the time. While the signals get smaller, they are also exposed to interfering signals and to increasing electronic noise. At this point, failure analysis can take advantage from the strategies employed in advanced physics laboratories in order to boost the signal-to-noise ratio of measurements. Effective signal processing approaches are today performed utilizing fast analog-to-digital converters and field programmable gate arrays (FPGA). Join this presentation if you would like to brush-up your signal processing knowledge that can be employed for failure analysis.

ABSTRACT. The continuous developments in CMOS IC technology towards 7/10nm FINFET EUV devices, the final product reliability qualification approach is impacted too. The introduction of new materials, process steps and smaller geometries lack long term reliability test exposure and results. The behavior of these devices have an individual character with a large deviation in the junction temperature. In order to balance the stress parameters (Tj) for a proper statistical processing of the test lot results, an individual device approach is required. Also the lower core voltages, higher currents and build in test capabilities have to be addressed by the HTOL system. MASER Engineering will present its latest extension of our wide qualification test offerings in Enschede, NL.

ABSTRACT. Semiconductor device feature dimensions have been getting smaller and smaller to meet market demand for faster and more efficient designs every year. To address this challenge, manufacturers must have the capability to fulfil metrology requirements that simultaneously call for enhancements in resolution, accuracy and reliability. Current technological solutions were designed to enable engineers to use Atomic Force Microscopy to acquire accurate and repeatable nanoscale images of target devices for various applications as needed in failure analysis. Here we present the impactful latest developments, which guarantee more throughput, higher accuracy and reliability for topography measurements but also for electrical characterization.

ABSTRACT. TDM® (Topography and Deformation Measurements) system was developed by Insidix to answer new issues of the electronic industries, and permits to characterize deformation of boards, wafer, components and assemblies when they see thermomechanical loads, as those typically imposed during assembly processes or operating conditions (gluing, reflow, aging, etc). A new multi-physical platform for advanced warpage and strain measurement has been launched by Insidix: the TDM Compact 3. It has been designed to meet the new challenges for warpage measurements and includes numerous unique features.

ABSTRACT. Because of the high cost of failure, the reliability performance of capacitors is becoming a more and more important factor in many energy conversion applications. Since temperature is one of the main stressors that leads to the wear-out of capacitors, the impact of uneven thermal loading on the reliability of DC-link capacitors is investigated for a photovoltaic application study-case. According to a generic model-based reliability assessment procedure, a reliability evaluation tool is developed and the lifetime of the capacitor/DC-bank is estimated and benchmarked under even/uneven thermal loading conditions. The outcomes of the analysis indicate that the uneven thermal distribution among DC-link capacitors can have a significant impact on both component and system-level reliability performance.

ABSTRACT. Photovoltaic (PV) systems are employed worldwide and power electronic devices for the PV-grid connection are required to operate under different meteorological conditions, also referred to as mission profiles. Mission profiles vary from locations and they can impact the energy production and the loading on the power converter (thus, the inverter reliability). Another important fact that influence s the inverter lifetime is the PV panel thermal dynamics (i.e., RC thermal network). Thus, this paper presents an evaluation of the lifetime of a grid-connected single-phase PV inverter under meteorological variations (i.e., mission profile variations), considering the PV panel thermal capacitance. A rainflow counting algorithm is applied. The Bayerer’s model and Palmgrem-Miner’s rule are used to calculate the Life Consumption (LC). The results show that the increase in 30% of irradiance generates 33% more energy; however, it increases the LC by four times (i.e., the reliability is degraded). In addition, when considering thermal dynamics, a 30% increase in the ambient temperature reflects in a reduction of more than 10% in the LC, showing that the PV panel thermal capacitance cannot be neglected in the lifetime evaluation of PV inverters.

ABSTRACT. This digest studies the impact of modulation scheme, mission profiles and PV panel types on the reliability of a double-stage single-phase PV inverter. A single-phase double-stage inverter with two boost-based Maximum Power Point Tracker (MPPT) is considered and the reliability of dc/dc stage is estimated under different mission profiles. Furthermore, two types of PV panels with different output characteristics are considered to demonstrate the impact of PV array design on the PV converter reliability. Moreover, a phase shifted-switching scheme for the dc/dc converters and inverter is proposed to improve the overall reliability. The outcome is the PV converter reliability enhancement by both suitable PV panel selection and proposed phase-sifted modulation scheme.

ABSTRACT. The operating condition and reliability of Photovoltaic (PV) inverters are strongly affected by the mission profile. Since the mission profile of the PV system can vary considerably, the time-resolution of the mission profile becomes an important factor in the reliability prediction. In this paper, the impacts of mission profile resolutions on the reliability of the PV inverters are investigated. The results indicate that the mission profile resolution can deviate the reliability prediction considerably during the fluctuating solar irradiance condition.

ABSTRACT. A Converter Monitoring Unit (CMU) which was retrofitted in a multi Mega Watt wind turbine converter is presented. Contrary to previous work, power module characteristics were obtained by the field operation alone, without dedicated calibration routines. Synchronized sampling of semiconductor voltage (vce_on) and semiconductor current (i_c) enables the condition monitoring. A vce_on measurement circuitry for field operation is presented. A novel method of numerical integration of rogowski coil voltage enables current sensing. Data from a whole year of operation show that the presented methods are consistent throughout long term operation, and that both the measurement principles and reference functions (model) are consistent during long time operation. It is thus expected that degradation of power modules and gate drives can be monitored.

ABSTRACT. Gate Oxide Scaling has traditionally been one of the key enablers of performance enhancement from one node to the next. Back in 1999, it was thought that dielectric breakdown would prevent scaling thinner than ~25A.  Model improvement, such as progressive breakdown and power law voltage acceleration, supported scaling below 15A.   Now with replacement metal gate FinFETs, dielectric breakdown is not preventing further scaling, but rather end of life performance loss due to excessive NBTI.  This talk will explore the optimization of gate oxide thickness and end of life performance.

ABSTRACT. In this work, a protection structure for the silicon chip backside is presented, which is a protective TiO2-Ti-TiO2 layer stack with angular dependent reflectivity. It uses a selected p-n junction as light emitter and other junctions as photodetectors of the light reflected in various angles inside the silicon. The measurement of this structure highlights strong angle dependent reflectivity for the light reflected on the backside of the chip. Detecting these photocurrents indicates whether the IC backside is subject to a hardware attack that violates backside layer integrity, like FIB or preparative damage of the layer. By making a pattern of photocurrent ratios when the IC is running can notify the IC if those physical attacks from the backside have occurred. For this protection concept, there is no need to add additional masks or circuitry of the IC, since it could use the drain or source junctions of transistors already available.

ABSTRACT. With the term of “counterfeit electronic components”, we refer to electronic devices that are misrepresented as to their origins or quality. The larger risks of using the counterfeit parts are personal injury, mission failure and dramatic reduction of the reliability of system and apparatus. Reliability issues concerning counterfeit electronics will be considered because the severity of this problem is likely to increase in the near future. Several examples will point out as entire lots of unreliable microelectronic have reached the final users and only incoming lot inspection and screening procedures could have avoided a large amount of field failures. The conclusion is a warning against the lack of reliability culture for end users of microelectronics devices under-evaluating the higher risks due to the low quality and poor reliability of the consumer electronics purchased in the open market sources than from authorized ones

ABSTRACT. Disguising non-authentic electronic parts as otherwise, so called as electronic counterfeiting, continues to inflict significant damages on government, industry, and society. This calls for finding effective ways to identify counterfeits. The current approaches involve acquisition of 2D and 3D images of the alleged part using a spectrum of microscopy tools, followed by having them assessed by a group of subject matter experts. This approach, nevertheless, entails two important shortcomings. First, the intensive computations needed for visualization, processing, and analysis of the large microscopy data is not affordable by all. Second, due to lack of an objective measure for most classes of counterfeit, many defects are overlooked and even in some cases, they are falsely identified. Our proposed solution provides a collaborative platform to acquire assessments from a larger group of experts, towards forming a collective insight and minimizing defect overlooking. Our first-of-its-kind web-based crowdsourcing platform can be leveraged for 3D visualization of microscopy data without imposing any computational load on the users, as well as collaborative analysis by collecting information from each user. Further, the collected information is compiled in a databank, which serves as a valuable source for developing quantified measures and for training automated defect classification algorithms.

ABSTRACT. In this paper a new methodology is proposed to investigate variability and reliability correlated with self-heating effect (SHE) in digital circuits during random operation. In this methodology, the arbitrary power waveform (APW) self-heating model is applied to carry out self-heating evaluation with the input sequences generated by the power waveform generator (PWG). Based on the proposed method, self-heating induced variability and HCI degradation in Nanosheet-FETs based SRAM are investigated. The results show it is essential to take the self-heating variation into account for circuit design and reliability prediction.

ABSTRACT. In order to obtain lower harmonics distortion and higher power factors, single-phase pulse-width modulation (PWM) rectifiers are adopted in AC railway drive systems. Therefore, its reliability is of most importance with regards to the safe operation of the train. In this paper, a fault diagnosis method for open switch fault in single-phase PWM rectifier is proposed based on the switching system theory. It requires no additional sensor, nor extra operation states need to be set. Four observers which correspond to four kinds of open switch faults are utilized to detect and locate the faults. Real-time simulations are carried out to validate the effectiveness of this method.

ABSTRACT. Typical high-current power modules used in traction and wind generation contain several dies in parallel. Non-ideal geometries and electrical parameter variations cause an unequal aging of each die which limits the effectiveness of using parallel devices. This paper presents an intelligent power module with junction temperature measurement and equilibration. It uses a TSEP-based method to estimate the junction temperature which is employed for stress-steering and the extends the lifetime. Automotive drive cycles are used to estimate the lifetime gain. This estimation makes use of a thermal transfer function deduced from experimental results. The lifetime is estimated using a stress-counting rainflow algorithm, a linear damage accumulation rule and a pre-determined damage law. Finally, 100 drive cycles, including the legislatives drive cycles, are simulated with the thermal model. A gain of up to two times in the lifetime can be expected with the temperature equalisation method. Therefore, the initial investment on the developed intelligent power module is justified by the benefit of the large gain in lifetime and of the monitoring functions.

ABSTRACT. During the last years applications for power modules with harsh environmental conditions have gained increasing importance. Static humidity tests with T=85°C and RH=85% with high voltage have established as basic testing method for the humidity robustness of semiconductor power modules. The present work is showing the improvement of humidity robustness with respect to the established test methods. Electrical performance monitoring and analytic approaches to prove the results with respect to established work on the field of humidity testing.

ABSTRACT. In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175°C and 24V, respectively, are adopted in order to accelerate the degradation in the device. Moreover, a recovery study is performed in order to understand if the degradation induced by HTGB can be reduced.

ABSTRACT. SELA continues to deliver best in the industry cleaving solutions for the cross-sectioning of the crystalline materials. New smart cleaving set of the MC20 provides capability of the wining micro-cleaving technology for cleaving of visible and buried targets, observation and cross-sectioning from the top and bottom of the wafer samples and dies in front end and back end failure analysis.

ABSTRACT. The presentation will be divided into two parts: For the first part, I will introduce MSSCORPS (MSS in short). MSS is a service lab based in Hsinchu, Taiwan. Its high-quality material analysis (MA) is now at the leading position in the world. In order to demonstrate its MA capability, the second part of the presentation, two most advanced CPU chips from iPhone (A11) and Samsung (Exynos8895) were used. The fabrication technology for these two chips is 10 nm, where A11 was fabricated by tsmc and Exynos8895 was by Samsung. With the help of high spatial resolution transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS), details of processes can be clearly unveiled and analyzed. Exynos8895 has a higher fin height and broader fin width, A11, on the other hand, has shorter fin pitch and thinner interconnection thickness. More detailed differences between these two chips will be presented.

ABSTRACT. Mitsubishi Electric has started development of SiC devices in early 1990s’. Since then, we have done several research works both in SiC modules and inverters, and launched world-first SiC-equipped Air conditioner in 2010, solar power conditioner in 2011, Railway converters in 2013, etc. This presentation reviews our typical system examples, together with high-performance SiC power modules and SiC MOSFET technology that has been used in these works. There are many tradeoffs to realize the high-performance modules, and these tradeoffs will also be addressed. Finally future performance enhancement such as trench MOSFET and SBD-embedded MOSFET will be discussed.

ABSTRACT. With the replacement of conventional gate dielectric SiO2 with high-κ materials, new challenges emerge on understanding the kinetics of dielectric breakdown due to the dual role of the bulk oxide and the interfacial layer with the substrate and the gate electrode. Among several complexities, dielectric relaxation and recovery have received a lot of attention due to their promising applications in RRAM. In this study, we explore the stochastic nature of hard breakdown recovery in HfO2, taking advantage of ramp voltage stress (RVS) measurements, which are theoretically equivalent to the widely used constant voltage stress (CVS), while being significantly less time-consuming. We found that the possibility of recovery is largely dependent on the ramp rate during RVS as the dielectric needs adequate time and sufficient thermal budget to recover. The clustering model is found to be a good fit to the RVS data sets for post-recovery subsequent breakdown events and the extent of defect clustering is found to be more severe after increasing number of recovery events. The breakdown mechanism in the stack is confirmed by measuring resistance change with temperature.

ABSTRACT. Because of the atomic nature of the system under study, an estimation of the temperature of the conductive filament (CF) in OxRAM devices as a function of the applied bias can only be obtained by means of indirect methods, usually electrothermal simulations. In this paper, a heuristic approach that combines time-dependent dielectric breakdown (TDDB) statistics for the already electroformed device with field and temperature-assisted ionic transport within the framework of escape rate theory is presented. Extended expressions for the exponential time-to-failure acceleration law and for the Kramers’ rate compatible with the standard models at moderate/high biases and with the principle of detailed balance at equilibrium are proposed. Approximate expressions for the CF temperature are also reported. For the investigated stress voltages (0.30V-0.65V), the estimated CF temperature at the SET condition is found to be in the range 350K-600K.

ABSTRACT. Established reliability test procedures from Si can widely be applied to SiC, however there are some differences and special challenges. A new test procedure for the gate oxide reliability is suggested,  it leads to evaluable results within a reasonable time. Temperature-sensitive electrical parameters (TSEPs), which are necessary for power cycling tests, are investigated. For the SiC MOSFET and the GaN GIT, possible TSEPs are compared and applied to power cycling tests. GaN-based devices have further issues regarding reliability, like charge trapping, dynamic R_on, and degradation effects. The test matrix from Si is not sufficient to cover the reliability requirements for GaN.

ABSTRACT. Threshold voltage shifts associated with NBT (Negative Bias Temperature) instability in power VDMOSFETs under the static and pulsed stress conditions are analyzed in terms of the effects on device lifetime. For that purpose, the method suitable for performing fast NBT instability measurements on power VDMOSFETs is proposed, and its practical implementation using simple boosting circuit for obtaining required gate stress voltage, and sweep I-V measurements for the threshold voltage shift determination will be presented. Experimental results will be discussed in terms of time necessary to perform interim measurements during NBT stress tests, and it will be shown that the measurements could be done fast enough to intercept dynamic recovery effect in these devices. It should be emphasized that the pulsed bias stressing is found to cause less significant threshold voltage shifts in comparison with those caused by the static stressing.. Accordingly, pulsed gate bias conditions provide much longer device lifetime than the static ones, which is shown by individual use of the 1/VG and 1/T models for extrapolation to normal operation voltage and temperature, as well as by combined use of both models for a double extrapolation successively along both voltage and temperature axes. A double extrapolation approach is shown to allow for construction of the surface area representing the lifetime values corresponding to a full range of device operating voltages and temperatures. The results of consecutive irradiation and NBT stress experiments performed on power VDMOSFETs will be also presented. It is shown that irradiation of previously NBT stressed devices leads to further increase of threshold voltage shift, while NBT stress effects in previously irradiated devices may depend on gate bias applied during irradiation and on the total dose received. In the case of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the case of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have positive role as it practically anneals a part of radiation-induced degradation.

ABSTRACT. In this work, trade-offs between performance and reliability in CMOS RF power amplifiers at the design stage are studied. The impact of transistor sizing, amplifier class and on-chip matching network design are explored for a 130nm technology and the implications of design decisions in transistor gate oxide reliability are discussed and projected. A strong trade-off is observed between efficiency and reliability, mainly for different on-chip output matching architectures. A comparison between two example designs is performed via SPICE simulations including reliability models and the effects of aging on the stress conditions of each amplifier are assessed.

ABSTRACT. A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. The application with the proposed surge-to-digital converter can improve the surge protection capability of microelectronic systems to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors. The proposed surge-to-digital converter has been verified in a 0.18-µm CMOS process.

ABSTRACT. This paper presents an analysis of the reliability of 20nm technology NAND Flash memory components based on Multiple Level Cells (MLC). The focus of the study is to assess the influence of temperature during programming, storage and reading operations. In order to reach this goal, several memories were programmed once at many temperatures from -40°C to 85°C, then they have been stored powered off in one case and have been activated in reading in the other case, under different thermal stresses.

ABSTRACT. Common problems with Oxide-based Resistive RAM are related to high variability in operating conditions and high programming currents during FORMING, SET and RESET operations. Although research has taken steps to resolve these issues, variability combined with high programming currents remains an important characteristic for RRAMs. In a conventional write scheme with fixed duration and amplitude, the programming current is not controlled, which degrades the cell performance (power consumption and variability) due to over-programming. In this paper, a self-adaptive write driver is proposed to control the write current. A feedback mechanism based on current comparison is used to switch off the write stimulus as soon as the preferred write current is reached. Compared to conventional write schemes, in the proposed write-assist circuit, the write energy per bit is reduced by 27% and the standard deviation of post-FORMING distributions is reduced by 57%.

ABSTRACT. In industrial, aerospace, medical and other mission critical electronics employing high density interconnection PCBs, high DC voltage gradient and adverse environmental conditions facilitate Conductive Anodic Filament (CAF) formation. To prevent catastrophic failures caused by CAF short circuits, monitoring of manufacturing process and proper laminate selection is essential. The purpose of presented work was to evaluate CAF resistance level of FR4, low CTE, CAF resistant and BT/epoxy-based laminates. Test coupons comprising 90 potential hole-hole failure points with 250µm spacing were fabricated and subjected to accelerated CAF test for 600 h in 85C, 87% RH. Surface insulation resistance measurements were performed to monitor coupons’ condition. Time to failure of examined samples, microscopic inspection results and failure root-cause analysis are presented.

ABSTRACT. The results of the recovery of hot-carrier degraded nMOSFETs by annealing in a nitrogen ambient are presentend in this article. The recovery rate is investigated as a function of the annealing temperature, where the recovery for increasing temperatures is in agreement with the passivation processes. At the original post-metal anneal temperature of T = 400 C, the devices original performance is fully restored. Higher temperatures induce a permanent, unrecoverable change to the devices, manifested in a gradual VT shift. The recovery rate is found to be independent of both the transistor gate length and the cooling rate upon annealing. These findings are used to gain further understanding of the mechanisms behind hot carrier damage recovery.

ABSTRACT. The study of physical mechanisms that occur during Flash memory cell life is today mandatory to approach the 40nm and beyond technological nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both the drain and bulk currents are measured and monitored toward the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with the equivalent transistor one. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

ABSTRACT. Many wafer manufacturing processes use plasma or other charge-based effects. The resulting currents can damage or destroy MOS gate oxides of transistors in products. This plasma induced damage (PID) can be in form of a reduction of the required lifetime of the devices, which can result in systematic early product failures in the field. PID damage and the resulting reliability reduction can be invisible in zero hour parameter and product tests, which can make it particularly dangerous. Products have to be made robust against PID by antenna design rules determined during technology development and verified in qualification measurements. To prevent early product fails due to unnoticed process excursions, fast wafer level reliability (fWLR) monitoring on the fully processed product wafer is required. The performance of PID fWLR on suitable test structures and the application of the fast diagnostic stresses will be presented. Details on options for data analysis for fast, sensitive and precise process excursion detection with a low risk of false alarms will be discussed in this paper. For some excursions detected by the fast diagnostic stresses the effect on the device lifetimes will be analyzed with long term MOS device stresses.

ABSTRACT. VTH subthreshold hysteresis measured in commercially available 4H-SiC MOSFET is more pronounced in trench than in planar devices. All planar devices from different manufacturers exhibit an inverse temperature dependence, with the hysteresis amplitude reducing as the temperature increases, whereas all trench devices from different manufacturers exhibit the opposite behaviour. In the final paper, a physical interpretation will be proposed, based on experimental evidence, which demonstrates that temperature dependence of the VTH subthreshold hysteresis is related to the structure of the device. The findings are relevant to the ongoing discussion on SiC bespoke validation standards development and contribute important new insight.

ABSTRACT. This paper presents an extensive analysis of the impact of substrate and buffer properties on the performance and breakdown voltage of E-mode power HEMT. We investigated the impact of buffer thickness, substrate resistivity and substrate miscut angle, by characterizing several wafers by means of DC and pulsed measurement. The results demonstrate that: (i) the resistivity of the silicon substrate strongly impacts on the breakdown voltage and vertical leakage current. In fact, highly resistive substrates may partly deplete under high vertical bias, thus limiting the total potential drop on the epitaxial layers. As a consequence, the vertical I-V plots show a “plateau”, that limits the vertical leakage. (ii) the depletion of the substrate may worsen the dynamic performance of the devices, due to an enhancement of buffer trapping . (iii) Larger buffer thickness results in an increased robustness of the vertical stack, due to the thicker insulating region. (iv) the miscut angle (0 °, 0.5 °, and 1 °) can significantly impact on both threshold voltage and the 2DEG density; devices with miscut substrate have higher current density. On the other hand, the dynamic on-resistance variation is comparable in the three cases.

ABSTRACT. GaN-on-GaN vertical devices are expected to find wide application in power electronics, thanks to the high current densities, the low on-resistance and the high breakdown voltage. So far, only few papers on the reliability of GaN-on-GaN vertical devices have been published in the literature. This paper investigates the degradation of GaN-on-GaN pn diodes submitted to stress at high current density. The study was carried out by means of electrical characterization and electroluminescence (EL) measurements. We demonstrate that: (i) when submitted to stress at high current density, the devices show significant changes in the electrical characteristics: an increase in on-resistance/turn-on voltage, an increase in the generation/recombination components, the creation of shunt-paths. (ii) the increase in on-resistance is strongly correlated to the decrease in the EL signal emitted by the diodes. (iii) the degradation kinetics have a square-root dependence on time, indicative of a diffusion process. The results are interpreted by considering that stress induces a diffusion of hydrogen from the highly-p-type doped surface towards the pn junction. This results in a decrease in hole concentration, due to the creation of Mg-H bonds, and in a lower hole injection. As a consequence, on-resistance increases while EL signal shows a correlated decrease.

ABSTRACT. The ability to monitor temperature variations during the actual operation of power modules is key to reliability investigations and the development of lifetime prediction strategies. This paper proposes an original solution, specifically devised with novel fast-switching silicon carbide (SiC) power MOSFETs in mind. The results show ability to track temperature variations resulting from active power cycling of the devices, including high speed transients, thus enabling to discriminate among different potential failure mechanisms. Validation of the proposed methodology and its accuracy is carried out with the support of infrared thermography.

ABSTRACT. This paper presents the impact of the short-circuit stress in SiC MOSFETs on the field-oxide gate reliability, which becomes more critical with increased junction temperature. The results show that two degradation mechanisms take place: (a) gate-leakage current increase and (b) drain-leakage current increase. A failure analysis has been performed on the degraded SiC MOSFET to find possible defects. The damage location has been identified through Focused Ion Beam micro-sectioning and the defects have been correlated with the increase in gate-leakage current and drain-leakage current.

ABSTRACT. Scribeless cleaving method for glass, sapphire, III-V, SiC and even cleaves freestanding structures deposited by e-beam lithography and silicon down to 1-mm. Surface touchless scribing tool to protect frontside features, ideal for compound substrates and off-crystalline cleaving. Nanofab cleanroom compatible.

ABSTRACT. ULTRA TEC will describe new measurement and alignment improvements available for selected area preparation techniques --- in particular the use of ‘In situ’ Remaining Silicon Thickness (RST) Measurement along with the ability to OVERLAY X-RAY and C-SAM images with live alignment coordinates. Upgrades to the user interface on our ASAP-1 IPS product will be described and how these techniques further assist in ensuring the highest quality sample preparation results.

ABSTRACT. For the first time, ultrafast AC pBTI measurements are applied to GaN on Si E-mode MOSc-HEMT and compared to DC pBTI. Full recess Al₂O₃ /GaN MOS gate is submitted to AC signals with various frequencies, duty factors and stress times. The degradation and relaxation characteristics are then modeled through a RC model combined to a CET map and fitted to experimental data. This map reveals the presence of two trap populations, also observed through ΔVth degradation kinetics. Acceleration factors (gate voltage and temperature) are estimated as well as TTF (Time to Failure) under AC conditions and show an extended lifetime compared to DC stress conditions. Finally dynamic variability is studied and indicates that our devices are ruled by normal distributions.

ABSTRACT. PN-junction diodes with different breakdown voltages have been subjected to surge pulses per the standard IEC 61000-4-5 and their transient behaviour has been studied. For medium breakdown voltages (20-40V) at high surge currents large transient oscillations in the voltage drop across the diodes are observed. After such an event the devices are still operational. 3D electro-thermal TCAD simulations have been done to understand the phenomenon. A comparison between measurement and simulation reveals that the periodic voltage drop is caused by non-destructive second breakdown.

ABSTRACT. Ionizing radiation and electromagnetic interference (EMI) can cause single event upset (SEU) in memory elements. This threat is one of the major concerns when considering the design of electronic systems for critical applications. Single Error Correction - Double Error Detection (SEC-DED) codes can be used to avoid data corruption caused by soft errors, protecting the memory against single errors. However, the presence of multiplebit upsets are becoming more frequent as technology scales down. Hereafter, we present an Error Detection and Correction (EDAC) approach, namely Parity per Byte and Duplication (PBD), to protect data stored in memory. The technique was implemented and validated in VHDL. The obtained results have shown that the proposed approach is very effective to detect and correct multiple bit-flips in memory arrays.

ABSTRACT. The purpose of this paper is to present a complete experimentation of the two failure modes in competition that can appear during short-circuit (SC) fault operation of single-chip 1,2kV SiC MOSFETs from different manufacturers including planar and trench-gate structures, well-known or recent devices. Ruggedness and selective failure modes are identified in relation with the power density applied on the chip and the simulated 1D-thermal junction. Finally, the chips of the components which failed in a “fail-to-open” mode have been studied in order to find the physical reason of this original and unusual fail-safe mode.

ABSTRACT. This paper proposes a evaluating method of power device condition based on the operating-waveform analysis. The proposed method measures and analyzes operating waveforms in a practical power converter. The analytic result exhibits power device condition under the operating condition. This paper also evaluated the power device reliability under the initial charge method using a short-circuit by using the proposed evaluating method. A reliability test of MOSFETs repeats the initial charge more than 10000 cycles and reveals that the initial charge method is applicable up to 150 cycles without any damage and difficult to apply after 1000-2000 cycles. The proposed evaluating method can achieve non-destructive evaluation under the operating condition and detect transition of the condition.

ABSTRACT. Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterised by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. This paper will also investigate the impact of uneven BTI-induced threshold voltage shift in parallel connected devices. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices.

ABSTRACT. The impact of electron injection from the substrate on the dynamic Ron of GaN-on-Si High Electron Mobility Transistors (HEMTs) has been investigated by means of back-bias transient and vertical leakage measurements and TCAD simulations. A strict correlation between electrons injected from the substrate and on-state drain current transients is demonstrated. Moreover, the contribution to the dynamic Ron of electron-type traps as opposed to hole-like traps is discussed making a case for their impact with different magnitude of substrate leakage current. A TCAD model has been developed and calibrated to both off-state vertical leakage and on-state drain current transient experimental results. The proposed charge dynamic has also been assessed against state-of-the-art theories. This analysis contributes to a deeper understanding of the complex scenario of different types of traps in the buffer layer of GaN-on-Si devices and highlights the impact that trap-states can have on on-state and off-state currents depending on the magnitude of the substrate leakage and therefore on different technologies.

ABSTRACT. This paper reports on the degradation processes of heterogeneous III-V/Silicon loop-mirrors laser-diodes designed as the optical sources for next-generation Photonic Integrated Circuits (PICs) operating at 1.55 µm. By submitting the devices to a series of constant-current accelerated aging experiments we were able to identify a common set of degradation mechanisms, including: (i) an increase in threshold current, (ii) a decrease of the sub-threshold emission, (iii) a decrease in the operating voltage of the device and (iv) a small decrease in the slope-efficiency of the laser. The strong correlation between these degradation processes suggests that the loss in optical performance experienced by the devices can be attributed to a decrease in the non-radiative carrier lifetime, as a consequence of the generation/propagation of defects towards the active region of the laser diodes.

ABSTRACT. We present the first comprehensive study of the degradation of 16mW state of the art UVC LEDs emitting at 280 nm. The study, based on combined electrical and spectral characterization, allows to identify different degradation regimes and mechanisms, and to formulate hypotheses on their origin.

ABSTRACT. A modified Hakki-Paoli method, for measuring optical gain in laser diodes, proposed at the past ESREF 2017 conference is here further improved in terms of practical implementation. In particular, averaging both the spectral function and its reciprocal, over an oscillation cycle is shown to lead to the gain function replacing the calculation of maxima and minima, a cumbersome task for noisy spectra at low injection level. The ultimate goal is to get rid of the many constraints that complicate gain measurements for other than the manufacturers, and to provide a new powerful tool for laser diode characterization and diagnostics.

ABSTRACT. The aim of this paper is to illustrate the dependence of DLTS characteristics and degradation of InGaN-based laser diodes (LDs) on the density of dislocations. Three groups of multi-quantum well LDs with different dislocation densities were submitted to constant current stress, at room temperature: the analysis is based on combined electrical-optical measurements and Deep-Level Transient Spectroscopy (DLTS) investigation was made before and after stress. DLTS results show the presence of a hole trap in all the samples, whose intensity is related to the dislocation density. Constant current stress induces a significant decrease in the optical power (subthreshold regime), not related exclusively to the dislocation density, and the appearance of a new deep level for electrons (point defect generated after stress).

ABSTRACT. Gaussian process regression (GPR) is a machine learning technique than can be used for both regression and classification purpose. In the GPR framework, a probability measure is defined according to one prior belief about the responses surface and the Bayesian rule is applied to combine the observations with prior beliefs to form a posterior distribution of the response surface, which is known as the surrogate model. Self-assembled nanostructures are increasingly used for nanoelectronic and optoelectronic applications due to their high surface area to volume ratio and their ability to break traditional lithography limits. However, they suffer due to poor yield and repeatability as the growth process is often not well studied or optimized. We propose here the use of GPR as an effective statistical tool to optimize the growth conditions of nanostructures so as to improve their yield, controllability and repeatability ensuring at the same time that the yield is not affected by process variations at the identified optimum process conditions. In effect, we are proposing a design for reliability and robust design strategy for optimization of self-assembled nanostructure growth. We use a case study of Cadmium Selenide nanostructures with an extensive design of experiment to illustrate the proposed methodology. The prediction accuracy of GPR is compared with two other commonly used statistical models → binomial and multinomial logistic regression.

ABSTRACT. Light-emitting diodes (LEDs) are widely used nowadays thanks to their high efficiency, environmental resilience, high reliability and long lifetime. Given their rampant use, there is a need to quickly qualify them and predict the remaining useful life of these devices. For LED lifetime prediction, filter-based prognostics techniques are normally used. Although, they are in general very effective, the main drawback they have is the need for a specific state-space model that describes the degradation. In many cases, LED degradation trends are affected by many unknown factors such as unidentified failure modes, unmeasured operational conditions, engineering variance, and environmental fluctuations. These unknown factors will complicate the selection of a suitable state-space model and in some cases; there may not be a single model that could be used for the entire lifespan of the device. If the degradation patterns of LEDs under test deviate from the state space models, the resulting predictions will be very inaccurate. This paper introduces a prognostics-based qualification method using a multi-output Gaussian process regression (MO-GPR). The main idea here is to use MO-GPR to learn the correlation between similar degradation patterns from multiple similar components under test or use to learn the degradation pattern evolution and thereby, bypass the need for a specific state space model using available data of past units that failed (for which sensor data has been collected).

ABSTRACT. Power consumption and reliability are nowadays the main concerns for nanoelectronic systems. In fact, these factors are closely related, the robustness of a system is strongly associated with its power supply voltage (Vdd), frequency, and body biasing. Therefore, power management and fault tolerance techniques need to be jointly implemented to guarantee better overall low-consuming and reliable solutions. This paper presents a novel body built-in cell to address these two issues. It is capable of: 1) detecting short-duration and long-duration TFs, thus enhancing robustness of system; 2) controlling the circuit’s threshold voltage (Vth), thus compensating alterations induced by aging or PVT variations; 3) optimizing the system’s trade-off between low-power and high performance through the implementation of adaptive body biasing (ABB) schemes.

ABSTRACT. The aggressive technology and voltage scaling which modern digital circuits are facing introduces a higher influence in metrics, as performance and energy consumption, due to process variability. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works points that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 13.5% and 24.7% improvement in average delay and energy variability robustness, respectively.

ABSTRACT. This paper evaluates a set of complex cells with different transistor arrangements that implement the same logic function. These cells were evaluated under nominal conditions and with gate variability at layout level. The purpose is to verify what topology is more appropriate to increase the robustness of cells regarding process variability. Results emphasize the importance of investigating the effects caused by process variability in FinFET technologies, as the electrical characteristics of circuits suffer significant changes. In general, the best choice is to use the network that the transistor in series is as far as possible to the output node. However, the main disadvantage is the penalties regarding performance and power consumption.

ABSTRACT. The reliability of Insulated Gate Bipolar Transistor (IGBT) has drawn much attention in recent years. On-line IGBT monitoring can be given before the module failure warning signal is to improve the reliability of IGBT operation is an effective means. The current IGBT on-line moni-toring are based on thermoelectric parameter extraction method, but the thermal conductivity of such methods is difficult to extract in the actual circuit. Based on the on-line monitoring of the traditional thermoelectric parameters based on the on-line voltage drop, a sin-gle-input-single-output neural network with IGBT on-resistance and easy measurement of DC voltage and output current in the circuit is estab-lished. Output neural network. Predict IGBT on-resistance by inputting circuit measurement into neural network. Simulations verify that the two neural network models established in this paper satisfy the accuracy requirements.

ABSTRACT. With scaling into sub-10nm technologies, many reliability concerns become both more severe and more variable between nominally identical transistors. Standard assessment techniques provide only limited information regarding individual transistors or face challenges in yielding representative results. In this paper we demonstrate bias temperature instability measurements with the Hyperion II Atomic Force Nanoprober system on several transistor geometries in 14nm finFET technology. We establish that this approach yields results in line with behaviour described in the literature and discuss the possibility of implementing a broad suite of reliability tests through nanoprobing. It is demonstrated that nanoprobing with sufficient probe stability can provide a direct method for assessing field effect degradation on individual transistors in-place within integrated circuit subsystems.

ABSTRACT. The IGBT power modules are widely used in photovoltaic power generation, high-voltage direct current transmission and other fields. Due to the need for high reliability in the application fields, the industry is very concerned about the reliability of IGBT power modules. Based on the two different working conditions of the three-level NPC photovoltaic inverter, this paper has monitored the health status of bonding wires of the IGBT modules inside the inverter. In addition, for the experimental results of monitoring, theoretical analysis and experimental demonstration from the perspective of multi-physics (temperature field, electromagnetic field, etc.) are innovatively introduced, which provides a new perspective for the research of power module reliability.

ABSTRACT. Analog to Digital Converter (ADC) is a necessary component of mixed signal designs. It converts the analog signal to the digital signal and is used as a bridge. This paper proposes R-Flash ADC (Reliable Flash ADC) which combines an area efficient multiplexer pass gate (MPG) encoding technique and low power ITIQ (Improved Threshold Inverter Quantization) comparator. The proposed Flash ADC is implemented using tanner EDA with 125nm technology. R-Flash ADC reduces the number of transistors by 39% and reduces the power consumption by 59% with high resolution quality. The reliability analysis shows that the proposed R-Flash ADC improves the reliability as 92%.

ABSTRACT. Quality variations in manufacturing are significant factors for product's reliability. In this paper, a manu-facturing process-based storage degradation modelling and reliability assessment approach is proposed to describe the uncertainty of product's storage degradation path caused by manufacturing process. Firstly, a storage degradation model of the output characteristic is constructed, by combining the functional rela-tionship between output characteristic and bottom level performance (BLP for short, such as dimension, mechanical properties, material properties, etc.) with the storage degradation mechanism of products. This model is able to reflect the unit-to-unit variability of batch products. Secondly, based on finite element simulation and approximate modelling method, the unit-to-unit variability caused by manufacturing pro-cess is analysed, and the distribution characteristics of the random effect parameters (REPs) of the model are calculated accordingly. Finally, the storage reliability of the batch products are estimated based on the model and the calculated distribution characteristics of REPs. A case study of the aerospace relay is car-ried out to illustrate the effectiveness of the proposed approach.

ABSTRACT. Over the last few years many architectures of body or bulk built-in current sensors (BBICSs) have been proposed to detect transient faults (TFs) in integrated circuits, all of them assessed through simulations in which only single TFs affect the circuit under run-time test. This work assesses and demonstrates the ability of a BBICS architecture in also detecting multiple and simultaneous TFs. Based on the classical double-exponential transient current model, multiple fault effects on a case-study circuit have been simulated with the injection of several current sources approximately representing the Gaussian distribution of a laser beam attack. Results show the BBICS architecture is able to detect multiple TFs simultaneously perturbing sensitive nodes of the case-study circuit.

ABSTRACT. The present work investigated the corrosion reliability of five Sn-Ag-Cu (SAC) based lead-free solder alloys. The microstructural and phase analysis of solder alloys has been carried out using the scanning electron microscope (SEM), energy dispersive spectroscopy (EDS), and X-ray diffraction (XRD) methods. With the potentiostatic technique, the galvanic corrosion has been confirmed between cathodically active Bi phase and anodic (Sn, Sb) solid solution in InnoLot alloy, while the Ag3Sn phase was cathodically active in the other four alloys. ECM susceptibility of five lead-free solder alloys has been carried out by water droplet (WD) tests on pure alloy ingot samples, and by accelerated humidity/temperature cycling tests on soldered surface insulation resistance (SIR) comb pattern. A ranking of susceptibility for five alloys has been confirmed by Weibull analysis (63.2% failure rate), leakage current level, and charge transfer over time.

ABSTRACT. The influence of DC and AC stress on leakage current Ileak of cell capacitor was analyzed. Experimental results indicated that Ileak increased due to the increase of trap-assisted emission electron when DC stress was applied to cell capacitor, and that increased due to formation of tunneling path in dielectric when AC stress was applied. At stress voltage VD1 ≥ 2.1 V, lifetime under AC stress was much worse that under DC stress, but the guaranteed voltage under AC stress at 10 years was extracted twice as large as that under DC stress due to the difference of acceleration constant factor between DC and AC. As these results, the increase of Ileak under DC stress should be considered more important than that of AC stress for estimation lifetime of cell capacitor in operating condition.

ABSTRACT. This paper proposes a fast and accurate method to extract parameters of the power law for nano-scale SiON pMOSFETs under negative bias temperature instability (NBTI), which is useful for an accurate estimation of NBTI lifetime. Experimental results show that an accurate extraction of the time exponent n of power law was obstructed by either fast trapping of minority carriers or damage recovery during measurement of threshold voltage Vth. These obstructing effects were eliminated using ΔVths obtained from fast and slow measurement-stress-measurement (MSM) procedures. The experimental SiON pMOSFETs had n ≈ 1/4, an activation energy Ea = 0.04 eV for the fast recoverable degradation, and Ea = 0.2 eV for the slow permanent degradation. Based on these experimental observations, a method to estimate NBTI lifetime is proposed; this method can estimate lifetime accurately.

ABSTRACT. A new multitime programmable (MTP) non-volatile memory (NVM) cell using high-voltage NMOS is proposed. A PMOS transistor is used for programming, erasing, and reading, and a high-voltage NMOS is used for selecting the memory cell. The memory cell is with fewer number of transistors and terminals compared with the typical conventional memory cell. These reduce the area consumption and simplify the memory external circuit implementation. In addition, the subthreshold slope (SS) of the memory cell is improved for larger coupling ratio. Experiment investigation on transfer characteristics, endurance, retention, and threshold voltage VTH shift and leakage current of the high-voltage NMOS of the memory cell are presented.

ABSTRACT. Semiconductor industry is exploring technology scaling to pursuit the Moore's Law. The actual processors operation frequency grows need for fast memories. Nowadays, SRAM occupy a considerable area in VLSI designs. This performance improvement achieved at each new technology node is followed by several negative aspects. In this context, this work presents an analysis of PVT variability, aging and SEU on 6T SRAM cell in bulk CMOS and FinFET designs. These effects are observed in delay, power consumption and static noise margins of 6T cell. Results showed that power consumption can easily increase over 100% under process variability. RSNM can present a deviation about 20% under process variability and reduce dramatically cell robustness at worst cases. FinFET technology and HP models are more robust against radiation. In other hand, the LP models are more sensitive to delay degradation due to aging effects.

ABSTRACT. A method to measure the threshold voltage degradation ΔVth along the channel direction due to electrical stress is proposed. This method uses ΔVths measured after electrical stress at different drain bias Vds, and calculated the depletion length Ldep into the channel for each condition under which ΔVth is measured. By substituting the measured ΔVth and calculated Ldep into the proposed equation, the amount of degradation generated in each region of the MOSFET channel can be calculated. The degradation profiles extracted by the new method show well-defined trends with stress conditions.

ABSTRACT. With the dramatic development of microelectronics technology, System-in-Package (SiP) becomes a brand-new direction for the More than Moore’s law. In order to satisfy the demand of small-size, multi-function and high-performance, complex structures and variable materials are applied in SiPs, which introduce many reliability problems. To implement reliability qualification and health assessment, a life prediction methodology of SiP based on physics-of-failure (PoF) is studied in conjunction with simplified life cycle profile. In this paper, typical structures of SiPs, such as dies, components, interconnects are evaluated. And related PoF mechanisms, such as time dependent dielectric breakdown, die metallization electro-migration, die attach fatigue, thermal cyclic fa-tigue and etc. are considered. The inputs of the methodology contain hardware information and lifecycle profile. The hardware information of SiPs includes materials types and structures size. Lifecycle profile provides environmental conditions that the SiPs should experience. Based on these inputs, thermal distributions and stress-strain distributions of the SiP are analyzed by finite element analysis (FEA) tools. With the utilization of PoF models, lifetime matrix of the SiP is obtained. The output of the methodology is the life-time matrix to predict lifetime of the SiP. Finally, a case study is done to guide engineering applications.

ABSTRACT. This paper investigates the effect of OFF-state stress occurring at nMOSFET in a SWD circuit under DRAM operating conditions. We found that the increase in the number of OFF-carriers by the OFF-state stress caused significant decrease in ON-current ION. During the initial period, the OFF-state stress generated the positive oxide charges (Qox) and interface traps (Nit), which caused the increased in Ioff and decrease in Ion. After the degradations were saturated, both of the Ion and Ioff decreased due to the increase in the number of OFF carriers. The OFF-state degradation increased with decreasing source voltage, channel doping concentration, and channel length. Furthemore, the sensitivity of OFF-state degradation to body bias Vb increased with scaling the oxide thickness Tox. This new observations suggest that the OFF-state degradation of core transistors can impose a significant limitation on the SWD circuit design in DRAM such as scaling of dimension and determination of word-line voltage.

ABSTRACT. With the fast development of microgrids in more electric aircrafts and ships, the higher reliability of signal acquisition and processing systems are required in the complex electromagnetic environment. This digest presents a novel easy-implemented nonlinear filter to record data accurately and reliably extract in the case of the complex electromagnetic environment. Based on the arithmetic of the signal confidence, the proposed filter determines the comprehensive influence of the deflected amplitude and deflected time. In addition, the filter is implemented based on the fuzzy control. The convictive signal characteristics can be retained, and the noises will be eliminated. The experimental results show that, the reliability and timeliness of the signal can be guaranteed in the complex electromagnetic environment. More in-depth analysis will be provided in the final paper.

ABSTRACT. This work investigates the relation of the two destruction modes, the so-called energy destruction and the current destruction, during short-circuit operation of an Insulated Gate Bipolar Transistor (IGBT). The critical energy as a function of the short circuit current reveals a kink indicating the transition between two different failure modes. The failure signatures show that energy destruction takes place for lower currents and current destruction at higher currents. This supports the hypothesis that there is a huge current range with non-destructive filaments at low dc-link voltages. For both destruction mechanisms, the final failure occurs locally. For the energy destruction, the current crowding happens very late during the runaway itself, whereas in the case of a current destruction, filaments are formed mainly by an electrical mechanism leading to a stronger local self-heating. Both mechanisms take place far above the safe operating area of the chip.

ABSTRACT. As the complexity of IC integration, electromagnetic effects will thus play an increasingly important role towards affecting system performance. This paper focuses the Direct Power Injection (DPI) immunity of processor chips with different external double data rate3 (DDR3) synchronous dynamic random access memory (SDRAM) in consumer electronics. To complete the DPI test, a test board complying with the standard IEC62132-4 and a dedicated test program have been designed. By comparing the test data of the pins in the DDR module, the results can be used to locate the position of the system-level EMC problem and optimize the design.

ABSTRACT. The electromagnetic compatibility (EMC) study is an indispensable step in the development cycle of power system modules. In power applications using normally off transistors, short-circuit mode can be recurrent during operation, especially when powering converters. In this paper, we present a study on the evolution of conducted interferences (in common and differential mode voltages) generated by a static converter after an aging test of silicon carbide (SiC) MOSFET transistors from the first generation of CREE subjected to repetitive short-circuit operations. This work presents an experimental investigation of the repetitive short-circuit aging effect of N Channel power SiC MOSFETs on the amplitude of resonances in the interference spectra after ageing tests. Experimental results are presented and analyzed.

ABSTRACT. Foldable electrode with a low electrical resistance and high mechanical fatigue resistance is expected for next generation electronic devices. Failure mechanism of fatigued Ag nanowire(AgNW) electrode and its effect on the electrical degradation was investigated. Instead of bending fatigue of previous researches, electrical resistance was measured in-situ during folding and torsion fatigue test up to 100,000 cycle in the presented study. Damage mechanism of the AgNW including welding of network junction, nano-cracking, fragmentation were revealed by microscopic observation for the 100,000 cycled-fatigued or interrupted specimens. Under high stain folding fatigue condition, electrical resistance was observed to decrease initially and subsequently keep increasing. This initial decrease is attributed to the junction welding phenomena and continuous increase is due to nano-cracking or fragmentation. For torsion fatigued electrode, electrical resistance increased with increasing torsional degree ale. The very increase in resistance with torsional degree was correlated with number of fragmentation of AgNW observed. Under the functional failure criterion of 10% change in electrical resistance, feasibility for a foldable and wearable applications of the AgNW electrode was considered.

ABSTRACT. Electronic Industry has been experiencing a growing counterfeit market, and electronic supply chains in other industries are prone to counterfeit parts. Over the past few years, several methods have been developed for evaluating the reliability of an IC and distinguishing between counterfeit and authentic one. Trained experts offer services for evaluating an IC based on destructive or non-destructive method. However, defect detection and recognition are always dependent on the human decision, therefore are vulnerable to error. In this paper, we propose a method to automatically detect and identify die face delamination on an IC die. Die face delamination is a predominant internal defect in recycled ICs but can be easily during defect detection Here We have acquired a 3D Image of an IC non-destructively using X-ray computed tomography and applied Image processing techniques and machine learning algorithms on the 3D Image to detect die face delamination such as thermally induced cracks and damaged surface.

ABSTRACT. The development of FinFET technology has made possible the continuous scaling-down of CMOS technological nodes. In parallel, the increasing need to store more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The manufacturing process variation has introduced several types of defects that directly affect the SRAM’s reliability causing different faults. Thus, resistive defects in SRAMs represent an important challenge for manufacturing test in submicron technologies as they may cause dynamic faults, which in turn increases the number of test escapes. In this context, this paper presents a hardware-based approach able to detect the presence of very-weak resistive defects by monitoring the current consumption of FinFET-based SRAM cells. The proposed approach has been validated and its detection capability is evaluated. Finally, the introduced overheads are analysed.

ABSTRACT. Reinforcing the reliability of power semiconductor devices is crucial for extending the lifetime of the power-converter based electrical systems. This paper aims at developing a novel prognostic methodology for estimating the Remaining Useful Life (RUL) of the power Metal-Oxide Field-Effect Transistors (MOSFETs). The variation of on-state resistance as an important fault indicator under thermal overstress is utilized as the main database. A recently proposed neural network paradigm, namely Echo State Network (ESN) is utilized here to derive a degradation model, taking into account its high efficiency in modeling nonlinear dynamical systems. Meanwhile, a particle filter approach is developed to give the probability distributions of the possible degradation states. The accuracy and efficiency of the proposed prognostic methodology has been verified and further compared with other existing prognostic methodologies based on an accelerated aging experimental dataset.

ABSTRACT. Probing attacks to arbiter PUFs (physical unclonable functions) using a time-resolved emission microscope are evaluated by simulation. It is assumed that signal delay in the arbiter PUF chip is measured directly by using a time-resolved emission microscope. Only two challenge inputs are required to do that. A simple procedure can predict the response of the arbiter PUF. The relationship between the rate of successful response estimation and the accuracy of signal timing measurement is evaluated by simulation. The simulated results show the rate of successful response estimation is 70% when the accuracy is around 30 ps. This result shows the feasibility of the probing attacks to arbiter PUFs using a time-resolved emission microscope.

ABSTRACT. We present two comprehensive failure analysis case studies using (spectral) photon emission techniques on various 24-40nm FinFETs of two tech generations. Different failure mechanisms within the FinFETs are discovered when investigating deeper into suspicious emission behaviour and spectra. The FA diagnosis is confirmed by electrical measurements for all FinFETs. The emission spectra even offer the opportunity to relate effects on the temperature of the hot electron gas within the channel to failure mechanisms. The obtained electron temperature slopes over drain voltage for 5 different gate lengths can be used to qualitatively and quantitatively determine the red-shift of FinFET emission intensities. The results clearly indicate that (spectral) photon emission analysis for FA can be carried out for modern low-voltage devices well below 1V, contrary to common opinion.

ABSTRACT. Electrostatic Discharge (ESD) problems are increasing and have become challenging in the semiconductor industry because of the trends toward higher speed and shrinking in technology node. By continually shrinking the transistor with technology scaling, the process, circuit design, and failure analysis (FA) are getting more challenging. This paper is about FA on a 14nm Fin-Field Effect Transistor (FinFET) device which has ESD failure after Charged Device Model (CDM) test. The purpose of this FA is to identify what caused the14nm FinFET ESD having leakage, it could be related to design or process. At the same time, this paper also discusses the difficulties faced, the FA technique used, the bottleneck of the 14nm FinFET FA by old technology node FA equipment. Finally, the ESD failure root cause was identified with Scanning Transmission Electron Microscope (STEM)/ Energy Dispersive Spectroscopy (EDS) analysis. The root cause of the failure is related to the front end of line (FEOL), the metal gate of FinFET was fused with active, and the material in the metal gate was out-diffused.

ABSTRACT. Cross-sectional sample preparation is one of the most important failure analysis (FA) techniques in the semiconductor industry. It was commonly used for film stack critical dimension measurement, defect identification, electrical fault isolation and etc. However, cross-sectional sample preparation to a specific target location on a sub-micron device is very challenging and time-consuming. This is because of mechanical polishing easily caused metal smear, delamination, film peel-off, micro-cracked and etc. This paper focused on cross-sectional nanoprobing (XNP) sample preparation improvement in quality and quantity. A laser blast to deprocess or create a groove at near to target location before conventional mechanical polishing and focus ion beam (FIB) fine milling. The proposed technique not only reduces the sample preparation time to the sub-micron target location but also prevent mechanical damages that caused by mechanical polishing technique.

ABSTRACT. Wafer level chip scale packages feature large numbers of solder bumps. These bumps are prone to having voids arising for instance from outgassing during the solder reflow. These voids are considered a reliability risk for the thermo-mechanical strength of the solder connection. Screening of bumps on void percentage is therefore required for quality control. Voids are well captured with X-ray imaging. Void detection in X-ray images is the topic of this paper. The large number of solder bumps necessitates the detection to be automated. In this article we first employ conventional threshold based methods to identify voids. Then, we apply a deep learning model to void percentage detection. We will argue that with a proper training data set deep learning can successfully bin solder bumps on their void percentage.

ABSTRACT. Switch mode power supply (SMPS) is widely used in various industrial fields. Due to the complex operational condition, various faults may occur in the SMPS. Locating the faults efficiently is necessary for the SMPS. Based on classical integer-coded dictionary (ICD) method, which is widely used in board-level analog circuits fault location, this paper presented an extended ICD method to solve the fault location problem in SMPS. An optimal boundary determination method was adopted in the extended ICD, which can improve the separating ability of each feature. In the paper, the fault problem, the available test points as well as the experimental setup were introduced first. Then, the optimal boundary determination algorithm was presented. Finally, the developed method was applied in the SMPS, and the test result showed 7 faults can be located only using 6 features with an accuracy of 92.5%.

ABSTRACT. In typical power electronic modules several semiconductor dies such as MOSFET or IGBT are soldered to a DBC substrate. During module production the quality of the solder layers can be monitored by the use of X-RAY inspection and the void rate can be determined. Recently, the more robust Ag-sinter technology is deployed for attaching the power dies to the substrate, especially for high reliability or high temperature requirements. Besides voiding also adhesion problems can occur during sintering due to multiple reasons (e.g. contamination). In contrast to volume defects, pure adhesion problems cannot be detected by means of X-rays. Therefore other methods have to be applied for process monitoring. The present investigation compares the advantages and disadvantages of different non-destructive imaging techniques towards the detection of defects in sinter layers. Besides X-RAY, Scanning Acoustic Microscopy (SAM) and Lock-in thermography methods (DLIT+ILIT) were evaluated towards the detectability of different defect types, the resolution (minimum defect sizes), the inspection time and possible integration in the assembly process.

ABSTRACT. Space and transport industries are facing a strong global economic competition which is setting economic constraints on the cost of the functions. In order to reduce development costs and to propose new features more quickly, using components of the shelf (COTs) is very suitable. This paper investigates the degradation of AlGaN/GaN HEMTs COTs submitted to HTRB lifetest. Steps in terms of temperature and voltage were performed in order to distinguish the effect of each stressor. The main aim is to establish a lifetime model, taking into account several degradation mechanisms, over a large range of temperatures and voltages. The experiments indicate the activation of different failure mechanisms during the stresses depending on the different ranges. In this work, experimental analysis has been performed in order to characterize and verify when multiple failure mechanisms can be activated on such components and on which range these mechanisms may superpose.

ABSTRACT. Despite their potential in the field of power electronics, many reliability issues still affect the electrical performance of Gallium Nitride HEMT power devices and require an effort of analysis and understanding. The characterization of the on-state resistance of this transistor is necessary to understand the dynamics of some phenomena such as trapping. The degradation of this resistance has always been related to traps in the 2DEG channel, without taking into consideration possible contributions from the source and drain contacts (metal/semiconductor). In this work, resistance measurements, with and without UV illumination, are performed on two different technological options to highlight the effect of illumination on contact resistances in some technological processes.

ABSTRACT. Short term step-stress tests were carried out to evaluate InAlGaN/GaN HEMT devices including 3 different passivation schemes, each one consisting of two dielectric layers. The results of these tests demonstrate that the upper layer of the passivation has a strong impact on the ageing of the devices. When Atomic Layer Deposited Al2O3 replaces the upper SiN layer of the passivation stack, the leakage currents at pinch off decrease and the stability of the electrical parameters is improved during the life tests.

ABSTRACT. In this paper, we use a pulsed technique for measuring the input impedance of power devices when they are operated in real operating conditions like short circuit for identifying the conditions where these devices can become instable. The measurement results are used to extract the stability plots of several device like IGBT, Power MOSFET in Si and in SiC, GaN power HEMTs. It is demonstrated that the proposed approach can be a very useful tool for designing the external circuit, and in particular the driver circuit, in such a way to prevent the SC instabilities of IGBTs.

ABSTRACT. Power Semiconductors are one of the most failure-prone components in a power converter in energy-producing systems such as wind turbines. It is desired to have a method of indicating an increased risk of wear-out failures of the module in order to enable predictive maintenance. In this abstract, recording of acoustic emission is used for non-invasively detecting the aging of a power module due to power cycling. It is found that the ageing can be detected by a decrease in the RMS value as the module is exposed to power cycling. This could indicate that changes in acoustic emission has the potential of being a precursor for wear-out failures in power modules.

ABSTRACT. Most failures of Multilayer Ceramic Capacitors (MLCCs) are mechanical in nature. Therefore, the reliability assessment of these parts depends heavily on available mechanical properties in the literature. As nano-indentation offers the advantages of testing small areas that yield accurate results, more mechanical properties on MLCCs measured by nano-indentation are being published in the literature. However, nano-indentation measured properties are known to vary with different factors such as measuring loads and residual stresses. In this article, nano-indentations are performed at different locations with two different loads on commercial MLCCs. By understanding the causes of variation, this article offers a baseline for adopting and comparing nano-indentation measured mechanical properties for ceramic dielectrics in MLCCs for reliability assessment or design.

ABSTRACT. The thermal couplings among capacitors in a bank could significantly alter the reliability performance compared to a single capacitor. The impact of thermal coupling is becoming stronger for high power density systems due to more stringent constraint in volume. Prior-art studies take into account the thermal coupling effects of a capacitor bank by either Finite Element Method or experimental characterization, which are case dependent and time-consuming. This digests proposes a nonlinear mathematical model for capacitor banks based on physics of thermal conduction, convection, and radiation. A simplified version of the model is also obtained and represented by an RC circuit network, which enables computational-efficient thermal stress modeling. The proposed models are convenient to use to support model based sizing of capacitor banks and is scalable for multi-cell rectangle layout. A case study with experimental testing is discussed to verify the accuracy of the models.

ABSTRACT. 20 years ago the IGCT (Integrated Gate Commutated Thyristor) was launched as a new power semiconductor device using design features where only few reference was available at that time. Especially the gate path that needs to take the full principal current for micro seconds was significant extension of the state of the art. In-between 20 years of field experience with IGCTs is available. In this paper test results from accelerated testing, quality monitoring results over many years, reliability date from evaluated field failure rates and analysis of devices that were in service for 15years under well-known load are summarized and show an excellent reliability of the power semiconductor.

ABSTRACT. This paper compares the most common used temperature sensitive electrical parameters towards their aging dependencies as well as to one another. Therefore a mission profile is extracted from an off shore wind park and a test plan is generated. IGBT power modules are tested against that test plan using active power cycling. The selected temperature sensitive electrical parameters (TSEP) are monitored online during the test and correlated to each other. This way the aging dependence can be extracted, so that the most aging independent TSEP can be used for condition monitoring during wind park operation.

ABSTRACT. Electro-mechanical Actuator (EMA) is a critical component of aircraft. EMA Pulse Width Modulation (PWM) Inverter degradation has significant influence on EMA performance, which may lead aircraft to catastrophic consequences. However, noise conditions bring much difficulty to EMA PWM Inverter health state characterization. To effectively characterize health state of EMA PWM Inverter under noise conditions, this paper presents an Health Indicators (HIs) extraction method based on Multi-dimensions Sliding Window Correlation (MDSWC). In MDSWC, the sliding window correlation of high monotonicity is utilized to extract EMA PWM Inverter HI. Experimental results show that MDSWC has better anti-noise performance in the field of EMA PWM Inverter HIs extraction.

ABSTRACT. This paper investigates two compact thermal model representations for multi-chip power modules, namely the thermal impedance matrix model and the thermal admittance matrix model. The latter can shape a multi-port thermal network without controlled temperature sources, and can be readily implemented in circuit simulators from the electrical engineer point of view. The mutual transformation between the two models and their relationship to parameters in the multi-port network are revealed. In addition, practical tips regarding the temperature recording and the curve-fitting in the process of the thermal model parameter extraction is discussed. The multi-port thermal model is verified by simulations and experimental results. It confirms that accurate temperature estimation can be achieved compared with the thermal model without the thermal coupling effect.

ABSTRACT. As insulated gate bipolar transistors (IGBTs) have gained an important status in a wide range of industrial fields, reliability and availability of these units are of paramount importance to meet stringent requirements spelled in aviation and industrial standards. Reliability of a power converter is mainly verbalized by the failure rate of power modules. Hence, monitoring the IGBTs degradation can prevent power-module-related failures in power converters, especially in safety critical applications. This paper proposes a new potential precursor parameter for IGBTs based on voltage change rate to detect early failure of power modules. The proposed method pays more attention to power modules with solder die fatigue and bond-wire lift off as major failure mechanism. Ageing of IGBT devices is conducted using an accelerated power cycling machine to trigger degradations and failures on the devices under test. The experimental results indicate that voltage change rates of the IGBT modules increase with ageing over time. It is found that the increase of the voltage change rate of an IGBT is because the parasitic capacitances of the device are affected by the local damage induced by ageing over time.

ABSTRACT. In this paper, we propose the criteria of bias voltage from parasitic capacitance and demonstrate the criteria in an experiment with the present IGBT. The bias voltage criteria are theoretically predicted for the new generation IGBT based on the scaling principle. For safe switching, the required gate voltage bias is predicted to be at least -1.2 V or below for the present IGBTs and -6 V or below is required for the complete cancellation of gate noise voltage. From the IGBT design, the bias voltage of scaling IGBT requires -2 V for complete gate noise cancellation.

ABSTRACT. Parallel connected Insulated Gate Bipolar Transistors (IGBTs) can be used to realize system with higher current and higher power rating. However, the operation of parallel connected IGBTs are prone to unbalancing due to variation in parameters of the semiconductor devices and asymmetric parallel system. In this paper, feedback control is proposed to balance the current of parallel connected IGBTs by minimization of peak current. A fully digital feedback control (DFC) is implemented using universal clock for balanced operation of the two parallel connected IGBTs.

ABSTRACT. Health monitoring of the power conversion system is very important. Therefore, we developed a new method for measuring IGBT currents and reproducing average load current to monitor IGBTs. This method was successfully tested on an experimental setup which showed that it can be integrated into intelligent power modules. We proposed an inexpensive analogue circuit which is suitable for capturing current information from a tiny PCB Rogowski coil. The method was named “Envelop tracking” as it simultaneously measures the currents of the high and low side switches of a power converter and reproduces the upper and lower edges of the load current which can be averaged by further digital processing.

ABSTRACT. Reliable and unceasing exploitation of power electronic converters plays a major part in every application. Concerns of manufacturers about guaranty time period as well as the maintenance cost and its time period encourage researchers to evaluate reliability of converters with an acceptable accuracy. This paper concentrates on a new opened-up reliability assessment framework and demonstrates the feasibility of using sensitivity analysis for a much more accurate estimation. This paper deals with a conventional boost DC-DC converter as a case study for electric vehicle application. The article presents that significant self- and reciprocal-effects of components can thoroughly impress the reliability assessment in the thermal coupled structure. It is shown that by IGBT or Diode aging due to thermo-mechanical fatigue, an increase in the IGBT or diode junction temperature has been occurred, while electrical operating point maintains constant even as a case of capacitor degradation. It also reveals that the useful lifetime of IGBT and diode can also decreases by 35% and 44% respectively. The results reveal the importance of reciprocal aging and self-aging effects on the reliability assessment.

ABSTRACT. The aim of this paper is to investigate the impact of electro-thermal device parameter spread on the avalanche ruggedness of parallel silicon carbide (SiC) power MOSFETs representative of multi-chip layout within an integrated power module. The tests were conducted on second generation 1200 V, 36 A – 80 mΩ rated devices. Different temperature-dependent electrical parameters were identified and measured for a number of devices. The influence of spread in measured parameters was investigated experimentally during avalanche breakdown transient switching events and important findings have been highlighted.

ABSTRACT. The paper presents the results of a post failure analysis performed on commercial 650V GaN power HEMT after short circuit tests. The used experimental set up includes a protection circuit which avoids the sample explosion and limits the energy involved in the failure in order to facilitate the identification of the area where the failure is initiated. The post failure analysis confirms that DUTs exhibit two kinds of failures. In the first failure mode, for which large energies are dissipated in the device before the failure, the damaged area of the chip is quite large and is located close to external contacts. In this area, very likely, the temperature exceeds the melting temperature of the metallization. The second failure mode is observed for higher values of the drain voltage and involves lower energies dissipated in the DUT during SC before the failure. In this case, it is shown that the damaged area is very small and is located below the source filed plate at gate edge on the drain side. 2D finite element simulations show that in this region the electric field becomes very high supporting the hypothesis that the failure mechanism is associated with instabilities due to current filamentation taking place in the device at high test voltage.

ABSTRACT. GaN-based power components are known to exhibit reversible instabilities in their electrical characteristics and primarily in threshold voltage. This is due to trap effects in the structure. Works presented in this paper attempt to answer the question of how are these traps affected during aging by power cycling and especially if there is irreversible degradation. For this purpose, power cycling tests were performed using two stress conditions in ∆Tj (80K and 100K) on Normally-ON Al2O3/AlGaN/GaN MOS-HEMTs power chips reported on a direct copper bonding (DCB) substrate. The aging has been regularly interrupted in order to perform characterization of several aging indicators. Furthermore, trap characterizations, based on the analyses of transient current measurements, have been performed during the aging process. The results showed that irreversible degradation affects threshold voltage with drift to negative values for all tested samples. These shifts have been mainly attributed to an evolution of traps under the gate. Preliminary trap characterizations have presented increase of some traps time constants whereas others remain quite constants. This point should be confirmed by further tests and analyses. These results may reflect a possible degradation of the surface under the gate.

ABSTRACT. This paper provides a comprehensive investigation on both static characteristics and short-circuit performance of 1.2 kV SiC MOSFET power modules with 2nd generation planar-cell chips. The results of short-circuit waveforms and gate leakage current variation corroborate the hypothesis that a gate structure degradation appears after short-circuit tests. Some degradation indicators, in particular, positive shift of threshold voltage, gate leakage current increase and variation of drain leakage current are evidenced and discussed in this work. Furthermore, the impact of room-temperature recovery on the gate leakage current is presented.

ABSTRACT. In this paper, we study the effect of short circuit aging on Short Circuit Safe Operating Area and Reverse Bias Safe Operating Area of SiC MOSFETs. SCSOA and RBSOA are determined using short circuit and unclamped inductive switching tests, respectively. Aging of SiC MOSFETs are performed with repetitive short circuit tests at low dissipated energy, with different dissipated energies, which allows to validate the relevance of different aging indicators measured during the aging process. The decrease in dissipated energy leading to failure in short circuit and unclamped inductive switching tests allows to link clearly the evolution of Safe Operating Area to the degradation of drain and gate leakage currents. The on-state resistance increase represents smaller impacts in the decrease of Safe Operating Area compared to the degradation between drain and source or the degradation of the gate oxide.

ABSTRACT. Forward AC stress and relaxation have been performed on GaN-on-Si Schottky diodes to study the shift of diode characteristics such as threshold voltage. Influence of frequency and length of first anode field plates are studied. PBTI measurement performed on HEMTs with gate similar to the first anode field plate rules out the degradation of the dielectric under the anode field plate and tends to prove that Schottky contact itself could be the cause of forward stress degradation.

ABSTRACT. In this article, a repetitive and non-destructive short-circuit aging test is developed to characterize the electrical parameters evolutions of a 600V GaN Gate Injection Transistor (GIT). The evolutions of C-V and I-V characteristics during the repetitive short-circuit tests with a relatively low bias voltage and long pulse duration are presented and summarized. The reverse capacitance CRSS at on-state mode and the gate current at relative high gate voltage show significant degradations before and after test.

ABSTRACT. In this paper, the light emission of a SiC MOSFET during reverse conduction, caused by the LED-like behaviour of the body diode, is studied and investigated. The light emission from a 1.2 kV / 20 A commercial device has been measured experimentally using a silicon photodiode. A behavioural characterization of the light output under different junction temperatures and current values has been performed. This allows the implementation of an inexpensive and non-invasive temperature sensing strategy for SiC MOSFET chips based on the measurement of light emission during reverse conduction.

ABSTRACT. Silicon Carbide power MOSFETs are used in numerous studies to improve the efficiency or the performance of power electronic converters. However, the gate-oxide technology weakness is a main reliability issue of Silicon Carbide MOSFET transistors. The threshold voltage shift is a critical phenomenon that addresses the reliability of industrial power applications. It is important to have a better understanding of the phenomena implied in the gate threshold voltage shift. In this context, a static ageing test based on JEDEC standard is proposed and the resulting gate oxide stress is studied and discussed in this paper. Complementary testing was performed with dynamic reliability and gate oxide characterizations, such as the charge pumping technique. The results obtained are used to add insight to the current discussion of SiC MOSFET robustness. Additionally, test benches and measurement protocols are detailed.

ABSTRACT. The synergetic effects of High Temperature Gate Bias (HTGB) (0h, 162h, 332h) and Total Ionization Dose (TID) radiation (0 kGy, 1 kGy, 3 kGy, 5 kGy, 10 kGy) response of 1200V commercial SiC power MOSFETs were studied, along with annealing characteristics at room temperature. Electrical parameters were investigated with Current-Voltage (I-V) and Capacitance-Voltage (C-V) measurements. Results show that Gate Threshold Voltage (Vth) is sensitive to combination of HTGB and TID. Gate Leakage Current (Igss) and Vth increase while Input Capacitance (Ciss) decrease after HTGB stress. Drain-Source Leakage Current (Idss) and Igss rise up due to TID radiation while Ciss and Vth decrease. HTGB mitigates the shift of parameters due to radiation to some extent, especially Idss. No obvious annealing effect was observed at room temperature for one week on all Device Under Tests (DUTs) in this work.

ABSTRACT. An antiparallel PiN diode is present in the structure of the SiC Power MOSFET. For simplicity and cost reasons, it sometimes may be preferable to use this diode rather than to add an external Schottky diode to the MOSFET. However, SiC PiN diodes are sensitive to defects in the SiC crystal, and their performance can degrade rapidly. In this paper, we assess the effect of several stresses on the characteristics of a SiC MOSFET, focusing on the stresses which involve their body diode. We demonstrate that using the body diode does not degrade its performances. However, it produces a noticeable shift in the threshold voltage of the MOSFET.

ABSTRACT. The advent and widespread adoption of the ‘ultrathin’ notebooks in the market has resulted in a push for even thinner devices. Thin notebooks require thin electronic packages and these pose design and manufacturing challenges in terms of warpage. At a total thickness of less than 1.5mm, the package has very low flexural rigidity resulting in high warpage. Warpage shapes also deviate from the typical concave and convex to more complex wavy shapes. High warpage results in a highly stressed part. In addition, high warpage can result in yield loss due to bump bridging and solder extrusion. For accurate warpage and reliability assessments using finite element analysis (FEA) based simulation tools, accurate material properties for substrates is required. High anisotropy in the metal patterns, imbalance between copper layers and temperature-dependence of constituent materials make the substrate a challenging material to characterize and model. This work compares the various methods currently used to determine the material properties of the electronic substrate, ranging from simple analytical models that incorporate rule of mixtures to experimental techniques and even simulation methods. Each of the different methods is then evaluated by comparing the correlation of warpage simulations to experimental warpage measurement. For accurate warpage and reliability simulations, characterization methods need to provide higher resolution of material property inputs. Simulation methods such as detailed models and trace mapping improve accuracy but also increase the time taken for the analysis. More efficient methodologies are required for modeling these substrates. In this work, digital image correlation (DIC) is proposed as a technique to increase the resolution of material properties used as input to simulations and will be evaluated against more time-consuming methodologies such as trace mapping.

ABSTRACT. In this paper, the effect of junction temperature swings on reliability of IGBT modules is studied with 600 V, 30 A, transfer molded power modules. This study is based on power cycling test results with 18 samples under three test conditions by means of an advanced power cycler. This paper starts with a brief explanation on the advanced power cycler and test conditions. Then, the results of power cycling tests under three different junction temperature swings are presented. Post-failure analysis results of the tested IGBT modules are also presented. Finally, lifetime analysis is provided and a relevant acceleration factor is modeled based on the test results.

ABSTRACT. While the power electronics are striving to higher power density, lower costs, and longer lifetime, one of the bottlenecks in this area is Thermal Interface Materials (TIMs), which contributes the large thermal resistance in typical power converters. However, the prior-art characterization methods for TIMs are neglecting the realistic joint conditions, or too complicated. Therefore, this digest proposes an empirical model to characterize TIMs, where the model inputs are only relied on two controllable parameters: initial thicknesses and screw torques. Based on the empirical model, thermal resistance of a TIM is easily characterized by a small number of tests. Experimental platform has been built. The corresponding experimental results will be shown in final paper.

ABSTRACT. Graphene conductive foams, have shown very high potential as cooling material in electronic systems. Its exploitation with discrete GaN transistors is demonstrated in this paper. A proper experimental setup is developed to extract the high temperature thermal performance of this material at different test conditions. The results are very promising, showing a noticeable reduction of the device maximum temperature, especially at high dissipated power densities. Moreover, experimental results allowed the validation of a 3D finite element model of the assembled device, which can be used for thermal layout optimization. Finally, preliminary stress tests are in progress, to evaluate the stability of electrical and thermal performance of the proposed graphene based assembly.

ABSTRACT. The reliability evaluation of GaN die-attach/DBC substrate was carried out by employing a Ag sinter paste /W thin film/Ag sinter paste sandwich die-attached layer. GaN chips were bonded to DBC substrate using Ag sinter paste with thin W film at 220 ℃ and at 0.4 MPa for 60 min. The joints structure was then subjected to thermal shock testing in temperature range of -50 to 250 ℃ for duration up to 1000 cycles. The initial average die shear strength of the GaN/DBC joints with Ag paste, about 30MPa, was maintained up to 1000 cycles. The microstructure was observed by FE-SEM and XRD analysis. In addition, the sandwich structure showed a stress-shielding effect from the external force evaluated by FEM numerical simulation. This study reveals that Ag sinter paste /W thin film/Ag sinter paste sandwich can provide a superior thermal shock resistant, and thus achieve a reliable power module structure for wide-bandgap semiconductors operated at high temperatures.

ABSTRACT. This work proposes a FEM-SPICE based methodology for an optimized design of water heatsinks for high power electronic converters. Cold plates are a key issue for power electronics systems, in order to obtain reliable applications. Often the design of custom heatsinks is done by manual procedures, which require the fabrication of several prototypes. On the other hand, FEM analysis is a powerful tool for cold plate best design, but it requires skilled technicians and long simulation studies. In this paper a SPICE based methodology is demonstrated able to assist the design of cold plates with negligible simulation cost, and limited use of FEM simulations and prototypes. A prototype was developed by the proposed methodology and used to validate the approach. Results show a good agreement between cold plate thermal-fluid-dynamics FEM simulation and the SPICE based methodology. A software tool was developed to easily exploit the proposed methodology in customized designing of cold plates for any specific application, and to extract necessary data for the datasheet: pressure drop, and thermal resistance.

ABSTRACT. Power electronics (PE)modules for inverter units in hybrid/electric vehicles (H/EV) generate a large amount of heat which needs to be dissipated. This is often done via a liquid cooled metallic baseplate which acts as a heat sink. The interconnect between the PE module and the baseplate is realized using a large area solder jointwhich under temperature cycling (TC) tests, develops adhesive cracks (delamination) at the solder-intermetallic compound (IMC) interface. Such cracks reduce the capability of the solder joint to effectively transfer heat to the baseplate and potentially lead to device failure due to overheating.

Considering the large number of potential designs for various application of such PE modules, an understanding of the influence of the mechanical behaviour of individual assembly components such as the power substrate, baseplate or the solder joint itself on reliability is of great interest and utility. This study therefore provides an in-depth reliability assessment of multiple physical variants aged under three different TC profiles. The investigation reveals certain clear trends with respect towarpage, stiffness and size of the joining partners. A detailed Finite Element Method (FEM) simulation methodology was also developed that represents the delamination behaviour for lifetime assessment.

ABSTRACT. This paper describes a reliability of low temperature soldering using In-Bi solders for flexible and wearable electric devices. The shear strength and effect of thermal aging on Cu substrate of In-Bi solders prepared by soldering under various aging conditions were examined. In addition, the cross-sectional microstructure of the Cu/In-Bi solder/Cu joints was investigated, and the fracture surface of the joints was examined after shear strength test.

ABSTRACT. Automotive environment generates vibration and temperature fluctuation, which can be damaging for electronic boards. Furthermore, combined temperature and vibration is a type of testing that recreates environments approximating more closely operating environments. In this paper, vibration tests are performed during thermal cycling to investigate the influence of temperature on Printed Circuit Board (PCB) responses. A combined test of temperature and vibration is designed to evaluate the PCB response after each step of one thermal cycle [-40/125]°C. Experimental results imply that temperature significantly affects the PCB responses. Temperature variation leads to striking differences in vibration loading intensity. The PCB first natural frequency shifts from 328Hz to 313Hz with temperature increases from 25°C to 125°C. A complex PCB is characterized using tension and flexure tests at different temperatures, to extract user input parameter for simulations. An accurate numerical model for sequential combined thermal cycling and vibration simulation is established and validated using experiments. These simulations allow assessing the displacement evolution due to combined loading.

ABSTRACT. Transient liquid phase (TLP) bonding is one of novel techniques, which is an alternative to conventional soldering used in power electronics packaging. In this paper, we report on formation and analysis of TLP bonded Cu-Sn-Mo and Cu-Sn-Ag-Mo systems for production of hybrid metal baseplates. The obtained bonds of intermetallic compounds (IMC) are characterised by shear testing, optical microscopy and energy dispersive x-ray spectroscopy. Cu-Sn-Mo systems show low reliability due to the lack of IMCs at the Sn-Mo interface and severe void and crack formation while Cu-Sn-Ag-Mo interfaces demonstrate high homogeneity and considerable shear strength. Thus, it is concluded that the low temperature TLP bonding using Cu-Sn-Ag-Mo is a promising candidate for the fabrication of hybrid Cu-Mo baseplates.

ABSTRACT. Power cycling test is often used for the developing of lifetime models of power semiconductor devices. The performance of devices in power cycling test is defined by their cycles to failure at certain given test conditions. In this work, power cycling tests with the same start test condition but different control strategies were performed. Three different control strategies were realized by regulating three different adjustable parameters. It is also found that the definition of failure criteria in power cycling test will strongly influence the test results, which should also be defined appropriately.

ABSTRACT. The effects of the compositional ratios of sputtering target on the device performance and instability in amorphous InGaZnO thin film transistors (a-IGZO TFTs) have been investigated. Four kinds of a-IGZO TFTs according to the contents of In, Ga, and Zn were fabricated by RF magnetron sputtering system. The electrical performances were enhanced with increasing In ratio in IGZO TFTs. The resistances of the source/drain electrodes and the effective channel length were decreased with increasing In ratio. The threshold voltage shifts under PBS were decreased with increasing the sum of In and Zn ratios. A-IGZO TFTs with high In ratio exhibit a conductor behavior under NBIS.

ABSTRACT. We have studied the effects of an ESD stress on polymeric solar cells, employing P3HT:PCBM as active layer. All the analyzed devices featured a behavior strongly related to the evolution of the internal parasitic paths. We found that the degradation of the OSCs during the stress is related to the initial shunt condition. In addition, no breakdown occurred during the stress and only minor changes are visible from the photocurrent characteristics.

ABSTRACT. In this work, we studied the impact of stair-case Gate bias stress on flexible Indium-Gallium-Zinc-Oxide ThinFilm Transistors and we estimated the breakdown voltage for different channel aspect ratios. The results show that the breakdown voltage exhibits a remarkable dependence on the channel width, while exposing no or marginal dependence on the channel length. The analysis of the threshold voltage evolution, shows that after an initial increase, a remarkable decrease occurs for larger bias, indicating the action of at least two charge trapping phenomena.

ABSTRACT. This work presents the analysis of the degradation mechanisms and of the electro-optical characteristics of LEDs submitted to electrical overstress. The analysis was carried out by a custom-setup, that allows us to measure the current-voltage and electroluminescence curves of the devices while pulsing the devices with increasing voltages, up to failure. We investigated a wide span of EOS time durations (from 1 ms to 10 s). The results provide information on (i) the dependence of failure voltage/power level on pulse duration; (ii) on the temperature-dependence of the pulsed I-V characteristics; and (iii) on the changes in electrical and optical properties reached at extremely high current densities. The results presented within this paper provide relevant (and so far unpublished) information on the characteristics of the devices in this extremely high stress regime.

ABSTRACT. Electronic systems based on solid state devices have changed to be more complicated and miniaturized as the electronic systems developed. The evaluation of HPEM(High Power Electromagnetics) has been mainly carried out in the system level, and the case of failure analysis on the device is very rare. If the electronic components(semiconductor) are exposed to HPEM, this semiconductor will be destroyed by the coupling effects of electromagnetic waves. Because the HPEM has fast rise time and high voltage of the pulse, the semiconductor is vulnerable to external stress factor such as the coupled electromagnetic pulse.

ABSTRACT. The degradation of GaAs devices with incident proton energy was analyzed based on experimental and simulation results. The degradation of device is not linear to the displacement damage dose induced by the proton with energy of 20-190MeV. The equivalent displacement damage dose which contribute to the point defects is recommended to perform displacement damage test for GaAs devices.

ABSTRACT. This work aims to characterize the sensitivity to atmospheric and cosmic radiation of GaN Normally-off commercial technologies used in switching power conversion. It is necessary for the Space, Aeronautics and Automotive industries to characterize the radiation robustness of these new COTS components in the operational and environmental conditions of their applications. Electrical behaviour of normally-off GaN power transistors under heavy ion test campaign is presented to define the cross section, determine the safe operating area (SOA) and analysis the mechanism of Single Event Effects (SEE) in these devices. This abstract represents only the first results of investigation that will be completed in the final version by several tests in progress. Based on our knowledge, this article is the first work that covers the sensitivity assessment of most normally-off HEMT/GaN technology that currently exist in the market.

ABSTRACT. The total ionizing dose (TID) response of leading-edge sub-30nm FDSOI transistor is presented. TID experiments were performed on NMOS devices under three different bias conditions (ON-state, OFF-state, TG-state). The results show that the charge trapped in buried oxide layer (BOX) causes a negative shift of threshold voltage. The worst bias condition during the TID irradiation test is related to the gate length (Lg). When a positive back bias is applied to achieve better performance, the threshold voltage degradation becomes worse. An explanation of back gate impact on front gate TID response is given with a TCAD simulation.

ABSTRACT. A long-term experiment has been carried out to characterize the energy and the charge deposition by environmental ionizing radiation in thick silicon depletion layers, as those encountered in high-power semiconductors. The main scope of this investigation is to provide quantitative and statistically consistent data to simulate and to design lifetime experiments for Single Event Burnout phenomena in high-power devices. Special attention is paid to the charge deposition immediately before the onset of carriers multiplication. The radiation detector is a calibrated, almost abrupt silicon PiN diode with a 100µm thick depletion layer, which has been designed for a maximum electric field of 10kV/cm to avoid local charge multiplication and to achieve full charge collection. The dedicated spectrometry chain has a sensitivity in the 1 to 1000fC range to detect interactions mainly due to terrestrial cosmic neutrons, but also to terrestrial cosmic muons and environmental gamma radiation. The experiment has been performed in Central Europe starting from August 2017 for a duration of six months, under none, moderate, and high shielding conditions, and it has been designed to resolve fluxes above 0.00023 cm-2 hour-1 with 90% confidence level.

ABSTRACT. During the lifetime of integrated circuit in the aerospace, they encounter not only the radiation degradation as the total ionizing dose (TID) effect, but also their intrinsic degradation mechanisms, such as constant voltage stress (CVS) effect. This paper analyse the both effect on the N type FinFET transistor with high-κ (HfO2) metal gate (HKMG). Various dimension and stress voltage on the nFinFETs are characterized under room temperature. The experiment results show that both effects could shift the threshold voltage (Vth) of the transistor towards positive. Comparing the TID induced degradation, the devices are relatively robust against the constant voltage stress.

ABSTRACT. The electrical characteristics of bulk nFinFETs under the total-ionizing-dose (TID) irradiation were experimentally evaluated with respect to the process variation (PV). The inconsistent transfer characteristics, particularly the different threshold voltage shifts under the identical bias condition and irradiation dose, are investigated through TCAD simulation considering the shallow trench isolation (STI) footing and asymmetrical sidewall. The influence of bias condition as an important factor including ON, OFF and transmission gate (TG) is included in this paper to better illustrate the PV dependence. The HfO2 high-ĸ metal gate and the STI, as well as the PV dependent geometry, are some of great impacts on the degradation of electrical performances with the increase of TID. A radiation-hardness strategy is, therefore, proposed to improve the electrical properties of FinFET devices in radiation environments.

ABSTRACT. The radiation-induced change in input bias current of bipolar input stage of BiCMOS operational amplifiers is studied as a function of the dose rate of gamma-irradiation and of the temperature applied during irradiation. It is shown that degradation enhancement factor KD provided by the temperature applied during irradiation exhibits a nonmonotonic dependence on the dose rate: an elevated temperature provides the maximum increase in the degradation, if the dose rate is chosen from the range 0.1-1 rad(Si)/s, while irradiation with high and low dose rate provides approximately the same values of KD. This range can be recommended for accelerated testing of bipolar and BiCMOS devices, if enhanced degradation in low dose rate conditions of space application is modeled by irradiation at elevated temperature.

ABSTRACT. In order to identify the physical mechanism of retention time drop in irradiated SDRAM cell, we implemented the Gossick model of displacement damage cluster into a TCAD simulation tool. Simulation results show that the cluster’s position is the key parameter of the phenomenon. Besides that, obtained results are coherent with previous studies and explained by semiconductor physics. Other technological parameters of the cell also influence its response to displacement damage clusters. Leakage current induced by clusters depends exponentially on temperature.

ABSTRACT. The comparator is a key component of analog to information converters. The speed and the accuracy of the comparator determine the conversion quality. As device-scaling enters in the nanometer dimensions, the circuit becomes more susceptible to temporary faults. In this work, Single-Event Transient effects on a dynamic comparator in 28nm FDSOI CMOS technology are investigated. The sensitivity of the circuit is simulated combined with the polarity of differential inputs and the working phases of the comparator. Moreover, the body-bias and the transistor channel modulation impact were analyzed. The minimum charge Qc to produce incorrect outputs is determined according to the striking time and the transistor involved by the strike. Results show that circuit vulnerability is a function of the individual transistor, the striking time, body-bias and the transistor channel modulation. Moreover, the minimum Qc value increases by 9.4% and 23.6% using the poly technique and the flip-well with back-bias configuration, respectively.

ABSTRACT. Single Event Burnout(SEB) due to the terrestrial neutron is considered as one of the catastrophic failures of power semiconductor devices. Since SEB is random failure event, it is necessary to take the long-term destructive tests or tests with special facilities such as neutron or heavy ion radiation accelerator. In this paper, we proposed non-destructive SEB failure rate estimation method using repetitive monitoring technique. Non-destructive large and small current spikes are observed and it is confirmed that these spikes originate from single event effects. The frequency of these spikes are related to the failure rate of the device.

ABSTRACT. Efficiency degradation due to modules soiling is a key factor in photovoltaic plants, which must be accurately taken into account in order to set a maintenance program which optimizes the production/cost ratio. In this paper a numerical model is developed, which accounts for the relation between the losses in the energy production and the maintenance operations cost. A small PV system with a proper measurement bench was set up and the model was tuned on the basis of an experimental campaign, obtaining a very good agreement with measurements. The test system was then improved by the introduction of a reference panel kept clean to quantify the uncertainty of the predictive model.

ABSTRACT. The reliability of the solar array, being the primary energy source, is a key factor that may affect the operation of the spacecraft. The equivalent circuit resistance plays a vital role in health monitoring of solar cells in the spacecraft power system. With time, the performance degradation of solar cells with increased carrier recombination and leakage current, result in a decrease of this resistance. However, the real-time detection of this change in the resistance is very difficult. In this paper, a relationship between the resistance change and bus voltage ripple is analysed, and the relationship can be used for the evaluation of the health state of the solar cell.

ABSTRACT. The multifunctional operation of photovoltaic (PV) inverters consists in providing ancillary services to the power grid, such as reactive power injection, harmonic current compensation and frequency regulation. However, it is necessary to quantify how much those extra activities affect the PV inverter life consumption. This work analyses the life consumption of a single phase multifunctional inverter during the harmonic current compensation. The mission profile of harmonic current, irradiance and temperature are considered by the lifetime model in order to result in a more realistic estimation. A rainflow counting algorithm is applied. The Bayerer’s model and Palmgren-Miner’s rule are used to calculate the life consumption. The results show that the life consumption is correlated to the harmonic phase angle. In addition, when the harmonic phase angle is equal to 180°, the life consumption can be lower than a conventional inverter.

ABSTRACT. Recently, modular cascaded H-bridge Multilevel Photovoltaic Inverters (MLPVIs) has attracted many researchers for grid-connected PV systems because of high efficiency with low switching frequency control methods and a possibility of eliminating the step-up transformer in high-voltage grid-connected PV systems. The inverter is one of the most unreliable part of the PV energy system operating in different environmental conditions, and the MLPVI requires more number of power semiconductor switches, which increases the probability of failure. In order to provide reliable operation, it is paramount important to predict the lifetime of an inverter by considering mission profile (solar irradiance and ambient temperature profiles). This paper focuses on the lifetime evaluation of the modular cascaded H-bridge MLPVI by considering the mission profile. The power loss calculation and electro-thermal analysis based on the mission profile has been conducted to unveil the thermal loading of MLPVI. A cycle counting algorithm has been employed to identify the mean junction temperature and amplitude of the temperature swings of each thermal cycle. At last, the lifetime of 5 kW grid-connected single-phase five-level modular cascaded H-bridge MLPVI is studied based on the lifetime models for power devices

ABSTRACT. The increasing penetration of Wind Power Plants (WWPs) have several impacts on the power system operation, such as voltage instability. In such conditions, the literature suggests the use of static synchronous compensators (STATCOMs). Additionally, the Modular Multilevel Converter (MMC) is featured as a very suitable topology for STATCOM application. In this context, this work analyses the effect of the modulation strategies in losses and lifetime of a 17 MVA MMC-STATCOM. The two most popular modulation strategies are benchmarked: Phase-Shifted Pulse-Width Modulation (PS-PWM) and Nearest-Level Control (NLC). The partial results indicate that both strategies have similar conduction losses, although, PS-PWM has almost twice more switching losses. As a result, the PS-PWM has the energy consumption 36% higher than NLC and the NLC increases in 90% the converter lifetime.

ABSTRACT. In this paper, a three-level NPC grid-connected system is taken as the research object. The direct power control strategy based on virtual flux is applied to grid-connected inverters. The grid voltage sensor can be discarded to reduce the system cost and ensure reliable and efficient operation of the system. Incorporating fault-tolerant technology and taking the short-circuit fault as an example, the whole system is simulated and experimentally verified

ABSTRACT. Proton Exchange Membrane Fuel Cell (PEMFC) system is a backup power, which is in standby status during normal power grid. Subsequently, it is necessary to ensure their operability in a periodic demeanor. In this paper, a fault tree analysis is used as one of the dynamic approaches to assess reliability and availability of the critical sub-systems and components of the power conditioner. By considering aging effects, it is fundamental to compute an appropriate time-dependent reliability distribution models to investigate the PEMFC reliability. In the following, by implementing the Monte Carlo simulation and the Weibull distribution, the reliability of five main components of the power conditioner is calculated for five years of operation. Then, a review and comparison of the reliability assessment of power conditioner are addressed using exponential and Weibull distributions. Furthermore, the maintenance is involved in establishing inspection and repair for once every month in an operational work period of five years. The results reveal an explicit evaluation of the use of distributions and the maintenance issues in assessing the reliability and the possibility of its generalization in power electronics.

ABSTRACT. Process optimization problem of additive manufacturing nowadays is a research hotspot in the field of manufacturing industry. However, parameter uncertainty has not been considered in the past. In this paper, the process optimization methods of additive manufacturing are reviewed, and a novel reliability-centered optimization combining stochastic finite element analysis (SFEA) with particle swarm optimization (PSO) method is proposed. Additionally, the whole model as well as the calculating flow have been explained in details. Finally, a case study has been investigated and results have verified the superiority of the proposed method.

ABSTRACT. The lifetime of power electronics modules is most often determined via analytical models which use accelerated test results as input. These lifetime tests usually assume experience-derived largely conservative values for the load pulse length, (so-called ton times), which lead to time/resource-consuming trial-and-error calibration work. Another way of investigating the effect of the thermo-mechanical stress on the components is to use numerical models to simulate the aforementioned tests. This work analyses the influence of the temperature swing and of the load pulse length (ton) on the lifetime of a representative sintered/soldered chip-on-substrate sample by means of the finite element method and sensitivity analysis.

ABSTRACT. Electro-thermal-mechanical simulation by Finite Element Model has been employed in fatigue analysis of a MOSFET structure under electro-thermal stress. Purpose of the simulation activity has been to estimate the effects of the solder layer thickness and tilt on device reliability. Thermal and power cycling have been simulated and stress, strain and number of cycles to failure have been evaluated. By simulation it has been observed that the solder area of maximum stress is located along the edge of the die and that the thickness increasing involves a gain in number of cycles to failure until a limit thickness is reached.

ABSTRACT. Y-source inverter has been proposed for a few years, but it inherits many problems from coupled-inductor impedance-source inverters (CISIs). So, many studies to address the issues of traditional Y-source inverter are now being carried out. However, the reliability of a field working Y-source inverter has never been studied. This paper proposed a modified topology of Y-source inverter that can solve the problems of its discontinuous input current and increase its boost ratio. The reliability of the proposed modified Y-source inverter is studied using Physics-of -Failure approach. The lifetime of the proposed topology is predicted under a real mission profile.

ABSTRACT. Since the replacement of hazardous materials by the RoHS directive, the intensive use of lead free solder materials generates countless studies to find new acceleration factors. In that scope, identifying the failure mechanisms involved in accelerated thermal tests has become of great concern for reliability design. Numerical tools are commonly developed for predictive analysis but their accuracy and capacity to be transposed to multiple technologies rely in part on the right choice of material behaviour. This study proposes to fit material coefficients of 4 different available creep laws to a same set of experiments. A unique couple of Finite Element models is defined using global / local calculations. The sub model represents a BGA bump that behaves following the Garofalo’s, Anand’s, Darveaux’s laws of creep. The discrepancies that can arise this comparison show how much care needs to be taken at that step of modelling for reliability prediction.

ABSTRACT. This paper proposes a system reliability modelling method for MMC system considering module redundancy and the physical-of-failure of the bond wires in IGBT module. Firstly, the unreliability of the IGBT module can be obtained based on the Monte Carlo analysis. Then, the distribution of the annual lifetime consumptionis estimated according to a long-term annual stress profile.Finally,the reliability ofthe MMC systemis estimated considering the module redundancy. Different redundancy settings are investigated and compared analytically.

ABSTRACT. Under some extreme operation conditions, such as external faults or load steps, the junction temperature would be danger for a semiconductor device. The traditional Cauer-type thermal model is fail to predict the junction temperature rising during the short pulse power. This paper proposes an improved Cauer-type thermal model by combining the transient thermal calculation into the model. The Finite Element Analysis (FEA) is used to validate the proposed model. A load current step condition is also performed to show the application of this model. The transient junction temperature estimation can provide a reference design for short circuit protection.

ABSTRACT. According to the reliability design requirements of the BMS, a distributed BMS was designed and the hardware of the BMS is divided into two modules that have the main control module and the sampling module. Focus on the main module and sampling module design, reliability and electromagnetic compatibility design, at the same time, the healthy state estimation, finally, the paper set the BMS test platform and the BMS was tested systematically, and the results show that the battery management system has high reliability.

ABSTRACT. In a turn off RCD snubber, the capacitor value is usually optimized by minimizing the power dissipated in the switch and the snubber. However, this is not the best value of the snubber capacitor from reliability point of view. In this paper, capacitor value was optimized based on reliability considerations. Proposed method presents a new capacitor value to achieve the maximum reliability for set of the switch and its snubber. The experimental results confirmed the validity of the theoretical analysis.

ABSTRACT. Cascaded DC-DC converters is commonly used in Electric and Hybrid Electric Vehicles. Stability analysis of cascaded DC-DC converters is a hot issue, since the interaction among the individual converter which can operate stably alone may lead to the instability of the whole system. The current researches mainly focus on the two-stage cascaded DC-DC converters. With the development of wide bandgap semiconductor devices and high-efficiency topologies, the application of cascaded system with multiple converters is promoted. Hence, it’s necessary to find a concise and accurate stability analysis method for cascaded DC-DC converters, especially for the cascaded system with multiple converters. In this paper, a time-domain stability analysis method with good extensibility for cascaded DC-DC converters is proposed. At the beginning, the stability criterion for cascaded DC-DC converters is derived by taking N-cascaded buck converters as an example. Further, a three-cascaded buck converters is studied as a concrete object and the theoretical results based on the proposed method are obtained. Finally, the accuracy of the proposed stability analysis method is verified by simulation and experimental results. Therefore, a concrete and effective stability analysis method with good extensibility is provided for cascaded DC-DC converters in this paper.

ABSTRACT. Traction drive system is an important part of rail transit vehicles, which directly determines whether the train can transport passengers safely, quickly and efficiently. For safety-critical and mission-critical applications, the reliability of traction drive system is still a concern. Studying the reliability of the traction drive system of rail transit vehicles has important guiding significance for the safe operation, after-sale maintenance and components replacement of rail transit. This paper reviews past developments and recent advance in the area of traction drive system reliability evaluation and presents challenges and future research directions in this area.

ABSTRACT. This paper proposes a novel Fault-Tolerant method for battery energy storage system (BESS) based on cascade multilevel converter. When batteries and battery management system (BMS) fail, the proposed method can achieve the active power distribution between different cascaded H-bridges with several batteries and several capacitors as dc sources. The stable operation region of proposed control method has been derived by vector analysis. The correctness and effectiveness of theoretical analysis has been verified by simulation.

ABSTRACT. Reliability and lifetime of high power IGBT multichip modules used in railway traction converters is key for traction manufacturers to meet operators requirements. High power IGBT multichip modules used today in railway traction are (sub)systems containing a (large) number of paralleled chips. Temperature distribution between paralleled chips in the module may induce predominant effects on performances and operational reliability. This paper presents an experimental set-up based on optical fibers to measure individual chip temperatures of a 6500 V – 750 A IGBT module during converter operation in real conditions of power and voltage. This set-up was used to study chip temperature distribution within high power IGBT multichip modules during different phases of converter operation and cooling conditions. It is also used to evaluate and validate different approaches of condition and health monitoring advanced functions based on indirect temperature measurements coupled with electro-thermal models.

ABSTRACT. Power utilization in digital circuits is based on system architecture, technology, basic cells and accuracy of given tasks. Low power utilization is the growing problem in IC design. For obtaining low energy consumption, the leakage power is mitigated by power gating technique. Regrettably, this technique introduces power to ground noise problem in circuits, which can be eliminated by the proposed N sleep shuffled phase damping technique. The need for the design is to improve lifetime reliability of today’s integrated systems. The proposed N sleep shuffled phase damping technique is designed to attain an increased reliability with high energy efficiency. This technique combines staggered phase damping and sleep transistor technique to reduce the leakage power and ground bouncing noise. Simulation results shows that proposed technique reduces the power consumption and energy to 10% and 19% respectively compared with the previous techniques.

ABSTRACT. The traction inverter is the power source of rail transit vehicles. Insulated Gate Bipolar Translator (IGBT) is the core component of the traction inverter. IGBT faults can cause serious problems in locomotive power supply system. The disadvantage of traditional fault detection methods for IGBT module is lack of real time and high efficiency. An on-line fault diagnosis method based on wavelet transform and multi-classification support vector machine (multi-SVM) is proposed for IGBT faults. Wavelet decomposition is used to process fault current signals and energy vectors are constructed. Multi-SVM is used to establish fault recognition model. The validity of this method is verified by simulation of MATLAB/Simulink.

ABSTRACT. The micro-grid usually uses energy storage system to stabilize the power fluctuations of DC bus caused by load changes. This paper uses a lithium battery and supercapacitor hybrid energy storage system (Li-SC HESS) to meet a demand of both the aspects of power and energy due to load changes. This paper researches on the model structure of hybrid energy storage system, and presents a PCH strong tracking control method for power coordinated allocation. Then it combines simscape to simulink, establishes an energy storage system model for photovoltaic (PV) micro-grid, and makes a comparative research with the conventional double-loop linear control, and also combines battery online monitoring system to establish the experimental system platform. The simulation and experimental results show that, the proposed HESS control strategy can effectively reduce lithium battery’s charging/discharging times, and smooth its charging/discharging process, with life span increasing, thereby improving the performance of the hybrid energy storage system. And it is also significant in making in-depth study of HESS’ power coordinated management in future.

ABSTRACT. Rail potential is affected by a variety of influence factors in the urban rail transit. This paper establishes a state space average (SSA) model of the traction power system to explore the effects caused by the traction network resistance, inductance, capacitance and rail-to-ground resistance. The SSA model solutions prove that the traction network inductance and capacitance have significant influences on rail potential. Moreover, based on the SSA model, the rail potential distribution of a metro line during the train timetable period is obtained for rail protections, which can improve the reliability of traction power system.

ABSTRACT. Permanent magnet synchronous motor (PMSM) is used in electric vehicle widely.However, the motor may have low frequency concussion due to the parameters of PMSM, or the parameters of controller, or external interference. In this paper, sliding mode speed controller is proposed in order to improve the dynamic quality of PMSM speed control system and suppress the phenomenon of low frequency concussion. The simulation and experimental results confirm the effectiveness of sliding mode speed controller compared with PI speed controller.