Signal and Power Integrity Analysis Using LIM – Recent Advances (abstract)

Practical aspects of FD-TDR co-modification for high-speed structures’ matching and what-if simulations (abstract)

Superconducting Circuit Quantum Computers: Fundamental Concepts and Scaling Challenges (abstract)

Chiplet Design and Heterogeneous Integration Packaging (abstract)

Abstraction for Heterogeneous Integration (abstract)

Packaging Technology for Next Generation mmWave Commmunications: Scalable Heterogeneous AiP Modules and the Future Role of Chiplets (abstract)

Accelerating AI with Chiplet Technology (abstract)

Multiphysics Simulation and Measurement Correlation of a Multichip Module IC Package Current Sensor (abstract)

Yield-Aware Interposer Design for UCIe Interconnects (abstract)

Efficient Thermal Analysis for Heat Dissipation in Three-Dimensional Chip-Stacking Packaging (abstract)

Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory (abstract)

Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network (abstract)

Optimization of TSV Array Based on Mathematical Model for HBM3 (abstract)

A Hybrid Polynomial Chaos Expansion and Gaussian Process Regression Method for Forward Uncertainty Quantification of Integrated Circuits (abstract)

Using Generative AI to Predict DC Electrical Performance (abstract)

Transformer Based Channel Identification (abstract)

Tree-Based Boosting for Efficient Estimation of S-Parameters for Package Electrical Analysis (abstract)

Tunable True-Time-Delay Unit Based on Bridged T-Coil (abstract)

Modeling Multiplexed Qubit Readout with a Josephson Traveling-Wave Parametric Amplifier (abstract)

Latency Insertion Method for Fast Electro-Thermal Simulation of FinFET with Self-Heating Effect (abstract)

Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing (abstract)

Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors (abstract)

Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz (abstract)

A DDR5 Interposer De-embedding Method Based on Transfer Function (abstract)

Parametric S-Parameter Prediction Using Deep Learning (abstract)

Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions (abstract)

Impact of Non-Functional Pads Location on Eye Diagram Performance (abstract)

High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing (abstract)

Analysis of Nonlinear Phase Interactions of a Differential Line in the Presence of a Signal Skew (abstract)

A 155 MHz Low-Jitter PLL for Enhanced Signal Integrity in High-Speed Interconnects (abstract)

Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate (abstract)

PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel (abstract)

Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6 (abstract)

Agile Analysis for Worst-Case Eye-Diagrams in Multi-Line Links of CoWoS Packaging (abstract)

A Signal Integrity Comparison of VIPPO Technology for PCIe 5.0 DC Blocking Capacitors (abstract)

Analysis of Interconnects in Multilayer SIW Bandpass Filters Design (abstract)

Design of an Ultra-High-Speed Digital Interface Based on a Coplanar Stripline (abstract)

Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System (abstract)

Keynote 2 - Advanced Chiplet Package Signal Integrity for Future Data Center and AI (abstract)

A Model Amongst us of the highest Order who can never be Replicated

Nonlinear macromodeling of voltage-regulated power delivery networks (abstract)

Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations (abstract)

Gradient-based method to find solution for Rational Polynomial Chaos coefficients for Uncertainty Quantification (abstract)

Automated Accurate Quadratic Formulation of Nonlinear Circuits (abstract)

Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch (abstract)

Modeling Microwave S-parameters using Frequency-scaled Rational Gaussian Process Kernels (abstract)

On the Parallelization of the MultiAIM Algorithm for the Fast Electromagnetic Analysis of 3D ICs (abstract)

Accuracy Study of the Differential Surface Admittance Operator for Lossy Metal Characterization (abstract)

A Highly-Scalable Parallel Boundary Element Method for the Full-Wave Electromagnetic Analysis of Large Interconnect Networks and Entire Packages (abstract)

Analysis of Echo and Crosstalk Cancellation in Simultaneous Bidirectional Transceivers for Dense Die-to-Die Interconnects (abstract)

Efficient parametric assessment of worst-case voltage droop in power delivery networks (abstract)

PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning (abstract)

PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements (abstract)

Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk (abstract)

Electro-Thermal-Mechanical Design Workflow for Printed Circuit Boards and Electronic Packages (abstract)

Ensuring the Power and Signal Integrity of Your High-Performance PCBs and Packages Using Ansys SIwave (abstract)

Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) (abstract)

Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) (abstract)

Limit of the Impact of the Via Stub Length on the Via Impedance in Printed Circuit Boards (abstract)

Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π-Type Filtering Structure (abstract)

A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency (abstract)

Simulation method for Quasi-static solver to effectively model parasitic components between Package and PCB (abstract)

Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module (abstract)

Recent Advances in Signal Integrity Simulation and Analysis of Interposers (abstract)

Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration (abstract)

Compact Fiber Weave Model for Full Wave Solvers (abstract)

Megtron 6 and 8 Characterization Methodology (abstract)

Full-Wave Analysis for Ground Via Placement with Layered Media Integral Equations (abstract)

Causal RL Prediction of Fine-Pitch Interconnects Using Neural Networks (abstract)

A robust optimization approach for High Bandwidth Memory interposer using Machine Learning (abstract)

Analysis and Modeling of Controlled Silicon Substrate Roughness for Silver-Based Backside Metallization in Power Electronics Packaging (abstract)

Worst-Case Voltage Droop Using Peak Distortion Analysis (abstract)

Equalization Techniques for Time Domain Signalling (abstract)

Machine Learning for EDA, or EDA for Machine Learning? (abstract)

Reinforcement Learning Based Automatic Router for Power Delivery Network Prototypes (abstract)

An Efficient Machine Learning Approach for PSIJ Analysis in a Chain of CMOS Inverters (abstract)

Hand-drawn Circuit Schematic Digitization and Netlisting using Machine Learning with Emphasis on Signal Integrity Applications (abstract)

A Tunable Inductor Peaking Technique for Optical Communication Systems (abstract)

Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics (abstract)

Digital Twin PI Simulations for 2000 Amp AI, Cloud Compute, and Multi-Die Packages (abstract)

Delay Rational Macromodelling of Noisy Tabulated Frequency Responses (abstract)

An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape (abstract)

Application of the Reverse Pulse Technique for Worst Case Transient Analysis in HPC PDN Design (abstract)

Optimizing Power and Power Delivery For Data Center GPUs (abstract)