ABSTRACT. Advanced Packaging Chiplet technologies have enabled large-scale deployment of heterogenous compute to address the disparate demands of the mega data center and the voraciously growing machine intelligence market. These advanced server CPU and GPU based systems require very high chip-to-chip IO connectivity and memory bandwidths with strict power, area, and latency optimization for scaling up and scaling out of rack-based systems. While dense integration brings together new capacity to solve the industry’s most pressing problems, these Chiplets and high-power systems have abundant mechanical complexity and sensitivity to manufacturing variation. Even minor imperfections can have a profound impact on signal-to-noise margin at large scale system production. This discussion is an overview of the unique signal and power integrity design challenges for building these advanced Chiplet based products and systems with low defect rate requirements.

ABSTRACT. We introduce a frequency-domain macromodeling approach that generalizes Vector Fitting to mildly nonlinear systems, such as power delivery networks including integrated voltage regulators described by averaged models. The proposed approach overcomes the limitation of linearized descriptions, and leads to a black-box nonlinear macromodel of the entire power distribution network with drastically enhanced accuracy.

ABSTRACT. We use operator inference for the accelerated simulation of rigid-flex printed circuit boards (PCBs). Nonlinear behavior associated with large deformation of rigid-flex PCBs is captured by polynomial terms in the model structure.

ABSTRACT. Rational Polynomial Chaos (RPC) is an emerging method for forming the surrogate model for uncertainty quantification in circuit applications. However, the use of Rational Polynomial Chaos can be prohibitive as it generally requires a large number of samples to generate the surrogate models. In this paper, we propose the use of a gradient-based algorithm to solve for the Rational Polynomial Chaos coefficients. Using the proposed approach we can compute the RPC coefficients with fewer samples than the traditional RPC method.

ABSTRACT. A new approach to automate the modelling of general nonlinear circuits in a quadratic type nonlinearity is presented. The proposed quadratic model is characterized by high accuracy when used in numerical simulation such as time marching.

ABSTRACT. A metal-oxide-semiconductor field-effect transistor (MOSFET) power switch is an electronic device that acts as a voltage-controlled current source. One critical aspect of the power switch's performance is its ability to dissipate heat into the environment efficiently. However, optimal dissipation is influenced by the combined effect of the device's electrical and thermal behavior. While standard methods such as increasing die and package sizes, using heat sinks, and employing top-side and immersion cooling techniques have improved heat dissipation, they mainly focus on the device's thermal behavior with little consideration for the electrical aspect. Additionally, these approaches come with added costs, making them less feasible for high-volume applications. This paper details a coupled electrothermal modeling, analysis, and silicon-package physical co-design optimization of an ultra-low on-resistance MOSFET power switch integrated circuit. Achieving optimal performance at the lowest cost is demonstrated successfully here by implementing the coupled modeling methodology early in the design phase of the power switch.

ABSTRACT. This work presents a machine learning technique to model the complex-valued scattering parameters (S-parameters) of passive microwave devices as a function of frequency and a set of design variables. The proposed Gaussian process (GP) model intricately models the real and imaginary parts of the S-parameters by employing a physics-informed kernel, adept at representing complex holomorphic functions and incorporating the Hermitian symmetry inherent in scattering parameters. Additionally, to extend the kernel's capabilities to higher dimensions beyond standard GP techniques, it is extended with a frequency scaling, enhancing the modeling capacity. The resulting physics-informed frequency-scaled GP model accurately predicts the S-parameter values at desired parameter configurations in the design space. One application example demonstrates the superiority of the new kernel, compared to standard GP kernels.

ABSTRACT. We propose a parallelization strategy for the MultiAIM algorithm, to accelerate the electromagnetic analysis of multiscale integrated circuit layouts. We devise a solution for shared memory architectures. With a careful choice of numerical libraries, we achieve a code that can be easily adapted to distributed-memory clusters. Preliminary tests on a commercial 3D integrated circuit show good scalability up to 32~cores, and outline a few directions for further improvements.

ABSTRACT. The analytic, complete solution of a boundary integral formulation consisting of the electric field integral equation (EFIE) and the differential surface admittance (DSA) operator is presented for lossy conductors. Through a Galerkin Method of Moments with two complete sets of orthogonal vector spherical harmonics as basis functions, the complete system of equations is solved, including a closed-expression for the DSA elements via a generalized Fourier series. A comparison with the Mie series solution shows the range and accuracy of the DSA-EFIE formulation in dealing with lossy materials, and paves the way for a future study into the operator's fundamental properties, leading to improved tools for interconnect modeling.

ABSTRACT. We demonstrate a scalable parallelization strategy for an advanced boundary element method suitable for the full-wave electromagnetic analysis of very large interconnect networks and packages. A new preconditioning technique and charge neutrality enforcement strategy show significant promise to overcome the scalability bottlenecks of existing methods. The proposed method is scaled up to 10,240 cores, extracting the scattering parameters of a complete electronic package in less than 2.5 minutes per excitation and frequency point.

ABSTRACT. The impact of echo and crosstalk cancellation in die-to-die interconnect links that employ simultaneous bidirectional (SBD) signaling is analyzed in the context of a 24-wire transceiver operating over a four-layer interposer. Simulation results show that these techniques allow for a 4-rank transceiver system with 40µm bump pitch to occupy only 240µm die edge width and signal up to 128Gb/s per data channel wire over a very tight 4µm signal-to-signal pitch, resulting in a 46.9Tb/s/mm edge density. The proposed crosstalk cancellation circuitry can compensate for power-sum near-end crosstalk (PSNEXT) and far-end crosstalk (PSFEXT) of -22.43dB and -23.69dB, respectively, at 32GHz and improve the inbound signal voltage margin by 22% at a BER=10^−12.

ABSTRACT. Power Delivery Network (PDN) optimization is crucial for guaranteeing adequate power integrity performance in modern microprocessor systems. In this work, we introduce a novel surrogate modeling workflow for efficiently predicting the worst-case voltage droop occurring at the loading points of a PDN including a set of free design parameters. We apply the proposed approach for modeling the impact of a set of decoupling capacitors on the performance of a template PDN structure.

ABSTRACT. In this paper, we first propose power supply noise induced jitter (PSIJ) based optimal power distribution network (PDN) design using reinforcement learning (RL) to achieve costeffective solid state drive (SSD). PSIJ is increasingly accounting for a larger portion of the overall jitter margin. Compared to the traditional PDN impedance design, designing based on PSIJ, which includes current noise and timing information, allows for more precise PDN optimization. The proposed method allows for the development of an optimal PDN design that meets the target PSIJ with minimal decoupling capacitor (decap) area usage. In order to achieve a cost-effective SSD board design, the RL reward includes both PSIJ and the decap area. This enables the RL agent to learn to satisfy the target PSIJ using minimal resources from decap library. To derive PSIJ, the process includes adding decaps to the z-parameters of the SSD board's PDN plane to extract PDN impedance and modeling PSIJ in the frequency domain through jitter sensitivity. Finally, the successful optimization is demonstrated through performance comparison with a representative genetic algorithm (GA).

ABSTRACT. This paper estimates and analyzes the power supply noise induced jitter (PSIJ) caused by system-level power noises in high-capacity PCI express (PCIe) Gen 6.0 SSDs. To guide optimal design of the hierarchical power distribution network (PDN) with consideration of PSIJ before mass production, a measurement-based jitter sensitivity function (JSF) is employed during the PCIe PHY IP chip-level verification stage. For accurate JSF measurement, it must be ensured that the 64 Gbps PAM-4 eye of the PCIe interface is open during operations. In this paper, we propose a test architecture that can measure signal jitter with PAM-4 eyes opened while removing decoupling capacitors (de-caps) at the off-chip level so that single tone power noise applied to the off-chip test point (TP) can be transmitted safely to the on-chip stage without filtering. Using a hierarchical PDN model of the proposed test architecture, JSF was extracted in the 300 kHz to 300 MHz frequency range, considering the voltage transfer ratio (VTR) from TP to the target die bump. We confirmed, for the first time, that PSIJ caused by worst-case system power noise in a high-capacity PCIe Gen 6.0 SSD operating at full performance is estimated to be 1.32 ps, which corresponds to 42.2 % of the eye width specification of the PCIe Gen 6.0 base specification.

ABSTRACT. The M.2 connector has been widely adopted in the host interface of client Solid State Drives (SSDs) for high-speed data storage in consumer electronics. The pin arrangement of the M.2 connector, where transmitter (TX) and receiver (RX) lines are positioned adjacent, can lead to issues such as near-end crosstalk (NEXT). Particularly, with the upcoming PCI Express (PCIe) Gen 6.0 standard, concerns arise over the potential degradation of NEXT in M.2 connectors, which could negatively affect SSD performance and reliability. This paper analyzes the signal integrity (SI) requirements for connectors to ensure the host interface of SSDs operates reliably at PCIe Gen 6.0 speed. We investigate whether the NEXT in existing M.2 form factors for client SSDs meets these requirements and experimentally examine its impact on PCIe Gen 6.0 64 Gb/s PAM-4 eye diagram at the system level. Furthermore, by applying Compression Attached Memory Module 2 (CAMM2) to the SSD PCIe interfaces, we experimentally demonstrate the capability to reduce NEXT by over 50 % compared to M.2 and limit PAM-4 eye degradation to less than 1 %. This illustrates how CAMM2 connector can overcome the limitations of M.2 connector and enhance performance in PCIe Gen 6.0.

ABSTRACT. This paper outlines a comprehensive workflow using Ansys tools to address electrical, thermal, and mechanical design challenges in printed circuit boards (PCBs). The methodology, applicable to various ECAD types including IC packages and silicon interposers, systematically explores critical aspects of PCB design. Through Multiphysics simulations, power dissipation, thermal performance, and mechanical integrity can be analyzed. By evaluating temperature distributions for IC chips and the board, one can assess compliance with safety limits and predict overall PCB reliability, considering components and heat sinks.

ABSTRACT. Ansys SIwave is a specialized design platform for DC, power & signal integrity as well as EMI analysis of IC packages and PCBs. SIwave helps you model, simulate and validate high-speed channels and complete power delivery systems typical in modern high-performance electronics. It accurately extracts multi-gigabit SERDES and memory buses, providing product sign-off compliance for various designs. This introductory webinar will provide an overview of the SIWave tool, review the different solvers and techniques within SIwave and present some of the workflow automation capabilities. We will also briefly describe how SIwave can integrate with thermal and structural simulation to allow a more complete understanding of in-service performance.

ABSTRACT. This paper proposes the extended scale cache (ESC) stacked-graphics processing unit (GPU)-high bandwidth memory (HBM) module architecture. The main concept of the proposed architecture involves stacking an ESC, which is an L2 cache, atop a GPU to decrease off-chip data movement, thereby reducing power consumption and latency. However, the simultaneous switching noise (SSN) of the proposed architecture is increased due to additional switching noise transferred from the ESC to the GPU cores, leading to degraded power integrity (PI) performance. To ensure stable PI performance of the proposed architecture, we design and analyze the hierarchical power distribution network (PDN) of the proposed architecture and the simultaneous switching current (SSC) for both the GPU and ESC. Additionally, we conduct modeling and analysis of the SSN of the proposed architecture. By employing decoupling capacitors (decaps) with a total capacity of 1,152 nF, the SSN of the proposed architecture is reduced to 3.96 mV, which is 0.36% of the supply voltage (VDD), demonstrating that the proposed architecture guarantees reliable PI performance.

ABSTRACT. In this paper, for the first time, we propose an explainable reinforcement learning (XRL)-based decap placement optimization method for high bandwidth memory (HBM) considering power integrity (PI). The proposed XRL-based method enhances explainability by transforming the sum of various types of rewards into a vector sum operation for the trained model. A CNN-based network was used for training, with each reward considered from a multi-objective RL perspective. To verify the proposed method, we applied it to solve the problem of placing decaps at VDDQ domain of HBM3 module. In this paper, rewards were set as the suppression of self-impedance and transfer-impedance at each probing port. The proposed method achieved improvements of 2.8% compared to usage of general scalar sum reward. Ultimately, the vector differences in the Q-value for different actions provided grounds for action taken and allowed for the evaluation of whether the model was well-trained.

ABSTRACT. This paper investigates the impedance discontinuities due to residual via stubs for a differential via pair. Different stub lengths are investigated. The influence of the stub is comparable to the influence of the via pad.

ABSTRACT. In this article, we studied the phenomenon of test failures in CLK phase noise assessment, identifying the antiresonance in the power supply network of clock chip. We found that the jitter of the CLK signal is strongly correlated with the filtering effect of the power supply network of the clock chip. To improve the jitter performance of CLK signal, we implemented a π-type filtering structure into the existing circuit topology. This modification successfully mitigated the antiresonance peak. In order to minimize jitter as much as possible, we have optimized and compared the π-type filtering structure from simulation and test perspective. Finally, we have provided a general conclusion regarding this issue.

ABSTRACT. This article is dedicated to solving the problem of how to help engineers to optimize the power filtering circuit design. Through a thorough investigation, we discovered a significant relationship between the total capacitance in the circuit and the occurrence of antiresonance point. When the ferrite bead or inductor is constant, an increase in the total circuit capacitance leads to a proportional decrease in the antiresonance frequency. This inverse relationship is mathematically expressed in Eq. (4), which illustrates the ratio between the increase in capacitance and the corresponding decrease in antiresonance frequency. The finding contributes to a deeper understanding to the PDN (power distribution network) design and offers insights for optimizing circuit design to minimize the impact of antiresonance phenomenon.

ABSTRACT. A methodology to simulate Package and PCB with a quasi-static solver is developed. The widespread cascade method, where Package and PCB are first simulated standalone to reduce the required computational effort and then recombined, is improved to consider electromagnetic interactions between the two systems. The proposed approach provides results very similar to that achieved with the full system simulation, but with a computational cost that is very similar to that of the standard cascade method.

ABSTRACT. In this paper, we propose an ultra-high bandwidth (UHB) graphic processing unit (GPU)-ring structure for next- generation superchip modules. The interconnection via switches in multi-GPU system involves high latency and power consumption, which undermines the performance of artificial intelligence (AI). To address this issue, UHB GPU-ring architecture connects 4 GPU-high bandwidth memory (HBM) modules with short interconnection and high data rate on the same computing node. Proposed UHB GPU-ring architecture integrates the GPU-HBM modules directly, which enables to function 4 GPU-HBM modules as 1 module, decreasing the non-uniform memory access (NUMA) effect. To ensure the signal integrity of the proposed UHB GPU- ring, we designed the hardware system with the continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE) at the receiver referring to Peripheral Component Interconnect Express (PCIe) 5.0 system. As a result, we verified 32TB/s bandwidth and 0.6 pJ/bit between GPU-HBM modules, which enhances bandwidth by 17.7 times and energy consumption by 2.5 times. The result showed that the UHB GPU-ring can be a promising solution for the next generation superchip module.

ABSTRACT. This paper presents recent advances for analyzing signal integrity in interposer-based interconnect systems. It proposes a BEM solver methodology show that reduces the computational resources by over 40 times compared to FEM.

ABSTRACT. This paper presents an efficient and accurate method to perform multiphysics-informed floorplan and placement of heterogeneously integrated chiplets. Traditional multiphysics simulations, often impractical in optimization due to high computational cost, are replaced by a high-fidelity and efficient generative model via image-based machine learning (ML). Utilizing the ML model for fast performance assessment, we further accelerate the physical design by developing a dynamic rank-revealing algorithm for solving the underlying large-scale constrained optimization problem. Application to chiplet floorplanning and comparison with prevailing methods have demonstrated the superior performance of the proposed work.

ABSTRACT. n modern, high-speed PCBs, the fiber weave effect can introduce differential in-pair skew leading to eye closure. Using 3D solvers, skew was computed by constructing simplified 4-cell models directly from datasheets.

ABSTRACT. Laminate characteristics play an important role in design and simulation. We establish a methodology to electrically characterize two types of laminates (Megtron 6 and Megtron 8) using two methods: measurement-based model and de-embedding.

ABSTRACT. As signaling rates exceed 40 Gbps, detailed electromagnetic analysis of the Ground Return Vias (GRVs) becomes essential. Incorrect GRV placement, whether too far apart or poorly arranged in a ball-grid array, can cause a signal via's insertion loss (IL) to increase substantially. Historically, signal integrity (SI) engineers have placed GRVs near signal layer transitions following conventional practices, often without a precise understanding of the optimal quantity and spacing required. This paper proposes accurate full-wave electromagnetic analysis framework for via placement optimization. The method solves the layered medium Mixed Potential Integral Equation (MPIE) coupled with the Surface-Volume-Surface Electric Field Integral Equation (SVS-EFIE), making it suitable for analyzing composite 3D metal/dielectric structures within layered substrates encountered in GRV placement problems.

ABSTRACT. In this study, we compare physics-aware neural networks for modeling fine-pitch interconnects. Results show a 5-fold reduction in test loss when imposing DC resistance through analytical equations and preserving the causality relation between resistance and inductance.

ABSTRACT. Conventional optimization approaches are computationally inefficient and insufficient for time-sensitive optimization exercises. This paper presents a machine learning (ML) based approach to optimize the interposer structure of High Bandwidth Memory (HBM) by optimizing channel parameters.

ABSTRACT. In this paper, the analysis of a controlled structuration approach of the silicon (Si) substrate surface roughness through standard acidic wet chemical etching is proposed for the first time, for silver-based backside metallization (BSM) in power electronics packaging applications. Periodically spaced circular openings with diameters and separation distances from 1 um to 5 um were patterned using maskless laser lithography and wet etched in a Si substrate with a standard acidic HNP (HF:HNO3:H3PO4) mixture for 30s. The etched cavities were characterized by scanning electron microscopy (SEM). The extracted etching parameters from SEM observations were used to implement simple analytical models for the estimation of the average arithmetic surface roughness Ra and the normalized etching depth (with respect to the opening’s diameter after etching) as a function of the circular openings’ dimensions, separation distance and the corresponding underetch. Roughness values ranging from 165 nm to 555 nm were estimated depending on the design specifications. A good correlation was observed between the experimental and theoretical values of the normalized etching depth. The introduced approach allows a rapid estimation of the surface roughness after etching without the need for photoresist removal for profilometry or AFM measurements, which makes it suitable for both rapid prototyping as well as for additional etching cycles after SEM if needed.

ABSTRACT. This paper introduces a method for calculating the worst-case voltage droops experienced by a power distribution network. Through peak distortion analysis, each port in a multiport model is stimulated to produce patterns that will result in a large voltage swing at a selected observation point. This approach enables power integrity engineers to anticipate worst-case scenarios at the beginning of the design process and initiate the optimization of power delivery. The methodology is demonstrated using a real system as an example.

ABSTRACT. This paper describes inter-symbol interference (ISI) and crosstalk correction techniques for time domain signaling. The two novel digital equalization techniques introduced in this work can improve the data rate to 40 Gb/s compensating 40 dB loss demonstrating 15 to 20 dB additional loss compensation capability compared to traditional equalization techniques. Similarly, crosstalk cancellation technique can achieve 20 dB reduction of crosstalk noise without any additional signal processing.