Program for Tuesday, October 8th: Talk View

PROGRAM FOR TUESDAY, OCTOBER 8TH: TALK VIEW

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View: with abstracts session overview

8:00

8:30

9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

18:00

18:30

19:00

19:30

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20:30

21:00

21:30

22:00

09:00-10:00

Keynote 2 - Advanced Chiplet Package Signal Integrity for Future Data Center and AI

Dean Gonzales

10:00-10:20

A Model Amongst us of the highest Order who can never be Replicated

Madhavan Swaminathan

10:20-10:40

Nonlinear macromodeling of voltage-regulated power delivery networks

Antonio Carlucci, Stefano Grivet-Talocia

10:40-11:00

Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations

P. den Boef, W. Schilders, J. Maubach, N. van de Wouw, D. Manvelyan

11:20-11:40

Gradient-based method to find solution for Rational Polynomial Chaos coefficients for Uncertainty

Karanvir Singh Sidhu, Roni Khazaka

11:40-12:00

Automated Accurate Quadratic Formulation of Nonlinear Circuits

Germin Ghaly, Emad Gad, Michel Nakhla

12:00-12:20

Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch

S. Ankamah-Kusi, B. Travis, S. Kamath, R. Murugan, T. Kronenberg

12:20-12:40

Modeling Microwave S-parameters using Frequency-scaled Rational Gaussian Process Kernels

Thijs Ullrick, Dirk Deschrijver, Wim Bogaerts, Tom Dhaene

14:00-14:20

On the Parallelization of the MultiAIM Algorithm for the Fast Electromagnetic Analysis of 3D ICs

Yongzhong Li, Piero Triverio

14:20-14:40

Accuracy Study of the Differential Surface Admittance Operator for Lossy Metal Characterization

Martijn Huynen, Vladimir Okhmatovski, Daniël De Zutter, Dries Vande Ginste

14:40-15:00

A Highly-Scalable Parallel Boundary Element Method for the Full-Wave Electromagnetic Analysis of Large Interconnect Networks and Entire

Damian Marek, Jasper Hatton, Yongzhong Li, Piero Triverio

15:00-15:10 EPEPS 2025 Announcement

15:30-15:50

Analysis of Echo and Crosstalk Cancellation in Simultaneous Bidirectional Transceivers for Dense Die-to-Die

Tong Liu, Taeyang Sim, Samuel Palermo

15:50-16:10

Efficient parametric assessment of worst-case voltage droop in power delivery networks

T. Bradde, A. Carlucci, R. Trinchero, P. Manfredi, S. Grivet-Talocia

16:10-16:30

PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning

Shin, Choi, Ahn, Kim, Lee, Suh, Park, Kim, An, Song, Kim

16:30-16:50

PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements

Ko, Song, Hong, Lee, Jeong, Kim, Jang, Jin, Roh, Choi, Kim, Chun

16:50-17:10

Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk

Jin, Song, Hong, Ko, Kim, Roh, Jang, Choi, Kim, Chun

15:30-16:00

Electro-Thermal-Mechanical Design Workflow for Printed Circuit Boards and Electronic Packages

Satyajeet Padhi

16:00-16:30

Ensuring the Power and Signal Integrity of Your High-Performance PCBs and Packages Using Ansys

Laila Salman

17:10-18:20

Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity

Park, Choi, Kim, Shin, Son, Yoon, Lee, Suh, Kim, Ahn, An, Kim

Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory

Kim, Park, Son, Choi, Shin, Lee, Yoon, An, Kim, Choi, Choi, Kim

Limit of the Impact of the Via Stub Length on the Via Impedance in Printed Circuit Boards

Katharina Scharff, Xiaomin Duan, Dierk Kaller

Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π-Type Filtering

Xinlin Tang, Shuxiang Li, Tao Fang, Yuan Fang

A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency

Shuxiang Li, Xinlin Tang, Tao Fang, Yuan Fang, Greg Fu, Stephen Scearce

Simulation method for Quasi-static solver to effectively model parasitic components between Package and

Silvia Simone, Fabio Pareschi, Davide Lena, Gianluca Setti

Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip

Ahn, Choi, Shin, Lee, Yoon, Kim, Son, Suh, Kim, Park, An, Song, Kim

Recent Advances in Signal Integrity Simulation and Analysis of Interposers

Jonatan Aronsson, Feng Ling

Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration

C. Do Nascimento, Hwang, Smith, Qiu, Koh, Subbarayan, Jiao

Compact Fiber Weave Model for Full Wave Solvers

Stefan de Araujo, Daniel de Araujo, Bhyrav Mutnury

Megtron 6 and 8 Characterization Methodology

Stefan de Araujo, Daniel de Araujo, Roger Delbue, Ryan Keegan

Full-Wave Analysis for Ground Via Placement with Layered Media Integral Equations

Alireza Niazi, Vladimir Okhmatovski

Causal RL Prediction of Fine-Pitch Interconnects Using Neural Networks

Hasan Said Unal, Ahmet Cemal Durgun

A robust optimization approach for High Bandwidth Memory interposer using Machine Learning

Anandajith Jinesh, Xuan Chen

Analysis and Modeling of Controlled Silicon Substrate Roughness for Silver-Based Backside Metallization in Power Electronics

Mohamed Bellaredj, Goran Miskovic, Luka Vojkuvka

Worst-Case Voltage Droop Using Peak Distortion Analysis

Mohamed Sahouli, Isaac Ali, David Reinamendivil, Gerry Talbot

Equalization Techniques for Time Domain Signalling

Shakib Mahmood, Parneet Tethy, Richelle L. Smith, Carl W. Werner, Masum Hossain

18:20-18:30 Bus pickup

19:00-19:15 Check in at the CN Tower

19:15-20:30 Cocktail Reception and Awards Ceremony

20:30-22:00 Conference Dinner

08:00-09:00 Breakfast

11:00-11:20 Coffee Break

12:40-14:00 Lunch

15:10-15:30 Coffee Break