Talk Author Index

TALK AUTHOR INDEX

Shortcuts: A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

A
Achar, Ramachandra	An Efficient Machine Learning Approach for PSIJ Analysis in a Chain of CMOS Inverters Hand-drawn Circuit Schematic Digitization and Netlisting using Machine Learning with Emphasis on Signal Integrity Applications
Ahmed, Shameem	Impact of Non-Functional Pads Location on Eye Diagram Performance
Ahn, Jungmin	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Ahn, Seungyoung	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
Ahn, Sung-Oh	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
Akinwale, Oluwafemi	Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions
Ali, Isaac	Worst-Case Voltage Droop Using Peak Distortion Analysis
An, Hyunjun	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Ankamah-Kusi, Sylvester	Multiphysics Simulation and Measurement Correlation of a Multichip Module IC Package Current Sensor Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch
Araga, Yuuki	Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate
Aronsson, Jonatan	Recent Advances in Signal Integrity Simulation and Analysis of Interposers
Asadi, Reza	Impact of Non-Functional Pads Location on Eye Diagram Performance
Aygun, Kemal	Tree-Based Boosting for Efficient Estimation of S-Parameters for Package Electrical Analysis
B
Bae, Taeil	Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Bakir, Muhannad	Yield-Aware Interposer Design for UCIe Interconnects
Bandi, Sathvika	Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Bansal, Vinayak	Parametric S-Parameter Prediction Using Deep Learning
Bao, Tina	Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
Barnes, Heidi	Digital Twin PI Simulations for 2000 Amp AI, Cloud Compute, and Multi-Die Packages
Baydoğan, Mustafa Gökçe	Tree-Based Boosting for Efficient Estimation of S-Parameters for Package Electrical Analysis
Bellaredj, Mohamed	Analysis and Modeling of Controlled Silicon Substrate Roughness for Silver-Based Backside Metallization in Power Electronics Packaging
Benner, Peter	Parametric S-Parameter Prediction Using Deep Learning
Bogaerts, Wim	Modeling Microwave S-parameters using Frequency-scaled Rational Gaussian Process Kernels
Bracken, Eric	Using Generative AI to Predict DC Electrical Performance
Bradde, Tommaso	Efficient parametric assessment of worst-case voltage droop in power delivery networks
C
C. Do Nascimento, Vinicius	Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
Cai, Kevin	Impact of Non-Functional Pads Location on Eye Diagram Performance
Carlucci, Antonio	Nonlinear macromodeling of voltage-regulated power delivery networks Efficient parametric assessment of worst-case voltage droop in power delivery networks
Carta, Corrado	A Tunable Inductor Peaking Technique for Optical Communication Systems
Carusone, Tony Chan	Accelerating AI with Chiplet Technology
Chang, Zhu-Chen	Agile Analysis for Worst-Case Eye-Diagrams in Multi-Line Links of CoWoS Packaging
Chen, Jie	Multiphysics Simulation and Measurement Correlation of a Multichip Module IC Package Current Sensor
Chen, Xu	Yield-Aware Interposer Design for UCIe Interconnects
Chen, Xuan	A robust optimization approach for High Bandwidth Memory interposer using Machine Learning
Chen, Yen-Tung	Optimization of TSV Array Based on Mathematical Model for HBM3
Cheng, Chris	Transformer Based Channel Identification
Cheng, Yu-Ying	Optimization of TSV Array Based on Mathematical Model for HBM3
Cho, Chulhee	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Cho, Young-Chul	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Choi, Dongho	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Choi, Hyun-Chul	Design of an Ultra-High-Speed Digital Interface Based on a Coplanar Stripline Analysis of Nonlinear Phase Interactions of a Differential Line in the Presence of a Signal Skew
Choi, Jung-Hwan	Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Choi, Seonguk	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Choi, Sumi	Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System
Choi, Wooshin	Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Choi, Yongjin	Transformer Based Channel Identification
Chu, Xiuqin	A DDR5 Interposer De-embedding Method Based on Transfer Function
Chun, Sunghoon	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Cocchini, Matteo	A Signal Integrity Comparison of VIPPO Technology for PCIe 5.0 DC Blocking Capacitors
D
de Araujo, Daniel	Megtron 6 and 8 Characterization Methodology Compact Fiber Weave Model for Full Wave Solvers
de Araujo, Stefan	Megtron 6 and 8 Characterization Methodology Compact Fiber Weave Model for Full Wave Solvers
de la Rubia, Valentin	Parametric S-Parameter Prediction Using Deep Learning
De Zutter, Daniël	Accuracy Study of the Differential Surface Admittance Operator for Lossy Metal Characterization
Delbue, Roger	Megtron 6 and 8 Characterization Methodology
den Boef, Pascal	Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations
Deschrijver, Dirk	Modeling Microwave S-parameters using Frequency-scaled Rational Gaussian Process Kernels
Dhaene, Tom	Modeling Microwave S-parameters using Frequency-scaled Rational Gaussian Process Kernels
Dounavis, Anestis	Delay Rational Macromodelling of Noisy Tabulated Frequency Responses
Duan, Xiaomin	Limit of the Impact of the Via Stub Length on the Via Impedance in Printed Circuit Boards
Durgun, Ahmet Cemal	Causal RL Prediction of Fine-Pitch Interconnects Using Neural Networks Tree-Based Boosting for Efficient Estimation of S-Parameters for Package Electrical Analysis
E
Elkin, Samuel	Modeling Multiplexed Qubit Readout with a Josephson Traveling-Wave Parametric Amplifier
Eslampour, Hamid	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
F
Fang, Tao	A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π-Type Filtering Structure
Fang, Yuan	A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π-Type Filtering Structure
Feng, Lihong	Parametric S-Parameter Prediction Using Deep Learning
Franzon, Paul	Transformer Based Channel Identification
Fu, Greg	A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency
G
Gad, Emad	Automated Accurate Quadratic Formulation of Nonlinear Circuits
Gerba, Olani Baissa	A 155 MHz Low-Jitter PLL for Enhanced Signal Integrity in High-Speed Interconnects
Ghaly, Germin	Automated Accurate Quadratic Formulation of Nonlinear Circuits
Gonzales, Dean	Keynote 2 - Advanced Chiplet Package Signal Integrity for Future Data Center and AI
Grivet-Talocia, Stefano	Nonlinear macromodeling of voltage-regulated power delivery networks Efficient parametric assessment of worst-case voltage droop in power delivery networks
Guo, Mengmeng	Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
H
Haider, Clifton	Application of the Reverse Pulse Technique for Worst Case Transient Analysis in HPC PDN Design
Haider, Michael	Modeling Multiplexed Qubit Readout with a Josephson Traveling-Wave Parametric Amplifier
Hatton, Jasper	A Highly-Scalable Parallel Boundary Element Method for the Full-Wave Electromagnetic Analysis of Large Interconnect Networks and Entire Packages
Hickman, Alexander	Application of the Reverse Pulse Technique for Worst Case Transient Analysis in HPC PDN Design
Hong, Seokwoo	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Hossain, Masum	Equalization Techniques for Time Domain Signalling
Huynen, Martijn	Accuracy Study of the Differential Surface Admittance Operator for Lossy Metal Characterization
Hwang, Seunghyun	Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
I
Iseini, Festim	A Tunable Inductor Peaking Technique for Optical Communication Systems Tunable True-Time-Delay Unit Based on Bridged T-Coil
J
Jain, Ashish	Optimizing Power and Power Delivery For Data Center GPUs
Jang, Chorom	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Javaid, Ahsan	An Efficient Machine Learning Approach for PSIJ Analysis in a Chain of CMOS Inverters
Jeong, Jonghee	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements
Jeong, Sangnam	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
Jiao, Dan	Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
Jin, Sungwoo	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Jinesh, Anandajith	A robust optimization approach for High Bandwidth Memory interposer using Machine Learning
Jung, Haekang	Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
K
K. Mathew, Manish	Impact of Non-Functional Pads Location on Eye Diagram Performance
Kahmen, Gerhard	A Tunable Inductor Peaking Technique for Optical Communication Systems
Kaller, Dierk	Limit of the Impact of the Via Stub Length on the Via Impedance in Printed Circuit Boards
Kamath, Swathi	Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch
Kashyap, Priyank	Transformer Based Channel Identification
Keegan, Ryan	Megtron 6 and 8 Characterization Methodology
Keuseman, Jordan	Application of the Reverse Pulse Technique for Worst Case Transient Analysis in HPC PDN Design
Khazaka, Roni	Gradient-based method to find solution for Rational Polynomial Chaos coefficients for Uncertainty Quantification
Kikuchi, Katsuya	Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate
Kim, Donghyun	Impact of Non-Functional Pads Location on Eye Diagram Performance Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Kim, Dongkyun	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
Kim, Haeyeon	Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning
Kim, Hyunsik	Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Kim, Hyunwoo	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
Kim, Hyunwoo	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Kim, Jihun	Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System
Kim, Joungho	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Kim, Joungho	High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing
Kim, Juneyoung	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel
Kim, Kang-Wook	Design of an Ultra-High-Speed Digital Interface Based on a Coplanar Stripline Analysis of Nonlinear Phase Interactions of a Differential Line in the Presence of a Signal Skew
Kim, Keunwoo	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Kim, Kwangho	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Kim, Kyungsuk	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Kim, Mun-Ju	Design of an Ultra-High-Speed Digital Interface Based on a Coplanar Stripline Analysis of Nonlinear Phase Interactions of a Differential Line in the Presence of a Signal Skew
Kim, Nam Sung	Yield-Aware Interposer Design for UCIe Interconnects
Kim, Taesoo	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Kim, Woopoung	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
Kirchberger, Alexander	Delay Rational Macromodelling of Noisy Tabulated Frequency Responses
Ko, Youngjun	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Koh, Cheng-Kok	Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
Krishna, Ram	Yield-Aware Interposer Design for UCIe Interconnects
Kronenberg, Tom	Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch
L
Lau, John	Chiplet Design and Heterogeneous Integration Packaging
Lee, Hyeongi	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Lee, Jinan	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements
Lee, Jinwook	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
Lee, Junghyun	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Lee, Junghyun	PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning
Lee, Manho	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Lee, Sanguk	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
Lee, Seonghi	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
Lee, Youngjae	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Lena, Davide	Simulation method for Quasi-static solver to effectively model parasitic components between Package and PCB
Li, Aobo	A DDR5 Interposer De-embedding Method Based on Transfer Function
Li, Chaofeng	Impact of Non-Functional Pads Location on Eye Diagram Performance
Li, Guangxu	Multiphysics Simulation and Measurement Correlation of a Multichip Module IC Package Current Sensor
Li, Jingbo	Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
Li, Shuxiang	A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π-Type Filtering Structure
Li, Weizhe	Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
Li, Yongzhong	On the Parallelization of the MultiAIM Algorithm for the Fast Electromagnetic Analysis of 3D ICs A Highly-Scalable Parallel Boundary Element Method for the Full-Wave Electromagnetic Analysis of Large Interconnect Networks and Entire Packages
Lin, Chien-Min	Agile Analysis for Worst-Case Eye-Diagrams in Multi-Line Links of CoWoS Packaging
Lin, Chien-Min	Efficient Thermal Analysis for Heat Dissipation in Three-Dimensional Chip-Stacking Packaging
Lin, Han-Ting	A Tunable Inductor Peaking Technique for Optical Communication Systems Tunable True-Time-Delay Unit Based on Bridged T-Coil
Ling, Feng	Recent Advances in Signal Integrity Simulation and Analysis of Interposers
Liu, Dan	Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions
Liu, Dan	Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
Liu, Tong	Analysis of Echo and Crosstalk Cancellation in Simultaneous Bidirectional Transceivers for Dense Die-to-Die Interconnects
Lu, Cheng-Yuan	Efficient Thermal Analysis for Heat Dissipation in Three-Dimensional Chip-Stacking Packaging
M
Mahmood, Shakib	Equalization Techniques for Time Domain Signalling
Malignaggi, Andrea	A Tunable Inductor Peaking Technique for Optical Communication Systems
Manfredi, Paolo	A Hybrid Polynomial Chaos Expansion and Gaussian Process Regression Method for Forward Uncertainty Quantification of Integrated Circuits Efficient parametric assessment of worst-case voltage droop in power delivery networks
Manvelyan, Diana	Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations
Marek, Damian	A Highly-Scalable Parallel Boundary Element Method for the Full-Wave Electromagnetic Analysis of Large Interconnect Networks and Entire Packages
Mathur, Anuj	Hand-drawn Circuit Schematic Digitization and Netlisting using Machine Learning with Emphasis on Signal Integrity Applications
Matta, Kusuma	Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions
Maubach, Joseph	Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations
Mendez-Ruiz, Cesar	Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions
Min, Byung-Cheol	Design of an Ultra-High-Speed Digital Interface Based on a Coplanar Stripline Analysis of Nonlinear Phase Interactions of a Differential Line in the Presence of a Signal Skew
Miskovic, Goran	Analysis and Modeling of Controlled Silicon Substrate Roughness for Silver-Based Backside Metallization in Power Electronics Packaging
Mousavi, Mehdi	Impact of Non-Functional Pads Location on Eye Diagram Performance
Murugan, Rajen	Multiphysics Simulation and Measurement Correlation of a Multichip Module IC Package Current Sensor Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch
Mutnury, Bhyrav	Compact Fiber Weave Model for Full Wave Solvers
N
Nakhla, Michel	Automated Accurate Quadratic Formulation of Nonlinear Circuits
Niazi, Alireza	Full-Wave Analysis for Ground Via Placement with Layered Media Integral Equations
O
Okhmatovski, Vladimir	Full-Wave Analysis for Ground Via Placement with Layered Media Integral Equations Accuracy Study of the Differential Surface Admittance Operator for Lossy Metal Characterization
Oreifej, Rashad	Optimizing Power and Power Delivery For Data Center GPUs
Ouchi, Shinichi	Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate
Ozese, Doganay	Tree-Based Boosting for Efficient Estimation of S-Parameters for Package Electrical Analysis
P
Padhi, Satyajeet	Electro-Thermal-Mechanical Design Workflow for Printed Circuit Boards and Electronic Packages
Page, Andrew	A Signal Integrity Comparison of VIPPO Technology for PCIe 5.0 DC Blocking Capacitors
Palermo, Samuel	Analysis of Echo and Crosstalk Cancellation in Simultaneous Bidirectional Transceivers for Dense Die-to-Die Interconnects
Pappu, Santosh	Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Pareschi, Fabio	Simulation method for Quasi-static solver to effectively model parasitic components between Package and PCB
Park, Dongryul	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
Park, Eunkyeong	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
Park, Hyunah	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Park, Hyunwook	Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM)
Park, Joonsang	Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network
Park, Junho	Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System
Park, Junyong	Impact of Non-Functional Pads Location on Eye Diagram Performance Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Pelagalli, Nicola	A Tunable Inductor Peaking Technique for Optical Communication Systems
Peng, Zhekun	Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Penta, Srujan	Yield-Aware Interposer Design for UCIe Interconnects
Q
Qiu, Lu	Analysis of Interconnects in Multilayer SIW Bandpass Filters Design
Qiu, Qiang	Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
R
Rahal-Arabi, Tawfik	Optimizing Power and Power Delivery For Data Center GPUs
Rangaswamy, Granthana	Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Reinamendivil, David	Worst-Case Voltage Droop Using Peak Distortion Analysis
Roh, Sungwon	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Rosenbaum, Elyse	Yield-Aware Interposer Design for UCIe Interconnects
Roth, Thomas	Superconducting Circuit Quantum Computers: Fundamental Concepts and Scaling Challenges Modeling Multiplexed Qubit Readout with a Josephson Traveling-Wave Parametric Amplifier
Roy, Abinash	Reinforcement Learning Based Automatic Router for Power Delivery Network Prototypes
Ryu, Seunghun	An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
S
Sahouli, Mohamed	Worst-Case Voltage Droop Using Peak Distortion Analysis
Saidi, Mehdi	Optimizing Power and Power Delivery For Data Center GPUs
Salman, Laila	Ensuring the Power and Signal Integrity of Your High-Performance PCBs and Packages Using Ansys SIwave
Scearce, Stephen	A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency
Scharff, Katharina	Limit of the Impact of the Via Stub Length on the Via Impedance in Printed Circuit Boards
Schilders, Wil	Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations
Schutt-Aine, Jose	Signal and Power Integrity Analysis Using LIM – Recent Advances
Schutt-Ainé, José	Latency Insertion Method for Fast Electro-Thermal Simulation of FinFET with Self-Heating Effect
Seahra, Rajit	Optimizing Power and Power Delivery For Data Center GPUs
Sen, Bidyut	Impact of Non-Functional Pads Location on Eye Diagram Performance
Setti, Gianluca	Simulation method for Quasi-static solver to effectively model parasitic components between Package and PCB
Shim, Taehyun	PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel
Shimamoto, Haruo	Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate
Shimomura, Soshi	Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate
Shin, Jongchul	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
Shin, Taein	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Sidhu, Karanvir Singh	Gradient-based method to find solution for Rational Polynomial Chaos coefficients for Uncertainty Quantification
Sim, Taeyang	Analysis of Echo and Crosstalk Cancellation in Simultaneous Bidirectional Transceivers for Dense Die-to-Die Interconnects
Simone, Silvia	Simulation method for Quasi-static solver to effectively model parasitic components between Package and PCB
Smith, Michael	Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
Smith, Richelle L.	Equalization Techniques for Time Domain Signalling
Smutzer, Chad	Application of the Reverse Pulse Technique for Worst Case Transient Analysis in HPC PDN Design
Sohn, Young-Soo	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Son, Keeyoung	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Son, Sanghyuk	Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System
Song, Jinwook	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
Song, Sangsub	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
Srinivas, Vaishnav	Abstraction for Heterogeneous Integration
Subbarayan, Ganesh	Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
Suh, Haeseok	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Sundaram, Sriram	Optimizing Power and Power Delivery For Data Center GPUs
Swaminathan, Madhavan	A Model Amongst us of the highest Order who can never be Replicated Abstraction for Heterogeneous Integration
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Talbot, Gerry	Worst-Case Voltage Droop Using Peak Distortion Analysis
Tang, Xinlin	A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π-Type Filtering Structure
Teo, T. Hui	A 155 MHz Low-Jitter PLL for Enhanced Signal Integrity in High-Speed Interconnects
Tethy, Parneet	Equalization Techniques for Time Domain Signalling
Tian, Minzheng	Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
Tiruye, Mulat Ayinet	A 155 MHz Low-Jitter PLL for Enhanced Signal Integrity in High-Speed Interconnects
Travis, Blake	Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch
Trinchero, Riccardo	A Hybrid Polynomial Chaos Expansion and Gaussian Process Regression Method for Forward Uncertainty Quantification of Integrated Circuits Efficient parametric assessment of worst-case voltage droop in power delivery networks
Tripathi, Jai	An Efficient Machine Learning Approach for PSIJ Analysis in a Chain of CMOS Inverters
Triverio, Piero	On the Parallelization of the MultiAIM Algorithm for the Fast Electromagnetic Analysis of 3D ICs A Highly-Scalable Parallel Boundary Element Method for the Full-Wave Electromagnetic Analysis of Large Interconnect Networks and Entire Packages
U
Uematsu, Yutaka	Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate
Ullrick, Thijs	Modeling Microwave S-parameters using Frequency-scaled Rational Gaussian Process Kernels
Unal, Hasan Said	Causal RL Prediction of Fine-Pitch Interconnects Using Neural Networks
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van de Wouw, Nathan	Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations
Van der Arend, Paul	Optimizing Power and Power Delivery For Data Center GPUs
Vande Ginste, Dries	Accuracy Study of the Differential Surface Admittance Operator for Lossy Metal Characterization
Venkataraman, Srinivas	Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Victor, Ashita	Yield-Aware Interposer Design for UCIe Interconnects
Vilner, Pavel	Practical aspects of FD-TDR co-modification for high-speed structures’ matching and what-if simulations
Vojkuvka, Luka	Analysis and Modeling of Controlled Silicon Substrate Roughness for Silver-Based Backside Metallization in Power Electronics Packaging
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Wang, Jun	A DDR5 Interposer De-embedding Method Based on Transfer Function
Wang, Kai	Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions
Wang, Xu	Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
Watanabe, Atom	Packaging Technology for Next Generation mmWave Commmunications: Scalable Heterogeneous AiP Modules and the Future Role of Chiplets
Wei, Bing	Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
Weisshaar, Andreas	A Tunable Inductor Peaking Technique for Optical Communication Systems Tunable True-Time-Delay Unit Based on Bridged T-Coil
Wen, Yeujiang	Transformer Based Channel Identification
Werner, Carl W.	Equalization Techniques for Time Domain Signalling
Wu, Ruey-Beei	Agile Analysis for Worst-Case Eye-Diagrams in Multi-Line Links of CoWoS Packaging Efficient Thermal Analysis for Heat Dissipation in Three-Dimensional Chip-Stacking Packaging
Wu, Tzong-Lin	Optimization of TSV Array Based on Mathematical Model for HBM3
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Xu, Yan	A DDR5 Interposer De-embedding Method Based on Transfer Function
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Yang, Xian-Long	Analysis of Interconnects in Multilayer SIW Bandpass Filters Design
Yong, Seokbeom	Signal Integrity of Die-to-Die Interface with Advanced Packages for Co-Packaged Optics
Yoon, Jiwon	Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM) Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI) High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
Yoon, Sungjin	Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
Yuan, Felix	Reinforcement Learning Based Automatic Router for Power Delivery Network Prototypes
Yutaka, Suzuki	Multiphysics Simulation and Measurement Correlation of a Multichip Module IC Package Current Sensor
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Zhang, Kangkang	A DDR5 Interposer De-embedding Method Based on Transfer Function
Zhang, Zheng	Machine Learning for EDA, or EDA for Machine Learning?
Zhong, Yangfan	Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
Zhou, Yi	Latency Insertion Method for Fast Electro-Thermal Simulation of FinFET with Self-Heating Effect
Zhu, Xiao-Wei	Analysis of Interconnects in Multilayer SIW Bandpass Filters Design