ABSTRACT. With the increase in complexity and size of modern circuits, signal integrity has become an important aspect in the the study of the performance of electronic systems. Circuit designers are constantly in need of robust and efficient circuit simulation methods that can capture complex electromagnetic behaviors of networks and devices in fast turnaround time. As a result, there is a constant need for and push toward faster and more accurate circuit simulation techniques. The latency insertion method (LIM) has emerged as an approach of choice for performing fast simulations of very large circuits. By exploiting latencies in a circuit, LIM implements an algorithm that achieves linear numerical complexity. This results in a computationally efficient algorithm that is able to simulate large circuits significantly faster than traditional matrix inversion-based methods used in simulators such as SPICE.

In this tutorial we review the fundamentals of the latency insertion method and explore applications related to new technologies. Recent advances, several examples and case studies related to signal/power integrity and large circuits will be presented.

ABSTRACT. Time Domain Reflectometry (TDR) is a widely used technique in design of high-speed (HS) serial digital channels. It is frequently employed as a post-processing step for VNA measurements and Frequency Domain (FD) electromagnetic simulations’ results to assess the localized channel impedance as the assumed propagating signal sees it. The TDR well-known connection to the channel’s topology and design features makes it useful in identifying changes needed to achieve the desired system performance. Thus, when the TDR or FD results are not satisfactory, two questions often arise – (1) what the FD data will look like if some TDR feature is changed, and (2) what TDR feature needs to be changed to modify an undesired aspect of the FD data. Answering those questions requires co-modifying the TDR result and its respective FD representation.

While the Fourier theory underpinning FD-TDR co-modification is well known, this presentation deals with finer practical points needed to implement it. Extrapolation of the original FD data to achieve the desired bandwidth, application of the modification window functions, considerations in modifying the complex-valued FD data and influence of computational precision are discussed. Examples in MATLAB are given, and their usefulness in improving their respective HS structures’ topology is showcased.

ABSTRACT. Superconducting circuit devices are one of the most mature hardware platforms for developing quantum computers, but significant engineering advances are needed for them to reach their revolutionary potential in practical applications. One primary challenge is to scale the number of quantum bits (qubits) in devices by orders of magnitude while continuing to improve key performance metrics. In this tutorial, we will introduce the fundamental concepts of how superconducting circuit quantum computers operate assuming no prior knowledge in quantum mechanics. We will discuss the key aspects of the primary qubit type currently being used, as well as how microwave fields and electronic biases are used to control and measure qubit states. We will then briefly discuss current hardware and computational modeling efforts underway that are working to address the scaling challenges of these systems. We will conclude with comments on directions for future work and the roles the electronics packaging community can play in making these revolutionary technologies a reality.

ABSTRACT. Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.

- System-on-Chip (SoC) - Why Chiplet Design? - Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split - Chip partition and Heterogeneous Integration - Chip split and Heterogeneous Integration - Advantages and Disadvantages - Communication between Chiplets (e.g., Bridges) - Bridge Embedded in Build-up Package Substrate - Bridge Embedded in Fan-Out EMC with RDLs - UCIe - Hybrid Bonding Bridge - Chiplet Design and Heterogeneous Integration Packaging – Multiple System and - Heterogeneous Integration - Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration) - Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration) - Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration) - Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration) - Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration) - Advanced Packaging Driving by Artificial Intelligent - Summary - Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging - Trends in Chiplet Design and Heterogeneous Integration Packaging

ABSTRACT. Over the past few decades, the ASIC design methodology has evolved based on a sophisticated abstraction approach from RTL to GDS. This has enabled the design to transition through different areas of expertise seamlessly as the language of communication is transparent and easy to understand, owing to the abstraction. RTL gets synthesized, the netlist then gets floorplanned, placed and routed, signed off for timing and physical verification. Such an approach has enabled many positives, including  (1) EDA focused on each step in the process to include the appropriate abstraction, e.g., a .lib to contain the timing information, or LEF/DEF to contain the physical information; (2) Ability to suitably model for each step as the quality of the collaterals have different level of detail, e.g., power estimation at RTL, gate, layout stages; and (3) Not least, the ability for humans, and now AI, to understand the whole flow and enable co-design at various levels, e.g., chip architects can assess crude area impact of their decisions very quickly.

This tutorial hopes to show that a similar approach for packaging and system design is the need of the hour during the heterogeneous integration revolution we are in today. The packaging electrical, thermal and mechanical analysis lacks a systematic abstraction approach and often gets tied up in details that make the estimation-design loops quite long. The proposed abstraction approach will also define key intercepts with the ASIC design methodology, so co-design between die/package/pcb can be realized for 2.5D/3D designs. These include (1) Chip partitioning; (2) IO standards and SIPI specification; (3) Floorplanning; and (4) System Signoff. The tutorial will also highlight benefit of abstraction for multiphysics signoff and AI/ML based methods.

ABSTRACT. This talk cover the emerging packaging technology trends for mmWave communications with a focus on the design and integration methodologies for scalable phased array antenna modules. The presentation will first describe a heterogeneous integration strategy used to facilitate the effective integration of various active ICs, passive components, and decoupling capacitors into a substrate to form a 5G scalable phased array antenna module. The talk will also discuss the anticipated advantages of adopting a chiplet-based approach for digital baseband processing enabling the implementation of full end-to-end antennas-to-AI systems for the next generation of energy-efficient and adaptive mmWave networks.