ABSTRACT. Chiplet technology is revolutionizing our digital infrastructure. The reductions in cost, time-to-market, and power consumption of chiplet-based solutions are compelling, particularly for AI hardware. Custom silicon for AI significantly benefits from the chiplet approach, which allows for the integration of dense logic, memory, and high-speed connectivity. Chiplets provide the flexibility to create systems-in-package that balance cost, power, and performance for specific workloads without reinventing the wheel for each new design. As chiplet adoption grows, it drives increased bandwidth requirements within packages and across die-to-die interfaces. Scaling AI performance requires low-latency inter-die communication and lots of high-speed optical connectivity.

ABSTRACT. As the semiconductor market shifts its focus to 3D integration, lowest cost, and high performance, the need for advanced analog packaging technologies becomes paramount. Integrating multichip and passives onto cost-effective package technologies create opportunities for highly competitive semiconductor products. However, this aggressive integration also leads to complex multiphysics and multiscale interactions, especially for small-form-factor modules. This work describes the multiphysics (electrical-thermal-mechanical) co-design modeling methodology that resulted in the industry's first highly accurate, voltage-output multichip module current-sense integrated circuit. The reliability of the multiphysics modeling methodology was confirmed by directly comparing it to measurements taken on a 36V, bi-directional, precision current sense amplifier with an integrated shunt resistor evaluation module (EVM). The study demonstrates a strong correlation (within +/- 0.3-2.5% difference) between simulation and laboratory measurements, underscoring the practical relevance and impact of our research.

ABSTRACT. This work presents an interposer design methodology for UCIe die-to-die interfaces that maximizes yield given a set of signal integrity specifications. Four different routing configurations on a silicon interposer are considered, and the cost, performance, and yield tradeoffs are elucidated. The fabrication steps for the D2D interconnects are outlined and sources of yield-limiting variability are identified. The yield analysis is expedited by the use of a Gaussian Process Regression surrogate model.

ABSTRACT. The advancement of high-performance computing drives the need for thermal analysis in 3D chip-stacking system. This paper employs an alternative calculation method to finite-element to assess thermal distribution, ensuring computational efficiency and accuracy simultaneously.

ABSTRACT. In this paper, we propose an eye-diagram edge estimation (EEE) network for fast and accurate eye diagram prediction, which is a novel approach in through silicon via (TSV) design in high bandwidth memory (HBM). As HBM generation is developed, the number of input/outputs (I/Os) and data rate have increased for high bandwidth, causing degradation of signal integrity (SI) in TSV structures. However, SI evaluation takes much time due to time-consuming SI simulations including the eye diagram simulation. Therefore, there is a need for fast eye diagram estimation for TSV structures optimization. The proposed EEE network utilizes only four voltage values at each time step to predict the eye diagram edge. In addition, the EEE network does not require additional time-domain and frequency-domain simulations, enabling a significant reduction in model size and facilitating training with a small dataset and shallow models such as artificial neural network (ANN). As a result, the ANN-based EEE network generated an eye diagram edge with an approximate 1% error in under 1 ms, demonstrating high accuracy and time-efficiency. This novel approach has potential applications in other design scenarios.

ABSTRACT. This paper presents a design guide for silicon interposer channels and power distribution networks (PDN) in post-HBM3 high-density I/O implementations. We introduce a novel reference-paired shielding (RPS) scheme that mitigates crosstalk and reduces metal layer count. Our optimal RPS pattern, which takes into account crosstalk, simultaneous switching noise (SSN), and redistribution layer effects, achieves a maximum datarate of $7.1$ Gbps for high-density I/O implementation. This represents a $31.5\%$ improvement over conventional interposer channels while using one fewer metal layer. We also analyze the trade-off between I/O channel and PDN allocation within a limited interposer area, examining crosstalk and SSN effects relative to channel dimensions and PDN area.

ABSTRACT. Abstract— In this paper, we present a novel approach to optimize the through-silicon vias (TSV) structure by the multi-conductor transmission line (MTL) theory and a genetic algorithm (GA) for high bandwidth memory (HBM). A comprehensive mathematical model is developed for the TSV array based on MTL theory. The S-parameter estimated by the model is consistent with the full-wave simulated results. Moreover, GA, which iteratively adjusts the TSV parameters, is employed to minimize the insertion loss. The results demonstrate significant improvements in TSV performance, including reduced signal degradation and enhanced overall efficiency.

ABSTRACT. This paper introduces a novel kernel-based formulation for the efficient uncertainty quantification of integrated circuits. The method combines the polynomial chaos expansion (PCE) and Gaussian process regression (GPR) frameworks, the former to provide closed-form statistical information and the latter for an efficient training. In essence, the PCE coefficients are computed using a suitable Bayesian formulation that involves the definition of a special implicit kernel based on an infinite sequence of Hermite polynomials. The proposed method is illustrated based on a network with microstrip lines.

ABSTRACT. This paper explores the application of deep learning models to the DC power distribution problem in electronic packaging. A generative model based on an implicit neural representation (INR) is trained with meshed geometry and electromagnetic field data computed by traditional numerical methods. The model is constructed in a way that allows it to make predictions for previously unseen problem geometries.

ABSTRACT. Once an electrical system completes assembly, highspeed channel characterization is complex as access points are limited, and probing by a network analyzer is not a possibility. Further active channels may now have different types of I/O from NRZ to PAM4 levels, adding additional complications. This work describes a method for predicting a channel’s behavior and implicitly learning the underlying system parameters in two stages. The first stage uses an autoregressive transformer structure to predict the channel’s behavior as a single-bit response (SBR). The second stage uses the model’s latent space and unsupervised dimensionality reduction to determine the underlying system parameters. The results show that the model can predict the SBR for completely unseen channels for both NRZ and PAM-4 despite the model training using only NRZ waveforms. Further, unsupervised dimensionality reduction enables the determination of system param

ABSTRACT. We propose a gradient boosted tree surrogate model for S-parameter prediction in high frequency structures with limited training data. Compared to data-hungry neural networks, our approach achieves reasonable accuracy and trains significantly faster.

ABSTRACT. This paper presents the design of tunable true-time-delay (TTD) units with both discrete and continuous time delay states. Tuning is achieved by varying the capacitances of a bridged T-coil (BTC) circuit. The effectiveness of the design approach is demonstrated with both switched capacitor banks and varactors. All tunable TTD units have been designed in a Tower Semiconductor 0.18μm SiGe BiCMOS process. Measurements of a fabricated two-state delay unit (20 ps and 25 ps delay) with capacitance tuning implemented with nfet switches show a tunable range of 25% over an 8GHz bandwidth with < 1.8 dB insertion loss and > 15.8 dB return loss. Full-wave simulation results for a varactor-tuned design demonstrate a tuning range of 16 ps - 25 ps (±25%) over an 8 GHz bandwidth.

ABSTRACT. To model multiplexed readout, a key ingredient for scaling quantum computers, we develop a numerical method for co-simulation of qubits and a Josephson traveling-wave parametric amplifier. The integrated characterization reveals behavior absent from independent analyses.

ABSTRACT. Self-heating effect (SHE) is prominent for FinFETs. With SHE, the power is dissipated into heat, affecting FinFETs’ performance. This paper proposes the Latency Insertion Method algorithm for fast and accurate FinFET electro-thermal simulation with SHE.

ABSTRACT. For the first time, this paper proposes a L3 cache embedded-GPU-High bandwidth memory (L3E-GPU-HBM) for reduced latency and enhanced energy efficiency of large scale memory intensive AI computing. Accessing HBM in conventional GPU-HBM architecture involves significant latency and requires high data movement energy. To address the challenge, we propose L3E-GPU-HBM in which L3 cache is embedded in interposer between GPU and HBM. To implement the proposed architecture, embedded SRAM interconnect (ESI) chip is employed, which consists of local silicon interconnect (LSI) die and L3 cache die, merged by hybrid bonding. Then, using Chip-on-Wafer-on-Substrate with Local interconnect (CoWoS-L) method, ESI chip is placed inside the reconstituted interposer (RI). The ESI chip functions as both interconnect and L3 cache between L2 cache of GPU and HBM. For verification of the proposed architecture, the circuit model of driver and channel is utilized to obtain the wire latency and energy. The result showed that the proposed L3E-GPU-HBM architecture reduced the wire latency and energy compared to conventional GPU-HBM architecture by 17% and 33%, respectively.

ABSTRACT. This study compares various fan-out design approaches for high-density SMT connectors in modular systems. Both simulations and measurements show significant crosstalk differences, which can be instrumental in layout optimization for PCIe 6.0 signal integrity design.

ABSTRACT. A method of cascading 3D models and 2D models to model the full channel of ASIC package substrate interconnects is proposed, showing good match to full-wave results in S-parameter and TDR up to 100 GHz.

ABSTRACT. A novel method for DDR5 interposer de-embedding is introduced in this article, utilizing transfer function and microwave network theory. The accuracy of this method is assessed through validation in frequency and time domain simulations

ABSTRACT. We construct a neural network model of S-parameters, from which the S-parameters can be quickly predicted. Numerical tests on a filter model show that the proposed method accurately predicts the S-parameters with multiple sharp resonances.

ABSTRACT. This paper comprehensively evaluates signal integrity (SI) performance in 100G-PAM4 Ethernet links under two different cooling methodologies: air cooling and immersion cooling. It focuses on how these environments affect the BER in high-speed data transmissions.

ABSTRACT. This study shows that placing four NFPs in selective PCB layers significantly improves signal integrity, reducing minimum jitter from 18.28 ps to 12.81 ps and maximum jitter from 27.66 ps to 22.03 ps.

ABSTRACT. In this paper, signal integrity (SI) design and analysis of high-speed interconnect of silicon interposer based heterogeneous integration for artificial intelligence (AI) computing was carried out. With the increasing popularity of AI services, there has been a significant surge in the demand for AI computing capabilities. As a result, high-performance, high-density AI computing modules based on multi-GPU architectures, rather than single-GPU configurations, have emerged as a prominent solution. For high-density GPU integration, the silicon interposer based heterogeneous integration of multi-GPU architecture is arisen. In this research, we design multi-GPU integration on silicon interposer and high-speed GPU links considering routability. Furthermore, we analyzed the designed high-speed GPU link considering SI, but also fabrication cost. Consequently, multiple GPUs are integrated on a silicon interposer, but it has been determined that adequate SI for GPU links cannot be secured on the interposer. Instead, utilizing a package for these connections ensures the necessary SI and offers significant advantages in fabrication cost with reducing metal layers of silicon interposer.

ABSTRACT. Nonlinear phase interactions between two signal lines of a differential line are analyzed with various signal skew levels and compensation distances. This nonlinear phenomenon may limit the operation of DL-based digital lines above ~10 GHz.

ABSTRACT. Designing high-speed interconnects faces challenges from factors like jitter, noise, and skew, which degrade performance. This study introduces a 155 MHz low-jitter PLL clock generator using 180nm technology. Operating with a 10MHz input, it achieves 2.832ps average jitter, crucial for signal integrity in high-speed interconnects.

ABSTRACT. In recent years, high-performance processors utilizing chiplet technology have appeared. Universal Chiplet Interconnect Express (UCIe) has become the mainstream standard for interconnect communication between chiplets. Improving processor performance requires an increase in throughput of UCIe communication. Although stacking interfaces vertically along the die edge is beneficial for enhancing wiring density, the large number of required substrate layers makes the interposer expensive. This paper discusses a method to implement UCIe wiring, typically using two layers, with a single layer to achieve cost-effective interposers. For single-layer wiring, we adjusted the UCIe form factor rules and identified the need for fine-pitch wiring as 10 um or less. In addition, to reduce crosstalk in the wiring between dies, we proposed a wiring layout that increases the wiring pitch only between dies. We modeled the interposer, conducted a signal integrity analysis, and confirmed that communication at the transmission rate of 32 Gbps is possible over die-to-die distances of 1-10 mm. We concluded that a cost-effective interposer is feasible using single-layer UCIe wiring.

ABSTRACT. This paper presents a system-level PCI Express (PCIe) Gen 6.0 PAM-4 receiver (Rx) signal integrity (SI) analysis using time-domain measurements at a system channel-end test point (TP) without any end-to-end passive channel information such as a S-parameter model. Insertion loss (IL), return loss (RL), and near-end/far-end crosstalk (NEXT/FEXT) for the entire interconnect path at each Nyquist frequency for PCIe Gen 3.0, 4.0, and 5.0 are calculated as a result of measuring voltage waveforms at the TP when the host as the transmitter (Tx) transmits compliance bit pattern. We demonstrated for the first time that reliable Rx PAM-4 SI analysis is possible for entire end-to-end PCIe Gen 6.0 interface channel using a mimic channel model based on the calculated IL, RL, NEXT, and FEXT values.

ABSTRACT. With the increasing demand for high-performance computing (HPC), the significance of high-speed SerDes channels is growing. An importance of crosstalk is larger than ever, in particular, peripheral component interconnect express (PCIe) Gen6 uses pulse amplitude modulation of four-level (PAM4), not non-return-to-zero (NRZ). In this paper, minimizing crosstalk Add-in Card (AIC) based on the network parameters and specific example of enhancement with reinforcement grounding is presented. And its effectiveness of that is evaluated in NRZ and PAM4 modulations. As a result, the crosstalk effect caused by the AIC's ground return path in NRZ is negligible, but case of PAM4, it has a significant impact that can directly degrade the signal quality.

ABSTRACT. The redistribution layer(RDL) in CoWoS packaging contains dense wires that suffer from crosstalk, degrading signal quality and distorting eye-opening margins. To assess this, a single-line equivalent-circuit scheme with Peak Distortion Analysis (PDA) is proposed. This method is applied to HBM links at 3.2 Gbps (HBM2E) and 6.4 Gbps (HBM3), and compared with PRBS simulation for accuracy and efficiency.

ABSTRACT. This work studies the signal integrity effects of VIPPO-style vias and DC blocking surface-mount capacitors required by many high-speed serdes interfaces, focusing on PCIe 5.0 transmitters. A test vehicle was built containing four via-and-capacitor configurations fixtured with coaxial probe contacts, as well as a calibration structure for broadband de-embedding. Passive measurements are discussed, and de-embedding is attempted. A set of 3D full-wave models are built that validate the reliability of de-embedded results after post-processing. The 0201-capacitor seated on VIPPO vias performs the best against the demonstrated tests from a high-speed signal integrity standpoint.

ABSTRACT. Two cross coupling substrate integrated waveguide (SIW) filters designed on multilayer structure, vertically interconnected with screws and prepreg respectively, are presented, analyzed and measured. Spurious signals caused by prepreg is analyzed to propose elimination suggestions.

ABSTRACT. A design for an ultra-high-speed digital interface, providing autonomous signal integrity improvement, is proposed. The proposed interface is on a coplanar stripline and verified to perform from DC to 30 GHz for 5G/6G communications.

ABSTRACT. In this paper, we analyzed signal integrity (SI) of peripheral component interconnect express (PCIe) channels in an infotainment system utilizing floating board-to-board (BtoB) connectors for automotive environments. The floating BtoB connector is designed to maintain reliable electrical performance at high frequencies, making it compatible with various I/O protocols. Thus, the floating BtoB connectors can be effectively used for PCIe interconnect between the CPU on the main board and the ECU on the daughter board. To accommodate numerous components, including connectors, packages, and chips within a single system, the placement of the ECU package varies across different scenarios. Accordingly, we explored PCIe channel configurations by altering the ECU package's position, both on top and bottom-side of the daughter board. By designing PCIe interconnects within the system, we conducted electromagnetic (EM) simulations to analyze differential insertion loss (DIL), considering the impact of routing paths containing floating BtoB connectors. To verify compatibility with PCIe, we achieved eye diagrams at 16 Gb/s via equalization. Finally, we suggest design guidance for the proposed system considering cost and SI.