ABSTRACT. The rapid advancement of machine learning (especially deep learning) in the past decade has impacted, both positively and negatively, many research fields. Driven by the great success of machine learning in image and speech domains, there have been increasing interests in “Machine Learning for EDA”. In the first part of the talk, I will explain the main challenge of data sparsity when applying existing machine learning techniques to EDA. Then I will show how some data-efficient scientific machine learning techniques, specifically uncertainty quantification and physics-constraint operator learning, can be utilized to build high-fidelity surrogate models for variability analysis and for 3D-IC thermal analysis, respectively. These techniques can greatly reduce the number of required device/circuit simulation data samples.

Another important but highly ignored direction is “EDA for Machine Learning”. The five decades of EDA research has produced a huge body of solid theory and efficient algorithms for analyzing, modeling and optimizing complex electronic systems. Many of the white-box EDA ideas may be leveraged to solve black-box AI problems. In the second part of the talk, I will show how the self-healing idea and compact modeling idea from EDA can be utilized to improve the trustworthiness and sustainability of deep learning models (including large-language models).

ABSTRACT. Reinforcement learning (RL) is applied to an automated power delivery network design process. Initially, a prototype board is created with multiple power rails. Using two RL agents, each power rail is routed from the voltage regulator to the integrated circuit (IC) pins. Secondly, the metal width of each rail is expanded to decrease the resistance and inductance of the rail.

ABSTRACT. In this paper, an efficient machine learning approach based on the knowledge-based and recurrent neural networks to predict power supply induced jitter in the presence of multiple power supply noises is presented. The proposed approach provides a reasonable accuracy and a significant increase in speed compared to conventional approaches.

ABSTRACT. There is an emerging keen interest in the design and academic communities to automatically generate a simulatable netlist from hand-written schematics. This paper presents a novel machine learning-based circuit digitization and netlisting methodology.

ABSTRACT. A tunable inductor peaking technique for loss compensation in optical communication systems is presented. The proposed technique is based on creating a tunable damped resonator with a fixed peaking inductor and a high-frequency transistor with low intrinsic capacitance. The tuning technique is first demonstrated with a generic equivalent circuit model and then implemented and evaluated using the high-speed bipolar transistor in 130 nm IHP SG13G2 BiCMOS technology, featuring ft/fmax of 350 / 450 GHz. Our proposed technique has been simulated in a real case scenario demonstrating the effectiveness of the tunable inductor peaking technique for loss compensation in optical communication systems.

ABSTRACT. To meet the high demands in Artificial Intelligence (AI) and Machine Learning (ML) applications, the conventional electrical interconnect has limitations on bandwidth, latency, and power consumptions. Co-Packaged Optics (CPO), and advanced heterogenous integration of optics and silicon on a single package, has attracted much attention to achieve higher bandwidth and power efficiency. Samsung has dedicated to develop advanced packaging technologies, such as 2.5D I-CubeS with a silicon interposer, 2.3D I-CubeE with an embedded silicon-bridge and organic redistribution layer (RDL), 2.3D I-CubeR with an organic RDL, and 3D X-Cube with a fine bump pitch Thermo-compression Bonding (TCB) and hybrid Cu bonding. Using I-CubeS or I-CubeE technologies, the feasible CPO architecture can be built by optoelectronic engine arrangement, stacking of photonic integrated circuit (PIC) and electronic integrated circuit (EIC), and PIC coupling type. This paper presents the signal integrity of die-to-die (D2D) interface for the logic of XPU to the logic of EIC. The signal integrity under simplified I/O models for a transmitter and receiver, W-element interconnect of Si-bridge, and through-silicon via (TSV) in the PIC was compared and verified from Universal Chiplet Interconnect express (UCIe) specification.

ABSTRACT. Delivering thousands of amps to the next generation of high-speed digital designs is fast becoming the biggest design challenge for the next generation of custom multi-die packages, AI Chips, and cloud server applications. End-to-end power integrity digital twins with multiphase voltage regulators, PCB PDN with 100’s of capacitors, and dynamic loads are critical for mitigating expensive hardware failures when working with thousands of amps. This presentation will explore the model fidelity trade-offs and lessons learned from simulating the Picotest 2000 Amp Transient Load Stepper demo board with a 55-phase MPS horizontal power delivery topology and over 700 decoupling capacitors.

The digital twin PI simulations will be demonstrated using Keysight Power Integrity designer tools. Keysight EDA Power Integrity designer tools in the ADS environment bring together a full workflow to solve the challenge of designing for high current low voltage power delivery. The solution includes DC IR Drop with electrothermal, AC EM with Decap optimization, and Conducted EMI with dynamic DC/DC regulator switching models. The solution is well integrated with multiple time domain and frequency domain solvers including Harmonic Balance (HB) for fast steady-state solutions and spectral data. HB works with the latest in state-space behavioral models for cascaded and parallel voltage regulators. Traditional frequency domain analysis with target impedance also includes the Non-Invasive Stability Margin for assessing phase margin to mitigate resonances by designing for low Q flat impedance.

ABSTRACT. This paper presents a scheme to fit delay rational macromodels of electrically long electric networks from noisy frequency domain tabulated data. Delay regions of the tabulated data are estimated by evaluating the energy of the frequency responses over time. Then, the frequency responses of each delay term are obtained as a rational approximation using a vector fitting-instrumental variable technique. The combination of rational approximations of each delay region provides a delay rational macromodel for the entire network.

ABSTRACT. This paper presents the SPICE-compatible model to efficiently simulate and analyze the multilayer PCBs with arbitrarily shaped plates, signal/power/ground vias, and multicoupled traces. This model is compared and evaluated using full-wave simulation. The results demonstrate that the proposed model significantly reduces computational time while maintaining high accuracy for complex PCB designs, achieving high efficiency.

ABSTRACT. The reverse pulse technique (RPT) predicts peak voltage deviation in the presence of worst case transient (WCT) load current. While RPT has been vetted through simulation, this paper addresses the practical application in lab hardware.

ABSTRACT. GPUs are used in products from ultra-low power mobile devices to high performance machine learning accelerators in data centers. Across the products, power and power delivery have become top limiters to performance and are key considerations in the early stages of product definition and design. In particular, the power and power delivery problem has been significantly exacerbated with the recent trends in the growth of AI workloads. In this paper, we present some of the data centers driven power optimizations used in latest generation of AMD GPUs including the recently announced AMD Instinct™ MI300 GPU. To this end, we cover power and power delivery optimization techniques spanning the product life cycle from architecture, physical design, validation, test, and manufacturing with an eye on the challenges in the road ahead