Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX (abstract)

Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters (abstract)

Linearization for High Speed Current-Steering DACs Using Neural Networks (abstract)

Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC (abstract)

A Redundancy-based Background Calibration for Comparator Offset/Threshold and DAC gain in a Ping-Pong SAR ADC (abstract)

Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators (abstract)

Reconfigurable E-band Receiver Development for Joint Communication and Sensing (abstract)

An ISM-Band Multi-Phase Injection-Locked Ring Oscillator (abstract)

A strategy to achieve competitive performance in basic RF LNAs (abstract)

A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS Process (abstract)

Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing (abstract)

28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer (abstract)

Assessment of key parameters in a microwave imaging system design for breast cancer detection (abstract)

An Energy-Efficient Wavelet Haar Transform Architecture for Respiratory Signal Processing (abstract)

Design of a Constant Current Laser Driver for Biomedical Applications (abstract)

Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA (abstract)

Residual Impedance Impact on MAX30001 Accuracy for Bioimpedance Applications (abstract)

Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors (abstract)

Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding (abstract)

Non-memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks (abstract)

Towards analog computing devices for matrix algebraic problems (abstract)

A Brazilian Sign Language Gesture Recognizing System Using Gait Energy Image (abstract)

Femto-Watt CMOS Voltage Reference Design (abstract)

Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits (abstract)

A 1V, 450pS OTA Based on Current-Splitting and Modified Series-Parallel Mirrors (abstract)

On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with Mismatch (abstract)

ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications (abstract)

Simulating large neural networks embedding MLC RRAM as weight storage considering device variations (abstract)

A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators (abstract)

Design Considerations for the Development of Computational Resistive Memories (abstract)

A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication (abstract)

Chronos: an Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution (abstract)

FPGA Implementation of a New PUF Based on Galois Ring Oscillators (abstract)

Hardware Trojan with Frequency Modulation (abstract)

A Wearable Wireless Sensing System for Capturing Human Arm Motion (abstract)

Study of a Voltage-Mode Readout Configuration for Micromachined CMOS Transistors for Uncooled IR Sensing (abstract)

Estimating Cole-Impedance Parameters from Limited Frequency-Band Impedance Measurements (abstract)

Design and implementation of a trans-impedance amplifier for a miniaturized saturated absorption spectrometer (abstract)

Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops (abstract)

Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers (abstract)

An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers (abstract)

Background Compensation of Frequency Interleaved DAC for Optical Transceivers (abstract)

Novel Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF Communications (abstract)

The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network (abstract)

Soft Error Sensibility Window at FinFET DICE SRAM (abstract)

A JTAG-based Fault Emulation Platfrom for Dependability Analyses of Processor-based ASICs (abstract)

On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory (abstract)

Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit (abstract)

Current Behavior on Process Variability AwareFinFET Inverter Designs (abstract)

Monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysis (abstract)

Edge Computing Technique for a 87% Energy Saving for IoT Device Dedicated to Environmental Monitoring (abstract)

Robust Passive Coherent Location via Nonlinearly Constrained Least Squares (abstract)

FPGA Implementation of Stair Matrix based Massive MIMO Detection (abstract)

High-Speed and Low-Energy Dual-Mode Logic based Single-Clock-Cycle Binary Comparator (abstract)

EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD Processors (abstract)

Electrical Evaluation of Logic Network Generation Methods for Supergates using SwitchCraft (abstract)

Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures (abstract)

A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders (abstract)

A Library of High-Level Models for the Simulation of DC-DC Converters (abstract)

RF-DC Multiplier for RF Energy Harvester based in 32nm and TFET technologies (abstract)

On the Possibility to Use Energy Harvesting on Beta Radiation in Nuclear Environments (abstract)

A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS (abstract)

High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring (abstract)

Reliability Analysis in Less than 200 Lines of Code (abstract)

A CMOS Implementation of the Tent Map for Random Number Generation (abstract)

Benchmarking Open Access VLSI Partitioning Tools (abstract)

TailoredCore: Generating Application-Specific RISC-V-based Cores (abstract)

Analog and RF Circuit Constrained Optimization Using Multi-Objective Evolutionary Algorithms (abstract)