LASCAS2021: 12TH IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS

This page contains an index consisting of author-provided keywords.

1
100GbE	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers
2
22nm FDSOI	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
A
abstract modeling	Chronos: an Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution
accuracy	Residual Impedance Impact on MAX30001 Accuracy for Bioimpedance Applications
analog	Analog and RF Circuit Constrained Optimization Using Multi-Objective Evolutionary Algorithms
Analog computing	Towards analog computing devices for matrix algebraic problems
analog IC design	A 1V, 450pS OTA Based on Current-Splitting and Modified Series-Parallel Mirrors
analog simulator	A Library of High-Level Models for the Simulation of DC-DC Converters
analog-to-digital converter (ADC)	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers A Redundancy-based Background Calibration for Comparator Offset/Threshold and DAC gain in a Ping-Pong SAR ADC
answer set programming	Reliability Analysis in Less than 200 Lines of Code
AOMedia Video 1	Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding
Approximate Adder	A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders
Approximate computing	Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures
approximate matrix inversion	FPGA Implementation of Stair Matrix based Massive MIMO Detection
Arithmetic circuits	High-Speed and Low-Energy Dual-Mode Logic based Single-Clock-Cycle Binary Comparator
ARM Cortex-A9	High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring
Artificial Neural Network	On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with Mismatch
ASICs Dependability	A JTAG-based Fault Emulation Platfrom for Dependability Analyses of Processor-based ASICs
ASIP	TailoredCore: Generating Application-Specific RISC-V-based Cores
automotive	Reconfigurable E-band Receiver Development for Joint Communication and Sensing
AV1	Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding
B
background calibration	Background Compensation of Frequency Interleaved DAC for Optical Transceivers A Redundancy-based Background Calibration for Comparator Offset/Threshold and DAC gain in a Ping-Pong SAR ADC
Backpropagation algorithm	An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers
behavioral models	A Library of High-Level Models for the Simulation of DC-DC Converters
Binary comparator	High-Speed and Low-Energy Dual-Mode Logic based Single-Clock-Cycle Binary Comparator
Bioimpedance	Estimating Cole-Impedance Parameters from Limited Frequency-Band Impedance Measurements Residual Impedance Impact on MAX30001 Accuracy for Bioimpedance Applications
biomedical	Design of a Constant Current Laser Driver for Biomedical Applications
Body biasing	Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX
Breast Cancer Detection	Assessment of key parameters in a microwave imaging system design for breast cancer detection
Bridging defect	On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory
C
cache memory	On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory
Calibration	Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX
capsule endoscopy	Design of a Constant Current Laser Driver for Biomedical Applications
CCDD	RF-DC Multiplier for RF Energy Harvester based in 32nm and TFET technologies
cell design automation	Electrical Evaluation of Logic Network Generation Methods for Supergates using SwitchCraft
chaotic oscillator	A CMOS Implementation of the Tent Map for Random Number Generation
Charge balance analysis	A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS
Charge pump	A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS
Circuit models	Assessment of key parameters in a microwave imaging system design for breast cancer detection
circuit simulation	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
classification	A Wearable Wireless Sensing System for Capturing Human Arm Motion
Clock generator	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
CMOS	High-Speed and Low-Energy Dual-Mode Logic based Single-Clock-Cycle Binary Comparator
CMOS analog design	A strategy to achieve competitive performance in basic RF LNAs
CMOS analog integrated circuits	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
CMOS Hybrid SAR ADC	ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications
CMOS integrated circuits	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
CMOS voltage reference	Femto-Watt CMOS Voltage Reference Design
CNN	Non-memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators
Cole-Impedance parameters	Estimating Cole-Impedance Parameters from Limited Frequency-Band Impedance Measurements
comb filter	Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors
Comparators	Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX
Comparison	Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters
compensator	Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors
computational memory	Design Considerations for the Development of Computational Resistive Memories
Computer Vision	A Brazilian Sign Language Gesture Recognizing System Using Gait Energy Image
Confocal algorithm	Assessment of key parameters in a microwave imaging system design for breast cancer detection
Contact-less temperature measurements	Study of a Voltage-Mode Readout Configuration for Micromachined CMOS Transistors for Uncooled IR Sensing
Continuous-time	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators
Control Flow Monitoring	High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring
Convolution Hardware Accelerator	A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators
Convolutional Neural Network	Non-memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks
Coprocessors	Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA
CoreSight	High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring
COTS components	Monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysis
crossbar	Design Considerations for the Development of Computational Resistive Memories
cryptography	A CMOS Implementation of the Tent Map for Random Number Generation
CTLE	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers
CTSDM	Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators
Current Behavior	Current Behavior on Process Variability AwareFinFET Inverter Designs
Current-mode Readout System	ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications
Current-steering	Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters
D
D/A converter	Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters
Data Aggregation	Edge Computing Technique for a 87% Energy Saving for IoT Device Dedicated to Environmental Monitoring
Datacenter	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers
DC-DC power converters	A Library of High-Level Models for the Simulation of DC-DC Converters
Decimation	Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors
decoupling cells	Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit
Delay-locked loop	28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer
delay-locked-loop (DLL)	Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits
Delta Sigma	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
Design automation	TailoredCore: Generating Application-Specific RISC-V-based Cores
design strategy	A strategy to achieve competitive performance in basic RF LNAs
design tools	TailoredCore: Generating Application-Specific RISC-V-based Cores
device variation	Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
DFE	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers
Diffusion charge redistribution	On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with Mismatch
digital-to-analog converters	Linearization for High Speed Current-Steering DACs Using Neural Networks
direct conversion	Reconfigurable E-band Receiver Development for Joint Communication and Sensing
discrete-time chaos	A CMOS Implementation of the Tent Map for Random Number Generation
DNA Computing	Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA
Down-Conversion	A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS Process
DPD	Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters
Dual-mode logic	High-Speed and Low-Energy Dual-Mode Logic based Single-Clock-Cycle Binary Comparator
dual-rail code	A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication
Dynamic voltage and frequency scaling	EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD Processors
dynamical systems	Towards analog computing devices for matrix algebraic problems
E
EDA	Benchmarking Open Access VLSI Partitioning Tools
embedded memory	On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory
Energy harvesting	A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS On the Possibility to Use Energy Harvesting on Beta Radiation in Nuclear Environments
Energy-delay product	EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD Processors
Environmental assesstment	Monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysis
Equalization	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers
error backpropagation	Background Compensation of Frequency Interleaved DAC for Optical Transceivers
error propagation	Reliability Analysis in Less than 200 Lines of Code
evolutionary algorithms	Analog and RF Circuit Constrained Optimization Using Multi-Objective Evolutionary Algorithms
F
Factorial DLLs	28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer
fault detection	On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory
Fault Emulation	A JTAG-based Fault Emulation Platfrom for Dependability Analyses of Processor-based ASICs
Fault Simulation	A JTAG-based Fault Emulation Platfrom for Dependability Analyses of Processor-based ASICs
FDSOI	28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer
femto-watt consumption	Femto-Watt CMOS Voltage Reference Design
FFE	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers
FFT	A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders
Field Programmable Gate Arrays	Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA
FinFET	Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit Soft Error Sensibility Window at FinFET DICE SRAM Current Behavior on Process Variability AwareFinFET Inverter Designs
FIR-DAC	Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators
Forward body biasing (FBB)	A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS
FPGA	FPGA Implementation of Stair Matrix based Massive MIMO Detection FPGA Implementation of a New PUF Based on Galois Ring Oscillators High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring Hardware Trojan with Frequency Modulation
frequency interleaving DAC	Background Compensation of Frequency Interleaved DAC for Optical Transceivers
Frequency Modulation	Hardware Trojan with Frequency Modulation
Frequency Synthesizers	28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer
front-end electronics	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
full wave rectifier	RF-DC Multiplier for RF Energy Harvester based in 32nm and TFET technologies
G
gain calibration	An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers
Gait Energy Image	A Brazilian Sign Language Gesture Recognizing System Using Gait Energy Image
GARO	FPGA Implementation of a New PUF Based on Galois Ring Oscillators
Gauss Seidel	FPGA Implementation of Stair Matrix based Massive MIMO Detection
Genomics	Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA
GPU	Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
Graph Models	Benchmarking Open Access VLSI Partitioning Tools
H
half-delay	Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits
Hardware Architectures	An Energy-Efficient Wavelet Haar Transform Architecture for Respiratory Signal Processing
Hardware Design	Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding
Hardware Neural Network	Non-memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks
hardware security	FPGA Implementation of a New PUF Based on Galois Ring Oscillators
Hardware Trojans	Hardware Trojan with Frequency Modulation
Harmonics	Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures
high-speed optical transmitter	Background Compensation of Frequency Interleaved DAC for Optical Transceivers
HNN	Non-memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks
I
in-memory computing	Design Considerations for the Development of Computational Resistive Memories
in-memory logic	Design Considerations for the Development of Computational Resistive Memories
inductorless	A strategy to achieve competitive performance in basic RF LNAs
Injection-locking	An ISM-Band Multi-Phase Injection-Locked Ring Oscillator
integrated circuit	A CMOS Implementation of the Tent Map for Random Number Generation
integrated circuit modelling	A Library of High-Level Models for the Simulation of DC-DC Converters
Integrated circuits	On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with Mismatch
Integrated photodiode	Novel Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF Communications
Interface circuit	Study of a Voltage-Mode Readout Configuration for Micromachined CMOS Transistors for Uncooled IR Sensing
Internet of Things	Monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysis
Intra Prediction	Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding
intrinsic noise	Femto-Watt CMOS Voltage Reference Design
ionizing radiation	On the Possibility to Use Energy Harvesting on Beta Radiation in Nuclear Environments
IoT	The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network Edge Computing Technique for a 87% Energy Saving for IoT Device Dedicated to Environmental Monitoring
ISFET	ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications
J
Jitter	Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators
JTAG	A JTAG-based Fault Emulation Platfrom for Dependability Analyses of Processor-based ASICs
L
laser driver	Design of a Constant Current Laser Driver for Biomedical Applications
laser spectroscopy	Design and implementation of a trans-impedance amplifier for a miniaturized saturated absorption spectrometer
LEDR code	A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication
LeNet-5	Non-memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks
Libras	A Brazilian Sign Language Gesture Recognizing System Using Gait Energy Image
linearization	Linearization for High Speed Current-Steering DACs Using Neural Networks
link-level simulation	Reconfigurable E-band Receiver Development for Joint Communication and Sensing
LMS	Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures
LNA	A strategy to achieve competitive performance in basic RF LNAs
low noise amplifier	Reconfigurable E-band Receiver Development for Joint Communication and Sensing
low power	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
low voltage	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
Low-noise amplifier	A strategy to achieve competitive performance in basic RF LNAs Novel Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF Communications
Low-power	An ISM-Band Multi-Phase Injection-Locked Ring Oscillator
Low-Power Frequency generation	28nm FDSOI Ultra Low Power 1.5-2.0 GHz Factorial-DLL Frequency Synthesizer
low-power wireless	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
M
Machine Learning	The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network
manycores	Chronos: an Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution
Massive MIMO	FPGA Implementation of Stair Matrix based Massive MIMO Detection
Mathematical modeling	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
MAX30001	Residual Impedance Impact on MAX30001 Accuracy for Bioimpedance Applications
Maximum power point tracking	On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with Mismatch
Medical imaging	Assessment of key parameters in a microwave imaging system design for breast cancer detection
memristor	Design Considerations for the Development of Computational Resistive Memories
Memristors	Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
Microelectronics	The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit Current Behavior on Process Variability AwareFinFET Inverter Designs
Microeletronics	Benchmarking Open Access VLSI Partitioning Tools
microprocessors	TailoredCore: Generating Application-Specific RISC-V-based Cores
MIMO detection	FPGA Implementation of Stair Matrix based Massive MIMO Detection
Minimap2	Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA
Mixed analog digital integrated circuits	Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
mixer	Reconfigurable E-band Receiver Development for Joint Communication and Sensing
MNIST	Non-memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks
model-based design	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
modified comb filter	Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors
motion	A Wearable Wireless Sensing System for Capturing Human Arm Motion
Multi-band	A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS Process
Multi-standard	A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS Process
Multiplier	RF-DC Multiplier for RF Energy Harvester based in 32nm and TFET technologies
N
nanotechnology	Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit
Neumann Series	FPGA Implementation of Stair Matrix based Massive MIMO Detection
neural networks	Linearization for High Speed Current-Steering DACs Using Neural Networks Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
Nitrates monitor	Monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysis
noise figure	A strategy to achieve competitive performance in basic RF LNAs
Noise reduction techniques	Novel Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF Communications
non-recursive structure	Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors
nonlinear optimization	Robust Passive Coherent Location via Nonlinearly Constrained Least Squares
numerical matrix computation	Towards analog computing devices for matrix algebraic problems
O
Offset voltage	Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX
Online Trace	High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring
Open-Source	Benchmarking Open Access VLSI Partitioning Tools
operational transconductance amplifiers	A 1V, 450pS OTA Based on Current-Splitting and Modified Series-Parallel Mirrors
optical coherent receiver	An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers
Optical receiver	Novel Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF Communications
optimization	Analog and RF Circuit Constrained Optimization Using Multi-Objective Evolutionary Algorithms
OVP	Chronos: an Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution
P
PAM4	Design Methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers
Parallel Computing	EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD Processors
partial fault tolerance	Reliability Analysis in Less than 200 Lines of Code
Particle Swarm Optimization	Estimating Cole-Impedance Parameters from Limited Frequency-Band Impedance Measurements
Partitioning	Benchmarking Open Access VLSI Partitioning Tools
passive coherent location (PCL)	Robust Passive Coherent Location via Nonlinearly Constrained Least Squares
Passive radar	Robust Passive Coherent Location via Nonlinearly Constrained Least Squares
Pattern Matching	Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA
PCE	RF-DC Multiplier for RF Energy Harvester based in 32nm and TFET technologies
Phase noise	An ISM-Band Multi-Phase Injection-Locked Ring Oscillator
photodetector	Design and implementation of a trans-impedance amplifier for a miniaturized saturated absorption spectrometer
photodiode	On the Possibility to Use Energy Harvesting on Beta Radiation in Nuclear Environments
Photovoltaic optimization	On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with Mismatch
physically unclonable function (PUF)	FPGA Implementation of a New PUF Based on Galois Ring Oscillators
pipeline	A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication
pipeline TI-ADC	An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers
Polynomial Regression	Edge Computing Technique for a 87% Energy Saving for IoT Device Dedicated to Environmental Monitoring
Power Consumption	Edge Computing Technique for a 87% Energy Saving for IoT Device Dedicated to Environmental Monitoring
PPA	A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators
Pre-distortion	Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters
Process Variability	Current Behavior on Process Variability AwareFinFET Inverter Designs
Q
QDI asynchronous logic	A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication
R
radar	Reconfigurable E-band Receiver Development for Joint Communication and Sensing
radhard design	Reliability Analysis in Less than 200 Lines of Code
Radiation-Hardness-by-Design	Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops
Radix-2 Butterflies	A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders
random number generator	A CMOS Implementation of the Tent Map for Random Number Generation
Reconfigurable	A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS Process
redundancy	A Redundancy-based Background Calibration for Comparator Offset/Threshold and DAC gain in a Ping-Pong SAR ADC
reference current	Design of a Constant Current Laser Driver for Biomedical Applications
Reliability analysis	Reliability Analysis in Less than 200 Lines of Code
residue amplifier	An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers
resistive open defect	On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory
resistive RAM	Design Considerations for the Development of Computational Resistive Memories
resistive switch	Design Considerations for the Development of Computational Resistive Memories
Respiratory Signal	An Energy-Efficient Wavelet Haar Transform Architecture for Respiratory Signal Processing
Ring oscillator	An ISM-Band Multi-Phase Injection-Locked Ring Oscillator FPGA Implementation of a New PUF Based on Galois Ring Oscillators
RISC-V	TailoredCore: Generating Application-Specific RISC-V-based Cores
RRAM	Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
S
SAR	A Redundancy-based Background Calibration for Comparator Offset/Threshold and DAC gain in a Ping-Pong SAR ADC
SAS	Design and implementation of a trans-impedance amplifier for a miniaturized saturated absorption spectrometer
Schmitt Trigger	Current Behavior on Process Variability AwareFinFET Inverter Designs
sensing	Reconfigurable E-band Receiver Development for Joint Communication and Sensing
sensor networks	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
Series residual impedance	Residual Impedance Impact on MAX30001 Accuracy for Bioimpedance Applications
short channel effects	Femto-Watt CMOS Voltage Reference Design
Sigma-Delta Modulator	Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators
Sign Language	A Brazilian Sign Language Gesture Recognizing System Using Gait Energy Image
Simulation	Assessment of key parameters in a microwave imaging system design for breast cancer detection Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
Single Event Effects	Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops
single event upsets	Reliability Analysis in Less than 200 Lines of Code
single-ended	A strategy to achieve competitive performance in basic RF LNAs
Single-Event-Upset	Soft Error Sensibility Window at FinFET DICE SRAM
sizing	Analog and RF Circuit Constrained Optimization Using Multi-Objective Evolutionary Algorithms
Soft error Reliability	The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network
soft errors	Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit
speed-independent control circuit	A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication
split-source (SS) comparator	A Redundancy-based Background Calibration for Comparator Offset/Threshold and DAC gain in a Ping-Pong SAR ADC
sports	A Wearable Wireless Sensing System for Capturing Human Arm Motion
SRAM	Soft Error Sensibility Window at FinFET DICE SRAM
stair matrix	FPGA Implementation of Stair Matrix based Massive MIMO Detection
Startup circuit	A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS
static CMOS complex gate	Electrical Evaluation of Logic Network Generation Methods for Supergates using SwitchCraft
Successive approximation register (SAR)	Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX
switched-capacitor circuit	A CMOS Implementation of the Tent Map for Random Number Generation
switching power converters	A Library of High-Level Models for the Simulation of DC-DC Converters
T
target location	Robust Passive Coherent Location via Nonlinearly Constrained Least Squares
tent map	A CMOS Implementation of the Tent Map for Random Number Generation
Terms—Analog to digital converters	Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC
TFET 32nm	RF-DC Multiplier for RF Energy Harvester based in 32nm and TFET technologies
Thermal sensor	Study of a Voltage-Mode Readout Configuration for Micromachined CMOS Transistors for Uncooled IR Sensing
TIA	Design and implementation of a trans-impedance amplifier for a miniaturized saturated absorption spectrometer
time-domain adder	Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits
Time-domain amplifier	Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits
time-domain integrator	Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits
time-domain register	Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits
tracking	A Wearable Wireless Sensing System for Capturing Human Arm Motion
traffic evaluation	Chronos: an Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution
Transconductance Amplifier	A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS Process
Transimpedance amplifier	Novel Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF Communications
transistor network	Electrical Evaluation of Logic Network Generation Methods for Supergates using SwitchCraft
Triple Modular Redundancy	Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops
U
ultra low transconductance	A 1V, 450pS OTA Based on Current-Splitting and Modified Series-Parallel Mirrors
Ultra-Wideband	Assessment of key parameters in a microwave imaging system design for breast cancer detection
V
varactor	Femto-Watt CMOS Voltage Reference Design
VCE	RF-DC Multiplier for RF Energy Harvester based in 32nm and TFET technologies
Verilog-A	A Library of High-Level Models for the Simulation of DC-DC Converters
Video Coding	Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding
VLSI	Benchmarking Open Access VLSI Partitioning Tools FPGA Implementation of Stair Matrix based Massive MIMO Detection Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures
Voltage readout	Study of a Voltage-Mode Readout Configuration for Micromachined CMOS Transistors for Uncooled IR Sensing
voltage scaling	Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit
W
wake-up radios	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
wake-up receivers	Ultra Low Power < 9nW Adaptive Duty Cycling Oscillator in 22nm FDSOI CMOS Technology using Back Gate Biasing
Wavelet Haar Transform	An Energy-Efficient Wavelet Haar Transform Architecture for Respiratory Signal Processing
Wearable	A Wearable Wireless Sensing System for Capturing Human Arm Motion
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