ABSTRACT. This paper presents the a design methodology for 112Gb/s PAM4 ADC-based receivers. The methodology is based on channel equalization to validate the specifications is proposed. A complete high-speed serial link in MATLAB Simulink was simulated. It is demonstrated the receiver is capable to equalize input data with channel losses close and up to 30dB at Nyquist Frequency. A combination of CTLE, long FFE taps with one-tap DFE presents as the best solution to cancel ISI. The resulting Bit Error Rate (BER) is within the specified range of 10^-4 to 10^-5.

ABSTRACT. A novel background calibration technique for the residue amplifier gain of a pipeline time-interleaved analog to digital converter (TI-ADC) is proposed in this paper. The technique is based on the backpropagation algorithm, which is widely used in neural network training, and can be applied to any pipeline topology, regardless of the number of stages. Backpropagation-based calibration is applicable to digital communication receivers, and the particular application discussed in this paper is coherent optical transceivers. The technique is able to operate in conjunction with other backpropagation-based TI-ADC mismatch calibration algorithms without introducing additional complexities. The main advantages of the technique proposed here are its robustness, its speed of convergence and the fact that it always works in background mode, which makes it suitable to track any process, voltage and temperature variations. Simulations are reported to demonstrate the effectiveness of the proposal for two different pipeline ADC topologies.

ABSTRACT. This work proposes a novel adaptive background compensation scheme for frequency interleaved digital-to-analog converters (FI-DACs). The technique is applicable to high speed transceivers such as those used in coherent optical communications. Adaptive background techniques for FI-DAC have not been reported so far. They can compensate errors caused by process, voltage, and temperature variations in the technology(e.g., CMOS, SiGe) implementation of the data converters, and therefore ensure high manufacturing yield. Background compensation is important because it does not need to interrupt the normal operation of the transceiver. The key ingredients of the proposed technique are a multiple-input multiple-output (MIMO) equalizer and the backpropagation algorithm used to adapt the coefficients of the latter. Simulations show accurate compensation and analog mismatch impact elimination, resulting in a high performance transmitter system.

ABSTRACT. This paper presents a novel technique to increase the sensitivity of optical receivers with a large integrated photodiode (PD). It consists of manufacturing the PD in several pieces, instead of a single device, and connecting a TIA to each of these pieces. The output signals of the TIAs are combined achieving a higher signal-to-noise ratio than with the traditional approach. This work shows a remarkable improvement of the sensitivity and transimpedance using a well-known TIA configuration without the need of additional modifications or compensation techniques. The results show an increase in sensitivity of 7.8 dB and in transimpedance of 8.7 dB and when dividing the PD in 16 pieces. The proposed technique can be applied to any TIA design and is independent of the core amplifier structure, which means it is compatible with every technology that allow the integration of PDs.

ABSTRACT. Machine learning (ML) algorithms are being incorporated in resource-constrained IoT platforms, which typically rely on reduced memory footprint and low performance processors. While performance improvement, customized, and reduced-precision implementations of such algorithms have been studied extensively, their susceptibility to soft errors caused by radiation particles is still an open question. This work contributes by investigating the impact of precision bitwidth on the soft error reliability of the MobileNet convolutional neural network (CNN) when executed on an Arm Cortex-M processor. Results obtained from more than 500k fault injections show that the soft error reliability varies depending on the precision bitwidth of the convolutional layers.

ABSTRACT. This work shows the soft error robustness of a FinFET DICE SRAM at 7nm technology. With the voltage scaling, the Dual Interlocked Cell robustness decreases as expected. Despite that DICE SRAM at hold state shows a high level of soft error immunity, there is a sensibility window for SEU during the read operation. The read operation is the most critical for SEU, and the operation at 0.4V shows a reduction of 58% on the LETth and 33% on the Read Static Noise Margin with similar behaviour compared with traditional 6T cell.

ABSTRACT. This paper presents a fault emulation platform to support dependability analyses of safety-critical ASICs. Differently than existing works, the focus of this paper is the fault detection mechanism that allows to mimic the detection mechanisms of a fault simulator (including fault dropping). The proposed platform can be integrated in the already-existing JTAG infrastructure of the target ASIC. Therefore, it can be easily accessed with standard tools and perfectly compatible with the modern industrial FPGA-based emulators.

ABSTRACT. With the advanced submicron process technology, the yield and reliability of the system majorly depend upon the embedded SRAM, a dominating component on system-on-chips. In deep submicron technology, the complex manufacturing technique results in an increased number of imperfections in the devices. To increase the yield, the effective test solution is required with less cost and time penalty to detect all kinds of defects in the SRAM. The technological advancements in the very deep submicron area have raised the challenges in normal operation with the effects of temperature and process variations. In this paper, a built-in circuitry integrated with embedded memory is proposed for the detection of a major number of defects in the memory and also diminishes the requirement of a separate testing circuit. In this work, the proposed assist circuit increases the coverage of weak resistive open defects with strong defects as well as bridging defects in the cell with less area overhead. This paper estimates the effectiveness of the proposed method that applies the word line stress with a predischarged bit line to detect the resistive open defects in the memory cell. The fault detection competencies are analyzed for a large range of resistive values at random locations in memory and validated with different process corners. The implementation of the proposed method gives a minimum area overhead of 3.87% and less time penalty of 20.48µs for 1KB of memory.

ABSTRACT. Although FinFET devices present attractive properties to control the radiation-induced soft errors, an accurate evaluation is important to ensure more reliable circuits, mainly at the near-threshold regime. This paper provides an evaluation of the SET sensitivity trends for a circuit-level benchmark, exploring different supply voltages using FinFET technology. Also, the adoption of decoupling cells, as a radiation-hardening technique, is evaluated to reduce the soft error susceptibility. Results show that near-threshold operation increases the fault rate in at least 53.2%. In this benchmark, the use of decoupling cells as a hardening technique is more efficient at 0.6V and 0.7V, reaching up to 10.4% on fault rate reduction.

ABSTRACT. The two main advancement fields which enabled the wide adoption of mobile applications for ICs (Integrated Circuits) are the scaling of technology nodes and battery density. Although, given that such improvements are not short of challenges, one of the main concerns for the bleeding-edge semiconductor industry is the impact of process variability upon the devices characteristics. This paper presents a behavioral investigation of the relationship between transistor sizing, supply voltage, and process variability level into the current behavior of inverter circuits, trying to indicate the possibility to replace traditional inverters for more robust circuits. Results show that robustness enhancing inverters can bring up to 44.45% and 6.26% decrease in dynamic and static current normalized deviations, respectively.

ABSTRACT. Pollutants originated by specific natural events, sudden or systematic inputs from anthropogenic activities in natural systems might be closely followed with the use of monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysis. The components settings of a data integrated flow monitor are adjusted with the analysis of current data trends, data functions and conditions for data evaluation. In this work, the data flow design and management of an environmental monitor is presented to optimize the MOLABS functioning, an IoT-COTS nitrates monitor for water quality assessment.

ABSTRACT. In this paper, we propose a method based on polynomial regression to perform data compression at the edge in order to reduce the energy consumption of connected objects. Our study is based on the trade-off between data compression at the edge and minimizing the error on data reconstruction on the server. A polynomial regression was experienced on a two-year database of temperature measurements. The error percentage between our data compression and the real temperature evolution have been assessed to determine the most relevant polynomial regression. A digital implementation of the data compression on an Arduino was carried out with a set of data collected over three weeks of experiments. The analyzis of the results concluded about the efficiency of our method with a reduction of 87% energy with an acceptable accuracy of 0.2◦C for temperature data collection.

ABSTRACT. This paper addresses the problem of target location by means of a passive radar. Existing approaches based on time difference-of-arrival (TDOA) measurements, namely spherical interpolation and spherical intersection, are revisited for the case of single transmitter and multiple receivers. The mathematical formulations of these state-of-the-art approaches do not take into account possible TDOA estimation errors, which degrade the target location performance. We extend those formulations by incorporating a nonlinear constraint into the underlying least squares problem, thus conferring robustness to the location technique against TDOA estimation errors, as corroborated by extensive numerical experiments.

ABSTRACT. Approximate matrix inversion based methods is widely used for linear massive multiple-input multiple-output (MIMO) received symbol vector detection. Such detectors typically utilize the diagonally dominant channel matrix of a massive MIMO system. Instead of diagonal matrix, a stair matrix can be utilized to improve the error-rate performance of a massive MIMO detector. In this paper, we present very large-scale integration (VLSI) architecture and field programmable gate array (FPGA) implementation of a stair matrix based iterative detection algorithm. The architecture supports a base station with 128 antennas, 8 users with single antenna, and 256 quadrature amplitude modulation (QAM). The stair matrix based detector can deliver a 142.34 Mbps data rate and reach a clock frequency of 258 MHz in a Xilinx Virtex-7 FPGA. The detector provides superior error-rate performance and higher scaled throughput than most contemporary massive MIMO detectors.