ABSTRACT. An optimized calibration methodology for high-speed comparators is proposed. The key features of this methodology are the offset extraction technique and the body-biasing calibration. The offset extraction technique uses a fast and accurate smart resettable successive approximation register (SR-SAR) algorithm to calculate the offset voltage (VOS). The body-biasing calibration is a simple iterative loop, where the body bias of the comparator's differential input pair is monotonically increased or decreased to counter balance the extracted offset voltage at each iteration. A study case using a strong ARM comparator implemented in 22nm FDX technology achieves a sigma VOS reduction by a factor of 12. The simulation time is reduced by a factor of 64 compared to the traditional linear approach showing the advantage of this methodology.

ABSTRACT. This paper introduces a variety of different pre-distortion/calibration methods for current-steering digital-to-analog converters (CS-DAC) and compares their respective performance. The comparison is done through simulations of the different methods with a static CS-DAC model in MATLAB and the subsequent calculation of the signal-to-distortion ratio (SDR) and the spurious-free dynamic range (SFDR). Since the requirements for high-speed, high precision applications are becoming more and more stringent on the data converters the need for calibration methods becomes also increasingly important. A quantitative comparison can help to decide on the right method for different applications in terms of reducing the distortions resulting from the static current cell mismatch of CS-DACs. This paper extends upon the previous research by using different input signal types for the simulations.

ABSTRACT. This paper proposes a novel foreground linearization scheme for a high speed current-steering (CS) digital-to-analog converter (DAC). The technique leverages neural networks (NNs) to derive a lookup-table (LUT) that maps the inverse of the DAC transfer characteristic onto the input codes. The algorithm is shown to improve conventional methods by at least 6dB in terms of intermodulation (IM) performance for frequencies up to 9GHz on a state-of-the-art 10-bit CS-DAC operating at 40.96GS/s (gigasamples-per-second) in 14nm CMOS.

ABSTRACT. In this paper we present the development of a Systematic high level design model based on MATLAB scripts. It is integrated into a graphical behavioral model toolbox for the synthesis and simulation of a Continuous-Time Delta Sigma ADC. For this, we decided to use a Model-based design approach which it is adopted to address problems associated with designing complex control and signal processing systems such as the case of Continuous-Time Delta Sigma ADC. The goal of our study is the design of a 10 bit ENOB ADC for energy measurement systems used in particle identification through a new generation of detectors based on diamond. Results of the synthesis of a proposed fifth order Continuous-Time Delta Sigma ADC modulator for 10-bit ENOB ADC based on a Cascaded Resonators Feedforward architecture and simulations of the dispersion of its components (due to fabrication process) using the proposed tool are demonstrated and discussed.

ABSTRACT. A background calibration algorithm is proposed for comparator offsets and thresholds, and DAC gains. It leverages redundancy in a 2-step ADC to detect errors without the need for additional analog blocks. It has been implemented off-chip for a 4× time-interleaved Ping-Pong SAR ADC, which demonstrates the tolerance for ±8% VDD variation and convergence within 180k samples after a sudden 5% VDD drop.

ABSTRACT. In audio applications such as Bluetooth and USB-C, where low power consumption and tight surface budget represent the greater constraints, continuous-time sigma-delta modulators (CTSDM) are the most interesting solution for data conversion. The main concern is their particular sensitivity to jitter which makes using specific countermeasures mandatory. Willing to use FIR-DAC single bit strategy to limit jitter impact, this paper wants to highlight the importance of a proper quantitative jitter analysis preliminary to design, which in prior works has always been made with approximations. To do so, a fourth order single-bit CTSDM clocked at 3.072MHz is also presented, showing that properly sizing the FIR-DAC with this method allow to reach the desired Dynamic Range (DR) of at least 100dB over 20kHz without taking certain kind of risks.

ABSTRACT. In this paper, a co-design methodology including link level simulation for an E-band reconfigurable receiver is presented. Receiver building blocks operating at 71 GHz - 76 GHz are developed to meet the needs of joint communication and sensing, targeted at smart systems for automotive applications. A reconfigurable architecture is proposed to reduce the silicon area, power consumption and other overheads of the realization. In a direct conversion architecture, the low noise amplifier (LNA) and mixer are designed to meet the wide bandwidth of such a mm-Wave system. The LNA provides a gain of 22.2 dB and a noise figure of 1.97 dB at 73.5 GHz. The mixer achieves a voltage gain of 6.6 dB and a noise figure of 7.8 dB. With the help of a Python based simulation framework, the feasibility of a joint communications/radar system is shown, by embedding a model of the circuit behaviour into a physical-layer simulation.

ABSTRACT. Low power applications entail the use of alternatives for phase-locked-loops in frequency generation for transmitter and receiver circuits. Regarding this idea, a ring oscillator based on the injection-locking principle has been designed using the UMC 180 nm process technology. The ring oscillator operates at an ISM band (432 MHz) and dissipates 308 uW with a nominal duty cycle of 50.6% and a phase noise of -98.9 dBc/Hz. The low-power operation capability makes the circuit a suitable candidate for biomedical applications.

ABSTRACT. Typically, low-noise structures tend to have a low number of elements; however, the constant search of better performance and improvement in Low-Noise Amplifiers (LNA) has led to much more intricate designs, and therefore to an increment in the number of components. This work suggests another option: returning to basic and efficient topologies and focus on the optimization methodology to solve the problem and achieve better results. Also, unsophisticated structures mean a higher degree of control over the circuit, and, hence, the reduced number of components enables methods unsuitable for more complex LNAs. An inductorless single-ended gm-enhanced common-gate LNA shows the advantages of this design strategy, obtaining competitive performance. The paper includes the analytical expressions of the topology, and all simulations and statistical analyses use complete technology models provided by manufacter.for accurate results.

ABSTRACT. A 100MHz - 5GHz down conversion mixer is reported for a multistandard wireless receiver with universal transconductance amplifier having reconfigurability in the form of RF band-width. In the proposed architecture RF bandwidth reconfigurability is reconfigured between low band (LB) RF frequency and high band (HB) RF frequency mixer modes. LB / HB reconfigurability is made through PMOS/NMOS switching the transconductance amplifier between these two modes. The proposed circuit is designed in UMC 65nm RFCMOS technology with 1.2V supply voltage. The circuit employs no inductors and operates from 100M - 600M in LB and 600M - 5G in HB. From the simulation results, the proposed circuit shows conversion gain of 35.4/27 dB, noise figure of 9/12.6 dB and IIP3 of -7.1/5.5 dBm in HB and LB respectively. The inductorless circuit can operate over a wide frequency range. Hence this circuit will be much helpful in multi-standard receiver design.

ABSTRACT. An ultra low power ring oscillator with less than 9nW of DC power at a supply of 0.5V for generating duty cycle signals for wake-up receivers is presented. It uses the possibility of FDSOI technologies to bias the transistor back gate separately to change the frequency in a wide range from 7kHz to 62kHz and pulse time within 90ns to 240ns. The circuit has a good compensation of drain current over temperature, which stabilizes the frequency and pulse time. The circuit is fabricated in a 22nm FDSOI technology. The core area occupies only 40µm x 80µm.

ABSTRACT. This work presents the design of an ultra-low-power frequency synthesizer based on a feedback loop composed by an improved version of the Factorial Delay-Locked Loop (F-DLL). Its output frequency is controlled by a set of current-starved delay units tuned by a standard DLL feedback loop and a set of logic circuits to generate an RF output frequency proportional to the reference. The objective of this circuit is to achieve a power consumption in the micro-watt range to generate the desired output frequency proportional to the reference frequency between 1.5 and 2.0 GHz, being capable of supporting a wide range of input frequencies with a low phase noise (lower than -90 dBc/Hz at 1 MHz offset) and 370 μW of power consumption. In order to ensure the locking state of the feedback loop and to reduce the phase noise, a modification of the biasing circuit for the voltage-controlled delay line (VCDL) is used to improve the linearity of the frequency response of the output using a complementary feedback loop architecture. The circuit was designed and fabricated using the 28 nm FDSOI technology from STMicroelectronics and the measurement results are presented.

ABSTRACT. This paper presents an assessment for a breast cancer detection microwave imaging system design, employing a multi-software simulation framework. The work aimed to identify circuits design key parameters to obtain quality images able to reveal malignant tumors. A set of backscattering signals were extracted from a 32 antenna system simulated scenario, and applied to a simulated proposed receiver model, including a Low Noise Amplifier, a Phased Locked Loop and Analog to Digital Converter. The design and implementation constraints arising in the context of event-driven simulation are discussed, targeting the most feasible key parameters for the circuit specifications. The results pointed out that better quality images with Signal to Mean Ratio greater than 11 dB can be obtained by choosing a 12-bit Analog to Digital Converter with 20 GHz of equivalent sampling frequency, a Root Mean Square maximum jitter of 0.1 ps, and implementing a Low Noise Amplifier architecture with a flatter frequency response.

ABSTRACT. This work proposes an energy-efficient Wavelet Haar transform for respiratory signal processing. We offer a Haar 5 transform for separating the frequency bands of the respiratory signals. The proposed fixed-point Haar transform uses multi-level M=1, M=2, and M=3 Haar transforms for the composition of five levels of resolution. The architectures were described in VHDL and synthesized using the ST 65nm CMOS cell library. The results show that the most area and energy-efficient Haar architecture employs one M=1 block and two M=2 blocks. The synthesis results show that the Haar-IV presents the maximum gains of 38.19% in cell area and 38.26% regarding both power dissipation and energy per operation compared with the other proposed architectures.

ABSTRACT. In this paper, an integrated constant current laser driver has been designed for biomedical engineering applications, along with an extra reference generator for nearby circuit blocks in the system using the same circuit core. The designed laser driver achieves a continuous wave operation for a vertical-cavity surface-emitting laser (VCSEL) by supplying a current of 12 mA. The reference current source provides a current of 95 uA. The total power consumption of both circuits is 49.4 mW. Monte Carlo analysis has been performed and the operation of both current references have been ensured despite a 3sigma process parameter variation.

ABSTRACT. Recent advances in DNA sequencing technologies include the generation of long reads, with lengths of thousands of base pairs or more. State-of-the-art Minimap2 algorithm is able to process these data besides the most common short reads, but is memory- and computationally-intensive; to process a human genome, its running times can reach up to several hours in powerful machines. Hardware accelerators have addressed these shortcomings in many short read mappers in the past, and their application to this new generation of softwares is an area of active research. Here we present a FPGA-based accelerator for Minimap2 with focus on its operation for short reads. We gathered profiling behaviors to determine the algorithm’s bottleneck. We generated a hardware block for one recurrent loop in the critical function that can be integrated into a parallelizable architecture. Execution with short reads has shown a reduction of 155x in terms of required clock cycles in the accelerated section. Data transfer overhead is measured and discussed.

ABSTRACT. In this work, the accuracy of the MAX30001 integrated-circuit for impedance measurements in conditions with series residual impedance between excitation and sensing leads (representative of bioimpedance applications) is characterized. Resistance and reactance measurements of 2R-1C configurations with |Z| < 200 Ohms in the frequency band from 1 kHz to 128 kHz are collected with residuals from 0 to 10 kOhms. In comparison to reference measurements without residuals, larger residual impedances decreased the accuracy of the MAX30001 reported measurements with the worst case observed for 10 kOhm.

ABSTRACT. This paper presents a low power non-recursive compensated modified comb decimation structure. A new simple wideband compensator for a modified comb is proposed. The compensator has only three coefficients, presented in a Signed Power of Two (SPT) form, which can be implemented by adders and shifts. As a result, we get a multiplierless compensator. Since the modified comb is a multiplierless filter, the overall filter is, like a comb filter, also a multiplierless filter. The compensated modified comb decreases comb-filter passband droop and improves its alias rejection. The benefits of the compensated modified comb are proven by the comparisons with the state of the art.

ABSTRACT. Abstract—AOMedia Video 1 (AV1) is a new bitstream format for royalty-free open source video coding, developed with the goal of providing competitive compression rates to state-of-the-art standards with high image quality. Due to the high computational cost of some tools included in AV1, the development of hardware solutions is required for real-time compression. This work presents a hardware solution for the directional intra-frame prediction of AV1 that explores operation sharing. An analysis over all bilinear filters that compose the 56 directional intra prediction modes was performed and allowed identifying that 37% of all prediction operations could be shared. The resulting proposed architecture was synthesized for the TSMC 40nm technology with a target frequency of 1,296 MHz, necessary for real-time processing of 4K video sequences at 60fps. The architecture achieved a power dissipation of 4,110 mW and a circuit area of 584.845 Kgates. The operation sharing strategy led to a decrease of 1.08% in power dissipation and 1.17% in circuit area when compared to a solution without sharing, on top of the automatic optimizations achieved by the RTL Compiler tool.

ABSTRACT. This work presents two hardware architectures for convolutional neural networks. The designs are concise, allowing for their implementation using programmable devices taking advantage of the high degree of parallelism and component reuse. Two different approaches are used: one architecture requires memory, while the other eliminates this need by exploiting a different sequencing pattern for the data processing. In the latter, it is possible to store only one intermediate result per network channel. We show that even when implemented on simple reconfigurable devices and using fixed-point precision, the proposed designs achieve low power, short processing time, and high hit rates, which are comparable to the hit rates obtained by a software implementation.

ABSTRACT. In this communication, some concepts related to matrix numerical computations are reviewed. In particular, the relationship among matrix computing with suitable dynamical systems is reported. It is also presented the possibility of obtaining the open-loop balanced representations of linear time-invariant systems by using an analog computation paradigm. This point of view allows to remark an analog circuit approach towards system theory computation.

ABSTRACT. A common problem faced by the deaf community is that most people do not know sign language so communication is still an issue. This is not different in Brazil, where the sign language is called Libras. Many technological solutions are being proposed but gesture recognition in video sequences is the less intrusive one. In this work, we address the problem of recognizing gestures of Libras in video sequences. To do so, we first segment the body parts of the person in the video using a deep neural network architecture, in a frame by frame fashion. Then, we employ Gait Energy Image (GEI) to encode the motion into a compact feature space. These features are fed to a classifier to attribute a label to each video. In our experiments, we achieved the 53.90±5.48% of accuracy using 1-NN and 79.57±2.39% using RF in the best configuration across the 24 dataset classes.