ABSTRACT. Using optical excitation with tunable photon energy from 0.5-3.3 eV, we have performed a capacitance based spectroscopy study of the energetic distribution of border traps in a SiO2-SiC system. Persistent photo-capacitance effect was observed in MOS capacitors due to optical excitation of electrons from the border traps. By scanning the photon energy from infrared to ultraviolet, both the energy and the concentration of the border traps are probed. Our findings reveal a high concertation of trapped charges near the valence band edge, as well as a significant concentration of localized charges in the bandgap. These localized charges likely stem from the charge transition levels (CTL) of defect species within the oxide. Additionally, a model for the optical excitation is also discussed.

ABSTRACT. In this study, we present a detailed EDMR study on p-channel 4H-SiC MOSFETs with dry oxidized. The dry-oxide MOSFETs showed the most degraded performance: its maximum field-effect mobility is 1.4 cm2V-1s-1 and threshold voltage is -17 V. An EDMR spectrum of the dry-oxide MOSFETs reveals a strong EDMR signal. We found several new carbon-related interface defects in p-channel MOSFETs, which are different from the PbC center and other interface centers detected so far. The new interface centers revealed hyperfine (HF) structures due to 13C nuclear spin, clearly indicating that their core atom is a carbon atom. We believe that a strong EDMR signal in p-channel MOSFETs mainly consists of three kinds of carbon-related defects, which we temporary call “center1,” “center2,” and “center3,” respectively.

ABSTRACT. Previous studies have shown that charge pumping electrically-detected magnetic resonance (CP-EDMR) is a powerful technique for detecting paramagnetic point defects at the SiC-SiO2 interface of a lateral n-type 4H-SiC MOSFET [1-3]. In this technique, the spin dependent CP recombination current (Icp) is generated from the source and drain to the body of the device by applying an oscillating voltage to the gate [4-5]. As a result, point defects at the interface are alternately filled with holes (accumulation) and electrons (inversion), when the gate voltage oscillates, with a given CP frequency fcp between a base voltage (Vbase) and Vbase + Va, with Va the amplitude of the CP experiment. A CP current is then generated when a trapped hole recombines with an electron at the interface, or vice versa. In CP-EDMR, the CP current is monitored while performing an EDMR experiment. In this case, the MOSFET is placed in the microwave cavity (X-band) of an electron paramagnetic resonance setup, and continuously exposed to microwave radiation with a fixed frequency while sweeping a magnetic field. Upon magnetic resonance, i.e. when the microwave energy matches the energy difference between the spin up and spin down level of the trapped electron/hole, a spin flip occurs which can then change the CP current. This is because recombination can only occur for electron/hole pairs with opposite spins, therefore spin flips can either increase or decrease the recombination rate which is directly reflected in a change of the CP current [6]. These changes can then be measured as a function of applied magnetic field.

Since the CP current itself is dependent on Vbase, also the CP-EDMR signal intensity, i.e. the change in the CP current upon magnetic resonance will depend on Vbase. A close correlation between both was reported in previous work [1], which in this work is investigated in more detail. In Figure 1, we present the CP current (in blue) and the corresponding CP-EDMR signal intensity (in red), using sinusoidal CP modulation at a frequency fcp = 313 kHz. Although the regions with CP and CP-EDMR signals overlap each other, the CP-EDMR curve is shifted to lower Vbase indicating that the signal primarily originates from recombination of trapped holes with electrons. Such a shift has recently also been observed in vertical-diffused (VD) MOSFETs [7].

Moreover, and different from CP, the CP-EDMR curve shows two distinct maxima at Vbase = −14 V and −12 V. Interestingly, when doing the same experiments at lower CP frequencies (fcp = 13 kHz), the difference between the CP and CP-EDMR curves becomes very pronounced, with the latter showing a sharp intensity decrease around Vbase = −14 V, as shown in Figure 2. A more in-depth investigation reveals that the CPEDMR signal results from the competition between two different signals, originating from two distinct point defects: for one defect the CP current increases on resonance, while it decreases for the other one (Figure 4). This signal inversion is clearly shown in Figure 3, where the change in CP current is measured directly (i.e. without field modulation) upon magnetic resonance for selected Vbase values left and right of the minimum. When examining the two CP-EDMR spectra recorded in these conditions, a clear difference can be observed in their hyperfine structure (red and blue arrows in Figure 5).

In conclusion, these results demonstrate selectivity in CP-EDMR for detection of two defects based on the trap energy as well as on the (positive or negative) response to magnetic resonance, which will be discussed in more detail. Also, CP-EDMR at high and low CP frequencies shows interesting qualitative differences that may related to defect and device properties, calling however for further analysis and interpretation.

ABSTRACT. We demonstrate the potential of the measurement of the photoelastic effect as a non-destructive and fast full-wafer method for quality control of 4H-SiC wafers and to assess the crystal growth process. For that purpose, we performed full wafer measurements of the stress-induced birefringence of 150mm diameter 4° off-axis 4H-SiC substrates. The results show that the measurements can be used to analyze qualitative differences between different substrates, but also for a very sensitive analysis of the residual stress in the wafer itself with a currently achieved detection limit below 1 MPa. We further correlate these measurements to the density and propagation direction of basal plane dislocations (BPDs) measured by x-ray topography (XRT), which gives additional insights into stress relief by dislocation formation. From the analysis of wafers from different manufacturers, we found that most of them exhibit a radial stress distribution as shown for wafer 1 and 2 in Fig.1. The tangential stress to the edge ranges between 5 and 15 MPa, whereas the stress in the center is below 2 MPa. Such a residual stress distribution is expected from a radially symmetric temperature profile during crystal growth. Guo et al. have observed that such thermal stress leads to prismatic slip resulting in a characteristic BPD orientation distribution[1]. We have analyzed the BPD orientation and can confirm this characteristic in our wafers. It is also expected that a higher thermal stress during growth leads to higher density of dislocations. In this study we observe a strong correlation between residual stress and BPD density giving a strong indication that we measure residual thermal stress in these wafers. Previously we have shown that SiC wafers exist which show a totally different BPD distribution[2]. We performed stress measurements on such wafers as well. Wafer 3 in Fig. 1 represents an example of such a specimen. The radial stress distribution as expected from a radially symmetric growth furnace cannot be observed here. In addition, the stress levels are very low. Nevertheless, this wafer exhibits a significant BPD density. This indicates differences in the growth process or a post-treatment, which results in a reduction of the stress by dislocation formation or multiplication. Besides observing the thermal stress field on a wafer scale, also local changes in the magnitude and direction of residual stress can be studied. We also address these effects and how they are related to different crystallographic defects in this study. Apart from thermal stress, also mechanically induced stress can be an important topic in the wafering process and might affect the (hot) bow behavior of the wafer during epitaxy and further device processing. Our measurement show increased stress at the wafer flat for most wafers which likely has been introduced during the preparation of the flat or the laser scribe. This stress introduced at cold process steps does not result in dislocations as verified by XRT measurements and is thus invisible to methods relying on dislocation detection.

[1] J. Guo et al., J. Electron. Mater. 46, 2040-2044 (2017). [2] P. Wimmer et al., poster presentation at ICSCRM 2023, Sorrento. [3] M. Fukuzawa, N. Kudo, J. Electron. Mater. 52, 5172-5177 (2023). [4] K. Kamitani et al., J. Appl. Phys. 82, 3152-3154 (1997).

ABSTRACT. Recent developments in the integration of microwave sources in an ASIC have allowed to develop so-called electron paramagnetic resonance on a chip (EPRoC), allowing for extremely compact and low-cost EPR instrumentation.[1] Recently, this method has showcased its potential for electrical detection of magnetic resonance (EDMR) in a thin a-Si:H solar cell, detecting EDMR through a change in conductivity in the photoactive layer.[2] Here, we extend EDMRoC spectroscopy to measurements of EDMR in lateral SiC MOSFETs, combining it with the powerful charge pumping (CP) characterization technique. In CP, the gate voltage is periodically changed between inversion and accumulation so that a rectified current can be extracted from the transistor channel region originating from a recombination of charges at defect trapping sites.[3] CP-EDMR has demonstrated the capability of identifying and quantifying charge traps within the transistor channel of SiC MOSFETs [4], but requires advanced instrumentation and is therefore not generally applicable in both fundamental and applied research as well as in industrial environments. In this paper we demonstrate for the first time CP-EDMRoC as a versatile, fast and sensitive method to detect EDMR in SiC MOSFET devices. Figure 1 shows a photograph of the EDMRoC printed integrated circuit board. The microwaves are integrated using an array of voltage-controlled oscillators (VCO) (indicated by the red rectangle) with overall dimensions of 6cm x 12 cm, which can be mounted between two permanent magnets (Figure 2). The sample is positioned above the microwave antenna using a customized holder PCB (Figure 3) providing the electrical connections for the CP experiments. In conventional EDMR the device is inserted inside a microwave cavity at a fixed microwave frequency to create a standing wave with maximal magnetic and minimal electrical component of the microwaves at the position of the device for highest magnetic resonance signal and lowest losses. A spectrum is then obtained by scanning the applied magnetic field. In contrast, in EDMRoC the microwave frequency is not fixed, allowing for scanning of either the magnetic-field or the microwave frequency. Moreover, for sensitive detection, conventional EDMR uses magnetic field modulation, which causes induction currents in the device circuitry that yield a background signal, while in EDMRoC this can be avoided using frequency modulation. Hence intrinsically, EDMRoC is expected to result in lower background signal and better signal intensity, though in the previous solar cell work [2] signal-to-noise ratios worse by at least a factor 10 were reported for EDMRoC. In this work, by the clever design of the device and device holder, matching the dimensions of the microwave antenna, we demonstrate signal-to-noise ratios that are very similar in state-of-the-art cavity-based EDMR and in EDMRoC (Figure 4). Moreover, the large sweepable magnet used in conventional EDMR was found to result in additional noise, such that EDMRoC using a permanent magnet as in Figure 2 demonstrates an even better signal-to-noise ratio (Figure 5). A detailed comparison will be presented to compare representative microwave powers, demonstrating EDMRoC as a versatile, compact, and low-cost alternative to conventional EDMR.

ABSTRACT. Medium-voltage (MV) power conversion systems (>3.3 kV) are currently limited to low switching frequencies of several hundred hertz or below due to losses in solid-state switches and diodes. The existing wide-bandgap solutions for MV-class switches and diodes are limited due to the lack of availability of high-quality uniformly doped SiC thick epitaxial layers with low defect concentration. Additionally, SiC unipolar switches and diodes rated >3.3kV suffer from high conduction losses at elevated temperatures. SiC superjunction (SJ) devices promise the best performance at >3.3 kV, with lower conduction loss at elevated temperatures. To date, 1.2–3.3 kV multi-epitaxial SiC SJ devices have been demonstrated [1-2]. Fabricating such devices by conventional ion implantation of dopants requires many iterations of epi regrowth due to the shallow depth of conventionally implanted atoms in SiC. GE Aerospace is currently exploring a novel third fabrication architecture for >3.3 kV device using ultra-high energy implantation (UHEI) and epitaxial overgrowth. This technology is based on successful development of charge-balanced (CB) devices, an intermediate structure between conventional and superjunction designs [3-4] . Recently, the team demonstrated the world’s first 3.5 kV SiC SJ deep implanted junction barrier Schottky (JBS) diodes (Fig.1) and the world’s first 5kV SiC SJ deep implanted MOSFETs (Fig.3). Deep-implanted SJ devices are formed through a small number of thick (12 µm each) epitaxial overgrowths. After each overgrowth, 12 µm deep high energy implants form P-doped and N-doped pillars extending through the full epilayer. Fig. 2 shows the resulting SJ-JBS diode has Ron,sp of 4.5 mΩ·cm2 at room temperature and 9.6 mΩ·cm2 at 150°C, which is ~45% below the SiC unipolar limit. The breakdown voltage is 3.8 kV with a low leakage prior to breakdown. The conduction and blocking characteristics of the 5kV deep implanted SJ MOSFET are plotted in Fig. 4. Ron,sp at room temperature is 9mΩ·cm², which is 25% below the SiC unipolar drift region limit. The device demonstrates a sharp and stable avalanche breakdown voltage at 5.1kV and leakage current density of <10µA/cm² below 4kV. To fully recover defects following UHEI, deep implanted SJ devices need to undergo a high temperature activation anneal at 2000 °C; devices receiving only a conventional activation anneal at 1700 °C exhibit high leakage (Fig.5) [5]. Fig.6 is a comparison between GE‘s CB and deep implanted SJ devices and the SiC unipolar entitlement showing a scalable path toward realization of more efficient MV converters.

ABSTRACT. Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are progressively displacing Si in lower voltage classes. However, in high voltage applications (>3000V), their conduction losses match those of Si IGBTs. To address this, Superjunction (SJ) and semi-superjunction (SSJ) technologies have been proposed to enhance the tradeoff between conduction losses and breakdown voltage (BV). Nonetheless, commercializing these designs encounters hurdles due to the intricate formation of deep P-type pillars. Recently, cost-effective methods for fabricating Schottky Barrier Diodes (SBDs) were introduced, advocating for a semi-superjunction design employing oxide-filled trenches and P-doped sidewalls to facilitate the superjunction effect with minimal implantation depth. This study proposes a 3.3 kV SSJ SiC MOSFET utilizing such techniques, potentially reducing fabrication costs. TCAD simulations assess the performance of standard planar structures, planar MOSFET Semi SJ (P SSJ), and trench MOSFET Semi SJ (T SSJ) devices. Static characteristics, including charge balance analysis, are examined, alongside a proposed solution involving a graded doping top epitaxial layer to maintain an equal charge balance. The expected result is an additional 4.9% reduction in specific on-state resistance (RONSP), compared to a uniform doped top layer. In conclusion, the proposed semi-SJ structures aim to decrease RONSP by 35.5% and 46.8% for planar and trench configurations, respectively, while ensuring ample sidewall implantation space and comparable off-state performance.

ABSTRACT. In medium-voltage applications (> 3.3kV), the predominant devices are SiC MOSFETs (Fig. 1(a)) and Si IGBTs. However, these devices face challenges such as high conduction losses for SiC MOSFETs and significant switching losses for Si IGBTs. Consequently, vertical high-voltage 4H-SiC superjunction (SJ) (Fig. 1 (b)) devices present a superior solution, offering improved conduction and switching characteristics. SJ devices exhibit a better trade-off between the specific on-resistance RON,sp and the breakdown voltage (BV) (RON,sp ∝ BV) to the conventional, uniform doped, vertical power devices (RON,sp ∝ BV2.3) as shown in Fig. 2 [1]. The imperative design of SJ devices is the alternating P and N pillars, where the thickness determines the breakdown voltage and their widths and doping influence the specific on-resistance. Fabrication of SJ devices necessitate precise processes involving multiple steps to ensure the desired charge-balanced pillars, particularly for thicker high-voltage pillars. Various techniques have been explored, including multi-epitaxial growth [2], trench-refill processes [3], and a series of MeV implantations and epi-growth processes [4]. However, these methods contribute significantly to the overall cost of SJ devices, potentially outweighing their benefits compared to conventional devices with similar breakdown voltage and current ratings. This paper conducts a comparative analysis of chip costs between SJ and conventional MOSFETs at specified breakdown voltage and current ratings, shedding light on the economic feasibility of SJ devices in 4H-SiC. We construct our cost model referring to GE’s previous study [4], leveraging their scalable devices that exhibit no performance degradation compared to other fabrication methods [2, 3]. We used the closed form set to calculate the performance parameters as a function of drift layer thickness for conventional MOSFETs [5]. For SJ MOSFETs, we employed the empirical formula developed by [6] for the blocking performance (BV) and [7] for the conduction performance (RON,sp). Additionally, we validate our static calculations through TCAD simulations. To estimate the active area for both devices, we have used Eq. (1), which is a thermal-based analysis developed in [8]. Assuming a JTE and periphery width for both devices to be 10µm + 5×drift layer thickness; the chip size can be estimated to calculate the total chip cost from using Eq. (2). For conventional MOSFETs, the substrate and fabrication costs are assumed to be $2000 plus a $50/µm for epitaxial growth cost, while SJ MOSFETs incur an additional cost of $3000 (or a variable as seen in Table 1) to produce 12µm pillar structure [4].

Table 1 outlines our assumptions for SJ MOSFET costs with different chip designs; the breakdown voltage crossover (see Fig. 3), where the chip price for both conventional and SJ MOSFETs become even is ~ 14kV for the baseline Chip#1 design. A $1000 reduction in pillar manufacturing cost can reduce the crossover to 8.5kV, yielding a 41% advantage for SJ MOSFET (Chip#2). When increasing the yield to 0.8 (to match that of conventional) or decreasing pillar width to 1μm (technological limit) can enhance it to 46 and 47% (Chip#3 and #4, respectively). Chip #5 reflects the lowest BV crossover achievable (Fig. 4). This analysis underscores the potential improvements in the SJ fabrication process and design to enhance its cost-effectiveness to benefit from its low RON,sp especially at higher BV ratings. The design methodology, cost model, and underlying assumptions will be elaborated upon in greater detail in the full paper.

ABSTRACT. We present a numerical exploration of the trade-off between specific on-resistance and breakdown voltage in silicon carbide superjunction (SJ) devices along the [0001] crystal orientation, spanning from full-SJ structures to hybrid configurations that integrate SJ and non-SJ layers (semi-SJ structures). In semi-SJ devices, where the SJ layer is thinner than the optimized thickness required for full-SJ devices to maintain a given breakdown voltage, performance falls short of that achieved by full-SJ devices. Systematic analysis of the performance against the thickness of the SJ layer also reveals a shift in the breakdown path. While full-SJ devices experience breakdown via a peak electric field at the interface of n- and p-pillars by the anisotropic impact ionization process, the path parallel to [0001] through the center of the p-pillar is responsible for breakdown as the thickness of the SJ layer decreases. The path switching in semi-SJ devices is intriguingly attributed to the reduced electric field at the interface compared to their full-SJ counterparts, stemming from the lower doping density of the SJ layer. Quantitative analysis offers insights into the transitional performance accompanied by the shift of the breakdown path from full- to semi-SJ devices.

ABSTRACT. In this study, we conduct a pulse test on the 10-kV-class thyristor to evaluate its on-state characteristics under high-current conditions. The pulse test involves gradually increasing the peak current in an LC resonant circuit formed by the thyristor and a charged capacitor. Results show that the thyristor withstands currents up to 157 A without breakdown, demonstrating its capability to energize large currents on the order of 1 kA/cm2. From he locus current–voltage characteristics obtained from the high-current pulse test waveforms, energization with an order of magnitude of 1 kA/cm2 has a small voltage drop of less than 20 V.

ABSTRACT. The mechanism of a positive Vth drift of trench and planar SiC power MOSFETs under bipolar AC gate stress was investigated by measuring electrical characteristics and detecting light emission from the channel. The positive Vth drift in bipolar AC stress can be explained by a photon-assisted electron injection model. In this model, electrons in the inversion layer are excited by receiving photon energy from recombination of holes and electrons at interface states, and subsequently injected into the gate oxide. Trench MOSFETs showed a stronger light emission above 2.7 eV and a larger positive Vth drift than planar MOSFETs. This can be attributed to a higher interface state density near Ev and a smaller conduction band offset.

ABSTRACT. SiC MOSFETs are promising as power switches but suffer from their small drain current. While it is commonly understood that interface defects reduce the number of electrons that contribute to the conduction, the limiting factors of electron mobility is still under debate. In this study, we investigate the impact of bias stress to have an insight about the limiting factors of mobility. Generally, bias stress induces oxide and/or interface defects and hampers the performance of MOSFETs. We investigate the impact of bias stress on the on-state characteristics of SiC MOSFETs. We show how the stress-induced defects affect the device performance and discuss the mobility-limiting factors of MOSFETs.

ABSTRACT. Anisotropy of SiC crystals leads to significant variance of their physical properties in different crystallographic directions and planes. In particular, it is well known that SiC channel mobility strongly depends on the chosen crystallographic direction [1], and a trench gate has a higher channel mobility than a planar one [2]. Other advantages of MOSFET trench geometry over a planar design include lower on-resistance, reduced conduction and switching losses and elimination of the JFET region [2, 3]. Nevertheless, these benefits come hand in hand with lower short-circuit tolerance and challenges of optimizing such MOSFETs for reliable and robust operation [3, 4]. Moreover, to our knowledge, apart from mobility [1] and mechanical characteristics studies [5], other differences between various crystallographic orientations perpendicular to c plane have not been thoroughly investigated yet. In this paper, we study the influence of trench orientation on threshold voltage shift (ΔVth) and its recovery in ultra-fast bias temperature instability (ufBTI) experiments and density of traps using the charge pumping (CP) technique. The prototype vertical trench devices used in this study were fabricated with several different trench orientations: 0° (anti-m) and 180° (m), 90° (anti-a) and 270° (a), along with intermediate 45°, 135°, 225° and 315° orientations. It is worth noting that due to standard 4° miscut of SiC wafers, only 0° and 180° coincide with true anti-m and m crystal planes, while all other listed trench configurations are 4° off from the corresponding crystal plane in one direction or the other. All measurements were performed on wafer level, each device had four contacts: drain at the backside of the wafer, source, gate and a separate p-body contact at the wafer surface. The gate oxide is a deposited SiO2 layer with subsequent NO anneal. The oxide thickness was 50 nm. We used the following equipment: Cascade microchamber attoguard Summit 11201B manual probe station and parameter analyzer Keithley S4200-SCS equipped with a 4245-PMU card, two 4225-RPMs and a 4200-PA preamplifier. In ufBTI, for each combination of stress conditions (gate voltage Vg=18/−5 V, stress time 10 μs/10 ms/10 s), six devices per trench orientation were stressed, and then ΔVth recovery data was collected. Box plots of recovery data obtained after 10 ms of stress at two different gate voltages are shown in Fig.1 (left panel) along with extracted median values of |ΔVth| for four recovery times (right panel). It can be clearly seen that (1) for positive BTI, three trench orientations have the smallest ΔVth values: 225°, 270° and 315°, with 270° (a) standing out; (2) for negative BTI, two trench orientations have the largest ΔVth values: 0° (anti-m) and 180° (m), while 45°, 135°, 225° and 315° orientations show comparable ΔVth values which are slightly better than the ones of 90° (anti-a) and 270° (a). These results are in line with the ones obtained at 10 μs and 10 s of stress. In CP, the data was collected at f=1MHz, trise=tfall=100 ns, duty cycle 50%, pulse amplitude 6 V. Three devices of each type were measured to get one CP curve shown in Fig. 2 (left panel). Peak ICP (and, consequently, the density of interface traps) decreases in the following order: 0° (anti-m) and 180° (m), 45° and 135°, 315°, 90° (anti-a) and 225°, 270° (a). One can also notice a ‘shoulder’ peak on the rising edge of CP curves for 90° (anti-a), 225°, 270° (a) and 315° orientations corresponding to donor states close to the valence band. Clearly, the density of these states should be the highest for 270° (a) configuration. Finally, we extracted threshold voltage and resistance for different trench orientations from their IDVG characteristics (Fig. 2, right panel). Although 225°, 270° (a) and 315° trench configurations demonstrate significantly lower resistance than the others, it comes hand in hand with a lower threshold voltage.

[1] H. Yano, H. Nakao, T. Hatayama et al., Materials Science Forum 556-557, 807 (2007); [2] R. Siemieniec, D. Peters, R. Esteve, W. Bergner, D. Kück et al., in Proceedings of the 19th European Conference on Power Electronics and Applications (2017); [3] C. Langpoklakpam, A.-C. Liu, K.-H. Chu, L.-H. Hsu, W.-C. Lee et al., Crystals 12, 245 (2022); [4] J. Wang and X. Jiang, IET Power Electronics 13 (3), 445 (2020); [5] S. Shi, Y. Yu, N. Wang, Y. Zhang, W. Shi et al., Materials 15, 2496 (2022).

ABSTRACT. In this work, we propose and experimentally validate a novel approach to achieve superior interface properties of the SiO2/SiC MOS capacitors through a low-temperature oxide deposition technique for gate dielectric followed by a nitridation process. Low interface trap density (~ 5×1010 eV-1cm-2), robust flat-band voltage stability under positive bias stress, and decent leakage current density (JG ~ 5×10-10 A cm-2) can be unambiguously verified after nitric oxide (NO) gas post-deposition annealing.

ABSTRACT. To address the issue of voids-defects, this study aimed to identify the cause of voids generation by surveying the position and shape of voids near the ends of CVD-filled SiC trenches. Additionally, we proposed a novel trench pattern design aimed at preventing the occurrence of voids-defects."

ABSTRACT. Silicon carbide (SiC) superjunction (SJ) technology is an attractive proposition to reduce the specific on-state resistance (Ron,sp) of unipolar SiC power devices. Previous works have achieved 800-1700 V 4H-SiC SJ devices using the multi-epitaxial process [1,2]. However, the cost of this method is prohibitively high, the low diffusion coefficient of 4H-SiC limiting each epitaxy/implantation repeat to approximately 1 µm of growth. Trench filling epitaxy (TFE), whereby trenches are etched into n-type 4H-SiC and subsequently refilled with p-type 4H-SiC through a partially selective epitaxial process, can overcome these limitations. However, many challenges must be overcome with this technology, including the etching artifacts of 4H-SiC trenches, the morphology change of 4H-SiC trenches by unintentional H2 annealing before growth, and the formation of voids within the refill regions. Here, we report an in-depth process and characterization of 4H-SiC TFE at a reduced growth temperature of 1550 °C with TCS+C2H4+HCl “over” chlorinated chemistry and investigate the influence of various growth parameters including Si/Cl ratio, trench aspect ratio, trench sidewall angle and misalignment to the [112 ̅0] offcut direction. 4H-SiC substrates were coated in 500 nm of SiO2 before a hard mask of Ni was patterned onto the surface via photolithography, sputtering and lift-off. Trenches of width 2 and 4 µm were etched to a depth of approximately 5 µm using a reaction ion etch (RIE) process using SF6 and Ar with an Oxford Instruments PlasmaPro 100 Cobra system. Following mask removal and RCA cleaning, epitaxy was carried out within an LPE ACiS M8 RP-CVD. The Si and C precursors were trichlorosilane (TCS, SiHCl3) and ethylene (C2H4) respectively. Samples were refilled with approximately 5 µm of 4H-SiC with n-type doping markers introduced at every 1 µm step. Additional HCl was added into the process to control the Si/Cl ratio and influence the trench refill process. Refilled samples were analyzed using scanning electron microscopy (SEM), atomic force microscopy (AFM) and cross-sectional transmission electron microscopy (X-TEM). Reducing the growth temperature to 1550 °C is observed to significantly minimize the mesa faceting effects often observed due to H2 annealing. The addition of HCl is shown to have a profound effect on the growth process of the 4H-SiC with an optimal Cl:Si ratio of 10, showing a clear preference to grow on defined crystal planes, see Fig. 1. As a result of more uniform growth, the surface morphology of the overgrown 4H-SiC is improved with additional HCl, resulting in a smoother coalesced surface, see Fig. 1a. The inclusion of doping markers in the 4H-SiC allows the growth rate to be extracted on various surfaces, see Fig. 1b. In the full submission, we will describe the characteristics and a mechanism for the growth in these modes. Increasing HCl flow rate is shown to modify trench growth rates affecting the trench filling percentage, see Fig. 1c. Trench sidewall angle also affects growth rates on different surfaces, see Fig. 1d. To assess the impact of trench orientation, trenches were fabricated at angles θmis of -5° to +5° with respect to the [112 ̅0] crystal direction. Trench refill was observed in all cases, however, the doping markers indicated that the angle θgrowth by which the growth propagated varied with the trench angle, see Fig. 2. θgrowth was found to stay close to 0° over a range of -1.5°< θmis<+1.5° offering a wide process window and tolerance on the fabrication of such trench structures. The trench sidewall angle can be controlled by tuning the dry etch process and the effect of this on 4H-SiC refill is shown in Fig. 3. As one would expect, void formation is more prominent in trenches with steeper sidewalls and can be eliminated at these growth conditions with a sidewall angle of 8°. This work is supported by funding from EPSRC through grant number EP/W004291/1 and by funding from Horizon Europe grant number 101075709.

ABSTRACT. The advancements in SiC crystal growth technology over the past two decades have been remarkable with a substantial reduction in threading dislocation and a significant increase in the wafer diameter. Despite these improvements, the complete elimination of dislocations critical for device performance remains challenging. In this context, lateral epitaxial growth through chemical vapor deposition (CVD) on standard 4-degree off-cut substrates with pillar structures presents a promising approach to minimize dislocation density replication into the device layer structure. The proposed method involves fabricating a pillar structure on the substrate surface through reactive ion etching, followed by lateral epitaxial growth and merging them into a continuous epitaxial layer. Through this approach we can minimize the substrate crystal replication into the epilayer and hence the dislocations and other extended defects. A pillar structure was fabricated through reactive ion etching on standard commercially available 100 mm diameter 4-degree off-cut substrates (Fig.1). These pillars had a height ranging from 1-2μm, a diameter of 1μm and an interspacing of 1-5μm. Epitaxial growth was conducted employing both standard and chloride-based chemistry at a growth rate of 10μm/h using a hot-wall CVD reactor. The growth was carried out in the temperature range of 1600-1660 ᵒC and pressure of 100-200 mbar. Intentional nitrogen doping was implemented within the range of 1.1015-1.1018 cm-3 and layers were grown up to a thickness of 15μm. Various analytical techniques were employed to characterize the epitaxial layers comprehensively. These techniques included optical microscopy with Nomarski contrast in reflection and transmission mode, atomic force microscopy (AFM), scanning electron microscopy (SEM), scanning transmission electron microscopy (STEM), electron backscatter diffraction, Raman spectroscopy, XRD, X-ray topography and room temperature PL imaging. One of the major challenges during epitaxial growth was the preservation of pillars during the temperature ramp-up phase under hydrogen as they were prone to etching under such conditions. The growth process was optimized to achieve preferential lateral growth on the side walls of the pillars i.e., in the a- and m-crystallographic direction at the early stages of growth forming a hexagonal structure, consistent with the crystal structure of 4H-SiC (Fig. 2 & 3). The non-staggered configuration of pillars leads to the formation of elongated grooves on the surface along the step-flow direction as anticipated (Fig. 4). To mitigate such surface morphological features, a staggered configuration of pillars was adopted, successfully eliminating groves on the surface. Through optimizing the growth rate and growth time a complete merger of the pillar structure was achieved (Fig 5). The hexagonal shape observed during the lateral growth of the pillar structure provides a visual indication of the 4H-polytype of SiC. However, to confirm this at a microscopic level, various analytical techniques were employed including Raman analysis, STEM, and EBSD. Following the lateral growth of the pillars, epitaxial layers were grown to a thickness of about 15 μm, with a highly doped thin buffer layer at the epi-substrate interface. These layers adhered to the layer structure required for 1.2kV MOSFET on 100 mm diameter wafers, as depicted in Figure 6. Despite exhibiting a slightly rough surface, the epitaxial layers attained a mirror-like finish. A comprehensive analysis of epitaxial wafers focusing on the structural, surface, and optical characteristics will be presented. Additionally, the reclamation of off-cut related step structure on the surface and epitaxial growth through step-flow growth and the feasibility of the lateral growth process for producing low-defect density epilayers suitable for electronic devices will be discussed.

ABSTRACT. The current SiC high-power device technology utilizes the Si-face SiC substrate, benefiting from high-quality interface and a large band-offset between the Si-face SiC and the gate oxide layer. However, carbon-face (C-face) SiC devices show potential due to their unique properties. First, a superior epitaxy process offers a large growth window and lower defect density [1]. Second, there is less defect generation during post-implant activation due to its higher polytype stability as compared with Si-face [2]. For trench device formation, the faster oxidation rate of C-face SiC compared to other crystal planes provides up to 3× thicker oxide at the trench bottom compared to the sidewalls, enabling simpler fabrication with improved gate breakdown voltage for C-face trench devices, despite the low band-offset between SiO2 and C-face SiC [3]. Moreover, C-face SiC enables graphene growth and new device architectures. There are few reports of epitaxy on C-face SiC, with most focused-on lab-scale processes using small size wafers [4]-[6]. Miyasaka et al. [5] reported epitaxy on 150 mm C-face SiC, but the growth rate is ~10 – 11 µm/h and defect density was ~ 0.9 cm-2. This paper reports the highest speed epi growth (~ 50 µm/h) on 150 mm C-face SiC and achieves a record-low defect density of < 0.1 cm-2.

ABSTRACT. The large work function of p-type SiC makes it difficult to form low-resistivity ohmic contacts. In terms of semiconductor physics, a metal with a large work function, which forms a small Schottky barrier on p-type SiC, should be adopted for ohmic contacts on p-type SiC. One of such metals is Pt, and there have been several studies on Pt-based ohmic contacts on p-type SiC. However, most of them are based on high-temperature annealing, which is similar to the current typical process to form Ti/Al-based ohmic contacts on p-type SiC. Since such high-temperature annealing causes various negative effects including electrode melting and surface roughness, it is important to develop a low-temperature process. In this study, current–voltage (I–V) characteristics, barrier height, and contact resistivity of the Pt electrodes formed on p-type SiC followed by annealing were systematically investigated by varying the annealing temperature. An ohmic I–V curve with contact resistivity of 3.2×10^-5 Ωcm^2 is demonstrated by 600°C annealing.

ABSTRACT. To ensure maximum device current is supplied through a vertical device having a backside ohmic contact, the specific contact resistivity, ρc, must be well characterized as it constitutes a portion of the device resistance. While there are multiple approaches to deduce ρc, the transmission line model (TLM) remains a convenient choice because of its simplicity in terms of fabrication, measurement, and analysis. For thick substrates where mesa isolation is impractical, the circular transmission line model (CTLM) is an attractive path. In this study we propose an additional restriction on the CTLM design such that the ρc is readily extracted from a simple linear regression just as is the case in a normal TLM. We demonstrate the simplified method by extracting ρc of an ohmic contact to the c-face of 4H-SiC substrate.

ABSTRACT. Nowadays, Schottky-barrier diode (SBD) on 4H-SiC is an established technology used in several real-world applications [1]. Although this large use, additional improvement is still possible for a fully exploitation of the 4H-SiC potentialities. Essentially, the properties of the metal/4H-SiC contact are at the base of the SBD performance and the achievement of a superior control on this interface drives an optimization of the use of the SBD. Over the last two decades, various approaches have been considered for gaining control in this system. Particular attention was paid to the choice of the metal and its evolution with thermal annealing in the Schottky contact formation [2,3]. Recently, the exploration of low-work function materials, such as W and Mo-based contacts, has demonstrated promising results for minimizing the power dissipation of Schottky diodes and offering good thermal stability [3,4]. In particular, Mo has demonstrated a large variability of the Schottky barrier height (ϕB) value dependently on the passivation treatment for the surface preparation [5] or the temperature of the deposition processing step [6], with the ϕB varying between 1.0 and 1.5 eV. From a structural point of view, Mo can readily form carbides and silicides and for that reason Mo-film deposited with Si or C element can be useful in preventing the reaction with SiC surface. For example, Mo-based contacts containing C were recently investigated, either deposited in laminated layers or from Mo-C alloyed targets [7,8], demonstrated stability of the electrical characteristics even at high annealing temperature. However, the origin of this electrical behavior is not clear and additional investigation is necessary to discriminate the role of the C. In this study we follow the evolution of the electrical properties of Mo/4H-SiC contacts with the increasing to the annealing temperature. The electrical characterization is combined with a microstructural analysis to shed light on the possible reaction at the nanometric scale to explain the electrical behavior. The starting material was a 4H-SiC wafer with a n-type epitaxial layer (1.5×1016 cm-3) grown onto a n+ doped substrate. Back-side Ohmic contact was fabricated by sputtering 100 nm-thick Ni layer, followed by a thermal annealing treatment at 950 °C in N2 for 60 s. Then, for the front side Schottky contact 80 nm-thick Mo film was sputtered with the contacts defined by optical photolithography and lift-off. Rapid thermal annealing treatments were performed in a furnace for 10 min in N2 at temperature of 700 and 950 °C. The electrical characterization under forward and reverse bias was carried out for a set of equivalent diodes by I-V measurements carried out in a Karl-Suss MicroTec probe station equipped with a parameter analyzer. For the microstructural properties, lamellae prepared by focused ion beam (FIB) of both samples were characterized by Transmission Electronic Microscopy (TEM). A GIF Quantum ER system was also used for electron energy loss spectroscopy (EELS) measurements. The forward current density–voltage (J-V) characteristics, representative of the electrical behavior in the as-deposited and 700 and 950 °C-annealed the Mo/4H-SiC contact contacts, are plotted in Fig.1. We observed that the as-deposited and 700 °C-annealed Mo/4H-SiC contacts have similar electrical characteristics, whereas a double-barrier behavior appeared in the J-V curves of the 950 °C-annealed contact, indicating an increase of inhomogeneity of the Schottky barrier. As shown in Fig.2, up to annealing at 700 °C only a slight variation of the ϕB, from 1.45 to 1.40 eV occurred while ϕB is 1.30 eV for the 950 °C-annealed contact. The ideality factor n kept low, considering for the 950 °C-annealed sample the highest barrier part of the double-barrier J-V curve. Regarding the reverse characteristics, we observed an anomalous increase of the leakage current when the annealing temperature reached 950 °C, as shown by the representative curves of the reverse electrical behavior in Fig.3. Moreover, Fig. 4, reporting the forward J value at 0.25 V against the reverse J value at 40 V, highlighted a larger statistical distribution after annealing at 950 °C. The combined TEM analysis on the two annealed contacts (Figs. 5a and b) demonstrated a different situation occurred after 700 °C and 950 °C annealing: in the first case, an unreacted 4H-SiC surface is still present, keeping the Mo layer in the metallic form with grain sizes in the range of few tens of nanometers and providing continuous and homogeneous interface. Instead, at 950 °C we observed the presence of columnar grain in the Mo-film, therefore with a vertical size of about 75 nm. The evolution of the electrical characteristics of the Mo/4H-SiC contact revealed stable properties up to tested annealing temperature of 700 °C, while the different electrical behavior at 950°C can be explained with the different Mo/4H-SiC interface and the variation of grain size in the Mo film. Additional analyses are in progress to discriminate the role of C and possible reactions with 4H-SiC in the Mo/4H-SiC interface and highlight the current transport mechanisms. [1] F. Roccaforte et al., Microelectron. Eng. 187–188, 66 (2018). [2] R. Yakimova et al., J. Electron. Mater. 27, 871 (1998). [3] M. Vivona et al., Semicond. Sci. Technol. 37, 015012 (2022). [4] R. Rupp et al., ISPSD 2017, Sapporo, Japan 2017 pp. 355–358. [5] A. B. Renz et al., J. Appl. Phys. 127, 025704 (2020). [6] T. N. Oder and S. B. Nardella, AIP Advances 12, 025117 (2022). [7] T. Suzuki et al., IEEE Electron. Dev. Lett. 37, 618 (2016). [8] Y. Yang et al., Microelectron. Eng. 239, 111531 (2021).

ABSTRACT. The 4H-SiC bonded substrate (SiCkrest) manufactured by SICOXS comprises an extremely thin (less than 1-μm thickness) monocrystalline 4H-SiC layer bonded on an n-type low resistivity polycrystalline 3C-SiC substrate by the surface activated bonding method. Such a unique hybrid structure is expected to bring some benefits that are not possible with a conventional 4H-SiC bulk substrate, such as reduction of on-state resistance in PiN diodes and reduction of forward bias degradation in PiN diodes. In this study, we focus on contact resistance between polycrystal and backside metal Ni/Ti of 4H-SiC bonded substrates and its temperature dependence. The circular TLM method was used to measure the backside contact resistance in order to improve the accuracy of the measurement. As result, bonded substrates have the low resistance backside contact can be formed without annealing, and no change in backside contact resistance at high temperature. In addition, the effects of on-state resistance reduction on power devices were evaluated by SBDs of bonded substrates. Unannealed bonded-SiC can reduce VF by 13% compared with annealed mono-SiC. These results suggest that the 4H-SiC bonded substrate can be greatly advantageous in reducing of on-state resistance of SiC power devices.

ABSTRACT. Abstract: This study investigates the role of ultra-thin conductive Indium-Tin-Oxide (ITO) as an interlayer at the Metal-SiC (MS) junction to lower the overall specific contact resistance (SCR) for source drain metallization applications on n-type 4H-SiC substrates. In this work, we demonstrate an improvement in SCR by 1 order of magnitude from ~10-6 Ω∙cm2 to 10-7 Ω∙cm2 through the integration of an ultra-thin ITO interlayer. Barrier height (ΦB) lowering by ~ 0.1 eV was observed at the MS interface as deposited which could have assisted in the reduction of the SCR. Titanium-based Ohmic contacts were subsequently formed at 950 °C. Various thicknesses of ITO were examined to assess their influence on the formation of ohmic contacts to n-type SiC. An SCR (ρc) of 6.9 × 10-7 Ω∙cm2 was achieved through integration of an ultra-thin conductive ITO interlayer at the MS interface. Introduction: The specific on-resistance (RON) in SiC devices consists of various components: n+ contact, channel, JFET, drift, and substrate resistances. In 4H-SiC power JBSFETs, the n+ contact resistance accounts for roughly ~50% of the total resistance, given a contact width of 1 μm [1]. Therefore, minimizing the SCR becomes crucial for reducing overall RON. The SCR in 7 nm CMOS node is much lower in comparison to SiC metal contacts due to the ease of silicide formation [2]. Our objective was to minimize carbon at the MS interface to achieve a lower SCR. In this study, a conductive metal oxide (ITO) was employed to facilitate the reduction of carbon during post metal deposition annealing (PMDA). Additionally, conductive ITO enables efficient charge transport across interfaces, acting as an effective passivation layer that can reduce surface states and enhance device performance [3]. This paper further investigates the role of ITO as an interlayer at the MS interface in SCR reduction. Results and Discussion: 4° off-cut N-type 4H-SiC substrates (0001), with a doping concentration of 5× 1018 cm-3, were cleaned by standard SPM and BOE (7:1) chemistries as per previous work prior to fabrication. Schottky Barrier Diodes (SBDs) were fabricated, as shown in Fig. 1 (a), with different ITO interlayer thicknesses followed by Ti/Al Schottky contacts. Subsequently, Circular Transmission Line Method (CTLM) structures for contact resistance measurement were also fabricated using a Ti-based metal stack (Ti/TiN) as shown in Fig. 2 (a-c). In Fig. 1 (b-c), I-V measurements on the SBD samples indicate a reduction in ΦB by ~ 0.1 eV with the incorporation of an ITO interlayer as deposited. Following the PMDA at 950 °C, only the ultra-thin ITO sample exhibited ohmic behaviour, as depicted in Fig. 1 (d). In thicker samples, the ITO could have hindered the intermetallic diffusion of the Ti-based metal stack into the SiC, resulting in rectifying behaviour. The deposited thickness of ITO had a notable impact on the ohmic behaviour of the sample. Passivation of the interface and surface states with ITO could have also lowered ΦB at the MS interface [3]. Results from Ultraviolet Photoelectric Spectroscopy (UPS) analysis indicated a slight decrease in the work function of the silicide, as shown in Fig. 2 (d). Electrical measurements on the CTLM structures with varying gap spacings of 20-100 μm revealed a ρc of ~ 10-7 Ω∙cm2 with the ITO interlayer, leading to a significant reduction by 1 order of magnitude as compared to samples without ITO [Fig. 3 (a-b)]. This reported value indicates a relatively low SCR as benchmarked in Fig. 3 (c) [4-7]. Intermetallic diffusion and silicide formation at the MS interface after 950 °C PMDA was investigated with Transmission Electron Microscopy (TEM-EDX) colour mapping as illustrated in Fig. 4 (a-h). We observed the clear formation of TiSi2 phase in the sample which forms the ohmic contact. An absence and clear out diffusion of carbon atoms from the silicide layer was also observed. This out diffusion could have been further promoted by positively charged Indium atoms from the ITO interlayer [8]. These carbon vacancies can serve as electron donors, potentially contributing to the improvement in ohmic contact formation, thereby achieving a lower SCR value. Conclusion: In this work, we have demonstrated that the incorporation of ultra-thin conductive ITO at the MS interface as an interlayer material had reduced the SCR by almost 1 order of magnitude to 6.9 × 10-7 Ω∙cm2 on n-type SiC. This was achieved through the reduction of ΦB and promotion of carbon out diffusion by the ITO layer. Acknowledgement: This work was supported by A*STAR (Agency for Science, Technology and Research Singapore), under Grant No. A20H9A0242.

ABSTRACT. Since a high Schottky barrier is usually formed at the metal/n-type SiC interface due to the low electron affinity of SiC, it is difficult to obtain low-resistivity ohmic contacts on n-type SiC without sintering. In the current process, ohmic contacts (typically NiSix) are formed by sintering at about 1000°C after metal deposition on heavily-doped n-type SiC, but the formation mechanism of ohmic behavior is not well understood. Since a metal with a small work function is desirable to achieve low contact resistivity (ρC) on n-type SiC, Ti which has the small work function (4.33 eV) is a promising candidate. In this study, the current–voltage characteristics, barrier height, and ρC of the Ti electrodes formed on n-type SiC were systematically investigated by changing the sintering temperature.

ABSTRACT. X-ray topography, particularly using synchrotron radiation has been key in characterizing and analyzing defect behavior in silicon carbide crystals from bulk growth through epilayer growth and device fabrication [1]. Understandings from these studies have contributed significantly to optimization of silicon carbide crystal growth to lower defect densities and improved performance of power devices. Rapid imaging and characterization of defects in silicon carbide crystals using X-ray topography has been greatly enabled by use of defect image simulations using the ray-tracing simulation technique [2]. Ray tracing simulation is based on the orientation contrast mechanism that has been shown to dominate contrast of defects observed on actual X-ray topographs. In this review, development of ray tracing simulation technique and its application to characterization of defects in silicon carbide crystals is discussed. The principle of ray-tracing simulation is introduced (Fig. 1) and simulated dislocation images such as micropipes, threading screw and mixed dislocations (TSD/TMD), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) are compared with experimental images (Fig. 2) [3]. Recent developments such as incorporating the effects of surface relaxation and photoelectric absorption to simulate different dislocations more realistically is discussed in both 4H-SiC as well as 6H-SiC crystals of various orientations. By incorporating the incident beam characteristics as well as the rocking curve of operative reflection, ray tracing simulations has also been adapted to simulate dislocations images recorded by weak beam topography [8] and plane wave topography [9]. A detailed investigation of effective penetration depth of all types of dislocations lying on the basal plane on grazing-incidence X-ray topographs is also presented [3]. Future developments of this indispensable tool for X-ray topography include extending its application to laboratory X-ray sources will be discussed.

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ABSTRACT. Reducing defects in SiC is key to improving device quality, and wafer scale techniques for identification of defects is critical for their mitigation. Although methods for imaging defects are well established [1-3], large image datasets are generated for wafer scale mapping. In order to classify each defect, creating an automated process is difficult as it requires a complex mathematical routine with improvement to the model requiring extensive research. Success using traditional programming techniques have been shown to detect basal plane dislocations in Ultra-Violet Photoluminescence (UVPL) images using their intense luminescence spectra [4]. However, some defects such as threading dislocations often show smaller, less consistent changes in intensity with a lower signal to noise ratio. In this work, we utilize advanced Machine Learning models to precisely detect and delineate dislocations in whole wafer images using a selective training dataset that also incorporates data where the model produces incorrect predictions. Thus, research into its effectiveness at defect mapping is valuable. This research focuses on studying the effectiveness of creating a machine learning model to count dislocations on SiC using UVPL imaging and x-ray topography (XRT) whole-wafer maps. The models were trained using a convolutional neural network (CNN) trained and tested with TensorFlow [5]. The training data consists of imperfect, manually classified defects on a small dataset (less than 25 MB). The CNN is used to pinpoint the probability of a defect being present with an example shown in Fig 1. The results of this study show that a CNN is a useful tool for mapping defects in SiC, as it can accurately locate dislocations defects and stacking faults and polytype inclusions with >95% accuracy using both UVPL and XRT images. The model was used to efficiently map the locations of the defects on a full 150 mm wafer (Fig 2), which allows for study of defect distribution, its formation in addition to providing allowing for direct study of a defects impact on device performance. Additionally, this work enabled identifying defects with higher precession than simple manual classification since our CNN model was able to detect defects missed during manual classification as highlighted in Fig 3. Thirdly, this project demonstrated that large datasets are not necessarily required to train a ML model, as only ~1500 defects in 10 images were needed for the training of the CNN model. Details of the CNN model and algorithms used for the classification of defects in the UVPL and XRT images will be presented.

Work at the U.S. Naval Research Laboratory was funded by the Office of Naval Research.

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ABSTRACT. For improving crystal quality of PVT-Grown silicon carbide (SiC) for power electronic applications, a comprehensive understanding of the mechanisms of generation, propagation, and conversion of defects during the growth process is of great importance. Prismatic punching can be induced through the formation and emission of dislocation loops of prismatic nature when a small particle with a strong contrast of thermomechanical properties vs. the host crystal forms an inclusion in the latter. The system behaves as an indentation punch that pushes prisms of the host crystal in the prismatic axis direction. The slip planes bounding the prism surface are displaced by the indenter with shearing stress, which can generate rings of dislocations through Frank-Read mechanism [1-4]. Such prismatic punched dislocation loops are primarily found in multiphase materials mainly with cubic structure [5-7]. However, observation of prismatic punching behavior has not yet been reported in published literature for hexagonal SiC. In this study, optically observable hexagonal shaped defect features (Fig. 1a) about 15-19 µm in diameter are found mainly distributed at the inner region of a 6-inch 4° off-axis 4H-SiC substrate wafer grown by physical vapor transport (PVT) method. Synchrotron X-ray topography (XRT) shows these defect features are foreign inclusions with large strain contrasts associated with each of them (Fig. 1b). On the grazing-incidence 11-28 reflection (Fig. 1c), these hexagonal features are found to be distributed at different depths within the crystal up to the effective penetration depth [8]. Inclusion contrasts are either white or dark (Fig. 1e), corresponding its position closer to the sample surface or embedded deeper into the crystal, respectively. This is confirmed by comparing the ray tracing [9] simulated inclusion contrasts at different depths below the crystal surface. The dislocations generated due to the presence of an inclusion are further investigated through synchrotron XRT in conjunction with ray tracing simulation. Indentation behavior is found to be induced by the presence of inclusions in both regular (9keV) and high energy (18keV) grazing-incidence topographs. These topographs show dislocation arrays that nucleated and propagated from inclusions along <11-20> directions, which supports the hypothesis of dislocation loop generation due to prismatic punching. These dislocation arrays exhibit opposite-signed threading edge dislocation (TED) pairs or basal plane dislocation (BPD) segments as determined by the position of prismatic loops with respect to the wafer surface (Fig. 2). The stress induced by inclusion embedded in the 4H-SiC matrix is estimated from the difference in the thermomechanical properties, as the crystal is cooled from the growth temperature. Moreover, generation of opposite-signed screw dislocation pairs, as well as BPD half loops, was also observed and attributed to the inclusions. This study will provide insights on the behavior of inclusions embedded in SiC as well as the activation of associated dislocations.

[1] F. Seitz, Rev. Mod. Phys. 79, 723 (1950). [2] D. A. Jones and J. W. Mitchell, Phil. Mag. 3, 1 (1958). [3] L. Brown and G. Woolhouse, Philos Mag. 21, 329 (1970). [4] M. Ashby and L. Johnson, Philos Mag. 20, 1009 (1969). [5] Y. Flom and R. J. Arsenault, JOM 38, 31 (1986). [6] M. Wada and J. Suzuki, Japanese Journal of Applied Physics 27, 972 (1988). [7] A. Giannattasio, et al., Comput. Mater. Sci. 30, 131 (2004). [8] Q. Cheng et al., Mater. Sci. Forum. 1062, 366 (2022). [9] X. R. Huang, et al., J. Appl. Cryst. 32, 516 (1999).

ABSTRACT. Silicon carbide (SiC) is one of the hottest semiconductor materials for use in high-power, high-temperature, and high-frequency electronic devices because of its wide bandgap, high breakdown electric field, high thermal conductivity, and device-applicable mobility of carriers [1]. Many kinds of structural defects were reported in 4H-SiC SiC substrates and epitaxial layers. Most of common defects in SiC materials are threading dislocations (TDs), basal plane dislocation (BPDs), and basal plane stacking faults (BSF) [1]. There are numerous studies on BSFs in 4H-SiC epitaxial layers and recently we reported investigations on Shockley-type and Frank-type stacking faults based on photoluminescence mapping and by high-angle annular dark-field (HAADF) high-resolution scanning transmission electron microscopy (HR-STEM) [2-3]. In addition to BSFs, there is other type of stacking fault, which is not existing on basal plane, called to prismatic stacking fault (PSF). Performance limiting surface defect in SiC p-n junction diode in 4H-SiC epitaxial layers was first reported as by T. Kimoto et al in 1999 and named to the carrot-like groove [4]. The carrot defect is one of the surface morphological defects in 4H-SiC epitaxial layers [4] and has been reported to the so-called killer defect, which strongly deteriorate SiC-based various devices [1]. In 4H-SiC, the PSF was reported in 2005 by M. Benamara et al. in studying a so-called carrot defect [6]. They concluded that the carrot defect consists of two intersecting planar faults on prismatic {1"1" ̅00} and basal {0001} planes. The PSF and the BSF are connected by a stair-rod dislocation at the crossover. J. Hassan et al. [7] systematically investigated various kinds of carrot defects and suggested the origins of the carrot defect. In this work, we investigated abnormal carrot defect which showed disconnected two surface groove lines and report buried PSF structure in the carrot, for the first time. Detailed structures of PSFs and BSFs inside the carrot defect were systematically investigated by HAADF HR-STEM. Fig. 1(a) and (b) show normal and abnormal carrot defects, respectively, and Fig. 1(c) shows typical zigzag feature of the PSF in the carrot defect. The normal carrot defect has one surface groove line connected from head to tail of the carrot. The abnormal carrot defect has two disconnected surface groove lines as shown in Fig. 1(b). At the region where the surface groove was disconnected we observed buried PSF inside the epitaxial layer as shown in Fig. 2(a). The buried PSF was not terminated on the surface, therefore, it inevitably could not from the surface groove. Fig. 2(b) shows HAADF HR-STEM image for the crossover pointe at the buried PSF and BSF of Fig. 2(a). Our finding implies that the PSF is existing from the head to the tail of the carrot defect even the surface groove was disappearing on the morphological surface defect of carrot. Detailed and systemic investigations of whole PSF and BSF structures with four crossover points and Burgers vectors for the relating stair-rod dislocations will be presented.

This work was supported by the Technology Development Program (Republic of Korea, No. 23A02029) funded by the Ministry of SMEs and Startups (MSS, Korea).

[1] T. Kimoto, Jpn. J. Appl. Phys. 54, 040103 (2015) [2] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Mater. Sci. Semicond. Process. 175, 108247 (2024). [3] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Appl. Phys. Lett. 124, 152109 (2024). [4] T. Kimoto, N. Miyamoto, and H. Matsunami, IEEE Electron Device Lett.,46, 471 (1999) [5] T. Kimoto, Z. Y. Chen, S. Tamura, S. Nakamura, N. Onojima, and H. Matsunami, Jpn. J. Appl. Phys., Part 1 40, 3315 (2001) [6] M. Benamara, X. Zhang, M. Skowronski, P. Ruterana, G. Nouet, J. J. Sumakeris, M. J. Paisley, and M. J. O’Loughlin, Appl. Phys. Lett., 86, 021905 (2002). [7] J. Hassan, A. Henry, P. J. McNally, and J. O. Bergman, J. Crystal Growth 312, 1828 (2010).

ABSTRACT. Silicon carbide (SiC) has become the material of choice for next generation high power electronic devices [1]. There are ongoing efforts to optimize the PVT growth process to obtain 150mm wafers with lower dislocation densities. The latter include threading screw mixed dislocations (TSDs/TMDs), as well as basal plane dislocations (BPDs). Prismatic slip systems were observed in SiC wafers. They were formed when threading edge dislocations (TEDs) lying in prismatic planes glide under the influence of radial thermal gradient stresses. Screw dislocation segments were left in their wake that can then cross-slip onto the basal plane. Previously, we reported on a radial thermal model of the PVT growth process developed to predict the distribution of prismatic slip [2]. This model, based on a cylindrical boule, predicted the occurrence of slip in different prismatic planes as function of radial position in the boule. The predicted distributions showed good correlation with observed distribution on X-ray topographic clearly demonstrating the role of radial thermal gradients in activating prismatic slip during PVT growth. Current studies, however, indicate surface-related prismatic slip nucleation at work, and an update from the cylindrical model to include the growth interface curvature complexity was needed to help further describe the behavior. Recent X-ray topography studies of 4H-SiC wafers reveal that during early stages of boule growth when the growth interface is relatively flat, prismatic slip dislocation distributions correlate well with the predictions of the previous thermal model [2] with high dislocation densities near the peripheral regions dropping to zero near the center (see Fig. 1(c) for wafer sliced from early stages). However, during the later stages of growth the dense distribution predicted by this model overlays a less dense distribution of prismatic slip dislocations that extends all the way to the center. This is observed in the wafer shown in Fig. 1(b) taken from later growth stages when the growth interface was more convex. The curved boule interface is composed of steps and terraces that will tend to form macrosteps. As the curvature increases, the resulting thermal profile at the growth interface was observed to result in sufficient thermal stresses to nucleate and propagate dislocations half loops from the surface steps (Fig. 2). In particular, kinks on the vertical step risers of the macrosteps may act as sites for nucleation of half loops on prismatic planes while the junctions between step risers and terraces can introduce BPD half loops. Additionally, the asymmetrical step configuration produced by off-axis growth can result in an asymmetrical distribution of prismatic slip due to the interface-shape mechanism. Manipulating the interface shape can make it vary from concave to convex with other complex shapes in between, having an effect on suppressing the prevalence of curvature-related prismatic slip generation when the surface curvature is lessened. Said another way, a higher radius of curvature reduces the contribution of surface prismatic slip generation. Based on these observations, a modified 3D axisymmetric thermal model using finite element methods that incorporates the shape of the interface is deployed and predictions of this model at different stages of growth will be presented and correlated to observations in wafers sliced from corresponding parts of the boule. Such studies can help optimize the growth to minimize occurrence of prismatic slip as boule diameters are increased to 200mm and beyond.

[1] H. Matsunami and T. Kimoto, Mater. Sci. Eng. R Rep. 20, 125(1997). [2] J. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quast and I. Manning, J. Electron. Mater. 46, 2040(2017).

ABSTRACT. It has been reported that high brightness single-photon sources (surface SPSs) are formed near the oxidation interface by thermal oxidation of a SiC substrate. However, the detailed defect structure is still not clear, which makes a device application difficult. In a previous investigation of the polarization properties of surface SPS, it was reported that all of them showed linear polarization and three orientations according to the basal orientation of 4H-SiC substrates. In this report, we investigated the polarization properties of samples with oxygen partial pressures of 1.0 atm and 2.0 atm in thermal oxidation of SiC substrates. As a result, it was found that the high-pressure oxidation (2.0 atm) tends to restrict the polarization to linear polarization oriented along a single basal axis.

ABSTRACT. The silicon vacancy in the silicon carbide (SiC) as a qubit system is a promising candidate for quantum repeater application [1]. Despite its advantageous properties such as an efficient spin-photon interface and long-lived spin qubit [2-3], achieving high-fidelity deterministic initialization of these qubits has not been fully investigated. In this study, we mainly focus on the photodynamic behavior of the V1 center in SiC using a 9-state rate model. This model intricately captures the complex population dynamics arising from static rate transitions, selective optical transitions, and the electron spin resonance transition (ESR). Notably, similar rate model approach has demonstrated good agreement with real-world data for defect-in-a-solid system [4]. Through careful analysis, we could successfully explain the underlying mechanisms governing population redistribution among the spin sublevels. We performed a systematic exploration of the parameter space of this rate model simulation. The key factors we investigated include the optical Rabi frequency, spin Rabi frequency, and laser excitation time. Through extensive simulations, we could find optimal parameter configurations that result in population condensation into specific ground states as in Figure 1. In other words, we found optimized parameters in achieving selective pure state initialization, a pivotal milestone in enhancing qubit fidelity and operational reliability. Furthermore, our study showcases notable advancements in qubit initialization fidelity, slightly exceeding the previous benchmarks 97% [2-3] as summarized in Table I. Specifically, we show that the initialization fidelity for the |+3/2⟩gs or |−3/2⟩gs ground state within a 1 ms time scale can exceed 99%. In summary, our study represents a pivotal contribution to the ongoing quest to unlock the full potential of silicon vacancy qubits, propelling them closer to real-world applications in quantum communication and computing. [1] D. D. Awschalom, R. Hanson, J. Wrachtrup, and B. B. Zhou, Quantum technologies with optically interfaced solid-state spins, Nature Photonics 12, 516 (2018). [2] R. Nagy et al., High-fidelity spin and optical control of single silicon-vacancy centres in silicon carbide, Nature Communications 10, 1954 (2019) [3] C. Babin et al., Fabrication and nanophotonic waveguide integration of silicon carbide colour centres with preserved spin-optical coherence, Nature Materials 21, 67 (2022). [4] N. Morioka et al., Spin-Optical Dynamics and Quantum Efficiency of a Single V1 Center in Silicon Carbide, Physical Review Applied 17, 054005 (2022).

ABSTRACT. Solid-state spin qubits are a building block of quantum applications including quantum computing, cryptography, and sensing. SiC is attractive as a host for the spin qubits due to its well-established crystal growth and process technologies. Various point defects in SiC such as N_CV_Si and V_CV_Si were demonstrated to act as optically addressable spin defects. Our recent theoretical study suggested O_CV_Si as a promising spin defect with near-infrared emission. As shown in these examples, complex defects including impurities and vacancies are an attractive candidate of spin qubits. In this study, we studied the stability and properties of complex defects in 4H-SiC by means of ab initio calculations. In particular, we systematically investigated the stable structure, formation energy, binding energy, and spin properties of impurity-vacancy complexes and the divacancy.

ABSTRACT. Single photon emitters (SPEs) are fundamental elements in quantum applications including quantum computing and communication. A part of the defects at the SiO_2/SiC interface is known to serve as SPEs. To yield practical applications, it is essential to have a precise control on the optical properties of the emitters. While bright emitters can be formed by thermal oxidation of SiC, overlap in their luminescence hinders the single photon characteristics. In a previous study, we proposed a method to generate isolated emitters; after formation of a high-quality SiO_2/SiC interface, low-temperature oxidation was performed to generate the emitters. In such a strategy, it is crucial to suppress the luminescent spots at the interface as the first step. In the present study, we systematically investigate the impacts of oxidation temperature and oxygen partial pressure on the photoluminescence (PL) intensity and seek a method to suppress luminescent spots at the SiO_2/SiC interface.

ABSTRACT. Despite recent advances in controlling plasmon polaritons in various metallic and semiconducting materials for applications in nanophotonics, the investigation of mid-infrared excited phonon polaritons remains underexplored. Phonon polariton excitation in polar crystals such as silicon carbide produces sharper optical responses due to weaker damping and reduced losses, offering unique opportunities for nanophotonic applications than it’s counterpart plasmon excited by visible range.[1,2] Furthermore, the investigation of phono polariton in emerging Two-Dimensional Silicon Carbide could lead to the novel application in the field of nanophotonics and optoelectronics as one of the most significant advantages of 2D SiC over any other 2D material is its high-temperature capabilities, as silicon carbide can tolerate high temperatures and extreme environments.[3] This work, thus, focuses on understanding light-matter interaction in 2D SiC using advanced structural and optical spectroscopy techniques. Our group employed the scattering-type Scanning Near-Field Optical Microcopy (sSNOM) based nano-FTIR to study the near-field absorption behavior of chemically exfoliated 2D SiC.[4] We performed the nano-FTIR spectroscopy of the sample surface with the illumination source provided by a difference frequency generation (DFG) laser covering range of 4.5 micron to 15.7 micron that overlaps with the Reststrahlen band of the various polytypes of SiC. Further, conventional far-field FTIR was performed on bulk SiC to study the far-field absorption behavior and blueshift was observed in near-field absorption compared to far-field. Figure 1. shows the near-field phase spectroscopy related to the absorption behavior of the exfoliated 2D SiC nanosheet, and far-field absorption spectroscopy of bulk SiC. Also, the structural characteristics of the synthesized SiC nanosheets were investigated using transmission electron microscopy (TEM).

ABSTRACT. In this work, SiC engineered substrate based MOSFETs were characterized statically and dynamically. Furthermore, the surge current capability of the body diode and short circuit type I robustness were investigated for these devices and compared with standard devices. It was found out, that the specific on-state resistance is reduced in comparison to reference SiC-MOSFETs based on single-crystal SiC substrate. The reverse recovery charge of the SiC engineered substrate based MOSFETs was reduced by 40% as compared to reference devices, especially at elevated temperatures. From a robustness point of view, there was no significant change in terms of critical surge current density or short circuit withstand time was observed. However, the critical energy density during surge current is decreased for SiC engineered substrate based MOSFETs.

ABSTRACT. In this work, the extrinsic reliability of the gate oxide for SiC MOSFETs is studied using 200 MeV proton irradiation. Damage in the gate oxide is not directly observable, as no threshold voltage shift is seen. Yet, gate leakage current investigations show that Fowler-Nordheim tunnelling (FN tunnelling) may introduce leakage paths in the oxide, which significantly reduce time-dependent dielectric breakdown (TDDB) measurement times of said devices, and thus reduce the gate oxide reliability.

ABSTRACT. A major challenge for SiC MOSFET adoption in EV applications is gate oxide failures due to surface defects. However, conventional screening techniques are not aggressive. Although infant failures can be removed, some non-infant failures close to the intrinsic failure line still survive, which causes 2%–3% failure of devices in EV inverters in the field. The purpose of this work is to develop an effective method to remove the extrinsic failure tail and find devices with more intrinsic lifetime uniformity. In this work, the relationship between gate leakage currents under different stress conditions and oxide lifetimes for commercial SiC discrete MOSFETs and power modules is investigated through Igss testing and constant-voltage (CV) TDDB measurements. Igss and tbd are correlated by utilizing Fowler-Nordheim tunneling and charge-to-breakdown mechanisms. Based on the fitted lines and the cumulative distribution function, the value of Igss for devices that cannot reach tF% is predicted.

ABSTRACT. 4H-SiC power devices are rapidly conquering the power semiconductor markets and are more and more implemented in commercial systems [1]. Therefore, competitive pressure is increasing, with yield and reliability becoming key issues for successful commercialization and application of SiC devices. One of the most critical components in terms of yield and reliability in a 4H-SiC VDMOS transistor is the gate oxide. In the past years, the focus of research has mostly been on the optimization of gate oxides by interface-engineering for improvement of mobility and threshold voltage [2]. Regarding the reliability of gate oxide, the investigation of intrinsic gate oxide failure was prioritized [3]. However, the next step is to investigate the failure mechanisms of the SiO2 on SiC in terms of electrical yield, namely initial gate oxide failure, and the extrinsic failures in the device lifetime. From past investigations a correspondence of epitaxial defects and device performance in general as well as the gate oxide performance in particular, is strongly suspected [4]. Therefore, an extended design of experiment was implemented, to investigate the extrinsic failures of gate oxides on 4H-SiC. The 4H SiC epitaxial wafers used in this work are investigated with surface inspection, including ultraviolet photoluminescence imaging and differential interference contrast, to further work out the role of epitaxial defects in the oxide breakdown behavior. MOS capacitors of different sizes were fabricated in a research and prototype 4H-SiC BiCMOS fabrication line on 150 mm 4H-SiC epitaxial wafers. The wafers were prepared with different oxidation processes and pre-oxidation treatment, including LPCVD TEOS and thermal oxidation, with a target gate oxide thickness of 55 nm. The implemented processing conditions are typically used for commercial power-transistor fabrication as well as channel mobility optimization, like H2-surface treatment and NO post oxidation annealing [5]. For the gate electrodes, an in-situ n-doped polysilicon layer is used. Time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) method with constant current stress (CCS) were used as characterization techniques. In Fig. 1 results of these measurements on capacitors processed by thermal oxidation (sample #1, S1) are presented. In Fig. 2 results of TDDB measurements for sample #1 and a sample with capacitors processed with LPCVD TEOS (sample #2, S2) are compared. Various aspects are investigated to analyze the root cause of gate oxide failure such as epitaxial defects, fabrication process, device size, temperature, and electrical stress. From these data sets, theoretical defect densities and distributions are calculated for oxide-damaging defects. The influence of high temperatures on the distribution and breakdown behavior is investigated on different samples, to draw conclusions on possible defect activation. It is further investigated, if the ratios of initial failure to both extrinsic and intrinsic defect mechanisms can be shifted by the implementation of processing conditions, different application temperatures, or by electrical pre-stressing of the oxide. Distributions of electrical failure and location sites are compared with the epitaxial defect distributions and locations. The origin of extrinsic failures is analyzed and a trade-off between performance and failure behavior of different processes is examined and discussed. Thus, a deeper understanding of initial, extrinsic, and intrinsic breakdown for 4H-SiC gate oxides is established.

[1] X. Yuan, IECON 2017, Beijing (2017) pp. 893-900. [2] K. Tachiki et al, Appl. Phys. Express 14, 031001 (2021). [3] K. P. Cheung, J. Appl. Phys. 132, 144505 (2022). [4] H. Schlichting et al, Mater. Sci. Forum Vol. 1090, pp.127-133 (2023). [5] K. Mikami et al, IEEE T-ED Vol. 71, Iss. 1, pp. 931-934 (2024).

ABSTRACT. The operation of gate driver circuits based on 4H-SiC MOSFETs at temperatures of up to 500℃ was investigated. When the ambient temperature increases to 500℃, while the rising time of the signal at the output terminal of the GD circuit remains stable, the falling time decreases. Meanwhile, the switching characteristics of the SiC power MOSFET is also improved when the operation temperature of the GD circuit increases. The extracted values from the transfer characteristics of the 4H-SiC MOSFET indicate that while the threshold voltage decreases, the field effect carrier mobility increases with the ambient temperature. The decrease of channel resistance induces the improvement in switching characteristics of the GD circuit with temperature. The results obtained from this research indicate that the GD circuit based on 4H-SiC MOSFETs is promising to apply for high-power applications.

ABSTRACT. Silicon carbide (SiC) power MOSFETs and diodes exhibit exceptional features for power electronics applications, with avalanche ruggedness being an advantageous characteristic.[1]–[3] This attribute underscores the device ability to endure high energy dissipation during avalanche breakdown, owing to the SiC inherent wide bandgap nature and low intrinsic carrier concentration. SiC MOSFETs, whether trench or planar structure, and SiC Schottky barrier diodes (SBD) or merged-PiN-Schottky (MPS) architectures, typically demonstrate outstanding unclamped inductive switching (UIS) performance. Fig.1a. depicts schematic structure of SiC MOSFET and an MPS diodes. Despite the widespread acknowledgment of UIS potential in SiC devices, discrepancies exist regarding its perceived importance, testing and screening, datasheet reports, and distinction made e.g., for automotive or non-automotive applications. In this study, we present UIS analysis in single and repetitive modes (SUIS & RUIS) on SiC MOSFETs and diodes, enabling to effectively defining measurement set points at both wafer-level and final test screening stages, and to assess its significance concerning device lifetime considerations. Our findings support the ongoing efforts aimed at establishing standards and guidelines for wide bandgap semiconductors, e.g., AECQ101. We conducted experiments using 1200V SiC MOSFETs (15mΩ, 40mΩ, 80mΩ) and 650V MPS diodes (10A, 30A), intentionally selecting devices with varying lifetime performance, particularly under high-temperature reverse bias (HTRB), high-temperature-voltage-humidity reverse bias (H3TRB), and temperature cycling (TC) conditions. This allowed us to investigate potential correlations between UIS and lifetime issues and assess its screening capabilities such as in termination designs and fabrication process parameters. Fig. 1b showcases a stepwise evaluation of SUIS performance for a 1200V/15mΩ SiC MOSFET (TO247-3L package), demonstrating flawless tester and device functionality without any unusual waveform ringing. Similar evaluations were conducted across different inductive load (L) ranges and product types, excluding any setup-devices related abnormalities. Further SUIS testing was carried out on such samples at different L, with the maximum pass current/energy values summarized in Fig.1c. The results highlight a rugged SUIS performance of devices, all showing reproducible high UIS ruggedness at very high energies. For a comparative study, we conducted SUIS on another known product in the market with the same voltage/RDSon class, as shown by C1 samples in Fig.1c. C1 samples also exhibited robust UIS performance but with approximately 80% lower SUIS current rating (~66% energy rating), which can be attributed to their smaller die size. Fig. 1d shows representative destruction physical analysis (DPA) revealing thermo-mechanical failure and breakdown in the active area following design expectations. Furthermore, dissipation energy is positively proportional to the inductive load in contrast to UIS current, thus it is important to properly select inductive ranges for final testing to effectively screen out latent-failures while avoiding unwanted destructive device overstresses. To this aim, we carried out repetitive UIS (RUIS) on 1200V/15mΩ SiC MOSFET devices with intentionally selected weak HTRB performance. The RUIS testing was performed at 80% of the SUIS current rating reported in Fig. 1c. The main static parameters were characterized before and after 100 cycles and 500 cycles of repetitive testing. The results after 500 cycles of RUIS are summarized in the table shown in Fig1.e, indicating almost no changes in the static parameters. The slight reduction in drain (IDss) and an increase in the gate (IGss) reverse current characteristics could be attributed to charge impurities or interfaces at oxide and termination areas. Both changes were still within the devices' specifications, with actual measurement values of IDss=240nA(VDS=1200V) and IGSS=100pA(VDS=0, and VGS=22V). Given the very short timing event of a few hundred to a few thousand microseconds stress time, it is reasonable that even weak-performing HTRB devices do not show any signs of degradation after 500 cycles of RUIS, leading to collectively a maximum of about 2 seconds of stress time at 5mH load. Our statistical analysis on other MPS and MOS devices with poor HTRB capability led to the same conclusion. Accordingly, even such devices safely well withstood at 80% of the RUIS current rating. In Fig. 1.c, with additional 20% safety margin, we highlighted safe testing areas of 60% current rating equivalent to 36% energy rating. Now, to effectively choose the UIS testing setpoint, we propose L around 500uH range for both 650v/1200 class MOS and diodes, highlighted by the green rectangle in Fig.1c. This enables both high current and minimizes energy dissipation, thereby reducing the risk of device overstress. To support this, we performed UIS testing on weak UIS devices, which revealed the highest distribution and fail rate under low inductive loads, indicating effectivity of UIS screening at low L. Additionally, to explore the impact of crystal defects, we conducted RUIS on devices with stacking faults and BPD inclusions posing a risk of bipolar degradation. [4-5] The detailed results of ongoing analyses will be further discussed at the conference. In conclusions, our findings shed light on the lesser effectiveness of UIS screening in correlation with lifetime issues such as HTRB/H3TRB. However, it underscores its paramount importance during the development phase for process window considerations and design optimization. We present the testing protocol and strategies which enables to properly implement UIS in final testing and screening, which effectively strikes a balance between avoiding parasitic loads, setup possible constraints while enabling UIS at high currents while minimizing energy and unwanted thermo-mechanical stresses, thereby facilitating screening of possible incipient failures without overstressing the devices. This work supports the effort for developing standard for wide bandgap semiconductor. [1] A. Fayyaz, B. Asllani, A. Castellazzi, M. Riccio, and A. Irace, Microelectron. Reliab., vol. 88–90, pp. 666–670, 2018. [2] K. Lee, M. Domeij, J. Franchi, B. Buono, F. Allerstam, and T. Neyer, PCIM. pp. 873–878, 2018. [3] T. Basier, R. Rupp, R. Gerlach, B. Zippelius, and M. Draghici, PCIM Eur.pp. 180–187, 2016. [4] D. Momeni, M. Mazzilo, S. Laha, S. Sani, J. Urresti Ibanez, T. Dai, C. Liguda, S. Habenicht, ICSCRM Conf. Sorrento, 2023 [5] S. Laha, J. Leib, M. Maerz, A. Schletz, C. Liguda, F. Faisal, D. Momeni, CIPS, Düsseldorf, 2024

ABSTRACT. This study proposed a method for estimating device lifetime under high gate voltage stress conditions for SiC-MOSFETs. Variation in threshold voltage (VGS(th)) may cause electronic circuits to fail to operate properly. Therefore, it is necessary to estimate not only the lifetime of dielectric breakdown but also the lifetime until the variation of VGS(th) exceeds the appropriate voltage range. Generally, the gate voltage stress wear-out failure lifetime of MOSFET is evaluated by accelerated life tests with high gate stress. Under high gate voltage stress condition of n-channel SiC-MOSFETs, VGS(th) fluctuations due to electron injection and the anode hole injection (AHI) effects are observed before dielectric breakdown of gate oxide film. Lifetime prediction for SiC devices is more complicated than for Si devices because of the significant AHI effect of gate voltage stress. In this study, the effects of electron injection and AHI on SiC-MOSFETs across a wide gate stress range were investigated. A method was developed to correct for AHI effects for improving accuracy in predicting device lifetime over a wide gate stress range.

ABSTRACT. MMC-VSC systems are currently implemented in silicon IGBT technology. Advocates of SiC as a high voltage technology have long suggested that SiC has the potential to enhance the performance of MMC-VSC systems by improving the energy conversion efficiency. The topology of choice for the latest HVDC-VSC systems is modular multilevel converters (MMC) comprised of cascaded half or full bridge voltage units with voltages ranging between 1.3 kV and 2.8 kV. However, the current state of the art SiC power devices are still off the ratings required for high voltage DC. Furthermore, the low switching frequencies used in MMC-VSC means that conduction losses dominate hence, the fast switching capability of SiC power devices is not necessarily an advantage. State of the art high voltage silicon IGBTs/PiN diodes exhibit comparable if not lower losses comparable with commercially available SiC power MOSFETs/Schottky diodes of similar ratings. This paper evaluates the potential performance of SiC power devices in MMC-VSC systems, compares them with IGBT and IGCT technologies and reviews the challenges ahead for high voltage SiC devices.

ABSTRACT. This work discusses a novel technique to estimate the distribution of interface trap density (Dit) at SiC/SiO2 interface closer to the conduction band edge of commercially available 1.2kV SiC Planar and Trench MOSFETs. This method utilizes the shift in threshold voltage with temperature using a constant current while varying the temperature in a wide range of 30K-450K.

ABSTRACT. Defect reduciton duing 4H-SiC growth is a major issue in SiC power device manufacturing. Among the dislocations existing in physical vapor transport (PVT)-grown SiC crystals, basal plane dislocation(BPD) is the most serious problem because BPD negatively affects the reliability of SiC devices such as SiC Mosfet and JFET [1-2]. When PVT growing, BPD is located perpendicular to the C-axis, making seed propagation difficult, but threading edge dislocations (TED), threading screw dislocations (TSD), micropipe (MP) is propagated along the seed. The temperature gradient inside the graphite crucible affects growth and polytype stability. However, thermoelastic stress inside the grown crystal generate dislocations during the cooling stage [3-4]. Therefore, BPD density control according to the cooling rate could be possible. Understanding the impact of the cooling stage on defect density can help grow high-quality SiC ingots [5]. In this study, a modified process condition has been proposed for the growth of high-quality 4H-SiC single crystal. Fig. 1 exhibited the schematic diagram of process condition and ingot image for SiC crystals grown with cooldown rate. The cooldown rate [℃/min] was controlled to investigate the effect on the SiC crystal quality. With different cooldown rate SiC ingot dramatically exhibited different surface. The crack was appeared after external grinding process in SiC ingot prepared with cooldown rate of 10~30 [℃/min] and a surface carbonization was observed on SiC ingot of < 1 [℃/min]. Fig. 2 exhibited optical microscope (OM) images and etch pit density of SiC etched wafer prepared with varying cooldown rate [℃/min] at the cooling stage of SiC crystal growth. When the cooldown rate was too high like Method A, BPD increases due to the effect of plastic deformation. Whereas in Method C, too slow cooldown rate becomes TED increases due to thermaloelastic stress. BPD and TED in SiC crystal grown with cooldown rate of 1~5 [℃/min] were definitely reduced (Method B). Various crystal properties of SiC crystals grown with differnt cooldown rate have been systematically investigated in this study.

ABSTRACT. As we see a strong growing demand for SiC material in automotive, high power energy storage, and all other high voltage applications, it is crucial to produce homogenous, defect free, high quality, epi-ready SiC wafers to build devices. Chemically inert and mechanically hard Silicon Carbide (SiC) material requires a long polishing time and aggressive chemical mechanical planarization (CMP) conditions. However, these aggressive polishing conditions can introduce surface defects, scratches, and subsurface damage that can render the wafers useless for device building and ultimately lower manufacturing throughput. To mitigate the challenges in SiC CMP, we have developed a high removal rate SiC slurry (Sabre Micropol CS G10) that gives 10-12 μm/hr removal rate, as well as lower wafer defectivity, higher process margins, and longer shelf life. The next-generation Sabre Micropol CS G10 slurry has been developed using a complex mixture of components, including oxidizers, co-oxidizers, rate boosters, and a complex blend of abrasive particles. These consist of differing chemical compositions, particle sizes, charges (zeta potential), and surface modifications. Surface modified particles with hard cores and softer outer coatings help to remove oxidized SiC surface layers during CMP, without damaging the subsurface. In fact, these modified abrasives also help to substantially reduce wafer and pad interfacial temperature, friction, and motor loads, allowing CMP process engineers to develop more aggressive process recipes that increase wafer throughput. The inclusion of inorganic catalysts has been shown to be an effective method for increasing material removal rates during SiC wafer polishing while keeping the abrasive and oxidizer unchanged. Comprehensive electrochemical studies have demonstrated the altered reaction pathways and reduction products of the oxidizer when these catalysts are introduced. In addition, spectroscopic analysis indicates that these catalysts may also facilitate a more efficient interaction with the oxidized SiC layer by coordinating with the bonds on the surface. This means they can accelerate material removal without compromising surface integrity. This approach significantly boosts the material removal rate, ensuring a more efficient and effective polishing process.

ABSTRACT. Wide-Bandgap semiconducting materials such as silicon carbide (SiC) are finding widespread applications for power electronics, and manufacturing of SiC is happening at full swing worldwide. Apart from its potential electronic properties, the material is also extremely hard which presents challenges when machining. In between the crystal growth and wafering processes, the SiC boule needs to be shaped into a cylindrical form factor suitable for wafering as shown in Fig. 1. This process typically consists of five steps. The top or “dome” and the bottom or “seed end” need to be removed. An outside diameter relative to the final wafer size (i.e., 150/200mm wafer) needs to be applied to the boule as well as a primary flat/notch so that specific orientation of the wafer during subsequent processes can be identified and controlled. During these manufacturing steps correct and precise crystal orientation needs to be achieved, so that the final wafer meets the SEMI or customer standards. To understand and appropriately compensate for crystal orientation, the boule must be exposed to an X-ray diffraction (XRD) [1] tool so that the crystal structure is known prior to and after the various processing steps. Lastly, the surface finish of the wafer-ready material (“puck”) needs to be suitable for whatever wafering process it will undergo such as fixed abrasive diamond wire slicing, diamond slurry wire slicing or laser ablation. All these processes, including bulk crystal grinding, orientation detection and correction, surface finish optimization, and material characterization need to be done in an optimal fashion to appropriately set up the downstream processes of wafering, polishing and epitaxial deposition. They also need to be performed in the most effective cycle time and at the lowest possible cost. Over the last year, USACH has optimized the boule to puck fabrication process through a fully automated machine tool shown in Fig. 2. that completes these process steps using an internal XRD to identify and automatically correct crystal orientation in the most accurate way possible in the final wafer-ready material. Compared to the standard approach where the boule is measured for crystal orientation with an XRD that is external to the machine and then subsequently glued to a spindle in order to facilitate the orientation correction grinding process, the BoulePro 200AX (BoulePro) produces results up to 500 times more accurate. This is due to how the boule is held during the grinding process within the machine. When the boule is measured for XRD it is held to a vacuum plate on the seed side as well as by gripping mechanisms on the OD of the part. Once the crystal orientation is known and ready to be corrected, the crystal never leaves the specialized workholding allowing its orientation in space to be controlled to an extremely high level during the grinding process. Sample results of actual boules corrected from various SiC producers are shown below (see Table I). Further data and a comparison of orientation correction via the conventional vs. BoulePro methods will be presented. In addition to establishing an optimized crystal orientation correction process through the BoulePro, USACH has also been working on implementation of several new technologies that would allow for the in situ analysis and identification of non-4H polytype. As foreign polytype is a regular occurring issue in SiC crystal growth, most producers have to remove it so that they are making only high yielding wafers. USACH’s solution utilizes a UV light source and a vision system that work together to identify, measure, and communicate back to the machine where and how much material needs to be removed from the boule prior to wafering. The resultant puck will consist of only 4H polytype as a result of this process. Use of this data to continually track the location of foreign polytype on the boule will aid in tuning the crystal growth process in order to increase yields. This capability will be discussed and data presented to show how this innovative technology further helps to automatically address issues experienced by SiC crystal growers during boule fabrication. In summary, this fully automated process that minimizes operator activity and intervention saves cost, reduces cycle time (see Table II), and eliminates operator induced yield losses due to the elimination of multiple manual handling steps. Advancements to this new methodology optimizes the boule to puck fabrication process and in doing so positively affects the tuning of the crystal growth process and also makes more accurately orientated wafers.

ABSTRACT. In the realm of semiconductor engineering, integrating P-type materials into N-type Silicon Carbide (SiC) to construct PiN structures is known to confer advantages in high current capacity and voltage endurance. Previous studies have indicated that forming these regions through P-material doping has been the standard; however, this method incurs substantial penalties in terms of cost, time, and complexity, along with concentration-related limitations of the P-region. Departing from traditional doping practices, our study explores alternative deposition techniques for device fabrication, employing two distinct methods and specifying different post-annealing conditions. Devices were fabricated as depicted in Fig. 1. The rationale for selecting RF Sputtering and Aerosol-Deposition (AD) in this study is to identify the most suitable deposition methods for fabricating PiN diodes. While RF Sputtering allows for the deposition of uniform thin films, AD is simpler and faster, and significantly enhances device performance following high-temperature post-annealing. According to prior research, Copper(I) Oxide (Cu2O) exhibits favorable mobility and resistivity characteristics when post-annealed in a nitrogen atmosphere. Yet, above 400 ℃, a phase transition from Cu2O to CuO has been observed, leading to a significant deterioration in mobility and resistivity of the device [1-3]. Our experiments, conducted under the conditions outlined in Table 1, and the XPS analysis presented in Fig. 2, confirm the absence of phase transitions at elevated temperatures. Furthermore, as shown in Fig. 2, The Satellite peaks for Cu 2p1/2, 2/3 have been removed by the post-annealing process, which has enhanced the mobility and ideal quality of the device [4]. The fundamental electrical properties of the fabricated devices were shown like this. Threshold voltage (Vth) of 2 V was identified, with a consistent saturation point at approximately 3 V. Moreover, a characteristic of lower reverse-bias current at increased temperatures was observed. To define the device’s quality, the ideality factor was calculated based on device’s current-voltage curve. As shown in Fig. 4, the ideality factor approaches 1 as the annealing temperature increases. Finally, leading to an examination of Hall mobility, as presented in Fig. 4. It was observed that the AD fabricated samples exhibited higher mobility than RF samples, especially demonstrating a significant increase from 500 ℃ to 700 ℃. And it shown similar tendency at the Fig. 3. The important observation is that, unlike previous works, decrease in mobility was not observed due to phase transition following high-temperature post-heat treatment. In addition, it was confirmed that the annealing process affects the crystallinity of the device, which has a positive effect on mobility in the AD manufacturing method [5].This research aims to optimize Hall Mobility by fabricating PiN diodes on 4H-SiC substrates with P-type materials under various methods and conditions. Our findings indicate that post-annealing removes satellite XPS peak values, which obstruct the operation of a device, including its mobility. The diversification of deposition methods and post-treatments presents a promising approach to analyzing and optimizing electrical and other characteristics, suggesting a more efficient and straightforward fabrication process for PiN structure devices.

ABSTRACT. Silicon carbide (SiC) for high-power MOSFET devices requires a drift layer of ~ 10µm in 4H-SiC epilayers with a doping concentration ~E16 cm-3. High mobility and uniform distribution of carrier density throughout the drift layer of 200 mm SiC wafers are critical factors for achieving high quality SiC epilayers for device fabrication. Conventional electrical characterization methods such as Hall-effect measurements, Raman and Fourier-transform infrared (FTIR) are commonly used to evaluate the quality of 4H-SiC epilayers by determining mobility and carrier density. However, these techniques are unsuitable for inline metrology tools used to inspect SiC epilayers especially in a drift layer. In this paper, we demonstrate a new methodology that comprises FTIR spectrometry and merged capacitance-voltage measurement (FTIR + Hg-CV) to obtain rapid and accurate characterization of mobility and carrier density wafer maps in SiC epilayers on 200 mm 4H-SiC wafers. This technique extends the capability of FTIR to obtain mobility at carrier density down to ~E15 cm-3 and could be adapted as an in-line methodology for measuring carrier mobility of the drift layer in the SiC MOSFET industry.

ABSTRACT. Wide band gap semiconductor material silicon carbide (SiC) plays an important role in the field of power applications because of its excellent material properties such as large band gap, high thermal conductivity, high critical breakdown electric field and high electron mobility. To enhance SiC-based device performance, research has explored the use of high-k oxide materials, like aluminum oxide (Al2O3) and hafnium oxide (HfO2), as silicon dioxide (SiO2) replacements for MOSFETs and MOS structures on SiC [1]. Barium Titanate (BaTiO3) is a ferroelectric material with exceptional dielectric properties and with numerous applications, including high-power electronics, actuators, sensors, and capacitive energy storage [2]. In this study, we analyzed the surface and electrical properties of BaTiO3/4H-SiC metal-ferroelectric-semiconductor structures. Fig. 1 showed metal-ferroelectric-semiconductor structures, ferroelectric properties and BaTiO3 phase transition dependent on curie temperature. Although previous studies on BaTiO3/4H-SiC MOS structures had been investigated, they encountered significant challenges such as leakage current and oxide defects, which resulted in a lower dielectric constant [3]. It was suggested that oxygen vacancies contribute to these film imperfections, which it could have been advantageous to anneal the films in an oxygen ambient [4]. Morphological and structural properties of BaTiO3 films on 4H-SiC were investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM) and atomic force microscopy (AFM), as shown in Fig. 2 and 3. We carried out CV measurements on the Ni/BaTiO3/4H-SiC MOS capacitors at 1 MHz, which enabled analysis of trapped oxide charge density (Ntrap), fixed oxide charge density (Qf) and the dielectric constant (k), as shown in Fig. 4 (a) and (b). In previous research, aerosol deposited BaTiO3 films on 4H-SiC, without PDA, were reported to exhibit Ntrap and Qf of 2.0 × 1012 cm-2 and 1.3 × 1012 cm-2 respectively [3]. The flat band voltage hysteresis decreased after annealing, leading to a reduction in the Ntrap from 9.1 × 1011 cm-2 to 5.5 × 1011 cm-2. Qf decreased from 4.0 × 1011 cm-2 to 3.6 × 1011 cm-2. However, the annealed sample exhibited a lower dielectric constant, which was attributed to the interdiffusion between the deposited film and the SiC substrate. The formation of pseudo-binary alloys such as BaTiO3+SiO2 was one reason for the decreased dielectric constant. Annealing in an oxygen ambient caused more silicon atoms in the film to oxidized to SiO2, which decreased the leakage current and refined the dielectric properties. We found that PDA led to a reduction in oxide defects attributable to oxygen vacancies, thus improving the quality of the BaTiO3 oxide films on 4H-SiC. According to the literature, it appears that oxygen vacancies were generated by distortions in the TiO6 octahedra of BaTiO¬3. Previous studies indicated that the distortion degree of the TiO6 octahedra decreased with increasing PDA temperature. At 500 ℃, the distortion degree of the TiO6 octahedra was reduced, and the number of oxygen vacancies from the TiO6 octahedron decreased dramatically [5]. Oxygen vacancies were compensated by oxygen atoms introduced from the O2 ambient during PDA. The PDA treatment of BaTiO3 led to a reduction in the gate leakage current and an enhancement in the rectification ratio from 9.1 × 108 to 1.6 × 109 for the w/o PDA and w/ PDA BaTiO3/4H-SiC, respectively, as shown in Fig. 4 (c). This study demonstrated the value of using the high-k ferroelectric material BaTiO3 as the oxide layer in 4H-SiC MOSCAPs, effectively addressing the challenges associated with oxygen vacancies through PDA.

ABSTRACT. Wide bandgap (WBG) semiconductor technology is the primary answer to the growing demands of high-power electronic devices. The continually advancing production of WBG epitaxial wafers and structures requires cost effective, fast feedback metrology, enabling precise wafer level monitoring of epitaxial properties, e.g., dopant concentration, dopant depth profile, uniformity and run to run reproducibility. Our development of such a noninvasive WBG metrology has been based on the adaptation of a Si IC production proven electrical characterization method, realized with corona charge biasing of the surface and measuring the surface voltage response with a vibrating Kelvin probe. The commercial tool, CnCV (Corona noncontact Capacitance Voltage), initially intended for SiC, was introduced by Semilab SDI in 2017 [1]. With a continuously refined performance improvement, the applicability of the CnCV tool expanded to other WBG semiconductors, including AlGaN/GaN HEMT structures and β-Ga2O3. New breakthrough improvements were initiated in 2023 with a discovery of the Kinetic CV technique [2]. It offers a new WBG doping characterization method with high wafer measurement throughput of 20 wafers per hour and a precision of 0.2%, satisfying the 4H-SiC epitaxial production requirement. Described in our already granted 2024 patent [2], Kinetic CV utilizes the photoneutralization of the corona-deposited surface charge measured as an illumination-induced surface voltage decay for surfaces charged to depletion. According to the invention, the photoneutralization time constant, ph, provides a measure of the dopant concentration. The ph values are adjusted by illumination intensity to a fraction of a second range, producing fast dopant measurement and corresponding high wafer monitoring throughput. The results shown in Fig. 1, 2, and 3 demonstrate the very first application of Kinetic CV method to epitaxial β-Ga2O3, which has an energy gap of about 4.8eV i.e., larger than the 3.26eV energy gap of 4H-SiC. The results in Fig. 3 confirm a fast 3min measurement time for 9 sites per wafer that would correspond to a throughput of about 20 wafers per hour. The Kinetic result shows excellent agreement with standard CnCV doping measured with the 1/C2 method. The repeatability in Fig. 2 demonstrates 0.1% precision of Kinetic CV for β-Ga2O3 i.e., better than the previous 0.2% observed for similar dopant concentration in 4H-SiC [3]. Kinetic mode characterization of AlGaN/GaN HEMT structures is especially beneficial. It provides a new, parameter-free determination of the pinch-off voltage (VP) that is about an order of magnitude faster than the conventional CnCV method. As illustrated in Fig. 4, the negative corona charge fully depletes the initially populated 2DEG. This is reversed in a fraction of a second by illumination causing charge photoneutralization. The resulting surface voltage decay in Fig. 5 gives the HEMT VP as the demarcation point defined by intercept of the two lines. The 49pt VP wafer map shown in Fig. 6, measured using the Kinetic CV mode, was obtained in 20 min compared to about 3.5 hours for the standard CnCV mode. A throughput of 18 wafers per hour is obtained with Kinetic CV for 9 site production HEMT monitoring of VP with a 0.15% precision. It may be of special interest that microscale Kinetic CV realized with Kelvin Force Microscopy (KFM) enables high resolution VP determination.

[1] M. Wilson, et al., ECS Journal of Solid State Science and Technology, 6(11) S3129 (2017). [2] M. Wilson, et al., U.S. Patent Application No.: 18/123,211 (U.S. Patent granted April 2024). [3] M. Wilson, et al., “Noncontact Measurement of Doping with Enhanced Throughput and High Precision for Wide Bandgap Wafer Manufacturing”, ICSCRM 2023 proceedings.

ABSTRACT. This paper sheds light on the nitrogen (N) incorporation kinetics determining the N doping uniformity during physical vapor transport growth (PVT) of 4H-SiC crystals through the investigation of the step-flow velocity dependence of N incorporation at the growth front of differently N-doped 4H-SiC crystals. We analyzed the obtained step-flow dependence using a two-site exchange model for impurity surface segregation and acquired two crucial physical parameters for N doping in 4H-SiC crystals: the kinetic barrier height and the Gibbs energy of N surface segregation. Based on the obtained kinematical parameters, we discuss the N incorporation kinetics during the PVT-growth of 4H-SiC crystals.

ABSTRACT. Silicon carbide (SiC) has garnered significant interest due to its superior properties over conventional silicon (Si) in emerging semiconductor technologies. With a bandgap of 3.2 eV, SiC excels under extreme high-temperature and high-power conditions, where Si typically underperforms [1]. However, SiC wafers are costly to produce, primarily because they are manufactured using the physical vapor transport (PVT) method, which has a slow growth rate of 0.1 to 0.5 mm per hour. While the standard SiC wafer size is 150 mm, sizes up to 200 mm have been commercialized. After growth of SiC, the wafers require chemical and mechanical polishing (CMP), which often leaves surface scratches. For SiC wafers to be effective in electronic devices, etching is necessary to ensure a smooth and flat surface, which is critical for high electrical properties [2-4]. Primary etching techniques include using hydrogen gas, which is highly effective but results in significant step bunching due to a precise terrace structure, and thermal decomposition, which, although less effective, can achieve lower surface roughness if the etching parameters, particularly the Si/C ratios in the chamber, are carefully managed [5, 6]. Therefore, alternative approaches like facing each of the two Si-cut SiC wafer or incorporating Ta foil have been suggested [7]. Here, we propose a new etching method that involves using SiC powder within a graphite crucible for thermal decomposition. Due to its greater surface area, SiC powder decompose more silicon than the SiC wafer, allowing for the production of highly ordered graphene and flat SiC surfaces. We have analyzed and compared the crystal structures and properties of the graphene layers developed through our process, using Raman spectroscopy, atomic force microscopy (AFM), and scanning electron microscopy (SEM).

[1] Neudeck, P.G., Progress in silicon carbide semiconductor electronics technology. Journal of Electronic Materials, 1995. 24: p. 283-288. [2] Yazdi, G.R., T. Iakimov, and R. Yakimova, Epitaxial graphene on SiC: a review of growth and characterization. Crystals, 2016. 6(5): p. 53. [3] Emtsev, K.V., et al., Towards wafer-size graphene layers by atmospheric pressure graphitization of silicon carbide. Nature materials, 2009. 8(3): p. 203-207. [4] Ramachandran, V., et al., Preparation of atomically flat surfaces on silicon carbide using hydrogen etching. Journal of Electronic Materials, 1998. 27(4): p. 308-312. [5] Van der Berg, N., et al., Thermal etching of SiC. Applied surface science, 2012. 258(15): p. 5561-5566. [6] Li, R., et al., Hydrogen etching of 4H–SiC (0001) facet and step formation. Materials Science in Semiconductor Processing, 2022. 149: p. 106896. [7] Jokubavicius, V., et al., Surface engineering of SiC via sublimation etching. Applied Surface Science, 2016. 390: p. 816-822.

ABSTRACT. The Laplace-transform photoinduced transient spectroscopy (LPITS) has been proved to be a unique technique allowing to resolve closely spaced energy levels in semi-insulating (SI) wide-bandgap materials [1, 2]. In this method the deep levels of point defects are filled with the excess charge carriers generated by the material illumination and the defects electronic properties are extracted from the photocurrent relaxation waveforms, recorded at a given temperature range [1]. The method is particularly useful for the electrical characterization of point defects in SI 4H-SiC, in which the impurities and native defects are located at the two, inequivalent lattice sites: hexagonal (h) and quasi-cubic (k) [2]. The slightly different energy levels positions in the bandgap for the same point defects occupying the h and k sites can be revealed only by a high-resolution experimental technique, such as LPITS. Therefore, this method can be of great importance for investigating the localized defect states in SI SiC in terms new applications of this material in quantum technology (QT). In this work we have used the LPITS technique to compare the properties and concentrations of midgap defect centers in two high-purity semi-insulating HPSI 4H-SiC wafers with different resistivities of ~1×107 and ~1×1011 Ωcm. The activation energies for the dark conductivity, corresponding to the Fermi positions extrapolated to the absolute zero, were 701 meV and 1530 meV, respectively. In the both materials six deep traps, labeled as T1, T2, T3, T4, T5, and T6, with the activation energies and pre-exponential factors in the Arrhenius equation (Ea, A) of (1375 meV, 2.4 ×108 K-2s-1), (1515 meV, 1.0 ×109 K-2s-1), (1425 meV, 8.5 ×107 K-2s-1), (1510 meV, 1.4 ×108 K-2s-1), (1350 meV, 3.3 ×106 K-2s-1), and (1490 meV, 1.5 ×107 K-2s-1), respectively. The one-dimensional Laplace spectrum, with the sharp peaks indicating the thermal hole emission rate values at 696.1 K for the resolved traps in the material with the resistivity of ~1×1011 Ωcm, is shown in Figure 1. For the material with the lower resistivity, the peaks positions in the Laplace spectra were the same, giving the evidence that the same defects in the both materials were observed. The Arrhenius plots from which the defects parameters were determined are shown in Figure 2. On the grounds of the current knowledge obtained both from the theoretical and experimental studies, the revealed traps are attributed to the charge states transitions (+/0) and (2+/+) of the carbon vacancies (VC) residing at h and k sites as well as to the transitions (0/-) of silicon vacancies (VSi) at the h sites and (2+/+) charge state changes of the CSi-VC complexes [3]. The VC concentrations [VC] in the both materials were found to be 7.0 ×1017 and 1.4 ×1017 cm-3, and those of [VSi] were 1.2 ×1018 and 1.2 ×1017 cm-3, respectively. [1] M. Zając, P. Kamiński, R. Kozłowski, E. Litwin-Staszewska, R. Piotrzkowski, K. Grabiańska, R. Kucharski, R. Jakieła Materials, 17, 1160 (2024). [2] P. Kamiński, R. Kozłowski, M. Miczuga, M. Pawłowski, M. Kozubal, M. Pawłowski, J. Mater. Sci. Mater Electron 19:S224-S228 (2008). [3] M.E. Bathen and L. Vines, Adv. Quantum Technol. 2021, 4, 2100003.

ABSTRACT. We have proposed the new screening method using UV irradiation to prevent bipolar degradation to occur, replacing the time-consuming burn-in process. This method is based on the knowledge that UV irradiation can reproduce the defect expansion phenomenon which is equivalent to bipolar degradation. In this paper, to further improve the effectiveness of this method, we report our attempt to accurately derive UV irradiation conditions that simulate current injection conditions, especially considering the carrier lifetime influence on the correlation of the current density and the UV irradiation intensity.

ABSTRACT. Silicon carbide (SiC) has attracted great attention due to its potentially superior properties to Si in terms of high-voltage and high-temperature power device applications [1]. However, the performance of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is hampered by low channel mobility and threshold voltage instability. These are mainly due to large amounts of interface traps (Dit) and/or near-interface traps [2]. It has been reported that a 4H-SiC/SiO2 interface with very low Dit and high channel mobility can be obtained by etching the SiC surface with H2 prior to SiO2 formation and subsequent interface nitridation [3]. In ref 3, the reason for the decrease in Dit is speculated to be that H2 decomposes C defects, i.e. carbon compounds remaining on the surface after thermal oxidation of SiC, since previous first-principles calculations have suggested that C defects are stable and form defect levels near the conduction band [4]. However, the microscopic mechanism of H2 etching has not been elucidated. Recently, the thermal oxidation process at the SiC/SiO2 interface has been demonstrated in classical molecular dynamics simulations [5]. The precisely fitted interatomic potentials reproduced the formation of C defects by oxidation, and are expected to be a powerful tool for elucidating the H2 etching process. In this report, we present the results of H2 etching simulations by using a charge-transfer type interatomic potential consisting of Si-C-H. The parameters of the potential were adjusted to reproduce the cohesive energies and atomic forces calculated from first-principles calculations for structures that emerged during molecular dynamics simulations: typical structures are shown in Figure 1. In the H2 etching simulations, we repeatedly added H2 molecules over the SiC surface after C defects were introduced. The first-principles calculations were carried out with the plane-wave code Quantum ESPRESSO [6], using ultra-soft pseudopotentials and generalized gradient approximation for electron exchange and correlation. The classical molecular dynamics simulations were performed with the LAMMPS package [7]. Figures 2(a) and 2(b) show the comparisons of cohesive energies and atomic forces respectively between first-principles calculations and the developed interatomic potential of Si-C-H. Our interatomic potential reproduced well the cohesive energies in the range of 0.5 eV for most of the structures. The correlation coefficient in atomic force is 0.86, which is comparable to the previous study [5]. Figures 3(a) shows cross sections of the 4H-SiC(0001) Si surface during the simulation with H2 at 1600 K for 2 ns. As the simulation proceeded, the C defects on the surface were decomposed by H2 molecules. This result supports the speculation in ref 3 that the decrease in Dit is due to the decomposition of C defects by H2 etching. After the decomposition of C defects, H atoms bound to the SiC surface and dissociated the Si-C bonds [Figure3 (b)]. These reactions caused desorption of SixCyHz molecules from SiC surface and after 2 ns, two layers of SiC were etched. Since it has been experimentally confirmed that SiC can be etched by H2 [3], it is assumed that a qualitatively effective force field has been established. Analysis of the reaction processes occuring in molecular dynamics simulations would lead a better understanding of the H2 etching process in 4H-SiC MOSFETs.

[1] T. Kimoto, Jpn, J. Appl. Phys. 54, 040103 (2015). [2] T. Kimoto, and H. Watanabe, Appl. Phys. Express 13, 1220101 (2020). [3] K. Tachiki et al., Appl. Phys. Express 13, 121002 (2020). [4] T. Kobayashi et al., J. Appl. Phys. 126, 145302 (2019). [5] S. Takamoto et al., J. Appl. Phys. 123, 185303 (2018). [6] P. Giannozzi et al., J. Phys. Condens. Matter 21, 395502 (2009). [7] A. P. Thompson et al., Comput. Phys. 271, 10817 (2022).

ABSTRACT. Silicon carbide (SiC) is a wide band-gap semiconductor that has gained popularity in various industries due to its unique properties, including higher voltage handling capacity and lower switching losses. This makes SiC an ideal candidate for use in high-performance power devices, which could play a significant role in energy efficiency, reduced power consumption, and lower carbon emissions. A key to utilize this high performance in power electronics is a low density of defects such as micropipes (MP), basal plane dislocations (BPD), threaded edge dislocations (TED), and threaded screw dislocations (TSD) in manufactured single crystals. One of the most common ways to reveal these defects is molten KOH etching. Counting and characterization of these defects, however, still poses a challenge, as size and shape of the corresponding etch pits vary depending on etching duration, etching temperature, and doping level of the crystal. Both MPs and TSDs are screw dislocations. MPs have a relatively large burgers vector. Since the energy of a dislocation is proportional to the square of its burgers vector, the MP reduces its energy by removing the dislocation core resulting in the creation of a hollow tube. Both MPs and TSDs develop larger hexagonally shaped etch pits, making them challenging to distinguish. TEDs manifest in, depending on the etching conditions, smaller round etch pits, and BPDs as elliptically shaped “comet” like etch pits. In some cases, dislocations can exhibit a mixed edge and screw character, making their characterization more complex. As part of machine learning, deep learning has already been successfully utilized in material science to detect features of interest in microscopic images. Deep convolutional neural networks (DCNN) have been proven to be very capable in computer vision tasks such as image classification, object detection, and instance segmentation. This often even superhuman- like performance can be achieved due to the DCNN mimicking to some degree the function of the human visual cortex. By subsequent application of filters and shrinking of the image (“pooling”), it is possible to detect features of different complexity. In this work, we demonstrate the application of Mask R-CNN, a region-based CNN, for the automatic detection and characterization of etch pits in images of SiC single crystals etched by molten KOH. Mask R-CNN is implemented trough transfer learning using the open-source deep learning libraries PyTorch and TorchVision. The main challenge for the network is posed by the correct distinction between overlapping etch pits, especially in Regions with high defect densities. The focus lies on achieving a high confidence score for detected pits, to minimize reliance on manual inspection. Figure 1 (a) shows an example for the detection of etch pits with displayed labels, masks and confidence scores. The trained network was able to achieve a mean average precision (mAP50) score of 96.9% on the validation set with the majority of relevant detections associated with a confidence score above 95%. Even overlapping etch pits can mostly be identified reliably, representing an advantage over the commonly used threshold-based methods that use approximations in such scenarios. The primary application lies in the automated mapping of entire wafers and the subsequent generation of dislocation density maps. An illustration of such a density map for BPD type etch pits is presented in Figure 1 (b).

ABSTRACT. The recent growth of silicon carbide (SiC) for high voltage and high-power applications, including electric vehicles, has propelled research into “killer” defects that detrimentally affect device performance. X-Ray Topography (XRT) is commonly employed to detect basal plane dislocations (BPDs), threading screw dislocations, and threading edge dislocations [1], while photoluminescence (PL) has proven less useful for these dislocations [2]. PL detection is commonly used for detecting many epi-layer bound defects [3], including stacking faults and surface triangles/polytype inclusions. Understanding the detailed morphology of defects has often been left to electron microscopy [4]. In this work, we present a new approach to defect detection using ultrafast nonlinear (NL) optical imaging. An ultrafast laser tuned to 392 nm, near the bandgap of SiC, serves as the input to the ultrafast microscope. The laser pulse is split into two replicas called a pump and a probe pulse, which impinge on the wafer separated by a delay T. The pump pulse excites carriers in the conduction band of the material, which alters the reflectivity of the probe. Small changes in the band structure caused by defects affect the reflectivity change of the probe near the band edge. Since defect states are often long-lived, while the bulk signal from SiC decays instantaneously, the temporal delay between the pump and probe pulse can be set to finite values to obtain a background-free defect image. The pump-probe pulse combination is scanned across the wafer with a Galvo-scanner/stage scan combination. We measure resonant linear reflectance (RLR) and NL images simultaneously. The information from the RLR image is helpful to distinguish between surface contamination and crystallographic defects. Fig. 1(a,b) shows RLR and NL images acquired for a 6” SiC wafer with this technique. We use a combination of analytical methods and machine learning to detect and classify defects from a combination of the RLR and NL images. The resulting defect map is plotted in Fig. 1(c). Surface triangle defects are one of several killer defects to which nonlinear imaging is sensitive. Surface triangle defect formation and morphology have been a topic of recent discussion [4-5]. In this work, we establish that the three-dimensional morphology of triangle defects can be obtained by our non-destructive, all-optical technique. Fig. 2(a) shows a top-view slice of a surface triangle with a large particle at its apex. This triangle defect consists of three triangles on top of each other, similar to the defects discussed in Ref. 4. The image in Fig. 2(a), taken at T = 0 ps, suffers from a large background caused by the bulk NL signal generated in the SiC wafer. Using a finite temporal delay of T = 2 ps, shown in Fig. 2(b), the background is nearly eliminated as the bulk signal decays while the defect state has a nanosecond lifetime. The triangle in Fig. 2 (a) and the triangle in Fig. 2(c), measured on the same wafer, both display ridges across a majority of the defect. The ridges follow a periodic pattern with a periodicity of 1.05 um. Fig. 2(b) displays curved ridges, especially towards the center, while Fig. 2(c) displays curving of the ridges mostly towards the edges of the triangle. The varying thickness of the 3C layers across the triangular defect is measured by performing volumetric NL imaging of the defect. The volumetric image of the surface triangle in the x-z plane is plotted in Fig. 2 (d). Based on the volumetric image, the triangle is shallower in the non-ridged area near the apex, and the bottom is tilted at an angle of 4°, consistent with the growth angle of the bottom of the triangle along the basal plane [5]. The ridges themselves do not display any measurable tilt. Volumetric imaging can help recipe developers better understand the nature and cause of defects, aiding in recipe improvement and defect reduction in SiC wafers. Non-volumetric NL imaging detects many killer defects at speeds comparable to photoluminescence and can be used as an in-line inspection technique.

[1] G. Chung, C. Lee, A. Soukhojak, T. Rana, Materials Science Forum 1089, 31-35 (2023) [2] A. Soukhojak, T. Stannard, I. Manning, C. Lee, G. Chung, M. Gave, E. Sanchez, Materials Science Forum 1062, 304-308 (2022) [3] PC Chen, WC Miao, T. Ahmed, YY Pan, CL Lin, SC Chen, HX Kuo, CY Tsui, DH Lien, Nanoscale Res. Lett. 17, 30 (2022) [4] Y. Pei, W. Yuan, N. Guo, Y. Li, X. Zhang, X. Liu, Crystals, 13(7), 1056 (2023) [5] J. Guo, Y. Yang, B. Raghothamachar, T. Kin, M. Dudley, J. Kim, Journal of Crystal Growth 480, 119-125 (2017)

ABSTRACT. Oxide defects have a detrimental effect on the flat-band voltage (VFB) of SiC MOS structures [1], but the nature of these defects is still controversial, e.g. carbon dimers ((CO)2) [1] or oxygen vacancies (VO) [2]. In order to shed light on this topic, we performed ion implantation on the thermal oxide of SiO2/4H-SiC structures, so to understand whether it is the presence of impurities or that of intrinsic defects affecting VFB. Ion implantation of C or N (5 keV, 1012 or 1014 cm-2) was carried out in a 50 nm thick thermal oxide grown on n-type 4H-SiC epilayer samples (~1016 cm-3). After implantation, the samples were annealed in vacuum in the 100-1000°C temperature range, for 15 min. After heat treatments, Ni was deposited on the oxide and Ag paste was employed as ohmic contact on the backside of the samples. CV (at room temperature, RT) and constant capacitance deep level transient spectroscopy (CC-DLTS) measurements were then carried out. CC-DLTS was performed in the 77-650 K temperature range, at 1 MHz, with a reverse voltage of -10V and a constant pulse voltage height of 30 V. In fig.1, we show the capacitance-voltage (CV) measurements of the as-grown and implanted (1012 cm-2) thermal oxide MOS samples. The CV measurements reveal similar values of around VFB of ~10.3 V for the as-grown and implanted samples. However, annealing at 400 °C shifts the VFB of the C implanted MOS to a lower value that is later recovered to the as-implanted value after higher temperature heat treatments. No significant changes were observed for the N implanted MOS. After implantation of C or N, with a dose of 1014 cm-2, the lowest VFB values are found after C implantation (fig.2). The VFB of C implanted MOS increases when annealing above 700 °C, up to 8V. In the case of N implantation, VFB is 2 V higher than C, but this drops after heat treatment at 400 °C. Subsequent annealing steps reveal similar VFB values in both N or C implanted MOS, after the same annealing temperature. The VFB values are reported in Tab.I. In fig.3, the CC-DLTS of the as-grown MOS shows a broad signal indicating the presence of high density of states and a high concentration of oxide defects. After C implantation (1012 cm-2), no much difference is seen except for a negative signal after annealing at 400 °C. This annealing temperature coincides with the lowest VFB value. No significant changes in the CC-DLTS signal are reported for N implantation. Fig.4 shows the CC-DLTS results implantation with a dose of 1014 cm-2. The C as implanted and 400 °C annealed MOS, show a negative peak which is not found for annealing above 700 °C. Again, we note that the lowest VFB values occur when the negative peak is present. Unlike C, after N implantation, the CC-DLTS measurement does not show any negative signal, except for the MOS annealed at 400 °C and this also coincides with a low VFB value. To conclude, the presence of a negative CC-DLTS signal can be associated to smaller VFB values. Negative DLTS signals in MOS structures have been linked to the presence of charged traps in the oxide [3]. In the present case, we can assume that C implantation leads to the formation of electrical states in the oxide. Such traps are filled during depletion (via tunnelling of holes through SiO2) and emit during accumulation. The presence of positive charges in the oxide leads to a shift of VFB to the negative direction [4].

[1]P.M. Mooney et al., J. Appl. Phys. 120, 034503 (2016). [2]R.H. Kikuchi et al., Appl. Phys. Lett. 105, 032106 (2014). [3]M. Aouassa et al., ECS J. Solid State Sci. Technol., 7, P24 ( 2018). [4]P.T. Lai et al., APL 76, 3744 (2000).

ABSTRACT. Silicon Carbide (SiC) has emerged as an important wide band gap semiconductor, particularly as an enabler for electric vehicles. As the automotive industry has stringent quality standards it is important that all stages of device manufacture are controlled and defect free. One of the key steps is the preparation of the SiC surface prior to the epilayer deposition. Plasma polishing as an alternative to CMP has been demonstrated in recent years [1], but requires more in-depth analysis to determine its effects on the underlying materials system. However, post-CMP treatments designed to remove the remaining subsurface damage have been reported recently [2]. Here, we present examination of subsurface damage modification by plasma preparation of 4H SiC surfaces for both wafers which have been processed via the plasma polish dry etch process and those processed with CMP. Production grade 150mm 4H SiC wafers have been obtained from major commercial manufacturers, in two grades, epi-ready CMP wafers, but also without the final CMP step. A matrix of process runs based on the OIPT Plasma Polish Dry Etch (PPDE) process has been carried out on both types of wafers, with variations of reactive gas composition, power and pressure. The wafers were etched in an Oxford Instruments Plasma Pro ICP tool. This yielded roughness reduction between about 3% and about 50% for non-CMP wafers (Ra values of 0.88-0.96nm) and zero roughness change, but an Ra of 0.05nm for CMP wafers, see figure 1. Etch rates were between 30 and 200 nm/minute. To analyze the subsurface damage, Raman Microscopy (RM) and Contact Resonance Atomic Force Microscopy (CR-AFM) are used to detect differences in the Silicon Carbide near surface environment after these different treatments and this will be reported in the final submission. CR-AFM gives both a measure of crystal stiffness and homogeneity of stiffness, so that a hard single crystal has a high frequency and small frequency distribution. Our measurement shows significant differences between untreated and etched surfaces for both CMP and non-CMP wafers. In all cases the frequency distribution decreased implying removal of inhomogeneous material, whilst a change in mean resonance frequency was found to depend on the process conditions. See figure 2. Raman gives information on local stress and ratio of polytypes, whilst the CR-AFM gives data around the surface stiffness. Remaining work will compare these results against defectivity level found after epitaxy, using a room temperature etching process to decorate the defects.

[1]A. Newton, S. Mazzamuto, L. Spasevski, D. Haspel, P. Trimby, C. Mulcahy, J. Moffat, J. Lea, T. Dieing, Proceedings of International Conference on Silicon Carbide and Related Materials, Sorrento, (2023). [2]Toda, Kohei, et al. Solid State Phenomena. Trans Tech Publications, Ltd., June 6, 2023.

ABSTRACT. We have successfully demonstrated the comprehensive trench etching of 4H-SiC for various crystal orientations. The results indicate that the trench profile and etching depth remain unaffected by the variation in crystal plane orientation. Our targeted trench etching depth of 1.9 µm was achieved, along with a vertical sidewall profile angle ranging from 87-90º for various crystal planes. Additionally, we conducted a qualitative analysis of the sidewall roughness for various crystal plane using a 3DAFM scan. It was observed that crystal angles of -60o to -90o with respect to (112 ̅0) plane exhibited a lower surface roughness.

ABSTRACT. The operation of the 4H-SiC MOSFETs with the gate oxide thickness of 20 nm and 30 nm are investigated when the ambient temperature increases up to 500℃. The field effect carrier mobility increases with the measurement temperature for both the MOSFETs. A higher carrier mobility is achieved with the MOSFET employing a thinner gate oxide layer. However, for the MOSFET with a thicker SiO2 gate, a lower gate leakage current is observed when the MOSFET operates in high-temperature ambient. The results obtained from this study indicate that optimizing the thickness of the SiO2 layer plays an important role in improving the performance and thermal stability of the integrated circuits based on 4H-SiC MOSFETs.

ABSTRACT. High-κ dielectrics have shown substantial benefits for SiC power MOSFETs for voltage classes less than 3.3 kV due to reduced ON resistance (RON,SP ), minimal hysteresis during switching, and improved ruggedness when compared to their SiOx counterparts [1,2]. However, there are still several challenges in the implementation of various dielectric materials in commercial SiC MOSFETs. The majority of high-κ insulators used in SiC power MOSFET technology suffer from undesirable polycrystalline phase formation due to the high temperature budget needed for annealing processes (Tprocess > 1000°C) [3,4]. In addition, such materials often come with undesirable flat band voltage (VFB) shifts when implemented in MOS gate stacks for SiC channels, hindering their true potential as next generation gate dielectrics [3,4]. Here, we show how to overcome both challenges via the implementation of a novel bilayer high-κ stack. The proposed stack provides a near ideal (-0.5 V) VFB with negligible hysteresis (< 30 mV) in a +/- 15 V gate voltage range in as implemented in metal oxide semiconductor capacitors (MOSCAPs). By preserving their overall amorphous nature, gate dielectric breakdown fields (EBR) of 10 MV/cm can be achieved. A comprehensive study of their behavior is here shown via the electrical characterization of the MOSCAPs employing single gate dielectric layers as well as the proposed bilayer stack.

Three different gate dielectric materials, namely, amorphous high-κ (high-κ1), a polycrystalline insulator (high-κ2) and a bilayer stack of high-κ1and high-κ2 (high-κ3), are compared in MOSCAPs fabricated on 1.2 kV rated n-epi wafers to gain detailed insight into their leakage current, oxide capacitance, and interface trap density (Dit) characteristics. Important device metrics such as VFB, hysteresis, as well as EBR have also been investigated.

Figure 1-4, show capacitance voltage (C-V) and current voltage (I-V) characteristics of the studied MOSCAPs as well as grazing incidence X-ray diffraction (GIXRD) spectra of high-κ2 samples. High- κ1 provides a negative VFB representative of the positive charge trapping nature of the interface and/or of the dielectric bulk in the SiC MOSCAPs. Due to a sufficient conduction band offset (ΔEC >1.5 eV) and amorphous nature, gate leakage current is suppressed at the operational voltage regime (VG < 20 V) and gate breakdown is observed only at 9 MV/cm. High-κ2 instead, has a positive VFB. Even though the as deposited layer is of amorphous nature and has high enough ΔEC (ΔEC >1.5 eV), consecutive processing steps result in polycrystalline phase formation in this dielectric, elevating the low field gate leakage and reducing the breakdown fields to as low as 6 MV/cm. In the bilayer dielectric stack (high-κ1/high-κ2/SiC), the thickness of the high-κ2 is reduced and it is capped with high-κ1 prior to consecutive processing steps. This allows us to successfully suppress the undesired VFB shifts as well as keep the structure amorphous. As a result, proposed stack provides a near ideal VFB of -0.5 V and a breakdown field (EBR) of 10 MV/cm. High-κ3also possesses a minimum interface state density Dit on the SiC MOS structures. In conclusion, we have shown that it is possible to implement high-κ dielectrics in a bilayer stack to offer ideal operation for the SiC MOSCAPs and for MOSFETs, providing desired VFB values, ideal interfaces to SiC epi layers as well as minimized leakage current values and exceptionally high EBR values. Detailed electrical characteristics of 1.2 kV as well as 3.3 kV rated planar SiC power MOSFETs employing the proposed high-κ stack will be included in the later stage to the study to be shared in the conference. Constant capacitance deep level transient spectroscopy (CC-DLTS) based Dit measurements will be shown as well.

ABSTRACT. With Silicon Carbide (SiC) power devices becoming more and more relevant in the electrification of the automotive sector as well as for renewable energies, a demand for more cost-efficient ways to manufacture these devices, in addition to a fabrication yield increase will be necessary. For this purpose, Soitec introduced its SmartSiCTM technology, which combines low resistivity polycrystalline SiC substrates with high-quality 4H-SiC top-layers, to minimize devices on-resistance and cost of ownership [1]. In this work, metal-oxide-semiconductor (MOS) capacitors were processed on both commercially available 4H-SiC reference (Bulk SiC), as well as Soitec SmartSiCTM 150 mm wafers, on which a similar epitaxial drift region was grown (1.0 µm, 1018 cm-3 buffer layer and 10.5 µm, 9.5∙1015 cm-3 drift layer). These wafers were used to evaluate the gate oxide quality (in terms of breakdown, interface traps, yield) and also investigated the influence of high temperature process steps on the intrinsic lifetime of MOS capacitors. The 55 nm oxide was thermally grown, and a highly phosphorus-doped 500 nm polycrystalline silicon layer was used as top side electrode. To investigate the influence of high temperature steps, which are usually not necessary for test devices such as MOS capacitors, but are necessary for transistor fabrication (i.e., field oxide or front side ohmic contact annealing), we subjected some wafers to a rapid thermal annealing (RTA) process for 2 min at 980 °C in Argon atmosphere. After manufacturing, capacitance-voltage (CV), current-voltage (IV) and constant-current stress time-dependent dielectric breakdown (TDDB) measurements were conducted on all wafers. Fig. 1 shows the capacitance measured at different frequencies and for different electrode sizes, displaying a clear shift of their flat band voltage (VFB) of about 0.89 V for wafers without RTA treatment. After conducting TDDB measurements on these wafers, a 27 % shift of the QBD intrinsic population (Fig. 2 & 3) can be observed, leading to the conclusion, that the lack of RTA reduces the dielectric lifetime. We suspect this to be caused by a difference in activated phosphorus ions in the polycrystalline silicon electrode [2], which affects the stress on the oxide layer, and will be further investigated. In parallel, a comparison of reference 4H-SiC and Soitec SmartSiCTM wafers was performed. To investigate the dielectric strength and capacitor yield, an IV measurement was carried out on a population of 224 devices for each size. The typical results are plotted as current density vs electric field in the oxide in Fig. 4. Even the 1 mm² devices demonstrated yield rates of 97.8 % and 97.2 % on reference and SmartSiCTM wafers respectively (criteria = breakdown above 9 MV/cm and zero excursions in leakage current). From quasi-static and high-frequency (100 kHz & 1 MHz) CV measurements we analyzed the interface trap density (Dit) with both the Terman [3] and high-low frequency [4] method for both wafer types. Fig.5 shows said densities from the conduction band (EC) to about 3.0 eV deep in the 4H-SiC band gap, whereby it should be noted, that these methods do not yield reliable results for the whole band depth displayed. Table I presents densities at certain energy levels with no significant difference in trap densities between the reference and SmartSiCTM wafer. More comprehensive results will be given in the full paper and presentation.

ABSTRACT. The ohmic contact between the metal contact layer and the semiconductor is of utmost importance for low RDS,on power electronic devices [1]. Therefore, the fabrication of low ohmic contacts is one of the essential aspects in the manufacturing and development of highly energy efficient SiC power semiconductor devices, especially for vertical devices. For low p-type ohmic contacts on the frontside usually titanium-aluminum compounds for p-type contacts [1]. A following temperature treatment of the metal layer is necessary to silicide the metallization and produce the low-ohmic contacts. This temperature step is generally performed by RTA (rapid thermal annealing) [1], although laser processing of backside contacts is now established [2]. However, laser annealing for alloying structured frontside contacts is difficult. Either only the ohmic contact areas are annealed, which requires good alignment of metallized areas and laser processing, or the entire surface is annealed, which can lead to damage or degradation of the layers outside the contact area. Another challenge is the laser processing of the titanium-aluminum layer itself. According to literature, a commonly used metal stack for the fabrication of p-type contacts is 300 nm Al / 80 nm Ti / SiC substrate, resulting in a TixSiCy layer after an annealing step [1]. However, aluminum has a reflectivity of over 90 % at a wavelength of 355 nm [3], which is the wavelength of the used short-pulse laser. As a result, only a small part of the laser radiation is absorbed and the metal layer hardly heats up. Therefore, a different layer composition or layer sequence must be used to produce p-type contacts using laser processing. In this work, a solution was developed to produce structured p-ohmic contacts using laser annealing. For this purpose, Ti / Al / Ti and Ni / Al / Ti metal stacks were investigated for p-type formation by laser annealing. To characterize resulting contacts, TLM structures were prepared, electrically characterized and analyzed using optical microscopy, FIB-SEM and XRD. Experiments were performed on commercial 150 mm 4H-SiC wafers with a n-type epitaxial layer of 10 µm thickness and 8·1015 cm-3 doping concentration. Al was implanted in the channel area of the TLM structures, between the ohmic contact area, and in the ohmic contact area for the p-type ohmic contact. The wafers were subsequently annealed at high temperature to activate the dopants. Afterwards the metallization layer was deposited. Therefore, a stack of Titanium and Aluminum was evaporated and a photoresist was spin coated and structured, before the uppermost Ti or Ni layer was deposited (see fig. 1a). Then the uppermost Ti or Ni layer was structured by lift-off and the whole wafer was laser annealed with different energy densities (see fig. 1b). Since the used Ti (5 nm) / Al (75 nm) / Ti (15 nm) metal stack has a reflectivity of 66 % and the Ni (20 nm) / Al (75 nm) / Ti (20 nm) stack one of 43 % at 355 nm for [4], significantly more radiation is absorbed in the ohmic contact areas with Ti or Ni layer on top, causing a reaction of the metal layers with the SiC substrate and diffusion between the metal layers (see fig. 2a). In the area between the contacts, however, where aluminum is the top layer, most of the radiation is reflected and no reaction takes place until very high energy densities (see fig. 2b). After irradiation the non-reacted Al-Ti-layer between the ohmic contact areas were removed wet-chemically (see fig. 2c). Finally, an Al layer is deposited and structured as contact metal. Fig. 3 shows FIB cross-sections of samples with deposited Ti / Al / Ti and Ni / Al / Ti metal stacks after laser processing. There are no longer three separate metallization layers and the thickness of the metal stack increased. This indicates a chemical reaction between the metal stack and the SiC substrate has taken place, which has to be confirmed by XRD analyses. Sheet resistance measurement of the investigated layers provide an indication that an ohmic contact is produced. Additional electrical results of linear TLM and circular TLM and a more detailed and critical discussion of the FIB cross sections with additional XRD analyses will be presented.

ABSTRACT. Understanding how 4H-SiC wafers deform and fracture under an applied load is fundamentally important for the semiconductor industry. Cracks inevitably generate during wafer thinning and die sawing, which can significantly impact device reliability. Nanoindentation is a versatile methodology that does not involve microfabrication, allowing for the study of hardness or Young’s modulus at different scales. It also enables the determination of fracture toughness and the identification of consequent plastic defects or crystallographic transitions. In this study, a series of indentation tests were conducted to determine the Young's modulus (E), hardness (H), and fracture toughness (K_IC) of 6-inch and 8-inch 4H-SiC wafers. The characterizations were performed at both room temperature and high temperature using the Anton Paar NHT3 and UNHT³ HTV indentation apparatus. A diamond Berkovich tip with a radius of about 10 nm was used as the indenter, applying loads ranging from fractions of a millinewton up to several hundred newtons to verify plastic deformation and monitor pop-in and pop-out events in the indentation curves. The indented regions produced at different loads were analyzed by SEM, and the crack length "c," crucial for determining the fracture toughness, was measured in the different regions under investigation. Calculated mean EIT, HIT and KIC are reported on Table I and Figure I shows the results of the indentation curves (a) and the corresponding SEM image (b). For load lower than 200 mN crack starts appearing (not shown) and the propagation is minimal. At a load of 200 mN, exclusively radial cracking have been observed with a maximum extension of about 7 um. The mean fracture toughness calculated is of about 3.84E7 N/m3/2 and is in line with the other reference values found in literature.

ABSTRACT. Unlike ordinary Si materials, SiC wafer thinning process is difficult because it’s a very high hardness. So, specialized grinding wheel is required also needed low grinding feed speed for SiC grinding. The SiC substrate is grinded by abrading the diamonds on the wheel. However, high diamond consumption results in high processing costs in the SiC manufacturing process. Research is continuously being conducted to reduce SiC grinding costs by applying optimized wheels and process recipes. The task is to maintain quality and secure capacity after SiC grinding and reduce process costs. In this paper, SiC grinding is We described experimental results on how to minimize process costs through grind wheel and recipe optimization.

Introduction SiC grinding is an essential process to create slim packages and low electrical resistance. To grind, first, thinning is carried out by directly contacting the grind wheel that will be grinded on the SiC Substrate. The grind wheel consists of diamond, a bond material for holds diamond grits, pores for dust discharge. It comes into physical contact with the SiC Substrate, the diamond is worn out due to direct contact, and at the same time, the SiC Substrate, which is the work material, is also grinded too.

Grind wheel configuration for optimized polishing There is a direct relationship between the diamond grit size and SiC grinding. Generally, the larger the diamond grit has better grinding capability. However, if the diamond grit size is too large, the physical damage is increased during grinding, so it is important to have an appropriate level of diamond grit size for SiC. In addition, the bond material that holds the diamond grit induces the diamond to fall off appropriately. In some cases, if the diamond grits fall off quickly, the wheel wear level goes high, which means increases process cost. If the diamond does not fall off properly, the wheel pressure load applied to the SiC Substrate becomes stronger, which can cause physical damage such as SiC burning or wafer broken issue. Also, the pores are important components for SiC grinding. Pores help to discharge SiC powder during grinding. if the discharge of SiC powder is not smooth, the diamond removal phenomenon may not occur properly, which may place a load on the wafer during grinding. Therefore, for SiC grinding, appropriate diamond particle size, bond material, and pore composition ratio for dust discharge are very important.

Consideration on SiC grinding conditions For SiC grinding, it is necessary to find the optimal conditions for the wheel and optimize the grinding conditions such as Wheel RPM / Feed Speed / Chuck RPM / Coolant Level at the same time. One of the major factors is grinding speed. It was discovered that grinding with a high speed increases the load rate to the SiC Substrate, also causes diamonds to fall off faster due to excessive forces lead to increasing Wheel consumption. while grinding with a slow speed has low throughput problem. This experiment was conducted from the perspective of minimizing the impact of SiC Sub and lowering process costs, and it is necessary to find optimum points through continued experiments and become competitive through continuous process improvement.

ABSTRACT. Silicon Carbide (SiC) is one of the promising wide band gap semiconductors for application in power electronics due to its high breakdown voltage, high sublimation temperature, and high thermal conductivity [1]. Formation of the gate region is a crucial technological step in SiC-MOSFETs fabrication, which requires development of reactive ion etching (RIE) technique for implementation of anisotropic SiC etching with smooth vertical side walls and corners rounding. Inductively coupled plasma reactive ion etching (ICP-RIE) system with biased pedestal is the most suitable technique. Its key advantage is almost independent control of ions and reactive species flux from plasma to SiC substrate and ion bombardment energy via the bias voltage control [2-4]. Etching profile of the trench is sensitive to reactive neutrals flux, ions flux, and ion energy-angular distribution functions within the trench. As the major reactive neutral in the mixture of SF6/O2, fluorine atoms are responsible for isotropic etching. Even small inclination of ions trajectories from a normal to the trench entrance can result in the deformation of the trench shape, for example, bowing, tapering, undercutting and micro-trenching effects [5-9]. As the SiO2 mask shape is changed during the SiC etching process, behavior of ions may be a complex function of time. Therefore, a development of SiC etching technique requires a parametric study of the sensitivity of the trench shape to process conditions in ICP-RIE chamber with time resolved dynamic change of the mask shape. Nowadays, a remarkable level of computational methods and performance allows a numerical modeling of industrial ICP-RIE processes to be frequently used together with experimental study and optimization. This eventually leads to a significantly reduced R&D time and costs for new device concepts. Here, we present results of numerical analysis of SiC etching with SiO2 mask in conventional ICP-RIE system with SF6/O2 mixture. Integrated modeling approach includes both chamber-scale and sub-μm gate trench-scale simulations. We performed numerical simulation of ICP-RIE chamber with biased pedestal to calibrate numerical model with available experimental data for blanket wafers. Particle-In-Cell Monte Carlo Collisions (PIC-MCC) simulations of the space charge sheath and ion trajectories near the biased SiC substrate at 13.56 MHz were performed to calculate ion energy-angular distribution functions (IEADFs) and determine effect of ion bombardment on etch rate. Monte-Carlo method was used for tracing ions and reactive neutrals within the sub-μm trench. The dynamic profile of the side walls and bottom of the trench was calculated with respect of the information about IEADFs. Integrated modeling of SiC gate trench ICP-RIE process was used for analysis of the typical trends in SiC etching: non-monotonic etching trend with O2 flow rate due to competing chemical processes in plasma; complex effect of the wafer temperature described by competing chemical reactions on SiC surface and changed limitation stage of etching process; non-linear dependence on DC bias voltage based on transition from ion bombardment controlled to radicals depletion regime in SiC etching. Simulations of SiC etching on pattered wafer with SiO2 mask demonstrate that IADF broadening at increased pressure results in trench corners rounding Fig.1 (left) due to the increased amount of ions approaching the side walls. However, relatively high pressure regimes up to 4 Pa are not preferable due to the side walls over-etching or bowing effect and poor selectivity SiC/SiO2 ~ 1 – 2 [10]. Presence of SiO2 mask on top of SiC provides an additional influence on the ion trajectories during the SiC etching, because a poor etch selectivity of SiC to SiO2 ~ 3 – 5 results in the dynamic change of SiO2 shape due to intense ion bombardment. Fig. 1 (right) demonstrates an example of side wall erosion due to evolution of SiO2 mask shape during the etching [11]. During the first 50 sec, the flux of incident ions is almost perpendicular to the SiC surface, the shape of mask and trench is rectangular. In 50 – 100 sec interval, the mask cut angle is increasing up to α ≤ 15º, specular reflection of ions results in the erosion of trench wall, followed by trench deformation. After 100 sec and until the end of process, SiO2 mask cut angle α > 15º, mask is etched by ions with no specular reflection, no changes in the trench walls occurs. Various combinations of SiO2 mask shape [9, 10, 11] and etching time were analyzed. It was demonstrated that time evolution of the cut angle of SiO2 mask strongly affects SiC gate trench shape due to specular reflection of ions on mask and their trajectories inclination. Large cut angle of SiO2 mask may help to minimize time period, when ions bombardment is focused on the side walls causing trench deformation. Possible ways of ICP-RIE process tuning in order to obtain rectangular trench with rounded corners are discussed. [1] C. Langpoklakpam et al, Crystals, 12, 245 (2022) [2] B. Li, et al, Appl. Phys. Lett., 73 653–655 (1998) [3] P. Chabert J. Vac. Sci. Technol. B, 19 1339 (2001) [4] F.A. Khan and I. Adesida, App. Phys. Lett., 75 2268 (1999) [5] K.M. Dowling, E.H. Ransom and D.G. Senesky, J. Microelectromech., S. 26 135 (2017) [6] L. Jiang, et al, J. Phys. D: Appl. Phys., 37 1809 (2004) [7] R.J. Hoekstra, et al, J. Vac. Sci. Technol. B, 16 2102 (1998) [8] L.E. Luna, et al, J. Micromech. Microeng., 27 095004 (2017) [9] J. Bobinac, et al, Micromachines 14, 665 (2023) [10] O. Seok et al, Phys. Scr. 95 045606 (2020) [11] X. Tan and Q. Xie, Conference of Science & Technology for Integrated Circuits, 3-65 (2022)

ABSTRACT. RTP (Rapid Thermal Process) anneals are used for the silicidation of top contacts and constitute an important step in the manufacturing process of the most advanced SiC power transistors (DMOS or UMOS).

The main challenge lamp RTP systems face when processing transparent SiC wafers is to satisfy the temperature control requirements. The temperature control challenges originate from the fact that the SiC wafers are transparent to IR radiation and must be inserted into graphite boxes. This complicates the wafer temperature measurements, makes “ true” RTP impossible (the thermal mass of graphite box considerably slows down wafer heat up and cooldown rates) and enhances the sensitivity to residual oxygen contamination.

This paper explains the potential of a conductive based RTP system to overcomes the main shortcomings of conventional lamp heated tools,. The advantage of conductive heating is that annealing becomes emissivity independent (equation 1). It means that the radiation-related properties of the wafer do not play a role, and consequently, that the whole RTP process becomes independent of wafer type.

In the work presented here, we successfully processed 200mm (+/- 0.5mm ) SiC wafers with a thickness of 500µm (+/- 50µm) with a conductive based RTP system (Levo Compact). The selected process was representing a Nickel silicidation step at 1000oC for 60s under nitrogen. The SiC wafers were directly inserted inside the reactor chamber without having to use graphite boxes. The heating and cooling speeds are high (>200degC /s) (see figure 1). High heat up and cooldown rates enable a perfect control of the silicidation process since the uncontrolled silicidation wich is occuring during heat up (and natural cooling) of the SiC wafer is avoided. The absence of a stabilization step during heat up (the SiC wafers were annealed in one go from room temperature to process temperature) combined with a forced cooldown guarantee a high throughput (figure 2). Table 1 reports the metal contamination levels before and after annealing. The residual oxygen level during anneal was less than 1ppm.

Conductive heating being substrate independent it also made possible to anneal simultaneously SiC wafers and Si wafers without any system adjustment. The silicon wafers were used to qualify the process (particles / Within wafer unfirmity and wafer to wafer repeatability).

ABSTRACT. With its excellent thermal conductivity, high critical breakdown field strength, and high-temperature tolerance, Silicon Carbide (SiC) is widely used in the fabrication of power devices. In recent years, many vertical high-voltage SiC PiN diodes with superior performance have been reported. However, since the cathode-anode voltage in these devices is vertically blocked in the semiconductor, the on-chip isolation between the devices is difficult to achieve. For this reason, the vertical power device is typically employed for high power densities in single-device packages or power modules. In contrast, effective isolation between lateral high-voltage devices can be achieved by using isolation structures, which enables monolithic integration with lateral PiN diodes, transistors, and resistors to achieve control, routing, and power density regulation in smart power integrated circuits. This work presents a novel design of SiC high-voltage lateral PiN diode (HVLPN), as well as the fabrication process, together with simulation and electrical measurement results for a demonstration of a 1000 V diode in an integrated circuit application.

ABSTRACT. Higher breakdown voltage devices based on 4H-SiC enables simplified circuit designs with simultaneous increase in efficiency and reduction in the size and weight of power convertors and power systems. With 1700 V 4H-SiC MOSFETs both low and high-power applications like auxiliary power supply and multi-phase invertors offer unparalleled advantages in solar, traction, solid-state transformers and EV/HEV drives. [1-3] For reliable and efficient operation at high voltages, optimization for both device design and processing are required. In this work, variations in critical device parameters like channel doping, channel length (Lch), gate oxide thickness (Tox) are studied for optimizing the design for any detrimental effects including short-channel effects on the device characteristics.

Fig.1(a) shows a schematic of the 1.7 kV VDMOSFET fabricated on 150 mm, N+ 4H-SiC wafers. The key device parameters including channel length and gate oxide are marked as p-well and oxide in the schematic. The variation in the device characteristics by varying channel length from 0.5 to 0.8 µm with a step-size of 0.1 µm and 50 nm and 65 nm for gate oxide thickness were considered on a design of experiment batch of 08 wafers.

The wafers were processed as follows, for defining P+/JTE/Pwell and N+/JFET usual aluminium and nitrogen implants were used, followed by a high temperature annealing for implant activation using a carbon cap layer. The gate oxide process involves thermal oxidation followed by post oxidation annealing to passivate interface and oxide traps. A self-aligned nickel silicidation process was used for enabling the front ohmic contacts to both N+ and P+ contacts followed by a power metal stack of Ti/AlCu deposition for the source and gate. While for the back contact, laser annealing process form an ohmic back contact followed by a solderable back metal stack.

Fig. 2 shows the effect of variation in the channel length and gate oxide thickness in threshold voltage of the devices. Fig 2(a) plots the variations in the threshold voltage, VT-mA, defined at a fixed drain current of 0.7 mA, with different Lch and Tox considered in this study. Fig 2(b) plots transfer curves for both Lch variation and Tox variations at Vds = 1.0 V. A continuous decrement in the threshold voltage with channel length scaling from 0.8 to 0.5 µm is accompanied by a corresponding increase in the peak transconductance. Thinner Tox of 50 nm shows an improved control of VT-mA variation over Lch variations indicating a scope of further design optimization. However, these improvements at shorter channel might come with a penalty of higher leakage current (IDSS) thus affecting the breakdown voltage (BVDSS) as well. Similarly, thinner gate oxide can affect oxide reliability through increased gate leakage current (IGSS). The effect of both Lch and Tox variations on the key device characteristics and the best trade-off scenario are explored in this study, enabling short channel and thinner gate oxide without compromising device performance and reliability.

This work was supported by the Innovate UK Project SiC-MAP [Grant number: 77743].

[1] B. J. Baliga, Fundamentals of Power Semiconductor Devices. New York, NY, USA: Springer, 3, pp. 91–155, 2008 [2] Information on https://eepower.com/technical-articles/eliminating-power-conversion-trade-offs-by-moving-to-1700v-sic-mosfets/ [3] H. L. R. Maddi et al., Energies, 14, p. 8283, 2021.

ABSTRACT. Silicon Carbide (SiC) is the most promising semiconductor for power electronics due to its high critical electric field, high switching frequency and high temperature operation capability. In this work, the recently presented SiC power MOSFET based on innovative vertical Gate All Around (GAA) concept is further investigated in terms dynamic and thermal performances. After an accurate evaluation of the thermal behavior of the device, an extensive campaign of TCAD simulations is carried out to analyze the performance in switching and short-circuit conditions.

ABSTRACT. The NO annealing after thermal oxidation is performed to improve on-resistance of SiC MOSFET. We investigate the interface electronic structures of 4H-SiC/SiO2 interface after NO annealing by DFT calculations. In our previous study, the screening effect of the nitrided layers on the Coulomb interaction of O atoms in the SiO2 layer was demonstrated. However, the areal N atom density in the previous study is three times higher than that in the practical devices due to the limitation of computational resources. In this study, we reduce the areal N atom density so that it corresponds to that of the practical devices. Our calculation using the large model with partially nitrided interface demonstrates that this conclusion is not affected even when the interface is partially nitrided and the screening effect of the nitride layer may be enhanced when the areal N atom density is increased.

ABSTRACT. 4H-SiC thyristors are of particular interest in pulsed power applications due to their ability to block high voltages and transfer high current densities along with fast switching times. Here, we present a paper that demonstrates both (i) the impact of the design parameters on the blocking characteristics based on simulations taking into account the anisotropy of 4H-SiC and (ii) a critical comparison to real devices having equivalent epitaxial structural design. Simulations and measurements show that an etched JTE is suitable to design high-voltage SiC thyristors. Concerning Vbr, the real devices data agree to simulations for DJTE in the relevant region. Besides uncertainties of the actual JTE thickness and doping concentration, the relatively thin field-stop layer might explain the discrepancy between experiment and simulation.

ABSTRACT. Multidimensional devices structures can improve the typical performance trade-off of semiconductor power transistors. In this paper, the on-state, reverse, and short-circuit performance of a SiC quasi-planar trench MOSFET are compared to those of a classical planar device through advanced 3-D TCAD simulations.

ABSTRACT. 4H-SiC semiconductors possess a wide bandgap, high breakdown electric field strength, high thermal conductivity, and high electron mobility [1]. It is one of the most attractive semiconductors for high-power metal-oxide semiconductor field-effect transistors (MOSFETs). Local residual stress significantly impacts the electrical properties of electronic devices [2]. To observe the local stress disribution, we have developed a scanning near-field optical Raman microscope (SNOM) using a hollow pyramidal probe (aperture size: approximately 150 nm) based on UV resonant Raman scattering [3]. In a previous study, we prepared two types of trench-test MOSFET structures on m- and a-faces in 4H-SiC, and reported the anisotropic stress distributions around the apex of the trenches occur in m- and a-faces by a SNOM [4]. We also found that the stresses were localized under the top of trench and that the stresses around the trench measured by a SNOM were significantly larger than those obtained by a standard far-field Raman microscope. In this study, we developed 4H-SiC Trench-Test MOSFET structures with different trench shapes on a-face and investigated stress distributions induced by the trench shapes. A Horiba Jobin Yvon single monochromator with 1 m focal length and a grating of 3600 grooves/mm was used to record Raman spectra. Measurements were performed at room temperature using the 355 nm line of a semiconductor laser in the backscattering configuration while moving the x-y piezoelectric scanner in 105 nm steps. A spectrometer equipped with a 2048 × 512 CCD detector was employed. All Raman spectra were measured using a power rating of < 0.4 mW on the sample to avoid peak-frequency shift by thermal expansion. A hollow pyramidal probe with an aperture measuring approximately 150 nm was used in measurements performed in this study [3]. Figures 1 and 2 show photographs and stress distributions of a cross-sectional Trench-Test MOSFET structure for (a)circular and (b)rectangular trenches obtained by a SNOM. We have investigated the stress dependencies of phonon modes in a 4H-SiC crystal, determining the deformation potentials of the A1 and E2(TO) modes [5]. As a result of the analysis based on the reference [5], we oberved anisotropic stress disributions in both trench shapes. We also found that the stresses at the top of trench in the rectangular trench were originated from the edges, while in the circular trench, the stresses were concentrated only at the apex of the trench. This result suggests that SNOM Raman measurement is an effective technique for observating local stress distribution and that the trench shape has a significant impact on the stress distribution. At the conference site, we also discuss the trench space-dependence of the stress distributions observed around the trenches with those calculated by a finite element method (FEM).

ABSTRACT. In this work, TCAD simulation of SiC MOSFETs design with deep (2 µm) p-base using single step Aluminum channeling implant along [0001] direction and JFET design using phosphorus implant is presented. The threshold voltage (Vth) was around 3 V for both the devices. Improvements to the specific on-resistance (Ron,sp) reduction by ~ 30 %, breakdown voltage (BV) enhancement by ~ 40 %, miller plateau (QGD) reduction by ~ 30% was reported. Furthermore, both the baliga figure-of-merit (BFOM) (BV2/Ron,sp) and high-frequency figure-of-merit (HFOM) (Ron,sp x QGD) with 2 µm deep p-base /JFET implant was enhanced as compared to shallow 0.7 µm p-base/JFET implant. This paper provides valuable insights into the advantages of a single-step channeling implant at room temperature, without the need for a hard mask. This approach offers high throughputs and a low-cost process for fabricating high-performance devices.

ABSTRACT. To properly measure the current gain and to further study the performance of commercial SiC BJT when connected in parallel, static measurements are conducted to measure the following electrical properties in paralleled BJTs: transfer characteristic, base-emitter leakage current (IRR(BE)), collector-emitter on-resistance (Ron), DC common-emitter current gain (β), and output (I-V) characteristics. Two-paralleled SiC power BJTs GA04JT17-247 are compared with the similarly-rated Silicon BJTs FJL6920 by means of extensive experimental measurements.

ABSTRACT. SiC devices such as SIC MOSFETs have the unique characteristic of managing several tens or even hundreds of Amps at high switching speed, creating hard to measure high current derivatives, di⁄(dt,) in the switching loop of power electronic circuits. The current measurement should be high-current, high bandwidth and low inductance, to properly measure the current without perturbating the switching behavior of the converter. The preferred devices to measure fast currents on the range of several tens of Amps are the coaxial shunts, but they are expensive and bulky, inserting a considerable inductance, several nH, in the switching loop. This work presents an inexpensive current measurement SMD network layout for high current, achieving the same dynamic performance of a coaxial shunt with reduced added inductance. The proposed field cancellation technique and radial layout add less inductance to the switching loop, proving it by both measuring the inductance with an impedance analyzer and by analyzing the switching waveforms. This paper provides experimental evidence of the superior performance of the proposed configuration in terms of added inductance when facing the challenge of measuring high currents fast.

ABSTRACT. Due to its excellent physical properties, the third-generation semiconductor silicon carbide (SiC) material has very clear application prospects in the fields of high-temperature, high-frequency, high-pressure, and high-power electronics and RF microwave devices [1, 2]. Limited by its own technical characteristics, using traditional physical vapor transport method (PVT method) to prepare SiC crystals still faces many technical challenges, making it difficult to meet the urgent demand for large-size, high-quality, and low-cost SiC single crystal substrates in current electronic devices [3-5]. The top-seeded solution growth (TSSG) can achieve SiC crystal preparation at lower temperatures and near thermodynamic equilibrium conditions, which can significantly compensate for the shortcomings of the PVT method, and is gradually becoming one of the highly competitive innovative technologies for high-quality SiC substrates preparation with lower cost [6, 7]. However, after decades of development, this way has not yet formed large-scale industrialization, mainly due to the fact that there are still some key issues that urgently need to be broken through, including solvent inclusions, step bunching, foreign polytypes, pores, polycrystalline and crystal cracking, as shown in Fig. 1 [8-10]. In this paper, the basic theory of TSSG method for SiC crystals growth is firstly introduced and the key points of each process are given. Then the main technical advantages of TSSG method are summarized by us and the research status at home and abroad are reviewed. Furthermore, the key technical issues, mechanisms, and possible solutions for the growth of SiC crystals by TSSG method are discussed, aiming to provide important theoretical basis and practical guidance for the further development and improvement of this technologies. Finally, our research progress is shown in Fig. 2.

ABSTRACT. The SiC power semiconductor market grows with impressive strength and the demand on SiC power devices is steadily increasing. However, this also requires a huge amount of SiC crystals and wafers in highest material quality, which are further processed in high temperature processes like epitaxy or oxidation. All these high temperature reactors typically contain hot-zone assemblies made of graphite which are extremely stressed by the harsh temperature and atmospheric environments. To protect these graphite parts from the environment as well as vice versa to protect the SiC semiconductor materials from contamination, particles etc. from the degrading graphite, in recent years the use of high temperature and corrosive protection coatings, e.g. based on TaC or SiC has been established in the industry. Especially coatings produced by chemical vapor deposition (CVD) are used. However, there are also some drawbacks of this technology concerning costs, process time, limited coating thickness and tendency to crack-formation. For this reason, Fraunhofer IISB has developed a new cost-effective and highly flexible technology to seal the porous graphite by converting its surface into SiC. The applied dense SiC coating layer withstands extremely high temperatures and corrosive gases like silane, hydrogen (SiC epitaxy) or oxygen (SiC oxidation). The technology is compatible with a wide range of graphite types (isostatic, extruded, …) having different properties like grain structure, porosity, or thermal expansion. Additionally, the coating technology is not limited to full sample/component coverage which makes it more flexible with respect to potential applications. To evaluate the coating performance some first experimental tests were carried out. On the one hand 4 inch SiC coated wafer carrier were tested in a single wafer Epi reactor under typical SiC epitaxy process conditions (1600°C, silane, propane, hydrogen) with promising results. After process no coating ablation or crack-formation was observed (see Fig. 1). Further, the contamination coming from the SiC coated wafer carrier was investigated by measuring the impurity level after the epi process on the SiC-wafer surface by VPD ICP-MS method. The results show no significant metal contamination after the process, which qualifies the coating system for industrial use. Beyond the investigation in epitaxial environment, the oxidation resistant behavior of SiC-coated graphite shards (50x25x10 mm³) was investigated in a tube furnace at 1100°C and synthetic air (20% oxygen) with total holding times of up to 220 hours. Hereby, a very good oxidation resistance could be demonstrated for process times > 200 hours, indicated by a non-existing mass loss (indicator for oxidation of laid open graphite sites) for that period (see Fig. 2). Perspectively, we will further work on increasing the oxidation resistance and adaption of our SiC coating technology to further graphite types.

ABSTRACT. Silicon carbide (SiC) is a wide bandgap semiconductor that is rapidly being adopted in many power electronic applications, including electric vehicle drive train and charging systems. However, SiC MOSFETs exhibit poor performance due to a high density of interface states, which leads to low channel mobility (< 5% of bulk mobility), primarily due to defects generated during thermal oxidation of the SiC. To mitigate this, various deposited-oxide processes have been explored, including ALD SiO2 [1], low-temperature oxidation of CVD silicon [2], and PECVD SiO2 [3], all of which minimize thermal decomposition of the surface. Tachiki, et al. [3] reported a 2x increase in peak field-effect mobility compared to a standard thermal oxide, but to our knowledge this result has not yet been independently reproduced. In this study, we report a surface pre-treatment in dilute SiH4 in H2, similar to Kimoto, et al. [4], followed by deposition of an amorphous silicon thin film and low-temperature oxidation to form the SiO2/SiC interface. This process achieved a peak field-effect mobility of ~ 80 cm2/Vs, more than 3x higher than identical thermally-oxidized MOSFETs on the same substrate. Details of the process are given next. Planar long-channel MOSFETs were formed on an n-type 4H-SiC epilayer doped 1x1016 cm-3. The p-type body region was implanted with aluminum to a surface concentration of 3.8x1016 cm-3, and source and drain regions were formed by heavy-dose nitrogen implantation. Implants were annealed under a carbon cap at 1700°C for 20 minutes. To form the gate oxide, samples were RCA cleaned and subjected to H2 etching at 1300°C for 3 minutes in an Epigress VP-508 hot-wall CVD reactor at a pressure between 500 and 900 mbar and a flow rate of 10 slm (see Fig. 1a). The etch was concluded by adding 5% SiH4 diluted in H2 for 3 minutes at a flow rate of 10 – 100 sccm to the existing H2 gas flow, as shown in Fig. 1b. This step was critical to achieving enhanced mobility. Immediately after unloading from the anneal chamber, samples were transferred to an LPCVD furnace for deposition of amorphous silicon at 580°C, followed by thermal oxidation at 750°C for 24 hours and an NO anneal at 1175°C for 2 hours. Polysilicon gates were deposited at 630°C and doped by diffusion from a phosphorus spin-on dopant. Nickel silicide ohmic contacts were annealed at high temperature, and aluminum was deposited as top metal. The final gate oxide thickness was ~ 44 nm, while the channel length and width were 140 μm and 110 μm respectively. Transfer characteristics of the fabricated MOSFETs are shown in Fig 2a. Devices with a 100 sccm SiH4 treatment show a sharp increase in drain current and a negative threshold voltage (Vth ~ ‑3 V), compared to those treated with lower silane flow rates or the thermally oxidized and NO annealed control sample (tox = 50 nm). The peak field-effect mobility (Fig. 2b) of the 100 sccm SiH4 treated device shows a dramatic improvement (~81 cm2 /Vs) compared to the control sample (~25 cm2/Vs). The 3x increase in peak mobility can be attributed to a significantly reduced density of the interface states. The negative threshold voltage is due to a corresponding reduction in negative interface charge. To explore the scattering mechanisms in the high mobility samples (100 sccm SiH4), the mobility was extracted at various temperatures (Fig. 3a). It is interesting to note that peak mobility exhibits a non-monotonic behavior as a function of temperature. The increase in peak mobility below 75°C may be attributed to a decrease in Coulomb scattering, while the peak mobility decrease beyond 75°C and at higher gate voltages may arise from increased phonon scattering. Finally, the breakdown characteristics of the gate oxides are shown in Fig. 3b. While the gate oxide from the new process exhibits a breakdown strength greater than 8 MV/cm, the low-field leakage is higher compared to a thermally oxidized control sample. In summary, we describe an oxidation-minimizing gate-stack process that yields a 3x higher peak channel mobility, confirming the results in [3] and [4]. This new process can lead to 1.7x–2x reduction in total on-resistance for SiC power MOSFETs in the 650 – 1200 V regime, a huge emerging market.

This work was supported by the Margot A. and Carl J. Johnson Foundation and the Coherent / II-VI Foundation. The work was performed at the Birck Nanotechnology Center, Purdue University, with assistance from Clas-SiC Wafer Fab.

[1] R. Ramamurthy et al., IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), pp. 242-245 (2017) [2] T. Kobayashi et al., Appl. Phys. Express, vol. 13, pp. 091003 (2020) [3] K. Tachiki et al., Appl. Phys. Express, vol. 14, pp. 031001 (2021) [4] Kimoto et al., US Patent Application No. 2023/0307503 A1 (Sept. 28, 2023)

ABSTRACT. SiC has been increasingly used in high-voltage, high-power applications due to its high critical electric field. Improvements in the on-current and specific on-resistance are continuously being sought after through various methods, such as process optimizations [1-3], cell topologies [4], and charge modulations [5]. In this work, we experimentally demonstrated >2.5x on-current improvement on 1200 V-rated 4H-SiC based VDMOSFET. Fig. 1 illustrates a schematic cross-sectional view of our device, which is fabricated in a standard 1.2 kV 4H-SiC process. Typical aluminum and nitrogen implants were used for p+/JTE/p-well and n+/JFET, respectively. One difference between this work and a conventional VDMOSFET is that separate contacts are formed for the p-well and source regions, allowing for independent biasing of the p-well and source regions. In this work, a positive bias is applied to the p-well region when the VDMOSFET is in the on-state and is removed when the VDMOSFET is in the off-state. In a conventional VDMOSFET, the p-well and source regions are shorted and typically connected to a common ground. The p-well and source front ohmic contacts are enabled via a self-aligned nickel silicidation, while the back ohmic contact for the drain region, metal is deposited followed by laser annealing. A breakdown voltage of 1500 V is obtained as shown in Fig. 2. Fig. 3 shows the transfer curves measured from a test structure having a JFET length of 15 um with different voltage applied to the p-well region for different Vds. As shown in Fig. 3, the on-current with a positive bias Vp=2.5 V applied to the p-well region is 2.5x higher than a conventional VDMOSFET (with Vp=0V applied to the p-well region). Fig. 4 shows the associated p-well current, demonstrating that the large on-current gain does not require large p-well current. The ratio between on-current gain to the p-well current can be calculated to be >10^4. Fig. 5 shows the corresponding transconductance curves. As the results show, both Vt shift and gm increase contribute to the on-current gain. TCAD simulations are performed to study the underlying mechanisms of the on-current gain. Fig. 6 illustrates the transfer curve from the TCAD simulations. Fig. 7 shows the current density of the VDMOSFET with Vp=0V and Vp=2.5V, respectively. When a positive bias Vp=2.5V is applied, the conduction area encompasses the source junction area and no longer limited to the area of the channel region. The additional conduction paths are not limited by the channel mobility, as can be seen from the higher transconductance in Fig. 5. Further process improvements on the conventional SiC VDMOSFET and JFET length optimization have resulted in lowering on-state resistance Rds,on to 3 mOhm.cm2 (Fig. 8). Using the p-well biasing technique described in this work, low Rds,on of 1.2 mOhm.cm2 can be achieved.