ABSTRACT. The bulk growth process of SiC using the physical vapor transport (PVT) method may be called mature. The single crystalline diameter of 150 mm is state of the art, while the crystal diameter of 200 mm is strongly pushed to take over the pole position. Major R&D efforts focus on the further reduction of the dislocation density. In this context the improvement of the yield of the PVT process is a key task. This work discusses three aspects of the PVT growth process to reach a higher SiC crystal yield: (i) Type of the carbon isolation material and procedure to maintain process-to-process reproducible growth conditions. (ii) Pro and cons between temperature and power control (or mixture of both) of the SiC crystal growth phase of the PVT process, (iii) selection of a set of process parameters and specs of the grown SiC crystal which are a fingerprint of reproducible growth conditions (related to selection and design of hot zone isolation components). Note: Other sources for process instabilities like graphite quality of the carbon crucible, SiC seed quality and seed mounting (to name a few among many other distortive sources) are not addressed in this work. In our study we are analyzing 34 PVT 150 mm growth process, all making use of the fundamentally equal hot-zone design (index I) where two minor design variations (cooling channel, crucible variant) are included. Compared to an industrial standard growth process, the number of crystals compared are rather low. Nevertheless, the study resulted in clear recommendations how to increase the process reproducibility and yield related to the challenging isolation components of the hotzone. The 150 mm PVT growth runs were carried out in a Sicma 3 system provided by the company PVA Crystal Growing Systems GmbH (Wettenberg, Germany). The experimental study was supported by a precise computer simulation of the temperature field of hot zone which makes use of an advanced data base on high temperature (T<2000°C) heat conductivity of the applied carbon isolations. Carbon isolation: At process temperatures above 2000°C mainly carbon isolations are applied which withstand the growth conditions. Nevertheless, at such high temperatures, degradation because of microscopic morphologic changes and aging related to Si-containing leakage of vapor from the growth cell are very common. We have designed the hotzone in a way that about 25% of the carbon isolation is replaced by new material before each growth run. Using this procedure, the T-measurement by optical pyrometers on top of the growth cell indicated a high process reproducibility. In the case of an induction heating power of 15.5 kW, we observed a constant temperature of 2020°C which varied only by +/-20°C (see Table 1). This value variation is less than 1% which comes close to measurement precision of optical ratio pyrometers. In addition, the observed crystal growth rate (determined in the center of the boule) varied less than 3%. Both values indicate, that the evolution of the SiC crystal has become very reproducible. Power versus temperature process control: Considering a T-measurement error of optical pyrometers of at least +/-10°C at T>2000°C and potential distortions in the optical alignment of the system during the growth process, a total T-measurement error of 10-20°C is typical, Nevertheless, distortions above 50°C may occasionally occur. In addition, a thermally highly isolated hot-zone (to save heating energy) exhibits long reaction intervals before a change in the heating paper affects the hot-zone temperature. Therefore, it is recommended to use the temperature measurement/control as an indicator that the right T-value for a given heating power has been reached at the beginning of the growth process. Throughout the growth process a constant heating power mode (including a precise monitoring of the temperature of the hotzone) is recommended for stable growth process conditions. In fact, experimentally (for several different hot-zone designs & fixed inert-gas pressure) we observed an almost linear growth rate to temperature (or heating power) relation. Since the growth rate is dependent on many thermodynamic as well as growth-kinetic phenomena, this finding represents more like a rule of practice, which proved to be valuable for the planning of new PVT growth processes. Fig. 2 depicts the temperature to growth rate evolution for two 150 mm hot-zone designs (= different cooling channel dimensions). This result on one hand it indicated that the constant power process control may lead to stead (= undisturbed) growth process. On the other hand it enabled quite precise tuning of the SiC crystal growth rate. Indicators for reproducible growth conditions: The simple dataset of Heating power, Temperature of the hot-zone (top or bottom pyrometer) and the Growth rate (or crystal length at given duration of the growth period, see Fig. 1) as used in Table 1 proved to be powerful to validate reproducible growth condition which are related to the selection and design of hot zone isolation components as discussed in this work. The presentation will include a more detailed discussion of the dataset of the 34 growth process carried out for this study. In addition to the experimental data, we will use computer simulation results to point out to which extend certain in-homogeneities or batch-to-batch variations of the carbon isolations affect the crystal growth yield. This work has been partially funded by the German Science Foundation (contracts WE2107-12, WE 2107-15) and PVA Crystal Growing Systems GmbH (Wettenberg, Germany)(contract wtt-19174).

ABSTRACT. For power semiconductor applications, SiC single crystals are manufactured by sublimating high-purity SiC sources at high temperatures ranging from 2100 to 2500°C, using the physical vapor transport (PVT) method. Currently, commercial substrates are typically produced at a growth rate of 0.2 to 0.4 mm/h via the PVT method, which is significantly slower compared to other single-crystal materials used in semiconductor applications. The slow growth rate of SiC via the PVT method is one of the major barriers hindering the productivity of SiC substrates. Although not via the PVT method, rapid growth of SiC has been developed recently so far [1-4]. They successfully controlled the growth rate of SiC single crystals to ~9 mm/h using the high-temperature chemical vapor deposition (HTCVD) method, even achieving high-quality crystals at the growth rate of ~3 mm/h. The HTCVD method allows the use of vapor phases as the source, which originally excluded the formation of carbon dust from the solid sources and freely controlled the composition of the vapors, thereby removing the source issue hindering the rapid growth. So, the high-quality crystals were achieved under rapid growth conditions by preventing the formation of excess crystal surfaces for heat dissipation by controlling the temperature gradient at the growth interface. However, practically, SiC single crystals are currently mass-produced via the PVT method with solid SiC as the source by all suppliers. Even if it is possible to manufacture high-quality, rapidly grown SiC single crystals, adopting an entirely different process like HTCVD as a mass production process would involve considerable difficulties. For the manufacturers producing bulk SiC crystal products, there is a need for technologies that can improve the mass production of products within the existing process framework. In recent studies, therefore, we have reported a method for rapidly growing SiC single crystals using the existing PVT method [5]. Instead of the traditional powdered SiC sources, CVD-SiC crushed blocks were used in our research [5]. These blocks are not in powdered form and have a very small specific surface area, thus they can prevent the inclusion of carbon dust into the growing crystals under strong fluid flow during rapid growth, thereby preventing quality degradation of the single crystals due to source problems. Previous studies have reported growth rates up to 1.7 mm/h for SiC single crystals with a diameter of 50 mm, but the crystal quality, especially at the edges, was not satisfactory. In this study, as part of efforts to improve single crystal growth characteristics, various growth results were obtained in the growth speed range of ~0.8 to ~2.6 mm/h by controlling the vertical and horizontal temperature gradients at the growth interface, and these were compared with the temperature gradient patterns obtained from PVT simulations, aiming to gauge future directions for the rapid PVT growth method.

ABSTRACT. Silicon Carbide (SiC) emerges as the dominant material for high-power, high-voltage power devices due to its superior performance compared to traditional silicon-based devices. Therefore, SiC devices constitute a disruptive technology with applications e.g. in solar inverters, datacenter power supplies, fast chargers and drivetrain inverters for e-mobility [1]. A shift from 6-inch to 8-inch wafer material results in approximately 78% more available area per wafer. This transition facilitates cost-efficient production due to the utilization of 8-inch high-end equipment, which was initially developed for the silicon device industry.

In the context of growing high-quality SiC crystals through physical vapor transport (PVT), precise control of thermal fields plays a critical role [2]. The primary drawback of inductive heating lies in its dependence on the electrical properties of the graphite crucible and insulation, specifically within the ‘Hot Zone.’ (see Fig. 1). Graphite’s electrical conductivity is challenging to control due to variations in density, porosity, and degree of graphitization during production. Additionally, critical material properties degrade significantly during the crystal growth process, necessitating frequent and costly replacement of crucible components.

Resistively heated furnaces for SiC PVT growth potentially enable enhanced control of the thermal field, with potential advantages for defect density reduction and additional benefits regarding reproducibility and cost [3]. Here, we demonstrate the feasibility of growing high-quality SiC crystals in resistive furnaces. For the assessment of the crystal quality, we show the results of defect mapping techniques such as photoluminescence (PL), X-ray Topography (XRT), and defect quantification using KOH etching and machine learning based image analysis using a region-based convolutional neural network (R-CNN) (see Fig. 2). In summary, the presented research contributes to our knowledge of silicon carbide (SiC) crystal growth in resistive furnaces. Our findings open-up opportunities for optimizing furnace technology and growth processes in terms of cost effectiveness and crystal quality.

ABSTRACT. Commercially available silicon carbide (SiC) crystals are produced by the physical vapor transport (PVT) or seeded sublimation process. Especially, bonding the seed substrate to the graphite seed holder is one of the most important processes to suppress generation of defects and dislocations in the PVT growth. The pores in the seed/graphite holder interface often form via degassing from carbon glue during baking process. The pores act as a thermal resistance which forms macro-defects in the grown crystal.[1] Since the wafer diameter on the market is changing from 6- to 8-inch, severe control of the seed bonding process is required. It is important to understand how the pores affect the thermal field of a growing crystal. In this study, we investigated an effect of interfacial pores on thermal field and crystal-shape uniformity in the initial growth stage by the Virtual Reactor (VR) simulation software.[2] Figure.1 shows a schematic illustration of (a) a crucible model used for PVT growth and (b) the model of the interfacial-planer-shaped pore (IP) filled with argon. Model parameters on the simulation were listed in table.1. The macro-defect formation from the pores was not considered in this simulation. The ratio of the thickness just above the IP (dIPC) to the growth thickness at the center of the crystal (dSC) was used to crystal-shape uniformity and named” the uniformity index” here. Figure 2 shows the simulated crystal shape on the 1.5 mm-thick seed after PVT growth of 30 hours. Without the IP, grown crystal shape was smooth convex. On the other hand, grown crystal shape was locally concave just above the IP. The difference in thermal resistance arises by the IP resulted in a decrease in growth rate and a clear difference in crystal shape. It is confirmed that the IP greatly affects to thermal field around seed, as a result, the crystal surface would be distorted for this condition. We investigated the uniformity index with different seed thickness. Figure 3 shows the relationship between the seed thickness and the dIPC/dSC ratio for growth time of 30 hours. For thinner seed thickness, the dIPC/dSC ratio becomes clearly lower. As increasing seed thickness, the dIPC/dSC ratio also increases and is getting closer to the unity, which means crystal-shape uniformity is improved. This result suggests that thicker seed can improve the uniformity of grown crystals, even if interfacial pores exist. These results provide a guideline for the control of interfacial pores in the actual crystal growth.

ABSTRACT. Due to the harsh environment and therefore a great deal of wear, analysts assume that there will be an overall shortage of graphite supply in the SiC manufacturing world. The basic applicability of a high-temperature and corrosion reistant TaC coating, applied by the spray coating technology TACCOTA® developed at Fraunhofer IISB, on graphite reactor components for typical SiC PVT growth environments has been already successfully demonstrated. However, to extend the use of graphite materials with deviating thermal expansion, the thermal stresses which initiate cracks in the coating have to be significantly reduced. The introduction of a crack-free or crack-reduced TaC-based mixed coating layer (MCL), with a varying CTE (cofficient of thermal expansion) lower than pure TaC, is one possible option to lower the degradation degree. In this contribution, it is shown that MCLs have a high potential to overcome the CTE mismatch issue and finally to enable the protection of further non CTE-adapted graphite grades by TaC related coatings.

ABSTRACT. In spite of extensive studies on SiC MOSFETs, SiC n-channel MOSFETs still suffer from the low channel mobility and the channel resistance is dominant especially in commercially available 600 and 1200 V-class MOSFETs. In recent years, SiC CMOS has attracted much attention for ICs operating under harsh environment, where performance improvement of not only n-channel but also p-channel MOSFETs is crucial. In this paper, recent studies on mobility enhancement in SiC n- and p-channel MOSFETs including the authors’ group are presented.

ABSTRACT. In 4H-SiC crystals, electron mobility exhibits an anisotropy. The electron mobility along c-axis is higher than that for perpendicular to c-axis, which is a beneficial relationship for a low on-resistance vertical power device fabrication. However, a different anisotropy has been reported for MOS channels on (11-20) a-face and (01-10) m-face, and the mechanism has not yet been clarified. In this study we found that MOS channels fabricated on semi-polar crystal faces exhibit a different anisotropy from conventional non-polar crystal faces.

ABSTRACT. The performance of silicon carbide MOSFETs is limited by a high density of traps at the oxide semiconductor interface (4H-SiC/SiO2) giving rise to low channel mobility for the MOSFETs. One effective method for quantifying the total interface traps is gated Hall measurements [1,2], which should also allow characterization of any interface degradation effects observed when threshold voltage shift is detected after gate stress [3,4]. In this work, gated Hall measurements are performed to quantify interface traps on the conduction band side of the bandgap. Furthermore, positive gate stress effects have been studied using lateral MOSFET Id-Vg evaluation, and gated Hall measurements. Figure 1 shows a MOS Hall bar top-view. The Hall bar is fabricated on a Si-face 4° off-axis SiC (0001) wafer, on a 2×1017 cm-3 Al-doped p-well. This device is a long channel (Lch=1 mm, Wch=200 um) lateral MOSFET with Hall voltage contacts, fabricated with a thermal oxide passivated with a NO anneal. Figure 2 shows the measured MOS Hall mobility (μ_Hall) and field effect mobility (μ_FE) versus gate voltage at room temperature. The lower value of μ_FE comes due to the high density of interface traps. μ_Hall gives the actual value of the carrier channel mobility, directly measured. The value of the interface trap density is calculated in Fig. 3 from the measured Hall data. First, the total carrier concentration (ntotal) is extracted from a split CV measurement. The free carrier concentration (nfree) is obtained from the gated Hall measurements and then subtracted from ntotal to extract the total trapped charge density (ntrap). As the gate voltage increases, ntrap increases rapidly due to faster occupation of interface traps, while at high gate voltage the trapped charge density increases at a slower rate but doesn’t saturate. These trap levels are in the upper half of the band gap and close to the conduction band edge, the density of which increases exponentially. Hall carrier concentration reveals that about half the channel charge is trapped and not contributing to channel current. Figure 4 shows the Hall and field effect mobilities at different body bias. The values of ntrap are extracted from these measurements as shown in Fig. 5. When the trapped carrier concentrations are plotted as a function of the gate overdrive voltage (Vgs-Vt), all the ntrap curves merge onto each other. This proves that body bias does not change the interface trap densities, only the value of transverse electric field changes, thus changing the mobilities. Next, Hall measurements are used to perform a channel degradation characterization. The gate is stressed at +36 V for different times (0, 10, 30, 100, and 300 sec) and the Hall measurements are performed. Figure 6 shows Hall mobilities as a function of gate overdrive voltage after each stress condition. At low voltage the mobility reduces due to the stress; however, at high gate voltage they overlap. In addition, trapped charge densities are calculated after each gate stress condition. Figure 7 shows that, with increasing stress time, the free carrier density drops, indicating an increase of trapped charge carriers at the interface. Figures 6 and 7 are summarized in Fig. 8 which shows the changes of Nit and mobility (extracted at Vgs-Vt= 15 V) with stress time. Mobility decreases, and the value of Nit increases as the stress time increases. Gated Hall measurements clearly reveal the free and trapped carrier densities and carrier mobility, and is a powerful way to analyze channel degradation under stress, showing the effects on Nit and mobility.

[1] M. Noguchi et al., IEEE Trans. Elec. Dev., 68, 12, (2021). [2] S. Das et al., MDPI Materials, 15, 19 (2022). [3] J. Berens et al., IEEE IRPS, pp. 1-5 (2021). [4] A. K. Biswas et al., ICSCRM, accepted (2023).

ABSTRACT. The SiC-gate dielectric interface of SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) has to be specifically processed to ensure reliable and highly efficient operation. Namely, the quality of gate dielectric-SiC interface is determined by a presence of (near-) interface traps, leading to reduced channel-carrier mobility and/or threshold voltage drift. This paper presents dynamic capacitor-voltage (C-V) measurements of the metal-dielectric gate stacks, enabling the characterization of the dielectric-semiconductor interface under more device-application relevant conditions than the standard quasi-stationary (QS) C-V measurements.

ABSTRACT. To ensure long-term reliable operation of SiC power MOSFETs, it is critical to understand safe operating conditions and the effects of voltage stress on device performance and defectivity, during both operation and testing. The evolution of threshold voltage (VT) and interface trap density (Nit) of SiC MOSFETs during positive high voltage gate stress (HVGS), wherein the oxide field exceeds the threshold for impact ionization, has recently been evaluated [1-2], and it was shown that Nit increases, thereby degrading the MOS interface [2]. In this work, we continue these investigations by studying the evolution of both Nit and field-effect mobility (μFE) during positive as well as negative HVGS on lateral test MOSFETs using ID-VGS and charge pumping (CP) measurements, revealing the practical impact of HVGS on device performance. The devices used for this study are lateral test MOSFETs fabricated on 4° off-axis 4H-SiC epitaxial wafers. The implanted acceptor concentration (NA) in the channel is 2×1017 cm-3 and the MOS interface is formed on the Si face by thermal oxidation followed by NO annealing. The MOSFET channel length and width are 8 μm and 200 μm, respectively. A schematic cross section of the MOSFET is shown in Fig. 1, along with the equations used to calculate µFE and the number of interface traps pumped per cycle (NCP). Each device was stressed at a given gate voltage well beyond the recommended operating condition to induce impact ionization in the oxide for a cumulative stress time of 30 minutes which was interrupted periodically by a CP voltage level sweep with a pulse amplitude of 15 V followed by an I¬D-VGS sweep. Fig. 2 shows the µFE and CP curves after each stress interval for stress voltages of +36 V and -36 V. Positive HVGS causes a significant degradation of both µFE and NCP with time. In addition, VT and the flatband voltage (VFB) quickly shift negatively (within the first minute), then remain nearly constant. This is consistent with past observations and is a consequence of impact generated holes filling pre-existing bulk oxide traps [2]. On the other hand, negative HVGS causes a negligible change in the peak µFE and a small increase in NCP. VT and VFB continuously shift negatively with increasing negative stress time, due to hole trapping in both bulk oxide traps and border traps. The difference in interface trap generation between positive and negative HVGS indicates that the trap generation requires either (i) the presence of hot holes, or (ii) the presence of both electrons and holes, in the oxide near the interface. This can be deduced because positive HVGS causes electrons to be injected from SiC into the SiO2, which can generate holes by impact ionization and/or anode hole injection which will then be accelerated back toward the SiC/SiO2 interface with high energy. But under negative HVGS, holes injected from the interface cannot reach sufficiently high energy to generate electrons, and require a finite distance to accelerate before becoming hot [3]. In Fig. 3 and 4, NCP and µFE are plotted as a function of stress time for different positive and negative stress voltages. Under positive stress, degradation of NCP and µFE increases with both stress voltage and time. Under negative stress, NCP slightly increases but µFE is unaffected. Fig. 5 shows the change in µFE versus the change in NCP during stress with the data for each stress voltage overlaid together. A linear correlation between NCP and µFE is observed for positive HVGS and each stress voltage follows the same universal curve. No correlation is seen for negative HVGS since the mobility does not degrade, perhaps indicating that only donor traps are created during negative HVGS which do not affect the channel mobility. In conclusion, negative HVGS causes significantly less channel degradation in SiC MOSFETs than positive HVGS with respect to interface trap density and channel mobility. Furthermore, CP is shown to be a valuable technique for characterizing SiC MOS degradation.

[1] F. Masin et al., J. Appl. Phys., 130, 145702, (2021). [2] S. Stein et al., IEEE IRPS, (2024). [3] D. Arnold et al., Phys. Rev. B, 49, 10278 (1994).

ABSTRACT. The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Based on material characterisation, we anticipate a benefit of up to 15% or 30% in terms of RDSon for state of the art 1200V SiC MOSFET and JFET. 1200V SiC diodes and 650V MOSFETs have been fabricated by respectively Fraunhofer IISB and ST Microelectronics within the EU funded program Transform. 1200V MPS diodes with voltage drop improvement by 12% and 650V MOSFETs with RDSon improvement by 24% at rated current have been demonstrated. Lowering of the development of SSF is demonstrated after UV illumination, opening the path for robustness to bipolar degradation. Path to reinforce the lifetime of silver sintering die attachment is also foreseen.

ABSTRACT. SiC has been studied intensively in the past decades due to its excellent properties such as high electric breakdown field, high thermal conductivity, and large saturation electron drift velocity. These properties lead to much better device performance than silicon for high-voltage power applications and high-temperature operations [1,2]. Up to now, all SiC power devices rely on single-crystal 4H-SiC substrates. Progress has been made by SiC suppliers to lower the crystal defectivity, but the dopant concentration is physically limited to a certain level leading, for single-crystal 4H-SiC substrates, to an electrical resistivity typically of 20mOhm.cm. Among the different doping elements, nitrogen is the main donor impurity in all the polytypes of SiC [3]. One challenge to improve SiC power device performance is to obtain a higher doped substrate which can give lower electrical resistivity. Starting from basic research studies [4], recently has been shown the ability of SiC engineered substrate (SmartSiC™) to be highly doped (with a polySiC handle substrate doping in the order of 1020 at/cm2) [5], which suggests the use of this material as a SiC engineered substrate for higher-performing SiC power device by lowering the electrical resistivity. In this paper, a study on the resistivity and mobility properties of SiC engineered substrates enabling an increase of the current density at the device level is shown. Compared to standard single-crystal SiC substrate, the SiC engineered substrate has almost one order of magnitude lower electrical resistivity. We have fabricated 650V JBS SiC diodes using both single-crystal 4H-SiC (STD) and SiC engineered substrates. Forward electrical characterization has been performed to compare the substrate electrical resistance of the two substrates. Forward characterizations were performed (Figs. 1a and b). The experimental results were fitted by simulations considering a value of resistivity 6 times lower for the case of the p-SiC (inserts Figs. 1a and b). To design the optimum device structures using SiC engineered substrate, it is necessary to know the electric characteristics in a wide temperature range of temperatures. Forward electrical characterization has been performed in the range 25-175°C. In Fig. 2 the delta resistivity between SiC diode with STD and SiC engineered substrate is shown. PolySiC material resistance increases more slowly than the STD one, with temperature. Indeed from 25° up to 175°C delta resistance increases by 3 mΩ.mm2. To better understand the nature of this temperature behavior we have simulated the experimental results with the electron mobility Arora Model [5], determining the parameters required to carry out the device simulations to be used for the SiC engineered substrate) (for STD substrate the one from [5] as been considered). The results of fitting optimization of the experimental results in Fig. 2, is shown. Using the Arora model for STD and the one modified for the SiC engineered substrate we have calculated the mobility for both materials. Fig. 3 shows that STD substrate has higher mobility than SiC engineered substrate one of 17 times at 25°C. By increasing the temperature, the ratio between the STD and SiC engineered substrate mobility increases up to 40 times. To explain the lower resistance of SiC engineered substrate (Fig. 2) with its lower mobility (Fig. 3) we need to take into account the doping of SiC engineered substrate, which is higher by two orders of magnitude compared to the one of STD substrate. Those results show that the electrical conductivity of SiC substrates depends on different factors such as mobility and doping level. The possibility of high-doped SiC, such as in SiC engineered substrate, is of high interest not only to better understand the electrical conductivity mechanisms in polySiC material but also to open the way for further optimization of the power device using SiC engineered substrate.

[1] K. Shenai, R. S. Scott, B. J. Baliga, IEEE Trans. Electron Devices 36, 1811 (1989). [2] T. P. Chow, R. Tyagi, IEEE Trans. Electron Devices 41, 1481 (1994). [3] H. Woodbury, G. W. Ludwig, Phys. Rev. 124, 1083 (1961). [4] J.Y. W. Seto, J. Appl. Phys., 48, 12 (1975). [5] E. Guiot, G. Picun, F. Allibert, W. Schwarzenbach, A. Drouin, JM. Bethoux, S. Rouchier, J.Leib, T. Becker, T. Erlbacher, PCIM Europe (2022). [6] Sudarshan Khrishnamoothy, Simulation of Wide Band-Gap Devices SiC and GaN, Mountain View, California: Synopsys, Inc. (2008).

ABSTRACT. Wide bandgap semiconductors like SiC and GaN are driving advancements in the power electronics industry by surpassing Si in power capability and maximum operating temperature. Owing to its superior properties such as thermal conductivity, SiC is preferred for many high-power applications. Despite the recent progress in SiC technology, providing both high-quality and cost-effective substrates is still a challenge. [1] Engineered substrates are a promising technology route to fulfill the requirements for high-quality and cost-efficient substrates for power devices. SmartcutTM [2], controlled spalling [3], and photoelectrochemical etching [4, 5] are key techniques for fabricating engineered substrates that strongly rely on reliable bonding techniques. The performance and the production yield of these structures depend significantly on the bonding quality of these unconventional hetero-structures emphasizing the importance of robust, low-cost bonding technologies [6]. Compared to conventional bonding methods such as fusion bonding, the intermediate adhesive bonding technique is cost-effective and user-friendly, offering advantages such as even load distribution, tolerance to surface roughness, effective surface sealing, and resilience against stress and vibrations [7]. For high-temperature stable bonding, the polymer class of vinyl group containing polycarbosilanes (PCS) is of interest as it is a one-component liquid precursor that yields high-purity ceramic SiC, with 72-78% amorphous SiC at 850-1200 °C and nanocrystalline β-SiC at 1250-1700 °C [8], thus offering the possibility to realize an electrically conductive bonding interface. In this work, PCS, also known commercially as SMP-10 (Starfire Systems Inc.), is mixed with m-xylene and AIBN (Azobisisobutyronitrile), a photoinitiator, and then spin-coated onto a monocrystalline 4H-SiC substrate (3000 rpm, 40 s). For demonstration purposes, another monocrystalline 4H-SiC substrate is placed on top, and the assembly is pre-bonded with an EVG bonder where a constant force of 350 N is applied. The sample is heated at 400 °C for 1 hour to facilitate bonding. Finally, the structure is annealed at 1550 °C at 20 mbar back chamber pressure and with Ar atmosphere in a custom-built high-temperature furnace from HTM Reetz, resulting in a bonded sample. During annealing up to 300 °C, the polymer precursors crosslink by creating 3D polymeric networks. Post-crosslinking above 300 °C converts the material to amorphous ceramic. Fig. (1) illustrates the effusion measurements where the spin-coated sample is heated to a peak temperature of 1000 °C over 10 min. We observe ionized gas molecules H+ (amu 1) and CH4+ (amu 16) which can be associated with the rearrangements, condensation, and radical reactions that form new bonds and gaseous reaction products like CH4, H2, CO, and CO2 [9]. We have minimal presence of H2O (amu 18), CO (amu 28), and CO2 (amu 44) as the measurements were made under high vacuum conditions. The measurements show that the outgassing from the adhesive bonding layer occurs predominantly up to an annealing temperature of 900 °C. In Fig. 2, the cross-sectional SEM image shows the bonded 4H-SiC substrates. The cross-section of the bonded sample reveals a uniform bonded closed layer with no visible defects, demonstrating PCS as a bonding interface for SiC at high temperatures. Further investigations will involve the realization of doped SiC bonding layers, and XRD to study the crystallinity of the obtained interlayers as well as vertical I-V measurements.

[1] G. Iannaccone et al., IEEE Access 9, 2021. [2] S. Rouchier et al., Materials Science Forum 1062, p.131-135, 2022. [3] W. S et al., presented at ICSCRM 2023, 2023. [4] M. Leitgeb et al., patent of US20240128080A1. [5] M. Leitgeb et al., The Electrochemical Society, vol. 164, no. 12, p. E337, 2017. [6] B. Kallingeret al., Solid State Phenomena 342, p.91-98, 2023. [7] F. Campbell, Manufacturing Processes for Advanced Composites, 2004. [8] [Online]. Available: https://www.starfiresystems.com/wp-content/uploads/2018/03/SMP-10.pdf. [9] B. Gilvan et al., J. Mater. Chem. A 7,p. 1936-1963, 2019. [10] S. K. Ionescu et al., Journal of the European Ceramic Society 34 issue 15, p.3571-3578, 2014. [11] G. Soraru et al., J Mater Sci 25,p. 3886-3893, 1990.

ABSTRACT. The fast growth of the silicon carbide (SiC) power device market is relying on a sufficient supply of high quality SiC substrate wafers. A reduction of material usage for substrates is highly desirable to reduce device and material costs and secure a steady supply chain. One strategy among others is to use a very thin 4H-SiC layer bonded onto a mechanical carrier. These so-called engineered substrates are regarded as sufficient for epitaxy and device production. In addition to reduced SiC crystal consumption, the device performance can be improved further thanks to lower conduction and switching losses in the device using ultra high conductivity receiver substrates. SOITEC’s SmartCut™ process [1] uses such a 0.6 µm thin monocrystalline SiC layer, which is transferred to a polycrystalline SiC carrier substrate and bonded utilizing a conductive bonding. This study extends a benchmark performed on early samples [2] and looks more into the feasibility for high volume manufacturing using a full cassette to cassette (C2C) epitaxy line. A larger set of current generation 150 mm SOITEC SmartSiC™ wafers will be compared with industry standard bulk wafers from multiple vendors. A first set of similar comparison data will also be presented for 200 mm SOITEC SmartSiC™ wafers and their monocrystalline industry standard competition. For this comparison between standard substrates and engineered wafers we are looking at doping and thickness uniformity as well as the defect performance and predicted device yield. As seen in Fig 1a and Fig 1b, which show two substrates processed in the same epitaxy run, the performance in the doping uniformity is very good and comparable between monolithic and engineered substrates. With respect to the killer defect density, which is an important factor for final device yield, the 150 mm SOITEC SmartSiC™ substrates of the latest generation perform on par with industry standard reference material (see Fig 2). The advanced capabilities of the AIXTRON G10-SiC epitaxy reactors also allow to measure and compare the wafer curvature during the high temperature step, giving insight into residual strain (see Fig 3). No abnormal bow behavior was found on the engineered substrates, and we were able to process them in a fully automated C2C environment with hot loading. This shows the feasibility of engineered SiC substrates for high volume production in epitaxy for silicon carbide power devices. Further details on layer uniformity, defect density and yield – also on 200 mm substrates - will be reported and discussed.

ABSTRACT. Doping-dependent fixed charges, which are not observed in Si MOSFETs, were found in SiC MOSFETs through the study on the relationship between threshold voltage and body doping. As body-doping density increases, positive fixed charges increase for p-body (n-channel) devices and negative fixed charges increase for n-body (p-channel) devices. It is suggested that the generation of the fixed charges is related to the Fermi level at a final treatment (NO annealing) temperature. These fixed charges cause a threshold voltage lowering from the theoretical value, especially in heavily-doped MOSFETs. Thus, the Fermi level at a final treatment temperature should be considered to precisely control threshold voltage in SiC MOSFETs.

ABSTRACT. Even though the SiC power MOSFET is an established product by now, there is still plenty of room for improving the transistor’s performance. To exploit the full potential of the superior material properties of SiC, namely the low drift zone resistance due to the high breakdown field strength, other series resistance contributions, such as the channel resistance, must be kept as small as possible. Despite the continuous progress in improving the SiO2/4H-SiC interface and therefore the channel mobility, the channel contribution to the overall RDS,on is still not negligible in most of the SiC power MOSFET products [1]. An innovative approach to minimize the channel contribution is to utilize high-k insulators as gate dielectric material. Due to their higher dielectric constant, the induced inversion charge is increased for the same applied voltage, leading to a reduced channel resistance. Furthermore, most of the high-k dielectrics are deposited by using an ALD process, which offers unique possibilities for in-situ interfacial engineering. However, there are still major challenges, which complicate the integration of these dielectrics into commercially available SiC power MOSFETs. One of them is the relatively low thermal stability of the commonly used high-k materials. During typical SiC power MOSFET production, temperatures up to 1000 °C are needed for ohmic contact formation. Moreover, compatibility with poly-Si gate electrode formation must be ensured. According to literature, these processes often lead to crystallization of the high-k layers, hampering their usage as gate dielectric due to inacceptable leakage currents and reliability issues [2]. In this work, we study the influence of the typical high-temperature processes on the electrical characteristics of poly-Si gated, Al2O3-based MOS capacitors. The schematic cross-section as well as the processing sequence of our MOS capacitors is shown in Fig. 1. We have chosen Al2O3 as the main gate dielectric material due to the relatively high thermal stability and large band-offsets to 4H-SiC. We modified the interfacial properties by using gate dielectric stacks, consisting of 5 nm thin SiO2 and AlN interfacial layers, followed by subsequent Al2O3 deposition. Fig. 2 a) shows the IV breakdown measurements, which were conducted in a cross-shape over the 6” wafers. The wafers #1 and #3 show a high uniformity with an average breakdown field strength around 6,3-6,4 MV/cm. Compared to that, wafer #2 with a 5 nm SiO2 interlayer has a much higher spread with premature breakdowns. Possible root causes for the different behavior of wafer #2 will be discussed at the conference. Fig. 2 b) displays quasi-static CV measurements in up- and down-sweep direction for five different devices per wafer. Especially wafer #1 exhibits a rather small hysteresis with a flat-band voltage close to the ideal one. Moreover, measuring the accumulation capacitance allows the extraction of the relative permittivity εr of the Al2O3 dielectric. The relatively high value of 11,3 could be an indication of possible crystallization of the Al2O3 layer. However, crystallization typically leads to deteriorated electrical performance, which is not observable for wafers #1 and #3. TEM analysis is ongoing and will be shown at the conference to elucidate a fundamental view on the atomistic structure of the investigated gate dielectrics. Due to the excellent uniformity of the IV measurements of wafer #1, constant voltage TDDB measurements at three different temperatures were carried out. An exemplary Weibull plot for a measurement temperature of 175 °C is shown in Fig. 3 a), whereas Fig. 3 b) depicts the intrinsic lifetime extrapolation plotted against the dielectric displacement field D. The D-field is used here instead of the E-field to have a fair comparison between Al2O3 and SiO2, as the D-field accounts for different εr values. Even though the Al2O3 measurement values are highly consistent, the intrinsic lifetime extrapolation yields values below the SiO2 counterpart from commercial SiC production [3], however in the range of 10-100 years. Possible root causes as well as improvement strategy will be part of future research.

[1] T. Kimoto, Proceedings of the Japan Academy, Series B 98 (4), 161-189 (2022). [2] R. Lo Nigro et al., Materials 15 (3), 830 (2022). [3] T. Aichinger and M. Schmidt, IEEE International Reliability Physics Symposium (IRPS), 1-6 (2020).

ABSTRACT. 4H-silicon carbide (4H-SiC) metal oxide semiconductor field-effect transistors (MOSFETs) have emerged as viable competitors to their Si insulated-gate bipolar transistor (IGBTs) counterparts, especially in electric vehicle (EV) drivetrains, where these devices typically operate between 600-1200 V [1]. One major challenge that hampers the further uptake of the technology is the increased density of interface traps at the SiO2/SiC interface, which is typically two to three orders of magnitude higher than in Si-based metal-oxide-semiconductor (MOS) systems [2]. Oxide deposition techniques such as atomic layer deposition (ALD) and low-pressure chemical vapour deposition (LPCVD) have already been shown to offer a solution to improve control of the interface and circumvent SiC-specific defects, such as carbon clusters, which are inherent in industry-standard thermal oxidation processes [3]. Post-deposition anneals (PDAs) of ALD SiO2 layers in forming gas (FG) have had a positive impact on both mobility and reliability [3, 4]. In this investigation, we further explore the effect of PDAs on ALD-formed dielectric stacks on 3C-SiC and 4H-SiC MOS-capacitors (MOSCAPs). The dielectric stacks, comprising SiO2, HfO2/SiO2, and Al2O3/SiO2, underwent PDAs across a temperature range from 600°C to 1100°C in either pure N2 or a forming gas (FG) mixture of H2-N2 (5% H2). Figure 1a) shows a schematic of the fabricated 4H-SiC MOSCAP and its corresponding equivalent circuit. Figure 1b) shows a transmission electron microscopy (TEM) image verifies the deposited thickness of stacked dielectrics. C-V and I-V electrical measurements were conducted to analyse interface characteristics such as flat band voltage (VFB), the density of interface traps (Dit), hysteresis (H) and breakdown field (VBD). Dit is extracted from high-low C-V measurements (300 Hz – 1 MHz). Figure 1c) displays representative C-V curves of 4H-SiC MOSCAPs, comparing those that underwent annealing with those that did not. It reveals that the devices without PDA did not achieve complete accumulation. In the full submission, we will report the effect of the PDA on the most promising layers with evidence from secondary-ion mass spectrometry (SIMS), x-ray photoelectron spectroscopy and (XPS) and deep-level transient spectroscopy (DLTS). For an ideal dielectric or dielectric stack, certain characteristics are desired: a high breakdown field a minimal shift in flat band voltage (ΔVFB= φms-VFB, where φms is the difference between metal and semiconductor work function and VFB is the measured flat band voltage) from its ideal value, low Dit, and minimal hysteresis. To evaluate the overall quality of gate dielectrics, a figure of merit (FOM) is proposed, and defined as the ratio of the breakdown field to the product of flatband voltage shift, hysteresis effect, and density of interface states: FOM=V_BD/(∆V_FB*H*D_it). We propose this as a metric to help gauge the effectiveness of gate dielectrics. Figures 2a) and 2c) summarise the individual extracted parameters necessary for calculating the FOM for 3C-SiC and 4H-SiC MOSCAPs. The final calculated FOMs to evaluate the optimum gate dielectric stack and PDA condition for 3C-SiC and 4H-SiC MOSCAPs are shown in Figures 2b) and 2d). In our analysis, we observed that the N2 PDA yields higher figures of merit (FOM) for the 4H-SiC stacks, whereas FG PDA demonstrates higher FOMs, indicating superior interfacial quality, for the 3C-SiC stacks.

[1] X. She, A. Q. Huang, O. Lucia, and B. Ozpineci, ‘Review of Silicon Carbide Power Devices and Their Applications’, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 8193–8205, Oct. 2017, doi: 10.1109/TIE.2017.2652401. [2]P. Fiorenza, F. Giannazzo, and F. Roccaforte, ‘Characterization of SiO2/4H-SiC interfaces in 4H-SiC MOSFETs: A review’, Energies, vol. 12, no. 12. MDPI AG, 2019. doi: 10.3390/en12122310. [3]A. B. Renz et al., ‘Development of high-quality gate oxide on 4H-SiC using atomic layer deposition’, in Materials Science Forum, Trans Tech Publications Ltd, 2020, pp. 547–553. doi: 10.4028/www.scientific.net/MSF.1004.547. [4]A. B. Renz et al., ‘Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications’, Semicond Sci Technol, vol. 36, no. 5, May 2021, doi: 10.1088/1361-6641/abefa1.

ABSTRACT. An oxidation-minimizing process using planar MOSFETs has been reported as a technique for achieving high channel mobility by reducing the interface state density (Dit) of the SiC/SiO2 interface. On the other hand, the application of the oxidation-minimizing process to trench MOSFETs has not been reported, and when it is applied, the ripple effect to the industry is extremely large. In order to effectively apply an oxidation-minimizing process to trench MOSFETs, a novel process using LPCVD was proposed to form an extremely thin Si layer on the trench side walls. As a result, the channel mobility was markedly enhanced on a heavily doped p-body, and the normalized on-resistance (RonA) at 473 K was 4.4 % lower than the reference for 400 A-class (6.5 mm□) trench MOSFETs with a BV of over 810 V.

ABSTRACT. Wide-band-gap (WBG) semiconductors are the materials of choice for future high-power applications as they enable pushing operation limits in terms of switching speeds, operating voltages, currents, or temperatures. An outstanding candidate is silicon carbide (SiC) which has become the WBG semiconductor with the most mature technology. Still, applications of SiC in devices is still largely limited by the challenges associated to the production of high-quality wafers with reduced defect densities arising from micropipes, dislocations, stacking faults or polytypes. To sustain the improvements in efficiency and performance of SiC-based devices, research efforts need to be continued especially on the level of material physics.

We present atomistic calculations of silicon carbide with a particular focus on crystallographic defects in different polytypes of SiC including 3C, 6H, 4H and 2H (Figure 1 left). We address point defects with density functional theory (DFT) including, in particular vacancies and dopants and elucidate their impact on polytype stability. Vacancies are key for understanding non-stoichiometry in crystals and their impact on the relative energetic alignment of polytypes in different growth conditions. Furthermore, N and Al are added as single dopants and also as dopant pairs to explore geometric and energetic modifications in the crystal. We show that N doping leads to a clear stabilization of the 3C polytype while Al doping causes only minor changes in the energetic ordering of polytypes (Figure 1, right). This effect is explained based on the differences in band-gap of the polytypes and the dopant-induced defect states in agreement with an explanation suggested previousely. [1] As a consequence, Al in proximity of N can entirely neutralize the donor and its stabilization effect. We demonstrate that charging of the defects can induce exactly the same trends providing a new view on polytype stability, which may lead to new approaches for adapting growth conditions to influence the occurrence or suppression of polytypes.

To investigate extended defects such as dislocations and micropipes, straightforward application of DFT is not possible due to the related system sizes larger than 1000 atoms. Therefore, we generate machine-learned interatomic potentials based on the atomic cluster expansion, [3] which are trained on a large number of small DFT calculations where cell dimensions and atomistic arrangements are varied over a wide range to sample the potential energy landscape (Figure 2 left). Our ML potential reproduces polytype energetics from DFT in contrast to available interatomic potentials (Figure 2 right). This allows us to treat large atomistic systems at DFT accuracy. We demonstrate the approach by investigating threading screw dislocations (TSD)s, which play a decisive role for the crystal growth process. We provide a fully atomistic view into the dislocation core with its heavily distorted environment arising from the large burgers vectors typical of TSDs in 4H (Figure 3) or 6H. We investigate at which magnitudes of the burgers vector removal of atoms from the dislocation core becomes energetically favorable to form the open core of micropipes and relate our findings to experimental results from the literature. [3] Finally, we discuss how our results can help establishing guidelines for improving crystal growth quality with the physical vapor transport method.

[1] V. Heine, C. Cheng, and R. J. Needs, J. Am. Ceram. Soc. 74, 2630, (1991). [2] R. Drautz, Phys. Rev. B 99 14104, (2019). [3] S. I. Maximenko, P. Pirouz, S. S. Tangali, Mater. Sci. Forum 527, 439, (2006).

ABSTRACT. In this study, we focus on the trap center generation by hydrogen implantation to investigate the reason for suppressing the forward bias degradation in 4H-SiC bonded substrates. In the manufacture of bonded substrates, hydrogen implantation is used for layer splitting. The carrier lifetime measured by the μ-PCD method was significantly shortened by hydrogen implantation. Annealing at 1700 °C reduces the implanted hydrogen below the detection limit of SIMS analysis, but the carrier lifetime remains short. DLTS measurements showed that a specific trap center was significantly increased by hydrogen implantation. After annealing at 1700 °C, the specific trap center disappears, but the Z1/2 center increases by more than two orders of magnitude compared to before hydrogen implantation. The trap centers including the Z1/2 center are expected to suppress the forward bias degradation.

ABSTRACT. This paper focused on how to convert survived BPDs (basal plane dislocation) to TEDs (threading edge dislocation) in epi-layer after epitaxial growth process. While BPD is not converted to TED by mere heat treatment, the EVC (Expansion-Visualization-Contraction) treatment may convert BPD to TED because the Si core dislocation moves to the C core dislocation to form BPD as in the case that the expanded SSF (Shockley-type stacking faults) contracts during heat treatment.

ABSTRACT. Chemo-mechanical polishing (CMP) is widely applied to produce the surface with outstanding global planarization before the epitaxial growth of the 4H-SiC thin film on the wafer. However, it has been reported that scratch-like surface defects consisting of rows of step bunching locally sometimes appear on the wafer surfaces after epitaxial growth on these surfaces even though there are no visible surface defects on the wafers after the CMP process. It has been elucidated that the rows of step bunching were caused by crystal defects which are introduced newly in the subsurface regions of the wafers during the CMP and remain after the CMP. The polishing damage consisting of crystal defects sometimes remains in subsurface regions of wafers after CMP even in recent years. They are barely detected by conventional optical microscopy. Mirror projection electron microscope (MPJ) can visualize slight potential change due to the surface morphology of the epitaxial layer and local charging of the crystal defects beneath the surface. Therefore, MPJ is one of the most powerful tools to inspect the distribution of such polishing damage, which cannot be detected using optical microscopy, over the whole wafer. However, the relationship between contrast formation in the MPJ images and the distribution of crystal defects in polishing damage is not yet thoroughly understood. The present study aimed to analyze the detailed structure of the polishing damage and reveal the relationship between the MPJ image contrasts and the defect structures. First of all, polishing damage locally remaining beneath the surface regions of the 4H-SiC wafer after CMP was non-destructively inspected by using MPJ. From MPJ images of polishing damage A, B, C, D and E, the inside and outside of the line contrasts of every polishing damage in the MPJ images were dark and bright contrast, respectively. The width and intensity of the line contrasts were different for each polishing damage. The widths and the contrasts of polishing damage A, B, D and C, E were wider and higher than those of polishing damage C and E. The widths of A, B, D and C, E were from 3.0 to 3.5 um and from 2.2 to 2.5 um, respectively. The plan-view TEM images of polishing damage A, B, C, D and E revealed that high-density dislocation loops were generated along local plishing damage line. The spreads of the crystal defects in polishing damage A, B, D and C, E were from 130 to 210 nm and from 50 to 70 nm, respectively. The result shows that there is correlation between the spreads of the crystal defects and the widths of the line contrasts in MPJ image. From, cross-sectional STEM images of polishing damage A, B and C, there was no significant difference between surface roughness of each plishing damage. In conclude, It is conceivable that MPJ detects the distribution of crystal defects in polishing damage more preferentially than the surface roughness.

ABSTRACT. This study investigates the role of ion implantation in suppressing stacking fault (SF) expansion in SiC epitaxial layers, a significant issue in the adoption of high-voltage SiC bipolar devices. The research focuses on the effects of helium and proton implantation on basal plane dislocations (BPDs). Using helium due to its low reactivity and tendency to diffuse out during annealing allows for an assessment of point defects introduced by ion implantation alone. Commercial N-type 4H-SiC epitaxial substrates were implanted with helium or proton ions, followed by annealing and analyzed using grazing incidence synchrotron reflection X-ray topography.

Results showed that while SF expansion was completely suppressed in some cases, a slight expansion was still observed in others, suggesting that the density of point defects plays a critical role. The ion implantation simulation indicated that the defect density from proton implantation was significantly higher than from helium. This implies that the suppression of SF expansion and dislocation movement is largely due to the point defects rather than the type of ion used. High-temperature observations of heavily nitrogen-doped SiC crystals confirmed that the interaction between dislocations and point defects can inhibit bipolar degradation, pointing to a similar mechanism in ion-implanted layers.

ABSTRACT. NASA Glenn Research Center has previously reported the world’s first and only semiconductor integrated circuits (ICs) to demonstrate stable electrical operation for over a year at 500 °C [1]. However, these initial prototype 4H-SiC Junction Field Effect Transistor-Resistor (JFET-R) chips were of limited circuit complexity (< 200 transistors per chip) and require detrimentally higher voltage, current, and power compared to functionally equivalent conventional-temperature silicon chips. Further upscaling of circuit complexity while reducing power consumption is clearly crucial towards realizing impactful infusion of SiC JFET-R ICs into extreme environment applications. This ICSCRM 2024 submission compares design layouts and circuit simulations of the next two planned SiC JFET-R IC prototype fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. These designs are based upon foundational mask layout and first-order SPICE model approximations calculated and posted online for these respective technologies [2]. Even though both generations employ the same physical JFET gate length (3 µm) and chip size (5 mm x 5 mm), SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are: (1) IC Gen. 13 n-channel epilayers are both thinner (Fig. 1) and completely uniform across each wafer, and (2) the switch to stepper-based photolithography for IC Gen. 13 enables smaller layouts to be implemented for functionally identical circuit blocks (Fig. 2). Fig. 3 exemplifies the calculated disparity in 500 °C JFET drain current characteristics that arise primarily from the difference in n-channel layer thickness. As seen in Table I, the resulting lower JFET threshold voltage (VT0) in enables power-saving ≥ 2-fold reductions in IC power supply and logic signal voltages for fundamental IC Gen. 13 logic circuits. Table II quantitatively compares application-relevant circuit metrics obtained for the most complex circuits that were designed and SPICE-simulated for prototype implementation in both IC Gen. 12 and IC Gen. 13. As seen in the right column, substantial ≥ 2X improvements in both chip functionality (e.g., memory capacity) and chip power are simultaneously realized for IC Gen. 13 designs over IC Gen. 12. In contrast to muti-chip circuit boards required to realize microprocessor and Venus lander control circuit functionalities in IC Gen. 12 technology, IC Gen. 13 enables highly advantageous monolithic single-chip circuit realization. Such “system on a chip” implementation impactfully improves system power consumption, packaging reliability, and physical compactness. So long as other factors (such as IC robustness) are not compromised, the superior capabilities of IC Gen. 13 can be expected to pave the technical path for further maturation, manufacturing, and beneficial application infusions of 500 °C durable SiC JFET ICs.

Acknowledgements: This work was conducted by The NASA Glenn Research Center in Cleveland, OH USA with funding from the NASA Science Mission Directorate under the High Operating Temperature Technology (HOTTech) and Long-Lived In-Situ Solar System Explorer (LLISSE) projects and the NASA Aeronautics Research Mission Directorate under the Transformational Tools and Technologies (TTT) project.

[1] P. Neudeck et al., Proc. 2018 IMAPS Int. High Temperature Electronics Conf. (HiTEC 2018), https://ntrs.nasa.gov/citations/20180003391 . [2] See IC Gen. 12 and IC Gen. 13 Technical Design Primers at https://go.nasa.gov/jfetic

ABSTRACT. This work assesses the field effect (FE) mobility and threshold voltage variation of both SiC n- and p-MOSFETs from room temperature (RT) to 400 ̊C and determines their stability under various stress conditions. Following this assessment, the high-temperature performance of thermally grown oxides and deposited oxides are compared, highlighting the superiority of the deposited gate oxide stack. Bias temperature instability (BTI) from RT up to 400 ̊C was conducted under ±25V of DC stress. For n-MOSFETs, the VTH shift was less than 3% even after 400 ̊C of DC stress. However, for p-MOSFETs, there are significant changes in VTH at HT. The results also indicates that the thermal oxides can operate up to 200 ̊C while UT+Thick CVD can operate up to 300 ̊C without significant degradation. Removal of stress and temperature result in complete recovery of n-MOSFETs however p-MOSFETs suffer a permanent shift in VTH. This indicates generation/activation of deep oxide traps near EV. Fig. 3 shows that there is no degradation of mobility for n-MOSFETs while the p-MOSFETs suffer mobility reduction above 300 ̊C after BTI stress. In conclusion, SiC CMOS devices maintain strong performance up to 400 ̊C. However, while n- MOSFETs recover well post-stress, p-MOSFETs show significant threshold voltage shifts and mobility reductions at high temperatures, underscoring the need for improved passivation near valence band. In addition, deposited oxide stacks demonstrate superior reliability compared to thermal oxides.

ABSTRACT. Silicon Carbide (SiC) power devices are of great interest for high power density, high switching frequency, and high voltage applications, including radiation environments such as space missions and particle accelerators. They offer better thermal conductivity and breakdown field than Si and GaN devices, allowing for device designs with larger current ratings, lower on-state resistance, and higher breakdown voltage for a given die size compared to their silicon device counterparts. However, like their silicon counterparts, SiC power devices are also susceptible to single-event effects (SEEs) defined as a perturbation of the normal operation of the component induced by a single ionizing particle. For power MOSFETs, single ions can cause catastrophic failures such as single-event burnout (SEB) and single-event gate rupture (SEGR), or permanent degradation leading to gradual increases in drain and gate currents, known as single-event leakage current (SELC) [1]. SELC usually occurs at lower biases than SEB or SEGR when irradiated under identical conditions. However, even below the SELC threshold, at low drain biases, SiC MOSFETs may exhibit latent damage to the gate oxide, as previously studied in [1−4]. In this case no electrical degradation is observed during the exposure, but the oxide rupture can be induced when applying additional electrical stress after the irradiation. Gate oxide degradation is more critical in SiC MOSFETs than in Si MOSFETs because of the smaller gate oxide thickness and the higher electric field that develops across the gate oxide in SiC MOSFETs. The effect of different parameters on the sensitivity to latent damage such as the gate layout, the total amount of ions, their energy and the VDS is still under debate and will be further explored in this work, being a critical problem for the long-term device reliability for radiation hardness. In this experiment, heavy-ion irradiation was performed with two variants of high voltage MOSFETs, as shown in Fig. 1 at the University of Jyväskylä Radiation Effects Facility (RADEF) with 2059 MeV xenon ions, with a linear energy transfer (LET) of 49.1 MeV/(mg/cm2) (i.e., the energy deposited per unit distance). The low epi-doping MOSFET variant has a breakdown voltage (BVDSS) of 4500 V, whereas the high epi-doping MOSFET variant has a BVDSS of 1800-2300 V. The structural difference between the devices is their different doping of the N- drift layer (the epitaxial layer). These devices were irradiated up to a drain-source bias of 200 V at different total fluences during each run, and both devices suffer latent gate oxide degradation when irradiated with Xe ions. Post-irradiation, the devices were stressed under a gate-source (VGS) bias from -5 V up to 20 V, and the IG-VGS responses were recorded. Table 1 shows the device responses when a constant voltage bias was applied, and the heavy-ion fluence was increased by one order of magnitude in every subsequent irradiation run on the same device. The results suggest that the different epitaxial layer doping and the pre-strike electric fields across the gate oxide and within the device between the two variants plays a negligible role in their latent damage responses. As shown in Figs. 2 and 3, both devices suffer gate oxide breakdown (i.e., reaching current compliance) under similar test conditions. The experimental data suggest that latent gate damage is unlikely to occur when very few ions strike the JFET region of the device, which is an important aspect to understand for space applications (102 fluence in Table 1). At total fluences of 103 and 104 ions/cm2, which is low compared to previous studies [1-4], the probability of a single ion striking the JFET region is high. A likely cause for a single ion causing the latent gate damage could be the electric potential dropping and collapsing across the gate oxide, as shown by the 2-D TCAD simulations, and their corresponding 1-D cutlines shown in Figs. 4 and 5. However, at these low ion fluences, the probability of multiple ions striking in the same local area of the JFET region is low, hence it is unlikely that latent gate damage is due to a cumulative effect.

ABSTRACT. Power devices for space applications require high single-event effect (SEE) tolerance. However, in SiC devices, the tolerance for a specific SEE, namely, the single-event leakage current (SELC). In this study, we fabricated a SiC trench MOSFET with improved gate-source SELC tolerance. From the result of heavy ions irradiation tests, it is proved that our developed device improved gate-source SELC tolerance. Based on the device simulation, the detail of SELC mechanism is also proposed.

ABSTRACT. In this work, nine of the main space power companies in Europe are asked about the future applications and missions they are expecting, and the technical figures they need to achieve in them. By performing individual meetings, and by filling in a form, the companies identified the main applications in which improved semiconductors are needed, and presented the technical requirements the semiconductor devices should have to make a positive impact in each application. This work gathers the answers, classifies, and explains the most mentioned applications, identifying the main drivers and the technical requirements. It is a link between the space power industry and the SiC manufacturers. It brings the attention to the new HP space missions and the specific challenges the space power industry will face, helping the SiC manufacturers to understand the needs this industry will have in the near future. By following this work, and collaborating with the main space agencies, the SiC manufacturers can take advantage of the technology gap and adapt their SiC products to provide an answer to the HP needs the space power industry has, with limited R&D time, effort and cost.

ABSTRACT. Single-Event Burnout (SEB) is a radiation destruction phenomenon of power devices such as Si devices known as a catastrophic failure caused by heavy-ions. SiC power devices also exhibit SEB failure under radiation environments, however, its mechanism remains controversial. In this study, to investigate the mechanism of SEB in trench gate SiC-MOSFETs, we verified the operation of the parasitic transistor, and the effect of the epi/sub-interfacial electric field relaxation. In conclusion, our results demonstrated that electric field relaxation using a buffer layer is effective against SEB in trench gate SiC-MOSFETs.

ABSTRACT. Micro- and nanomechanical resonators are important elements for future quantum technology applications, e.g. for the entanglement of quantum states of color centers via mechanical oscillations. For the fabrication of the required structures, such as cantilevers or disk resonators, high-quality 3D shaping techniques for SiC are key. Due to its chemical inertness, predominantly well-established dry-etching techniques are used.

ABSTRACT. In this paper, we examine the spatial uniformity of the response of 4H-SiC APDs operating in both linear and Geiger-modes by spatial mapping of their photoresponse to 285nm UV illumination. Both high gain (>10⁸) and single-photon counting operation are demonstrated on the same device. The potential origins of the observed spatial non-uniformity are investigated by TCAD simulation and full-band 3D Monte Carlo modeling. Our results link the orientation of spatially non-uniform photoresponse with the crystallographic axes and the anisotropic impact ionization created by the c-axis miscut commonly used to maintain a stable polytype during growth.

ABSTRACT. Spin-based quantum sensing based on NV-centers in diamond has been around for some time and already found its way into commercialization in form of a multitude of companies and startups employing its physical principles in areas ranging from biotech to material analysis [1]. However, there are major obstacles for diamond-based quantum technologies. Besides being a much more expensive material than silicon carbide, it does not fare well within the semiconductor manufacturing ecosystem, as it cannot leverage scalable existing wafer-based processes, that come with high-volume SiC fabrication, already available in power- and high-frequency electronics [2]. Silicon carbide has a wide bandgap and hosts stable crystal defects, that give rise to solid-state spin quantum systems, which do have favorable quantum properties due to low spin-orbit interaction [3]. Even though silicon carbide is a younger quantum technology platform than diamond, recent demonstrations of novel defect systems show quantum properties on par with diamond, making SiC a very promising candidate for high-volume quantum devices [4]. Quantum sensing can be implemented for different sensing parameters such as magnetic and electric fields, temperature, pressure and rotation, each requiring slightly different implementations but fundamentally rely on the same physical principle, which is detecting spin-dependent resonances. Therefore, in order to achieve high sensitivity, one requires a high resonance signal contrast, narrow linewidth and a high number of signal-counts [5]. The latter parameter is especially important, as it affects the integration time, i.e. the amount of time to measure until a good signal-to-noise ratio emerges, which should be as low as possible for sensors in real-world scenarios. As this work focuses on 4H-SiC silicon-vacancy ensemble-based quantum magnetometers at room temperature, one method in order to increase signal-counts is to expand ensemble density. This is at most possible up to a certain point, as higher ensemble densities lead to higher crystal damage, in turn causing severe deterioration of quantum properties as well as sharp decrease in signal contrast. Another strategy is to increase the active volume by keeping the ensemble density constant, which however requires an optical waveguide in order to efficiently excite the color centers and extract their signal. This work therefore shows the progress made on monolithic SiC optical waveguide integration for silicon vacancy ensemble-based quantum devices and gives a roadmap for further scaling.

ABSTRACT. Quantum networks are envisioned to provide secure communication, scale quantum computing systems, and enable distributed quantum sensing. In order to deploy a low cost, scalable quantum network, leveraging large-scale semiconductor manufacturing to build integrated chip-scale devices such as quantum network nodes is much desired. A CMOS-foundry-compatible monolithic material platform capable of hosting key elements such as spin qubits, low-loss photonic waveguides, nonlinear optical elements (i.e. for frequency conversion and entangled photon pair generation), electro-optically tunable components (i.e. for switches and filters), and single-photon detectors, would be an ideal photonic platform. To this end, 4H silicon carbide on insulator (4H-SiCOI) had been proposed for mass production of quantum integrated photonic circuits[1, 2]. However, the integration of more than one of these components (spin qubit, waveguide, entangled photon sources, etc.) onto a single chip remains a challenge. The scaling of SiC spin-photon interfaces requires that < 50 nm of total thickness variation (TTV) must be maintained across the 4”-6” wafer. This TTV allows the design and lithographic fabrication of precision photonic devices such as resonant filters, phase-matched nonlinear elements, efficient grating couplers, and other elements. The conventional grind and polish process for producing SiCOI results in micrometer or greater TTV and low yield of photonic devices. HRL has developed a new method to prepare wafer-scale SiCOI with a path to <50 nm total thickness variation (TTV) using dopant-selective photoelectrochemical (PEC) etching. Using PEC etching, HRL has demonstrated >7x reduction in TTV compared to grind-and-polish alone (Figure 1). SiCOI thin films, created by mechanical grinding and CMP, were then used to fabricate single mode photonic waveguide structures through ebeam lithography and dry etch. Microring resonators with various coupling length were designed and fabricated for waveguide loss measurements. Different grating couplers targeting the relevant wavelengths were used to couple light from a fiber onto the chip, and vice-versa. The spectral response was measured across a large regime spanning near infrared to telecom wavelengths. The propagation loss for waveguides at certain wavelengths was extracted from fits to particular sets of resonances. In Particular, 3.0 dB/cm loss at 1550 nm was demonstrated for a waveguide with 0.75 μm width, well within the single mode regime for this wavelength, making it promising for integrated photonics at telecom wavelengths. In the literature, most SiC divacancy defects have been probed by an out-of-plane objective lens with or without a photonic cavity. Integration of a divacancy defect ensemble into planar waveguides is an important milestone toward chip scale integrated nodes for a quantum network. For our samples fabricated specifically for optically detected magnetic resonance (ODMR), the SiC wafer was implanted with carbon atoms and annealed for divacancy creation before bonding. Single mode waveguides with grating input/output and metal microstrip for RF delivery were designed and fabricated. The device schematic and test setup are shown in Fig.2a. ODMR measurements were carried out by sweeping the frequency of our RF source while simultaneously monitoring the photoluminescence output from the defects in the waveguide. Using a longpass filter and spectrometer grating (both off-chip), the intensity from the zero phonon line (ZPL) of a specific defect orientation was monitored for each ODMR measurement, as indicated in Figures 2c-e. For each ZPL, the applied RF signal modulates the spin population at a particular frequency, which is detected as a change in photolumincescence intensity (constrast). The resonance peaks for these defect orientations well match published results from bulk silicon carbide samples[4, 5]. In conclusion, we successfully demonstrated a SiCOI platform for quantum defects and photonic device integration. The use of integrated waveguides for the collection of photons emitted from defects significantly reduces the background emission from the silicon substrate, which is problematic for measurements through vertical coupling via an objective lens. In the future, we will incorporate superconducting nanowire single photon detectors and on-chip photonic filters on the SiCOI platform, making it a near-complete solution for monolithic quantum network nodes.

ABSTRACT. Over the past decade, the advancements in fabrication techniques and material purity for silicon carbide (SiC) power devices have led to the growing interest in using optically active point defects, also called color centers, within SiC for quantum applications at room temperature. In this work, we fabricated nano-pillar arrays with RIE/ICP plasma etching in 4H-SiC to enhance the light collection efficiency of color centers such as the silicon vacancy and the divacancy carbon-silicon. Varying pillars' diameters and spacings were used and lateral etching of the pillars is observed. Silicon vacancies were generated by ion implantation of helium and hydrogen in n-doped 4H-SiC samples. Photoluminescence (PL) spectra of the un-etched samples confirm the presence of the defects. PL and cathodoluminescence measurements, comparing the signal obtained from the patterned and un-etched samples will be presented at the conference.

ABSTRACT. The Earth’s magnetosphere is a system of multiple, co-located particle populations interacting via plasma waves. Things to understand are driving processes, radiation belt and ring current issues, auroral physics, internal plasma processes, and magnetosphere-ionosphere mapping issues. These plasma-physics processes enable the Earth’s magnetosphere to evolve in response to temporal changes in the solar wind and they underlie the phenomena of space weather, which impacts spacecraft systems, astronauts, radio communications, and ground based electric-power grids[1]. The objective of 3SM is to measure magnetic field strength and to calibrate the Vector Magnetometer (VM) device to maintain absolute accuracy during a mission. The 3SM features make the instrument preferably suited not only for the traditional role of scalar magnetometers as absolute references for the calibration of the on-board vector instruments, but also for extended operational capacities, such as higher frequency scalar measurements (of potential interest for magnetosphere studies for the low frequency part of the spectrum) or autonomous scalar / vector operations. Diamond has been the solid-state platform of choice for quantum device technologies for some time, however, it suffers from difficulties such as scalability, integration, and cost. While the diamond platform is very useful for quantum technologies, further development is needed to make it viable. The material platform of choice for NASA Glenn’s Quantum Sensing And Spin Physics (Q-SASP) is silicon carbide (SiC). This is due to the much higher industry development of the SiC material platform for high-power and high-temperature electronics. It leverages both the decades-long SiC development expertise and infrastructure at NASA Glenn and its growing capabilities in quantum metrology. To make SiC devices usable for quantum technologies such as quantum sources, a much deeper understanding of defects is needed. Q-SASP is developing quantum metrology capabilities to evaluate the energy structure, defect formation energy, band structure augmentation, generation/recombination rates, and limits of dipole-dipole coupling in non-metal implanted SiC devices. This can be achieved by analysis of zero-field splitting, low-field resonance, and singlet-triplet mixing through various forms of Electrically Detectable Magnetic Resonance (EDMR) and Near-Zero Field Magnetic Resonance (NZFMR) spectroscopy. This work will discuss recent system developments, device developments, computational modeling, and spectroscopy results and analysis of defects created by non-metal implantations in SiC devices. The defect formation energies of V_Si,V_C, V_C V_Si, N_C V_Si, N_Si, N_C in 4H-SiC are previously reported values in other research [2]-[3]. The defect formation energies of P_Si and P_C were calculated in GPAW [fig 1A]. The basic underlying mechanism of the zero-field phenomenon is the mixing of singlet and triplet states [4]-[5]. In most spin-dependent transport, two electron spins are involved, and thus one must consider each of their interactions with the field. We investigated the electronic and magnetic properties of 4H-SiC and 6H-SiC. The defect formation energy helps us determine what types of defects we are observing in the SiC EDMR experiment. They have very low formation energy (it is negative). The phosphorus substitution in 4H-SiC is a very stable defect. The band diagrams provide us with vital information about how the electronic properties of SiC (such as band gap) change as we add non-metal defects. The zero-field splitting parameters allow us to study the inflection point in the NZFMR [fig 1B]. We clearly observed zero-field splitting. We also noted that the zero-field splitting remained constant with changing bias. We aspect it zero-field splitting to remain constant while the hyperfine and exchange interaction perturbations shift under the influence of an external magnetic field. This is the essence of quantum magnetometry and self-calibration.

ABSTRACT. Space missions will require high-power (HP) in the close future, several kW, with the unique characteristic of supplying the loads at the space standard voltage. The latching current limiters (LCL) are used for managing the loads in space electrical distribution systems. Si P-MOSFETs are the preferred devices due to their easy control. However, space graded Si P-MOSFETs are limited in terms of conduction resistance and blocking voltage, generating unacceptable losses if used at HP. This work studies a 120 V HP distribution based on a 10 kW LCL, enabled by the better electrical performance of SiC N-MOSFETs. A HP LCL in the range of tens of KW in space is not feasible, if Si P-MOSFET technology is used, because the losses are too high, the number of required parallel devices takes too much area and complicate the design. However, this paper shows a HP LCL for space is feasible if SiC N-MOSFET technology is used.

ABSTRACT. SiC power semiconductors have the characteristics of approximately 3 to 4 times higher thermal conductivity and breakdown voltage and a wide energy band gap, compared to Si, and are attracting attention as a power semiconductor material due to their excellent power efficiency [1]. Several methods for growing SiC single crystals are well known. Usually SiC single crystals have been grown by the PVT (Physical Vapor Transport) method. In PVT process, the powder is heated and sublimated at high temperatures and deposited on a substrate. However, recrystallization of SiC powder prevents the movement of the SiC source toward the SiC seed [2]. This phenomenon occurs when the horizontal and vertical temperature gradients of the powder are not properly achieved. Because of this, the PVT method has the disadvantage of having a low growth rate and consumption of the powder compared to other growth methods [3]. In this study, a modified filling design of source powder in the growth cell was proposed to improve the growth rate and consumption of source powder, as shown in Fig. 1. STR's Virtual Reactor 8.4 simulation tool was used in order to investigate the influence of the powder filling-design on the growth of SiC single crystal. Main observation factors were a temperature distribution throughout inside crucible including powder, SiC source flow, growth rate and consumption of source powder. Both structures were calculated under identical conditions and main parameters applied to the numerical simulation are shown in Table I. The temperature distribution and SiC source flow rate within the growth cells on two different structures were shown in Fig. 1(a)/(b). The high temperature area within the powder in the modified design (Fig. 1(b)) was reduced compared to the area formed in conventional design (Fig. 1(a)), due to the empty space in the center area of the powder source, which could increase the horizontal temperature gradient in the center area. Therefore, the SiC source sublimated from the powder can be easily transferred to the SiC seed through the empty space in the center area. Fig. 1(c) exhibited the vertical SiC source flow velocity and temperature gradient formed from the SiC seed surface to the SiC powder surface. Flow velocity of the modified design for powder-filling was measured to be faster than that of the conventional design. Based on the simulation results of the corresponding structures, an actual growth experiment was conducted under growth conditions similar to the simulation conditions in Table I. Fig. 2 exhibited the thickness of grown ingots with conventional and modified filling designs of powder source. While SiC ingot grown with the conventional design had an averaged thickness of 5.88 mm, SiC ingot obtained in the modified design showed 10.25 mm in averaged thickness. In other words, a higher growth rate in the modified shape was observed even though a small amount of powder was consumed, as can be seen in Fig. 2 (b)/(c). The crystal growth rate was observed to be modulated by simply modifying filling-design of powder source in crucible. The powder consumption was analyzed through CT (computed tomography).

[1] P. J. Wellmann, Semicond. Sci. Technol. 33. 10, 103001 (2018). [2] X. Lin, B. Y. Chen, L. X. Song, E. W. Shi, Z. Z. Chen, J. Cryst. Growth, 312. 9, 1486-1490 (2010). [3] N. Hoshino, I. Kamata, Y. Tokuda, E. Makino, N. Sugiyama, J. Kojima, H. Tsuchida, Appl. Phys. Express 7, 065502 (2014).

ABSTRACT. Silicon carbide is an important material for high voltage applications due to its various exceptional electrical and mechanical properties. To achieve reliable high voltage devices, defect free epitaxy is essential. On the other hand, to achieve epitaxy with low defect counts, it is essential to optimize substrate preparation. During the wafer processing, e.g. grinding, polishing etc., the substrate is damaged by scratches. This damaged surface is planarized by chemical mechanical polishing (CMP) to achieve a smooth scratch-free surface. Even though the surface is very smooth after CMP, (roughness <0.1nm RMS), it is expected that some subsurface damage is still present. Conventionally, hydrogen etching is used prior to the epilayer growth to create atomic steps on the surface. However, etching may not remove adequate material to eliminate subsurface damage due to its low removal rate in conventional epitaxial process. Subsurface damage has been discussed earlier. Efforts have been to mitigate subsurface damage by so called “Dynamic Aging”, where the substrate is treated at a high temperature [3] have been shown to be beneficial for the reduction of basal plane defects (BPDs) and stacking fault (SF) defects in epitaxy. As an alternative to chemo-mechanical polishing, plasma polish dry etch (PPDE) is currently gaining attention [4] with the potential benefit of removal of subsurface damage. In this research, we will explore the effect of plasma polish dry etching (PPDE) on 4H-SiC substrates (4° off cut) and consequent epitaxial growth for defect reduction.

ABSTRACT. 1. Introduction Tantalum carbide (TaC), with its great thermal stability, high purity, and outstanding chemical resistance, has been widely employed as a coating material for graphite furnace components to suppress the release of graphite impurities and to protect the graphite from corrosion in high-temperature chemically aggressive environments [1]. These features make TaC coatings increasingly used by industry to enhance the durability of reactor hardware and reduce the chance of product contamination, both of which bring significant economic benefits. Typical TaC applications include crucible assemblies in SiC physical vapor transport (PVT) processes in excess of 2200°C, and susceptors, carriers, and ceilings in SiC and GaN epitaxial chemical vapor deposition (CVD) processes at 1100 to 1600°C. For these processes, thermal profile is a key factor that governs yield and product quality. Recently, we measured the performance of a TaC-coated graphite heating device at temperatures up to 2650°C. Heating experiments, coating characterization, and thermal simulations were combined to investigate the TaC coating impact on heating devices, such as resistive heaters and inductive susceptors. The TaC coating was found to improve temperature uniformity while reducing power consumption by half.

2. Resistivity and TaC coating stability Test specimens made of 2 x 2 x 152 mm graphite bars and coated with 27, 46, or 55 µm of TaC were heated with high current under high vacuum. Their electrical resistance was measured between 1195 and 2644°C, and reported in Figure 1 along with a depiction of the test setup. It is interesting to find that the resistivity of TaC, extracted from the equivalent circuit and presented in Figure 2, decreases with increasing temperature. This behavior is consistent with the results reported by Savvatimskiy et al. [2]. High-temperature TaC emissivity, measured previously by the group in [3], was used with resistivity measured in the present work to develop thermal simulations.

3. Simulation A spiral heater was modeled in ANSYS with and without a coating at various target surface temperatures, Table 1. Temperature distributions on the simulated bare and coated heater at 1200oC are shown in Figure 3, alongside an IR image of the TaC-coated heater and show good agreement. As shown in Table 1, having a TaC coating reduces the power required to reach a target temperature by about 50%, and improves the temperature uniformity across the heater by around 15%. The greater power efficiency is attributed to the lower emissivity of TaC since much less power is lost in form of radiation. The more uniform thermal profile is attributed to the lower resistivity of TaC, which attracts more current onto the coating and minimizes the variation in current density due to heater geometry, Figure 3.

4. Conclusion An investigation on the impact of TaC coating on the resistivity of graphite heater at high temperature (1200 ~ 2600°C) was performed. Simulation of heaters using measured resistivity indicates that TaC coatings can significantly improve the power efficiency and temperature uniformity. The relationship between TaC resistivity and temperature was also validated via experiments. This study provides the necessary material properties to guide the design of TaC heating device to achieve desired thermal profiles.

References [1] Lee, Doe Hyung, et al. “Effect of TaC-coated crucible on SiC single crystal growth.” Materials Science Forum. Vol. 778. Trans Tech Publications Ltd, 2014. [2] Savvatimskiy, A. I., et al. “Thermophysical properties of tantalum carbide (TaC) within 2000–5500 K temperature range.” Ceramics International 48.14 (2022): 19655-19661. [3] Fan, Wei, et al. “Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition.” Materials Science Forum, vol. 1062, Trans Tech Publications, Ltd., 31 May 2022, pp. 136–139. Crossref, doi:10.4028/p-ppa587.

ABSTRACT. Silicon carbide (SiC) semiconductor technology can help maximize the efficiency of power systems and simultaneously reduce their size, weight, and cost as compared to legacy silicon-based systems. Demand and market size projections for SiC-based systems continue to grow significantly. Recent forecasts predict that the SiC device market will grow beyond $8.6 billion by 2027 from $1.6 billion in 2022 [1]. However, high defect density and high prices of SiC substrates are still delaying the expansion of the SiC device market. Silicon carbide growers have therefore continued to strive for larger diameters and higher quality, and have recently focused efforts on 200mm bulk crystals. Expansion of SiC crystals grown by physical vapor transport (PVT) is challenged by deviations in temperature and source vapor distribution relative to standard 150 mm processes. As the crystal diameter increases, the temperature difference between the outside and center of the crucible increases, making growth more complicated due to the horizontal temperature gradient of the crystal and the temperature difference inside the source. To address this, many experiments were conducted to ensure sufficient SiC vapor supply to the seed, and a flatter growth interface. Initial development focused on changing the top insulation conditions to control the shape of the crystal, and subsequently tested sublimation conditions to ensure the proper growth rate. As the size of the growth cell increases, so does the contact area of the source with the interior of the cell, and as the amount of vapor increases, it becomes more difficult to control the early stages of growth. To solve this, finding the right distance between seed and source optimizing the internal dimensions of the cell became the focus of development efforts. However, while lowering the temperature reduced sublimation, which was beneficial for polytype control, the growth rate was very low due to recrystallization arising from temperature variations inside the source. Towards the end of the growth, there was therefore less vapor supply, causing the crystal surface to etch. To address this problem, the source configuration was studied extensively to optimize its weight, height, and positioning, and to find the temperature zone that forms 4H-SiC. At the end of 2022, about 30% of crystals were observed to have etched, while seeds were etched during early growth stages due to the fast initial sublimation rate. The conversion to lower temperatures to address this resulted in 40% of the crystals being smaller than the expected length. After finding the optimal amount of source and temperature range, this failure rate improved significantly to less than 3% in both cases. These studies and more have resulted in yield improvements of more than 30% compared to 2022. The above development work also reduced in-grown stresses, as evidenced by improved wafer shape. Bow and warp, which were at -50 and 80 ㎛, have been reduced to -10 and 30 ㎛, respectively for 500 μm thick wafers. We are also working on a 350 ㎛ thick wafer process and have seen initial test results.

ABSTRACT. Optimizing the physical vapor transport (PVT) growth of high-quality, single-crystal silicon carbide (SiC) depends in large part on the consumable materials utilized within the hot zone. Due to the extreme temperatures used during growth, there are a limited number of construction materials that can be used in the crystal growth hot zone. Typically, these are graphitic materials. Various graphitic materials are used such as the isographite crucible that also acts as the susceptor for reactors heated via induction, graphite felt for insulation, and porous graphites used within the reactor to control growth rate and crystal quality. The system's thermodynamics require carbon availability in the system, which can result in the consumption of the carbon components during growth. The porous graphite is positioned between the source powder and the seed crystal and provides a carbon source to enable the appropriate stoichiometric balance. Incorporating porous graphites enables precise tuning of the carbon vapor species and Si/C vapor phase ratio inside the crucible. This facilitates optimal growth conditions that minimize structural defects such as micropipes while promoting the formation of the desired 4H-SiC polytype [1]. Furthermore, the increased surface kinetics from the graphite sources enhanced SiC growth rates by over 30%.

The microstructure of porous graphite is shown in the polarized light micrograph given in Figure 1. As can be seen by the optical texture domains, the material passed through an extended mesophase during development. These materials are required to be of high purity to avoid crossover contamination of the crystal. The graphites are subjected to high-temperature advanced purifications that reduce impurities to ppb levels. The properties of porous graphite impact crystal growth rates and quality. Incorporating porous graphite in the reactor enables higher growth rates, better crystal quality, and an improved radial temperature gradient as compared with PVT reactors run without the use of porous graphite [1]. The properties of the porous graphite have a direct impact on these parameters. However, the relationship between porous graphite properties and growth parameters is not yet well understood. In this study, the permeability of the porous graphite was investigated in relation to crystal growth rate. An experimental 2-inch PVT growth furnace was used to grow crystals with porous graphite of various permeabilities. The growth rate versus porous graphite permeability is shown in Figure 2. The experimental values are compared against predictive results from computer modeling with several designs in Figure 3. Results showed an increased growth rate with the use of porous graphite in different designs and are in good agreement. It was found that the growth rate increased with the increased permeability of the porous graphite. It is anticipated at some permeability the growth rate will flatten and future work is focused on identifying optimal properties for porous graphite that ensure high growth rates and exceptional crystal quality.

[1] H.J. Lee, H.T. Lee, H.W. Shin, M.S. Park, Y.S. Jang, W.J. Lee, I.G. Yeo, T.H. Eun, J.Y. Kim, M.C. Chun, S.H. Lee, J.G. Kim, Effect of porous graphite for high-quality SiC crystal growth by PVT method, in: Materials Science Forum, Trans Tech Publications Ltd, 2015: pp. 43–46. https://doi.org/10.4028/www.scientific.net/MSF.821-823.43.

Fig-1. Polarized light micrograph of a porous graphite used in single crystal SiC growth.

Fig-2. Crystal growth rate as a function of the permeability of porous graphite.

Fig-3. Experimental and simulated growth rates (dotted line is the reference of equality).

ABSTRACT. A thermal process that would enable mechanically as-sliced SiC wafers to reach the CMP-equivalent quality and to grow epitaxial layers without device-killer defects could revolutionize SiC device fabrication. We developed a planarization process using Dynamic AGE-ing® (DA), which reduces the roughness Ra of mechanically as-sliced wafers from 46.2 nm to 0.7 nm without any material loss [1]. DA is a thermal sublimation etching and growth process driven by a temperature gradient on the Si- and C-face of a single-crystalline SiC within a quasi-closed polycrystalline SiC container [2]. DA has two stable modes, SiC-Si and SiC-C phase equilibrium environment (SiC-Si/SiC-C PE), which can be controlled by the Si supply component. Due to their stability, the surface roughness can be easily controlled by the DA process. To demonstrate the effectiveness of the DA process as an alternative machining method, it is essential to verify whether device-killer defects caused by surface roughness or residual sub-surface damage (SSD) occur during epitaxial growth. Rough wafer surfaces prior to epitaxial growth weaken the [0001] component of the image force that drives the conversion of basal plane dislocations (BPD), which cause bipolar degradation, into harmless threading dislocations (TED) [3, 4]. Additionally, epitaxial growth on the wafer that has residual SSD from mechanical slicing can lead to the formation of in-grown stacking fault (IGSF) [5], which subsequently decreases the breakdown voltage of SiC devices [6]. Therefore, this study aims to evaluate the surface quality of mechanically as-sliced 4H-SiC wafer planarized by the DA process. To achieve this purpose, we investigated the densities of BPD and IGSF introduced into the epitaxial growth layer formed on that wafer using the DA process. We used a 3-inch 4H-SiC wafer that was 4º off-cut toward [11-20] direction with a thickness of 959 µm, sliced by a multi-wire saw with loose abrasive. The wafer was purchased in 2012 and had a basal plane dislocation (BPD) density of approximately 5000 cm⁻². Fig. 1 (a) shows the mapping image of the wafer obtained by the laser light scattering method, which reveals linear patterns in the [11-20] direction formed by mechanical slicing. Fig. 1 (b) is the SEM image of the Si-face on the wafer, revealing the rough surface. Fig. 1 (c) shows the cross-sectional profile, and the Ra was 75.3 nm (10×10 µm2) measured by AFM. Three DA processes were performed to planarize the as-sliced wafer. First, DA annealing was carried out at high-temperature (≥2000 ℃) and high-pressure (≥1 kPa). Then, DA etching under SiC-C PE was performed on the Si-face of the wafer at 1800 ℃ and 10-5 Pa. Subsequently, DA etching under SiC-Si PE was performed at the same conditions. To grow the BPD- and IGSF-free epitaxial layer, DA-growth under SiC-C PE at 1800 ℃ and 10-5 Pa was performed on the Si-face of the as-sliced wafer planarized by DA processes. We used UV-PL imaging (light source: Hg-Xe lamp, excitation wavelength: 313 nm bandpass filter, and receiving filter: 510-610 nm bandpass filter) and molten KOH-etching (500 ℃ for 6 minutes) to measure BPD and IGSF densities. An electronic caliper was used to measure thickness. PL images of the same area of the as-sliced wafer before and after DA-growth are shown in Figs. 1 (d) and (e). BPDs observed on the wafer before DA-growth are no longer detected after the process. Figs. 2 (a) and (b) are the BPD and IGSF distribution maps in the DA-growth layer, respectively. It is noted that the 5 mm from the edge of the wafer is excluded from this measurement. The BPD and IGSF densities of the epitaxial layer are 0.09 cm-2 and 1.37 cm-2, respectively. After the DA process, the thickness of the wafer is 981 µm. No material loss occurs during the DA process, rather the thickness increases by approximately 20 µm compared to the as-sliced wafer before the process. DA process enables as-sliced wafers to be planarized without material loss and to produce epitaxial growth layers with sufficiently low BPD density. However, the IGSF density must be further reduced.

ABSTRACT. With several government initiatives promoting renewable energy and electric vehicles, the demand for energy-efficient power electronics is rapidly growing. Driven by the increasing use of high-power density devices in automobiles, industrial drives, power supplies and renewable energy systems, innovation and advancements in Silicon Carbide (SiC) technology is further accelerated towards commercialization and improving cost efficiency. Nevertheless, reliability in electronic systems is the key to success in this emerging market.

An important challenge in this new supply chain is to develop and manufacture reliable SiC substrate materials in large volumes. Understanding the complexity of growing high-quality silicon carbide (SiC) crystals, this paper introduces the advancements in material testing, characterization and imaging in order to increase yield and production output.

With different crystal growing methods introduced by the SiC material manufacturers, testing and qualifying the bulk materials at an early stage helps in identifying the effects and defects before they become critical to wafer and, eventually, the device performance. This includes resistivity measurement, homogeneity analysis, facet and defect detection in ingots, boules and pucks. The emergence of undesired cracks, microcracks, SSD, micropipes, carrot, triangle and other anomalies at different stages of processing increase the defect density on substrates, eventually making them unreliable for device manufacturing.

This paper presents the state-of-the-art non-contact and non-destructive electrical characterization methods and shares insights of the advancements in eddy current impedance imaging techniques that provides high-resolution resistivity mapping and defect detection on flat and curved SiC materials. It finally addresses run to run control strategies to optimize growth processes.

ABSTRACT. High-resistive SiC substrate is the most attractive material for fabrication of GaN-based high frequency devices because of its excellent electrical properties and thermal conductivity. High resistive electrical properties of SiC crystals can be obtained by the formation of deep level states in the band-gap with vanadium doping (V-doped semi-insulating SiC: VDSI-SiC) or controlled intrinsic defects and minimization of residual impurities (high purity semi-insulating SiC: HPSI-SiC) [1]. In the former case, vanadium compensates for the donor and acceptor levels to hold the Fermi level position close to the middle of the band gap. However, there is a problem of back gate effect and poor conductivity at temperatures above 1,000℃, which limits its applicability [2]. When using high-purity SiC powder, intrinsic point defects such as carbon vacancy or carbon-silicon vacancy form a deep level that exhibits semi-insulation properties. The mechanism by which HPSI-SiC exhibits semi- insulation properties is known to compensate for the shallow level and form a deep level when the intrinsic point defect concentration is above the nitrogen concentration. These semi-insulating properties require a follow-up process because each application currently in use has different resistance properties.

In this study, the resistance characteristics of semi-insulating SiC single crystals grown using the physical vapor transport (PVT) method were investigated, considering the purity level of SiC source powders used in PVT growth and the cooling procedure after crystal growth. Two β-SiC powders with different purities were employed, and the cooling rate after growth was adjusted to achieve various resistance values. 4-inch HPSI-SiC ingots were grown using the PVT method, utilizing SiC powders with low nitrogen concentration and relatively high nitrogen concentration. These ingots were then subjected to different cooling procedures to modify the cooling rate. Transmission/absorption spectra and crystal quality of the grown crystals were analyzed through UV/VIs/NIR spectroscopy and X-ray rocking curve analysis, respectively. Additionally, electrical properties were investigated through non-contact resistivity analysis to identify the dominant factors influencing resistivity properties

ABSTRACT. The constantly growing silicon carbide (SiC) power device market for the automotive industry requires the production of high numbers of cost-optimized 1200 V SiC MOSFET and SBD devices. One major contributor to an overall high yield device processing is the SiC epitaxial growth step defining thickness/doping uniformity and defectivity of the layer stack. With our latest hardware and processes advances for the AIXTRON G10-SiC system first introduced on the ICSCRM 2023 doping uniformities below 1.6% sigma/mean are achieved stable over a whole maintenance cycle for 150 mm and 200 mm SiC substrates (Fig. 1.). Besides the thickness and doping uniformities, defects are the decisive factor for the yield on epitaxial layers. Carrots, triangles, and downfalls, combined as killer-defects in combination with basal plane dislocations (BPDs) reducing the number of usable devices on a wafer. For this purpose, controlling the seeding phase and ramping phase between different epi layers regarding C/Si and doping concentration is necessary. Tests in the AIXTRON SE SiC application lab have shown a clear dependence of the density of epitaxial defects – and with that the device yield – on the surface condition of the substrate just before and during the seeding step in the epitaxial growth. This is influenced by different factors: ▪ The quality of the wafer surface as prepared by chemo-mechanical polishing (CMP) and the following cleaning step. Experiments were able to show the influence of these steps on the layer defectivity. ▪ Changes to the substrate surface due to etching and evaporation just before the seeding of the epitaxial layer. This can be influenced with a careful design of the epitaxial process. ▪ Abrupt parameter changes during the epitaxial growth can also influence the defectivity. Here any ramps and their non-linearities are of special concern. ▪ A well-designed maintenance procedure will also help to keep the defect performance stable and predictable. We will present results of experiments of different factors out of this list and how these impact the number and distribution of epitaxial defects. A first impression on the achievable defect performance is given in Fig. 2.

ABSTRACT. In the domain of efficient energy conversion, the incorporation of wide bandgap silicon carbide (SiC) materials presents a transformative breakthrough. The exceptional properties of SiC enable it to excel in managing extreme conditions of power, voltage, frequency, and temperature [1-2]. Leveraging these unique attributes, energy conversion systems can attain remarkable efficiency and performance levels, spanning diverse applications from renewable energy generation to sustainable transportation. Despite these advantages, SiC-based semiconductors are still relatively new in the power industry, and concerns persist regarding the cost and crystal defects, limiting their widespread applications. The physical vapor transport (PVT) method is key for producing high-quality SiC single crystals. It relies on precise control of pressure and temperature to grow large, single-polytype crystals. Despite its widespread use, challenges remain, notably with temperature distribution affecting the growth rate and crystal quality. Non-uniform temperatures can cause thermal stress and dislocation formation. Since the process operates at extreme temperatures in a closed crucible, direct observation is not possible. Therefore, numerical modeling is essential for understanding and optimizing SiC bulk crystal growth.

In this study, COMSOL multiphysics simulations based on the finite element method are conducted to investigate heat transfer and mass transport. A numerical model combining radiation and conduction in heat transfer was developed to calibrate the thermal conductivity of the fibrous insulation. This calibration process involves varying parameters such as coil power, coil position, and pressure to accurately predict the insulation's thermal conductivity (see Fig. 2). Subsequently, two distinct experimental validations are conducted to validate the numerical model. These experiments entail monitoring temperature at specific positions: one in close proximity to the seed crystal and the other at the bottom of the crucible. The calibrated thermal conductivity derived from the first experiment is then compared with the second experimental setup, demonstrating a robust agreement between the model predictions and observed results. Various radiation models, such as the hemicube and ray shooting model, were tested and compared. The temperature differences between the models were investigated, and the resolution was incrementally increased until convergence was achieved (Fig. 4). To explain the growth process, we employ a physical growth model along with considerations for chemical reactions, vapor species transport, and the kinetics of decomposition and deposition. Drawing from the advancements described in Ref. [3], we evaluate the activities of silicon and carbon using a coupled multi-physics approach that integrates atomistic calculations of non-stoichiometric SiC crystals. This approach offers improved insight into SiC growth and polytypism.

References [1] O.S. Chaudhary et al., Energies, 2023,16(18), p.6689. [2] S. Yoon and I. E. Reimanis. Journal of the Korean Ceramic Society. 57 (2022) 246-270. [3] A. Kanaparin et al., CrystEngComm 18.12 (2016): 2119-2124.

ABSTRACT. Transition metal carbides, and specifically tantalum carbide (TaC), are a class of ultra-high temperature ceramics (UHTCs) used as structural materials or coating materials that exhibit a range of high melting points (3983 °C), high hardness (15–19 GPa), high strength, and chemical resistance [1]. These properties make TaC, in the form of a coating or a composite material, suitable for single-crystal growth (crucibles), high-temperature SiC epitaxy processes for the high-power electronics market (susceptors) [1], but also for many other applications [2-6]. TaC coatings are commonly used due to their thermal stability. Key challenges during the TaC deposition over graphite substrates, however, include, but are not limited to, substrate compatibility as well as low fracture-toughness and stress-induced cracking. The coefficient of thermal expansion (CTE) of TaC is larger than that of commercially and commonly available graphite [5, 6], resulting in inherent stress derived cracking behavior after film formation. Therefore, achieving good adhesion and minimizing interfacial reactions between TaC and graphite, as well as measuring said adherence, can be challenging. For a better understanding of the underlaying mechanisms that govern the delamination characteristics of the coating from the substrate, a series of different characterization methods was used. As the main influencing factors layer thickness and thermal cycling conditions were identified. To quantify the impact of those factors on the quality of the product, mechanical testing as well as different imaging techniques have been applied. For mechanical characterization scratch tests according to ASTM C1624 – 05 [7] were performed. Results show that the critical load for delamination is strongly dependent on the layer thickness. However, in some cases the critical load differed severely although the same coating thickness was analyzed. In depth cross-sectional analysis of the interface showed that this difference could be explained through inferior conditions of the interface. When there is bad adhesion between the coating and the substrate the critical load for delamination is low. Hence proper adhesion is crucial for proper product performance. In summary, depositing TaC coatings involves a delicate balance of process parameters to achieve high-quality, adherent, and uniform films suitable for applications in power electronics and other high-temperature environments. Research continues to explore innovative techniques to overcome these challenges and enhance TaC coating performance.

ABSTRACT. Extended defects in wide-bandgap semiconductors have been widely investigated using techniques providing either spectroscopic or microscopic information, but typically not both. Nano Fourier transform infrared spectroscopy (nano-FTIR) is a nondestructive characterization method combining FTIR with nanoscale spatial resolution (~20-nm), while simultaneously providing topographic information. We previously demonstrated the applicability of nano-spectroscopic techniques for the characterization of IGSF in 4H-SiC and observed an IGSF of 3C stacking order [1]. Here, we apply nano-FTIR to characterize the local infrared behavior of 4H-SiC in the proximity of threading mixed dislocations (TMD) and threading edge dislocations (TED) in the near-field. We observe a pronounced spectral blueshift of the nano-FTIR peak by 22 cm-1 for the TMD, and a lower magnitude shift of 5 cm-1 for the TED. The different magnitudes of this shift correspond to the differences in the corresponding Burger’s vectors of the different dislocation types, and we attribute the source the observed shift to strain induced shifting of the optic phonon frequencies [2, 3]. The region in which this blueshift occurs is found to be highly confined and adjacent to the topographic feature associated with both dislocations. The observed blueshift has the potential to serve as a characteristic shift of these dislocations, analogous to those observed in Raman spectroscopy. This approach enables new understanding at the individual dislocation level of how TSDs and TEDs affect the local crystal structure and infrared response.

ABSTRACT. This paper details the defect inspection and characterization of the 200 mm 4H-SiC (0001) n-type substrate pre- and post-epitaxy. The findings in this paper focus on the characterization of the micropipes (MPs) present in the 200 mm SiC substrate. Following epitaxy, the observations include how the micropipes were propagated from the substrate to the epilayer. This study explores the closing of micropipes during epitaxial growth. As a part of our efforts to better understand the crystal structure and elemental composition of the micropipes in the epilayer, we have conducted SAED and EDX experiments. To the best of our knowledge, it is the first report to demonstrate the region near the micropipe sidewall surface, is remarkably Si-rich (~ 9:1) than in the region towards the bulk (~1:1) after SiC epitaxial growth.

ABSTRACT. There is a strong need in the rapidly growing SiC epi industry for detection of defects and corresponding device yield diagnostics. Optical and UVPL mapping are currently used for inline defect detection however it can be difficult to determine with these techniques which defects will be electrically active and actually detrimental to devices. To address this need Semilab SDI introduced the Quality, Uniformity, and Defect mapping (QUAD) mode in their CnCV (Corona noncontact Capacitance-Voltage) line of tools. In the QUAD technique, the surface voltage is mapped after corona charging the whole wafer surface into deep depletion. Electrically active defects are detected as spots or clustered regions compared with the area surrounding the defect. QUAD demonstrated the electrical activity of defects such as triangular, downfall and carrot type defects and the QUAD detected defects were then compared with UVPL measurements [1]. A considerable fraction of the UVPL defects were found to be not electrically active and thus the QUAD detected electrically active defects provide a powerful compliment to UVPL and optical mapping measurements [2]. To facilitate comparison to final electrical device data, a new QUAD defect analysis is introduced in this work. It converts the map into a die grid of user selected size and creates a die bin map using the in-die values of depletion voltage. In such a parametric analysis, the die will be considered failed if the depletion voltage falls below or the reverse bias leakage current is above a certain defined threshold value. This provides an analogy to die failures in final electrical tests on Schottky diodes when the breakdown voltage (BD) falls below or if leakage is above a defined threshold. In this way the QUAD wafer bin map results can be directly compared to final electrical device test results. The goal of the approach is to use QUAD as an early, after epi growth indication of electrical parameter-based die yield. As an illustration of this new QUAD die bin map analysis, we present two examples of 4H-SiC epi grown in the same reactor run on 150mm substrates from two different vendors giving different device yield. QUAD map results after epi growth are compared to electrical wafer level test data of breakdown voltage and leakage on 1.5mm x 1.5mm 650V Merged PiN Schottky diodes. In Fig 1a and 1b, the original QUAD defect maps give a quick overall indication of defective regions on the Vendor A and B SiC epi samples. A smaller amount of defective regions (low depletion voltage in red) are seen for the Vendor A sample while the Vendor B sample shows a large defective area covering most of the center of the sample. In both cases, there are some discrete defect locations that are detected by the original QUAD analysis based on contrast, however there are also larger clustered defect regions (red) with defects not adequately resolved. The new QUAD die bin maps with a 1.5 x 1.5mm die size of the same surface voltage maps are given in Fig. 2a and 2b together with final device results. The new analysis not only identifies the localized defects as electrically active defective dies but the clustered regions near the wafer edge for both samples are also identified as defective dies. In Fig. 2a and 2b, overlay die bin maps are shown of both QUAD failed defective dies (blue squares) identified by a depletion voltage threshold and wafer level test failed defective dies (open triangles) identified by falling below a BD voltage threshold or if leakage is above a defined threshold. In each case there are regions of strong spatial correlation between the QUAD failed dies and the electrical device failed dies. This indicates the usefulness of the QUAD die bin map analysis in prognostics of device failures early in the process flow. One may also point out the presence of a certain number of device failed dies not observed in QUAD. Such dies may be indicative of process induced (or enhanced) defects not present in the as grown epi. UVPL defect maps were also measured on these samples in the present study in order to address correlation to the QUAD and electrical device failed die bin maps. The Lasertec SICA88 measured UVPL results are not shown here because of limited space and will be discussed in the final paper with an emphasis on progress in reliable device yield prognostics.

[1] V. Pushkarev, et al., Solid State Phenomena 342 (2023): 99-104. [2] M. Wilson, et al., CS Mantech 2021 Proceedings, Orlando, FL.

ABSTRACT. Wide-bandgap semiconductor-based electronics are in constant development, with Silicon Carbide (SiC) leading the way in next generation power devices. In particular within power electronics, SiC carries intrinsic advantages thanks to its higher thermal operation and lower switching losses compared to Silicon-based (Si) electronics [1]. However, the desirable properties of SiC comes with both a higher manufacturing cost and lower device-yield compared to the more conventional and malleable Si, owing to the complicated crystal growth process and subsequent manufacturing of SiC devices. Therefore, the importance of reliable metrology at an early stage of device making is, not only critical to steer material to the appropriate application, but also to close feedback loops ensuring improvement in the subsequent material growth and manufacturing. Herein we follow up on the study conducted and presented in the prior year on the topic of linking epitaxial defectivity with surface voltage and photoluminescence (PL) mapping of epitaxially grown SiC-layers on 25, 200mm 4H-SiC substrates [2]. We combined the industry standard way of classifying topographical variations, reflectance, photoluminescence, and phase shift, by using optical surface detection systems, with surface voltage mapping using non-contact C-V (CnCV) metrology incorporating the “QUAD” (Quality, Uniformity and Defect) method [3]. The QUAD technique uses whole wafer surface voltage mapping after charging the SiC surface to deep depletion. Electrically active defects are detected as cluster regions or spots with respect to the surrounding defect area. Applying a combined QUAD defect detection methodology, we have facilitated comparison to final electrical wafer sorting (EWS) of SiC MOSFETs devices using surface voltage contrast and in-die voltage value using die-bin map. Die-bin map creation converts the surface voltage map into die grids, which in turn can be aligned to match various die-sizes of devices in production. Fig. 1 shows an example of how the QUAD measured reduced depletion voltage sites and PL measured defects from the epitaxial layer are superimposed on MOSFET EWS grids. Utilizing the results from the 25 substrates in the previous study, we get a normal distribution of a range of failures in more than 40 000 unique dies. In this paper we will show how, not only do the reduced depletion voltage sites overlap well with epitaxial defects known to cause device failures, but also how this data complements PL mapping by improving the prediction rate of several EWS failures by up to 50%.

ABSTRACT. Based on the knowledge that ultraviolet (UV) irradiation reproduces defect expansion phenomena equivalent to bipolar degradation, we have proposed a new screening method to prevent the occurrence of bipolar degradation using UV irradiation. Numerical analysis has clarified the proper setting values, which are necessary to execute the screening, of UV irradiation parameters equivalent to current injection conditions for the case of PiN diodes. The two basic UV setting parameters are intensity (irradiance) and time. We have confirmed that the calculated values were in good agreement with our previous experimental results.

ABSTRACT. Dislocations in silicon carbide (SiC) epilayers generally act as nonradiative recombination centers by forming a deep-level state that absorbs energy released by electron–hole recombination [1]. In contrast, stacking faults exhibit radiative recombination, as evidenced by their emission of intense signals during photoluminescence measurements, because stacking faults are strongly localized in a direction orthogonal to the stacking fault plane, which forms a band state near the conduction band [2]. The overall shapes of stacking faults in SiC can therefore be imaged either by using photoluminescence mapping because of the radiative characteristics of SiC [3]. Most Shockley-type stacking faults in 4H-SiC epilayers have been observed to be “typical triangular” in shape under plane-view imaging [4]. On the othr hand, in case of Frank-type stackiong fault, Kamata et al. reported the Frank-type stacking faults with elongated triangular or knife-like [10,19]. There were no reports on the Frank-type stacking faults with the typical triangular shape, therefore, the typical triangular stacking faults have generally been regarded as Shockley-type stacking faults because the reported Frank-type stacking faults were knife-like and elongated triangular [5–7]. In this study, we observed the Frank-type stacking faults with typical triangular shapes. We performed photoluminescence mapping to investigate the stacking faults and measured the characteristic photoluminescence emission wavelengths. Based on the emission wavelengths from the stacking faults types of stacking faults could be determined [8]. Finally, we confirmed the types and structures of the stacking faults using high-angle annular dark-field (HAADF) high-resolution scanning transmission electron microscopy (HR-STEM). Commercially available 4H-SiC epitaxial wafer with diameters of 100 mm and thicknesses of 32 μm was used in this study; the off-cut angle was 4° in the [11"2" ̅0] direction. Nondestructive photoluminescence mapping was performed to detect and classify stacking faults using the MiPLATO-SiC (EtaMax, Republic of Korea). The stacking fault types were automatically classified using the auto-navigating function of the instrument according to their characteristic photoluminescence emission wavelengths. The stacking fault structures were directly confirmed by conducting HAADF HR-STEM using the Cs-corrected JEM-ARM200F (JEOL, Japan). Cross-sectional TEM specimens the targeted stacking faults were prepared using a dual-beam focused ion beam (FIB; Thermo Fisher Scientific, USA). Figure 1(a) shows photoluminescence spectra of two stacking faults with typical triangular shapes as shown Figure 1(b) and (d). The characteristic photoluminescence emission wavelengths of the stacking faults A and B were 483.8 and 457.3 nm, respectively. Based on the emission wavelength values the stacking fault A was expected to be an intrinsic Frank-type stacking fault (5,2), despite it exhibiting a typical triangular shape and not an elongated triangular shape (Fig. 1(b)) [8]. HAADF HR-STEM analysis (Fig. 1(c)) confirmed that the stacking fault A was an intrinsic Frank-type stacking fault (5,2). In case of the stacking fault B, it was expected to be a multilayer Frank-type stacking fault (4,2), despite its typical triangular shape (Fig. 1(d)), as its characteristic emission wavelength (457.3 nm) agreed with that of the multilayer Frank-type stacking fault (4,2) reported in previous studies (457 nm) [1,2]. HAADF HR-STEM analysis (Fig. 1(e)) confirmed that the stacking fault B was a multilayer Frank-type stacking fault (4,2). Based on our experimental observations and investigations discussed in Figs. 1, we clearly showed that the Frank-type stacking faults can exhibit typical triangular shapes, therefore, the shape of the stacking faults cannot be a criterion for determining their types. In conclusion, we found that the typical triangular stacking fault could be Frank-type, despite the similarity to the shape of Shockley-type stacking faults. In addition, we investigated that the characteristic photoluminescence emission wavelength of the intrinsic Frank-type stacking fault (5,2) is 483 nm, which differs from that reported in previous studies (488 nm) [2,3]. Furthermore, we will discuss a shaping of stacking faults, for the most frequently observed right-angled and isosceles triangular stacking fault shapes based on the preferred line vector directions of the partial dislocations bounding the stacking faults.

[1] T. Dalibor, G. Pensl, H. Matsunami, T. Kimoto, W. J. Choyke, A. Schöner, and N. Nordell, Phys. Stat. Sol. (a) 162(1), 199–225 (1997). [2] U. Lindefelt, H. Iwata, S. Öberg, and P. R. Briddon, Phys. Rev. B 67(15), 155204 (2003). [3] G. Feng, J. Suda, and T. Kimoto, Appl. Phys. Lett. 92, 221906 (2008). [4] G. Feng, J. Suda, and T. Kimoto, Appl. Phys. Lett. 94, 091910 (2009). [5] I. Kamata, X. Zhang, and H. Tsuchida, Appl. Phys. Lett. 97, 172107 (2010). [6] E. Tochigi, H. Matsuhata, H. Yamaguchi, T. Sekiguchi, H. Okumura, and Y. Ikuhara, Philos. Mag. 97(9), 657–670 (2017). [7] I. Kamata, X. Zhang, and H. Tsuchida, Mater. Sci. Forum 725, 15–18 (2012). [8] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Mater. Sci. Semicond. Process. 175, 108247 (2024).

ABSTRACT. Silicon Carbide (SiC) wafers exhibit unique properties that make them suitable for high-power and high-frequency electronic devices. Therefore, ensuring the quality and reliability of SiC wafers is of paramount importance. In this context, it has already been demonstrated that the high-resolution imaging of Applied Materials SEMVision equipped with Scanning Electron Microscope (SEM), Focus Ion Beam (FIB) and Energy Dispersive X-ray (EDX) turned out to be essential for deep understanding of the defects’ morphological characteristics and their source mechanisms. Thanks to the aforementioned studies it was demonstrated that the yield enhancement of incoming and processed wafers, at critical steps, dramatically increases. Another aspect of the quality assurance involves the review of the wafer edge bevel and apex of SiC wafers, which represent critical areas where defects can arise, potentially compromising device performance, increasing leakage currents, and reducing yield by causing device failure or degradation over time. The experience with the Si wafers was the main motivation to review the edge, bevel and apex of the SiC wafers. Indeed, the aim of the production is to align the quality of SiC wafers to the top quality of Si. The intrinsic hardness and chemical resistance of SiC make it a challenging material to cut and polish. SiC boules are typically sliced using a multi-wire saw equipped with diamond grains. After polishing, the integrity of the wafer surface, in terms of surface planarity, subsurface dislocation density and residual stresses, is crucial in view of the forthcoming deposition of high-quality epitaxial layers. The polishing sequence is multi-stage, starting with rough mechanical polishing using graded abrasives and culminating in chemical mechanical polishing (CMP). CMP for SiC involves a colloidal silica-based slurry used at slightly high temperatures for both the front and back side of wafers. This paper is a result of collaboration between Applied Materials and STMicroelectronics to evaluate the enhancement of both Si and SiC yield. The paper describes the methodology that was used at STMicroelectronics Catania to characterize defects at the edge, bevel and apex of 200mm SiC-bare wafers from different suppliers, identify their origins, and assessing their impact on yield and device performance by using the inline G3MAXFIB. SEM examination provides, for the very first time for a SiC fab, invaluable insights into these defects, but the integration of EDX enables elemental analysis, aids in pinpointing the precise composition and distribution of impurities or contaminants contributing to the defect formation. Moreover, the FIB cutting facilitates the precise cross-sectioning of the bevel and edge, enabling detailed examination of defect morphology and distribution. Challenges of performing review at the bevel of the wafer will be presented and some of the methods used for addressing these difficulties are discussed. The main result was the detection of metal Ni-particles in the bevel of SiC-8 inches wafers. Such particles, during thermal, diffusion, or cleaning processes, can be moved to the inner part of the wafers causing significant failures of the MOSFETs when trapped at the poly-Si mask level, during the gate-oxide-semiconductor interface diffusion. Then, addressing these root causes through optimized process control, material handling, and quality assurance measurements is crucial for minimizing defects on SiC wafers edge bevel and apex. By mitigating defects at their source, manufacturers can enhance the quality, reliability, and yield of SiC-based electronic devices.

ABSTRACT. Power devices electronics based on Silicon Carbide (SiC) are emerging as a breakthrough technology for a wide range of applications. To fulfill the requirements of the SiC industry, the SmartSiC substrate proposes to combine the high quality of a single-crystal device layer and the ultra-low resistivity of a handle wafer. To target high volume manufacturing (HVM) of bonded SiC engineered substrates, in-line defects monitoring and final quality control is key to guarantee device epitaxy yield. In this work, we focused on two crucial steps: the automatic defect inspection of the starting single-crystal donor material and the monitoring of the final epi-ready engineered substrate. A commercially available DUV laser-based inspection system (KLA Surfscan® SC1) was used in a HVM environment for high-sensitivity defect inspection of 150 and 200 mm substrates. Both surface and extended crystal defects were monitored to allow quality continuous improvement. Statistical data collected showed that SiC engineered substrates surface defect density is comparable to single-crystal bulk substrates used as donors down to 300 nm inspection threshold.

ABSTRACT. Extended defects in silicon carbide can cause devices built on them to fail, but their formation and influence on the material’s electrical properties is not fully understood. Typically, investigation of defects in SiC is either done destructively, in a diffraction-limited manner or limited to surface information. In contrast, scattering-type scanning near-field optical microscopy (s-SNOM) offers nanoscale optical information in a non-destructive manner up to a depth of 100 nm below the sample surface by using near-fields created locally at the apex of an atomic force microscope tip under illumination. Here, we apply infrared s-SNOM to identify a thin layer of 4H-SiC on top of the 3C inclusion forming a triangle defect, and analyze its thickness. We find that the layer thickness increases slowly into the defect, by a few nanometers thickness per micrometer length. Furthermore, we present an improved calibration method giving direct access to a sample’s optical properties, without the need for modelling of the tip or assumptions of the optical properties. We demonstrate the method on doped silicon microsctructures of differing doping level, where we use the optical properties for charge carrier profiling by determining the free charge carrier density and damping rate (defined by the mobility) through fitting. As the method only assumes sufficiently thick layers, its application to many SiC defects and devices is straight-forward.

ABSTRACT. Silicon carbide has become popular in the applications of power electronic devices since the emergence of electric vehicles. Despite the superior electrical properties, the defects observed on SiC materials are not yet fully understood to mitigate the impact compared to the well-known and correlated defects that are observed on cost conventional silicon-based devices. Efforts to understand the defect behavior and improve the growth process should be continued. In this study, a comprehensive evaluation on void defects observed in PVT growth of 4H-SiC crystals is conducted. Scanning electron microscopy is used to reveal the shape of the voids. They show up as hexagonal pits with a size of around 100 µm (Figure 1). Focused ion beam is used to reveal a side view of the pit, followed by EDS analysis (Figure 2). X-ray topography [1] is conducted on an axial slice sample containing void defects. Different from the previously reported forming mechanisms of void defects [2], it is found that the void defects are formed during crystal growth instead of migrating from the starting seed. In Figure 3, it is shown that TSD/TMDs are formed downstream the voids during crystal growth, which give rise to TSD/TMD in the wafers created from the boule with such defects present. Based on the observations, possible forming mechanisms of the defect will be discussed.

[1] B. Raghothamachar, M. Dudley, X-Ray Topography, Materials Characterization, ASM International2019. [2] T.A. Kuhr, E.K. Sanchez, M. Skowronski, W.M. Vetter, M. Dudley, Hexagonal voids and the formation of micropipes during SiC sublimation growth, Journal of Applied Physics 89(8) (2001) 4625-4630.

ABSTRACT. Controlled spalling of semiconductors is a technique developed for removing thin (10 – 50 micron) layers from atop a semiconductor substrate by triggered and deliberate propagation of a sub-surface crack across the entirety of the chip or wafer [1,2]. Stress is built up in the wafer subsurface by the deposition of an appropriate metal (stressor) layer on the wafer surface. The crack originates at the wafer edge and then propagates laterally at a depth of 10 – 50 microns to relieve this stress without a need for post-conditioning (e.g. heat treatments). Spall depth can be modulated by engineering the stress field via the metal film deposition. A significant benefit of spalling is that the bulk-like properties of the exfoliated film are preserved [3–5] since the crack depth is determined by an elastic stress field, rather than an intervention by ion implantation or by the deposition of heterogeneous layers at the separation interface. The principal breakthrough in spalling was made by Bedell et al. who introduced a controllable method for spalling using nickel films deposited under high tensile stress via sputtering or electroplating [1]. This method has proven to be highly versatile, and to date has been used to spall Si, Ge, and III-V semiconductor wafers [1,4–7]. Silicon wafers of up to 300 mm in diameter have been spalled [1]. However, the materials spalled so far have been semiconductors with moderate to low fracture toughness and there have been no reports of successful spalling of more refractory, hard materials with a significantly higher fracture toughness.

One such material with a significantly higher fracture toughness is the technologically important semiconductor, silicon carbide (SiC), particularly the 4H polytype. 4H-SiC high-power electronics are being increasingly adopted in electric vehicles (4H-SiC MOSFET based inverters) and photovoltaic power management (4H-SiC high power diodes) [8,9]. 4H-SiC is also a leading wafer scale candidate for solid state quantum coherent devices in quantum communications and sensing [10,11]. Successful spalling of 4H-SiC creates two principal unique opportunities. First, a hindrance to further widespread adoption of 4H-SiC is the high cost of manufacturing substrates. High intrinsic defect density, challenging polytype control, high temperatures, and long growth times contribute to low yields and high substrate cost [12,13]. Spalling offers a pathway for reusing a substrate multiple times if the spalled device layer can be integrated onto other substrates. Second, such layer removal via spalling motivates the heterogeneous integration of 4H-SiC device layers with other materials. This is particularly attractive for quantum technologies, where 4H-SiC has well characterized native defect-based qubits with long coherence times [14], and these native defects may be located and spalled to be integrated with silicon-based control electronics or embedded on photonic waveguides for applications in quantum communication [15].

By demonstrating successful spalling of 4H-SiC, we have overcome the challenge of spalling an ultrahard material which requires 2.5 times greater strain energy than needed to spall GaN, the previous hardest material to be spalled [6]. This result is enabled by novel scientific approaches taken in stressor layer design and spalling crack initiation. We present a controlled spalling-based solution for layer removal and transfer of few tens-of-microns thick films of single crystal 4H-SiC from bulk substrates. Bulk substrates are then repolished and can be reused to spawn further films for removal and transfer. We further show coherent spin control of a VV0 qubit ensemble in spalled 4H-SiC with T2* of the same order of magnitude as in bulk substrates.

S.G. acknowledges support from the Vannevar Bush Fellowship under the program sponsored by the Office of the Undersecretary of Defense for Research and Engineering and in part by the Office of Naval Research as the Executive Manager for the grant. This work is also supported by the Air Force Office of Scientific Research under award number FA9550-23-1-0330. Work performed at the Center for Nanoscale Materials, a U.S. Department of Energy Office of Science User Facility, was supported by the U.S. DOE, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.

A preprint of this work is available at https://doi.org/10.48550/arXiv.2404.19716

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ABSTRACT. Silicon Carbide (SiC) is being widely adopted in high-power and high-voltage applications. However, as the devices dimension shrink and new architectures emerge concurrently to the transition from 150 mm to 200 mm wafer size, some important device fabrication challenges need to be addressed. These include the formation of high-quality Hard Mask (HM), which is used in several key processing steps. It requires the co-optimization of both the HM deposition and etching as well as a proper metrology to characterize each processing step. Here we propose the use in the implantation process of Advanced Patterning Film (APF®), a PECVD Carbon-based film family deposited via Applied Materials Producer® either as a stand-alone HM or in conjunction with common SiO2 as a superior quality HM than the SiO2 HM stand-alone case. The HM stack is etched using Applied Materials E-Max® and it is characterized by Applied Materials Verity 6C SEM®. APF® and SiO2 present a similar ion-stopping power, hence each layer of the final stack can be optimized accordingly. The Transmission Matrix method1 was used to model the APF® and SiO2 stack illuminated orthogonally by a 633 nm mono-chromatic source. The final HM is shown for the APF® stand alone and APF+SiO2 case, respectively. Furthermore, APF® is proposed as a sidewall & bottom HM for advanced through-trench implantation schemes. The APF-based masks have also been characterized by Applied Verity 6C SEM. Along with the HM line-edge roughness (LER) and line-width measurements (LWR) wafer maps, tilted imaging was performed to better characterize the HM and look for potential defects not captured by the common top-view imaging. Additionally, roughness power spectral density is estimated by the Fourier transform of the exponentially decaying LER autocorrelation function S_xx In short, we propose the use of APF® as an advanced HM in SiC ion implantation processing.

ABSTRACT. The global shift in the market from 6" to 8" silicon-carbide wafers presents new challenges for wafer manufacturers. They need solutions that not only enable high throughput to meet mass-market demand but also ensure cost-effective production of high-quality wafers. However, achieving these goals can be counterintuitive, as shown in Fig. 1, due to the complexity of the process.

Lapmaster Wolters, a leading innovator in wafering equipment, has decades of experience in silicon wafering. They’ve successfully optimized their AC 1200 SiC batch polisher for 6" SiC wafers and are now continuing their advancements with the AC 1500 SiC for 8" wafers.

Silicon carbide wafers are hard and brittle, making them susceptible to damage during processing. While single-piece manufacturing is safer for protecting expensive raw wafers, it’s less efficient in terms of throughput, surface quality, and cost of ownership compared to double-sided batch processing. To address this challenge, Lapmaster Wolters has adapted its UPAC system from its silicon portfolio for the AC 1500 SiC, which ensures crash-protected wafer processing. The Upper Platen Adaptive Control (UPAC) dynamically adjusts the polishing plate shape to maintain parallelism during the entire polishing process, even in response to minor changes like temperature fluctuations (as shown in Fig. 2).

The AC 1500 SiC also supports the Rapid Thinning approach, developed collaboratively developed with Pureon- A total process solutions provider for substrate wafering. Rapid Thinning offers up to a 45% cost of ownership advantage due to 4-5x higher material removal rates compared to traditional pre-processing methods like grinding. The advanced composite pad IrinoTM from Pureon along with a specialized diamond slurry from Pureon lead to a material removal rate of 1.5 µm/min while maintaining the Ra on the C face to less than 6 nm. When combined with batch-processed CMP (chemical mechanical polishing), which provides a 30% cost of ownership advantage, as shown in Fig. 3, manufacturers can optimize both individual process steps and reduce the overall process chain.

Even in harsh CMP processes, the AC 1500 SiC delivers excellent results, achieving best-in-class TTV (total thickness variation) and roughness values. As shown in Table I, the new innovative approach of combining Rapid Thinning with an adapted CMP process, offers faster and qualitatively better results than established process chains.

In summary, the AC 1500 SiC demonstrates that seemingly counterintuitive production targets can be achieved through innovative solutions. This presentation will showcase the next step in SiC manufacturing, addressing real-world challenges while managing costs. Overcoming previous constraints will define the new era of wafer manufacturing.

ABSTRACT. Metal oxide semiconductor field-effect transistors (MOSFETs) utilizing silicon carbide (SiC) are emerging as promising alternatives to traditional power switching devices. Efforts in SiC MOSFET development have centered on achieving lower specific on-resistance (Ron,sp), minimizing switching losses, increasing breakdown voltage (BV), and enhancing short-circuit durability [1]. Trench gate technology has recently advanced the reduction of Ron,sp in SiC MOSFETs by refining cell pitch and enhancing channel mobility along the trench sidewall. Moreover, the adoption of a superjunction (SJ) structure has further diminished Ron,sp in silicon-based devices by facilitating heavy doping of the drift region and modifying the electric field distribution to concurrently achieve high BV and low Ron,sp. Specifically, SJ-configured devices with highly doped n-drift regions have demonstrated notably lower Ron,sp compared to conventional planar transistors [2]. Utilizing multi-epitaxial growth, a prevalent fabrication method for producing SJ-configured devices, has been pivotal [2, 3]. The quality of epitaxial growth across multiple layers is paramount for ensuring optimal device performance and reliability. In this investigation, we investigated the multi-epitaxial growth of SiC on an n+-4H-SiC substrate. We utilized metal-organic chemical vapor deposition (MOCVD) for the growth of n-type 4H-SiC epitaxial layers. A 10 μm-thick n-type SiC single layer (nitrogen-doped 4H-SiC) was grown on an n+-SiC substrate as a reference sample. For another sample, we grew three 2 μm-thick epitaxial layers with varying doping levels (step-graded nitrogen-doped 4H-SiC) on a nitrogen-doped 4H-SiC wafer. Our focus was on exploring the structural properties of the epitaxially grown 4H-SiC multi-layer on the n+-SiC substrate, intended for the fabrication of superjunction-structured power devices. This multi-layer structure comprised a 2 μm n-SiC (n=7E15 cm-3) layer, a 2 μm n-SiC (n=1E16 cm-3) layer, and a 2 μm n-SiC (n=4E16 cm-3) layer. Analysis via atomic force microscopy (Fig. 1) revealed comparatively rougher surface textures in the step-graded SiC multilayers compared to the reference sample. Fig 2 shows that Raman spectroscopy unveiled sharp and strong E2(TO) peaks, with a smaller intensity ratio of E1(TO)/E2(TO) compared to the reference and N-implanted SiC, suggesting superior crystal quality. Additionally, all three samples exhibited 4H-SiC (0004) peaks at 36.5° in the 2θ curves, and narrower full width at half maximum (FWHM) values in the omega rocking curves of the multi-layer structure. These findings from Raman spectroscopy and X-ray diffraction underscored the high crystalline quality of the SiC multilayer structure, affirming its potential suitability for SJ-structured power devices. Further details will be presented at the conference.

References [1] S. Rao, G. Pangallo, and F.G. Della Corte, IEEE Electron Device Lett. 36, 720 (2015). [2] F. Udrea, G. Deboy, and T. Futihira, IEEE Trans. Electron Device, 64, 713 (2017). [3] R. Kosugi, S. Ji, K. Mochizuki, K. Adachi, S. Segawa, Y. Kawada, Y. Yonezawa, and H. Okumura, in Proceedings of the 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), (Shanghai, China, 2019) p. 39.

ABSTRACT. [Summary] This paper shows the application of titanium nitride (TiN), which is a low-work function material, as a Schottky electrode to a Schottky barrier diode composed of 4H-SiC, an intervening layer containing SiN between SiC and the Schottky electrode.We have achieved a significant reduction in Φb at room temperature to 0.74 eV. It was confirmed that the significant reduction in Φb was influenced not only by the application of TiN but also by the intervening layer containing SiN at the SiC / TiN interface. Furthermore, TiN was applied to the device as a Schottky electrode, and a maximum Vf reduction of 14% was confirmed while suppressing the leakage current. [Background] Compared to Si devices, SiC devices have the advantages of high breakdown voltage, low on-resistance, high-speed switching, and high-temperature operation, and are expected to further expand the market to photovoltaic inverters (PVs), electric vehicle (EV) charging stations, on-board chargers (OBCs). In order to achieve low forward voltage (Vf), it is necessary to reduce select a material with a low work function and reduce Φb. Nitrides are known to have a lower work function as pure metals[1] . In Si, it has been reported that Φb can be reduced by inserting an ultra-thin insulating film into the metal/Schottky interface[2] . We adopted TiN as a nitride for the purpose of significantly reducing Φb in SiC devices. Furthermore, we formed an intervening layer having different thicknesses containing SiN and investigated the effect on Φb. [Experimental methods and results] Fig. 1 shows the cross-sectional structure. We prepare 4H-SiC (0001) wafers, and form an oxide film.Then, a part of the SiC surface was exposed by performing a contact opening. Thereafter, by sputtering TiN and sintering, intervening layers of different thicknesses were formed at the SiC / TiN interface. Fig. 2 shows the high-resolution STEM image. It can be seen that an intervening layer is formed. In addition, as the intervening layer thickened, TiN changed from a uniform azimuth to a polycrystalline with strong anisotropy. According to the EELS results (Fig. 3) in the intervening layer for the purpose of confirming the binding state of the elements present in the intervening layer, SiN peaks were observed around 107 eV in Si-L and around 405 eV in N-K, and the peak intensity increased as the intervening layer thickened. Fig. 4 shows the V-I characteristics. Each condition functioned as a Schottky barrier diode. When Φb was calculated using Shockley's diode equation, it was confirmed that Φb was reduced from the conventional level under each condition, and a significant reduction of 0.74 eV was confirmed under the condition of a thick intervening layer. Finally, in order to confirm the effect of Vf reduction, a device prototype was made by controlling the JBS depth using TiN. From the VF-IF characteristics of Fig. 5, Vf reduced. From the VR-IR characteristics of Fig. 6, IR was confirmed to be equal to or smaller than conventional samples.We summarize the relationship between VF and IR in Figure 7. Compared to conventional methods, VF can be reduced by up to 14%, and it was found that both low VF and IR suppression can be achieved. From the above, in order to achieve a significant reduction in Φb in 4H-SiC, it was found that the selection of nitride, which is a low-work function material, and the formation of an intervening layer containing SiN are effective.

[1]M.Yoshitake et al., J. Vac. Soc. Jpn.Vol.55,No.7 (2012) [2] D. Connelly et al., APL 88, 012105 (2006)

ABSTRACT. A current challenge in the fabrication of SiC power devices is a requirement for increasingly precise control of the dose, temperature, and energy of various implant steps. As the cell pitch of the SiC power device shrinks, it becomes increasingly sensitive to variations in the condition of the ion implantation process [1]. A metrology is needed to develop and control the implantation processes with the ability to measure the 4H-SiC wafer. To date the photo-modulated reflectance (PMR) technique has been successfully applied for ion implantation process monitoring in silicon [2]. The PMR signal depends on both the implant damage and carrier concentration change [3]. This results in sensitivity to key parameters of the implantation process, such as the dose, energy, tilt angle, etc. However, there are limited reports on the PMR based characterizations of the ion implantation processes in 4H-SiC wafers. Therefore, in this paper, the properties of Al implanted regions before the activation annealing process by using PMR have been investigated. N-type, 4o off (0001) oriented, 4H–SiC wafers with 10-µm thick epilayer doped with 7x1015 cm-3 of nitrogen were used to fabricate the Al implanted samples. The SiC samples were implanted using the Al ion beam of the Nissin IMPHEAT implanter. PMR analysis has been carried out by a Semilab PMR-2200C tool. Fig. 1 shows PMR signals of SiC samples implanted at room temperature (RT) and 500 ℃ (high temperature, HT) with a wide range of energies, and doses. The results reveal good dose, energy, and temperature detectability. In Fig. 2(a), the PMR signal monotonously increases with higher implantation energy both at RT and HT for a fixed dose of 1ⅹ1014 cm-2. The normalized PMR signal (NPS) was calculated by dividing the PMR signal of the implanted sample at HT by that of the corresponding set at RT. This is related to the relative damage level between the HT and RT implants. The implantation energy dependence on NPS is shown in Fig. 2(b). The results indicate slight non-linear energy dependence for a fixed dose of 1ⅹ1014 cm-2. Fig. 3(a) shows that the PMR signal increases with higher doses at RT and HT for a fixed energy of 200 keV. The dose dependence on NPS is shown in Fig. 3(b). The results demonstrate that the PMR signal is a monotonous function of the implantation dose for a fixed energy. Ion implantation introduces defect-related capture centers which enhance carrier recombination. On the other hand, ion implantation with HT leads to enhanced in-situ defect recombination and a decrease in the concentration of defect. Therefore, for samples implanted at higher temperatures, carrier recombination is reduced and free carrier concentration is increased, for similar excitation laser power density [3]. However, the amorphization threshold increases with the implantation temperature and the damage induced by a given dose decreases for HT implantation. These processes affect the net reflectance change so that the PMR signal for a sample implanted at a higher temperature will shift to lower values. More detailed analysis results will be discussed by using the activation annealing process.

ABSTRACT. Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) power devices have garnered increasing attention in power conversion and electronic vehicle applications as replacements for Si-based power devices. This is attributed to their advantages, including fast switching speed, high operating frequency, and low power losses [1] [2]. Despite these advantages, instability of threshold voltage (Vth) is challenge due to the high-density traps near the SiC-SiO2 interface (NITs). [3] When a positive stress voltage is applied to the gate, positive threshold voltage shift occurs, which can be fully recovered by applying a small negative voltage. This fully recoverable Vth behavior is attributed to the trapping and de-trapping of electrons at existing interfaces or oxide traps in the SiC layer, and the same holds true in the opposite case as well. [4] While high-density traps near the SiC-SiO2 interface predominantly influence Vth, ion migration also affects Vth by operating oppositely to the movement of charges at the interface. As commonly known, TiN barrier metal layers which serve not only to reinforce junction structures but also as barrier metal layers to inhibit ion migration is formed through the RTP process. [5][6]

In this study, we investigated the effect of different TiN barrier metal layers on the behavior of threshold voltage (Vth) while subjecting the devices to positive and negative bias. Also, we observed the Vth shift under the positive Hot Temperature Gate Bias (HTGB) and negative Hot Temperature Gate Bias (HTGBx), known as reliability tests. The Vth shift dramatically occurs in 504hrs duration, showing saturation trend. Our finding confirms that the thinner TiN barrier metal layer (less than 2kA) is vulnerable over time under each hot temperature gate biasing condition, showing abnormal Vth shift due to ion migration. Under both HTGB and HTGBx conditions, it was observed that an increase in the thickness of the TiN barrier metal layer not only led to a decrease in the magnitude of Vth shift (approximately 0.1V), but also prevented the possibility of ion migration.

In summary, the thickness of the TiN barrier metal layer not only affects Vth behavior under HTGB and HTGBx conditions, but also shows the potential to minimize the impact of ion migration that may occur at the package level.

ABSTRACT. Wide-bandgap (WBG) materials, especially SiC and GaN, show great benefits over legacy materials for efficient power switching devices. However, substrate material costs currently dominate the price of WBG device manufacturing, contributing the single largest cost for many next generation WBG applications [1]. Crystal Sonic’s Sonic Lift-off (SLO) technology provides a pathway for greater utilization of material, reducing the substrate cost of WBG materials. SLO uses a combination of pre-stress of the substrate via an adhesive stressor layer and cooling step, crack front initiation at one side of the wafer, and a controlled application of acoustic pulses that guide the crack front through the defined plane at a controlled speed. This results in the separation of a thin layer from the original substrate, leaving the parent substrate surface ready for reprocessing. The thickness of the thin layer can be controlled via the applied stressor material and acoustic conditions. After SLO, the stressor acts as a temporary handle for subsequent processing steps, and it can later be removed mechanically or chemically via a mild aqueous solution. This technology can reduce overall device cost by creating engineered wafers (Fig. 1a) or lifting off fabricated devices to allow substrate reuse (Fig. 1b). The SLO process has been previously demonstrated in GaAs with a range of thicknesses between 20m to 120m [2,3]. In this work, 100mm diameter, semi-insulating 4H-SiC wafers with a thickness of 500 ± 25m and no offcut were studied. Bare wafers were used to demonstrate the viability of the SLO process. The SLO conditions were adjusted to target a layer thickness of 50m. Figure 2a shows the substrate and the thin layer after SLO. The thin layer is attached to a stressor acting as a temporary handle (blue layer) which provides mechanical support in subsequent operations. These initial feasibility results have successfully lifted off ~95% of the available wafer area. Lift-off areas of >99% are achievable via further process refinements. Surface roughness was measured in four 1x1mm areas on each parent wafer following SLO using a Bruker Dektak XT stylus profilometer. Figure 2b shows surface mapped areas representing the higher and lower quality sections of the created surfaces with an average RMS roughness of 175nm±90nm across all measured areas. SEM (Fig. 3a, b) shows a unique lack of subsurface damage, and Raman spectra (Fig. 3c) indicate no evidence of crystal structure damage after SLO. Future work will conduct SLO tests applied to 100mm 4H-SiC with a 4° offcut. Classical spalling techniques are unable to maintain wafer offcut or avoid favorable cleavage planes, resulting in microscale terraces [2,3]. SLO overcomes this limitation and maintains a separation plane parallel with the original device face as previously shown when applied to GaAs and SiC with offcuts [2,3], resulting in thin layers and parent wafers that require minimal post-processing.

[1] “Taking Stock of SiC: Part 1”, PGC Consultancy, October 2021. [Online]. Available: https://www.pgcconsultancy.com/post/taking-stock-of-sic-part-1-a-review-of-sic-cost-competitiveness-and-a-roadmap-to-lower-costs [2] P. Guimerá Coll et al., "Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets," 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC), Fort Lauderdale, FL, USA, 2021 [3] P. Guimerá Coll et al, “Sonic Lift-off (SLO) to Enable Substrate Reuse and Lower Manufacturing Cost,” Compound Semiconductor Manufacturing Technology (CS ManTech), Orlando, FL, 2023.

ABSTRACT. Stress-induced damage by silicon nitride (Si3N4) in 4H-SiC is investigated in this work using Schottky barrier diode (SBD). Research indicates that both 100 nm and 315 nm Si3N4 layers induce surface damage. A 45-nm-thick sacrificial oxidation effectively mitigating damage from the 100 nm Si3N4 layer, but it is not enough to solve the damage caused by the 315 nm Si3N4 layer. Thus, an appropriate pad oxide layer is still necessary.

ABSTRACT. SiC MOSFETs are one of the promising candidates for efficient power devices, but their performance is limited due to a high density of interface states at the SiO_2/SiC interface. Previous studies have reported that H_2 etching and oxidation-minimized process improve the SiO_2/SiC interface properties. This would be due to the well-designed morphology of the SiC surface, which is crucial for improving the MOS interface properties. Although it was found that thermal oxidation at 1000˚C affects the morphology of SiC surface, few studies have investigated the surface of SiC processed under various oxidation or annealing conditions. In this study, we systematically studied the impact of thermal oxidation and forming gas annealing on the surface morphology of SiC.

ABSTRACT. In this study, the practical implementation of potential Superjunction topologies are analysed using Sentaurus TCAD simulations benchmarked to and adapted from a commercial 650 V rated double trench MOSFET. The location of the superjunction p-pillar is explored in planes both parallel (X-Y) and perpendicular (Z-Y) to the device active area. In addition, the effect of tilt in the X-Y direction is explored for the purpose of practical feasibility and expanding the otherwise tight implantation window for maximum breakdown voltage. The p-pillar thickness is varied in the Z-Y direction to quantify the specific on-resistance change that occurs due to pinch-off of the channel during on-state. In addition, the electric field profile of each structure is examined to view the impact on gate field crowding during breakdown.

ABSTRACT. SiC MOSFETs are emerging as promising candidates to replace traditional devices, attributed to their compact chip size and low switching loss, as well as their advantageous reverse recovery operation [1-3]. Most of the reported reverse recovery behavior only considered the built-in body diode in the active region and more detailed studies are needed [4-5]. SiC MOSFET can be broadly categorized into an active and an edge termination region. Although the main action occurs in the active region, many studies have shown that p+/n- junctions are also present in the termination, which influences their dynamic characteristics [6-7]. Further studies are required to fully understand and optimize the reverse recovery behavior of SiC MOSFETs including the edge termination (Fig. 1). In this study, the reverse recovery behavior of each region according to the active/termination area ratio (A/T ratio) was analyzed using the Double Pulse Test (DPT) (Fig. 2) and TCAD simulation. DPTs were performed at the same dI/dt (1000A/us) and load current density (200A/cm2) for all devices (Table I and Fig. 3). We use active-edge termination integrated mixed-mode simulations to investigate the reverse recovery behavior of each region (Fig. 4). During the turn-on, the active and termination recovery currents (Irr) flow from the high side to the drain of the low side SiC MOSFET (Fig. 5). The trends in maximum reverse recovery current (Irrm) and softness factor (RRSF=tb/ta) were evaluated as the area ratio increased (Fig. 6). As the junction temperature rises, carrier recombination becomes faster and the IF falls to zero (tb) becomes shorter. The reverse recovery current of edge termination itself is not high, but the Irr is almost the same regardless of chip size. At smaller devices (A/T ratio =1.71), the RRSF can increase due to low driving current and the drain-to-source capacitance (CDS) of edge termination.

ABSTRACT. 4H-SiC metal-oxide-semiconductor filed-effect-transistors (MOSFETs) are operatable as both n- and p-channel transistors, and enable us to design novel complementary-MOS (CMOS) circuits using a wide-gap semiconductor. For p-channel MOS interfaces, however, their interface states (Dit) are much unclear as compared to those in n-channel MOS interfaces. It is obvious that the nature of the Dit are considerably different between n- and p-channel interfaces. For example, a wet oxidation (hydrogen passivation) drastically improves the MOSFET’s performance only for p-channel transistors [1]. Therefore, we need more detailed and microscopic information on p-channel MOS interface defects. In this study, we conducted an electrically-detected-magnetic-resonance (EDMR) spectroscopy and spin-dependent charge pumping (SDCP) spectroscopy on p-channel 4H-SiC MOSFETs, to reveal their interface defects. So far, Ref [2] by Prof. Lenahan’s group is the only EDMR and SDCP spectroscopy on p-channel MOSFETs. We have detected SDCP interface signals different from those in the previous work. Furthermore, we found that the SDCP measurements can focus on interface signals different from those detected by the standard EDMR spectroscopy. We will compare the SDCP signals with the EDMR signals, and discuss the microscopic origin of the SDCP signals. We prepared p-channel lateral 4H-SiC MOSFETs (Si face and dry oxidation). Their maximum field-effect mobility and threshold voltages were estimated to be 1.4 cm2V-1s-1 and -17.4 V, respectively. Figures 1(a) and 1(b) are typical SDCP and EDMR spectra, respectively. In the SDCP measurement, we used a charge-pumping (CP) gate-pulse sequence shown in the inset of Fig. 1(a). As a result, we successfully detected a strong SDCP signal. As is seen in the 30 magnified spectrum, we for the first time succeeded to observe hyperfine (HF) structures due to 13C nuclear spins in the SDCP technique. It is thus clear that the observed SDCP signals originate from carbon-related interface defects. Furthermore, the above 13C HF structures are different from the known 13C HF structure of the PbC center (carbon dangling-bond center on Si face) [3]. We have confirmed that the same signal can be detected in a standard EDMR spectrum of the same p-channel MOSFETs, as shown in Fig. 1(b), where the same 13C HF structures are found in both the spectra. This EDMR spectrum was measured using the bipolar-amplification-effect (BAE) EDMR technique [3,4]. On the other hand, we also found that the SDCP measurements can reveal a wider range of the Dit as compared to the standard EDMR techniques. Figure 2 shows a CP gate-pulse dependence of the SDCP spectra (“Vbottom” bias was varied from -10.4V to -9 V). As is shown in the figure, the SDCP spectra were continuously changed from one to other signal, which could not be seen using the BAE-EDMR spectra. This result indicates that the SDCP measurements extend our spectroscopic survey range with respect to the interface defects. We will discuss this point more detailed. This work was supported by MEXT-Program for Creation of Innovative Core Technology for Power Electronics Grant Number JPJ009777.

ABSTRACT. Wide bandgap semiconductors such as silicon carbide (SiC) and beta-phase gallium oxide (β-Ga2O3) are increasingly utilized in next-generation power electronics [1-2]. β-Ga2O3 is distinguished by its high critical electric field, projected to reach up to 8 MV·cm-1, while SiC exhibits excellent physical properties including a high electric breakdown field, high saturated electron velocity, and high thermal conductivity. Moreover, both SiC and β-Ga2O3 materials demonstrate superior radiation tolerance [3-4], making them attractive for aerospace power electronics applications [5]. In this study, we fabricated vertical schottky barrier diodes (SBDs) based on wide bandgap semiconductor SiC and β-Ga2O3, respectively, and conducted proton irradiation experiments to comparatively analyze the radiation hardness of the SBDs. The effects of proton radiation on the SBDs' performance were assessed through measurements of forward current, capacitance, and breakdown characteristics. After the proton irradiation with an energy of 55 MeV and a fluence of 1014 cm-2, the forward current characteristics of both SBDs were reduced by the proton irradiation-induced DD effect because the high fluence proton irradiation increased resistance by forming the defect. The β-Ga2O3-based SBD demonstrated more pronounced deterioration compared to the SiC-based device, despite similar vacancy distributions as confirmed by SRIM simulation. Furthermore, devices with smaller radii showed a higher reduction rate in current, attributable to proton-induced damage in the confined contact area. The carrier concentrations of β-Ga2O3 SBD, extracted from capacitance characteristics, were further reduced by the displacement damage. However, the breakdown voltage of both devices increased, contrary to the current characteristics, due to increased resistance. These results demonstrate that the DD effects of SiC and β-Ga2O3-based vertical SBDs were induced by proton irradiation with high fluence, and the effects of proton irradiation are dependent on the dimensions of the device structure and the quality of materials. Thus, enhancing the quality of epitaxial and substrate materials will be a paramount research focus to enhance the radiation resistance properties of β-Ga2O3 semiconductors in the future.

ABSTRACT. A trench-gate SiC-MOSFET is expected to achieve a low specific on-resistance (Ron,sp) by increasing it’s the cell density and improving the channel mobility. We have previously reported on a 1.2 kV class trench-gate SiC-MOSFET that achieved a low Ron,sp with a breakdown voltage exceeding 1.2 kV. Various termination structures for the trench-gate SiC-MOSFET have also been reported. With the growing demand for 1.2 kV class trench-gate SiC-MOSFETs in the electric vehicle market, a cost reduction is necessary. In this study, we have investigated edge-termination structure using an oxide film along the trench surface. Since the trench functions as a guard ring, the process of making the guard ring can be eliminated, reducing the process load. Through simulation, we have confirmed that avalanche breakdown hasn't occurred up to the breakdown voltage of a cell region by providing a boundary region between the cell and termination region.

ABSTRACT. Silicon carbide (SiC) exhibits promising potential for power devices owing to its material properties, including a wide bandgap, high critical electric field, and excellent thermal conductivity. SiC Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are considered the next generation of high-efficiency power devices and are already commercially available [1, 2]. Another promising application using SiC MOSFETs is SiC Complementary-MOS (CMOS) Integrated Circuits (ICs) [2-4]. SiC CMOS ICs can operate under high temperature (≥ 473 K), which is not achievable by Si CMOS ICs due to the comparatively high concentration of intrinsic carrier for Si at room temperature. However, the basic understanding of n, p-channel SiC MOSFETs is still missing until now, which hinders the modeling of SiC CMOS devices. In this study, the field effect mobilities of 4H-SiC lateral n- and p-channel MOSFETs based on various channel designs have been investigated. Lateral MOSFETs were fabricated on an n-type 4H-SiC (0001) epilayer on an n-type substrate. Uniform doping profiles were created using nitrogen, and aluminum ion implantation at 500 ℃ to form the base and the source regions on the n- and p-channel MOSFETs. The doping concentrations of the n-, p-base with box shape were 1.0×1017, and 1.5×1017 cm-3 respectively. After the ion implantation, activation annealing was performed at 1700 ℃ for 60 min. To form the gate oxide, dry oxidation at 1350 ℃ for 18 min, followed by NO annealing at 1300 ℃ for 60 min. A detailed description of the fabrication procedures for the lateral MOSFETs has been given elsewhere [3]. The thickness of gate oxides was about 41 nm. MOSFETs' channel length (L) and width (W) were 2-500 μm and 20-500 μm, respectively. The channel mobilities were calculated from the maximum transconductance of the transfer curve on various channel designs. The reduction rate was calculated by dividing the difference between the maximum mobility and the minimum mobility by the maximum mobility. In Fig. 1, when L is short, the reduction rates of the mobilities for the p-channel MOSFET were higher in the 67-77 % range compared to 28-49 % of the n-channel MOSFET. On the other hand, as W increases, the reduction rates of the mobilities for the n-channel MOSFETs were higher in the 7-28 % range compared to 0.1-23 % of the p-channel MOSFET in Fig. 2. The results indicate that the parasitic resistance dependence of the source and drain regions may differ for the n- and p-channel MOSFETs [4]. The results indicate that the parasitic resistance dependence of the source and drain regions can be different for n- and p-channel MOSFETs [4]. Figure 3 shows that the n- and p-channel mobilities were studied by measuring the temperature range from 300 to 423 K. For the n-channel, the mobility increases as the measuring temperature increases with decreasing W and increasing L in fig. 3(a). However, for the p-channel, there are two kinds of temperature dependence in tendencies to change the mobilities in fig. 3(b). When L exceeds 10 μm, the mobility decreases with increasing measurement temperature. Conversely, when L is less than 10 μm, the mobility increases monotonically with increasing measurement temperature. This means that depending on the p-channel design, the dominant carrier scattering mechanism may be different from the n-channel. More detailed analysis results will be discussed by using the parameters of the MOSFETs such as parasitic resistances, threshold voltage (Vth), subthreshold swing (SS), interface trap density (Dit), etc.

ABSTRACT. Silicon carbide (SiC) exhibits promising potential for power devices owing to its material properties, including a wide bandgap, high critical electric field, and excellent thermal conductivity. SiC Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are regarded as next-generation high-efficiency power devices and have already seen commercial use [1]. For enhanced performances and numerous applications, the reduction of channel length is inevitable, thereby inducing the short-channel effect. For n-channel SiC MOSFETs, it is recognized that the short-channel effects occur for lengths around less than 0.9~2.7 μm, which varies depending on doping concentrations [2, 3]. Short-channel effects significantly influence the device performances, including the deterioration in subthreshold properties and punch-through. Recent studies have also reported that the dominant carrier scattering mechanisms varies significantly with temperature between n- and p-channels [4]. Understanding these phenomena is crucial for improving the transport characteristics, performance, and reliability of SiC MOSFETs. In this study, we report that the short channel significantly alters the temperature-dependent properties of p-channel SiC MOSFETs across a temperature range from 123 ~ 373 K.. We investigated the electrical characteristics of p-type 4H-SiC MOSFETs based on different channel lengths. Lateral p-channel MOSFETs were manufactured on an n-type 4H-SiC (0001) epilayer on an n-type substrate. Uniform doping profiles were created using nitrogen, and aluminum ion implantation at 500 ℃ to form n-base and P+ source regions on the MOSFETs. The doping concentrations of the n-base and P+-source were 1.5 × 1017 and 1.0 × 1020 cm-3 respectively. After the ion implantation, activation annealing was performed at 1700 ℃ for 60 min. To form the gate oxide was formed via dry oxidation (1300 ℃, 20 min), followed by NO annealing (1250 ℃, 70 min). The oxide thickness was about 41 nm. The channel width was fixed at 20 μm, while two dimensions of length were fabricated: 500 μm (L1) and 2 μm (S1). Gate characteristics of L1 and S1 at varying temperatures are depicted in Fig. 1(a) and (b), respectively. As the temperature decreases, deterioration in subthreshold properties and a shift in threshold voltage were observed, suggesting an increase in carrier trapping due to temperature reduction. Fig. 1(c) and (d) show drain characteristics of L1 and S1, when the gate voltage was varied from 0 ~ -20 V in -5 V steps. For the L1, the drain current reached saturation when the drain voltage exceeded the pinch-off voltage. In contrast, S1 revealed nonsaturation characteristics. These results indicated that the short-channel effects occur for S1. Fig. 2(a) and (b) illustrates the Dit distribution extracted from subthreshold swings (SSs) plotted against the normalized drain current at varying temperatures for L1 and S1. The Dit values corresponding to the normalized drain current in the subthreshold region of 1.0 × 10-10 A for p-channel MOSFETs at different temperatures were extracted. Fig. 2(c) shows the Dit distributions extracted from SSs of MOSFETs at different temperatures near the valence band edge (EV). The Dit values at ET – EV = 0.08 eV are 2.8 × 1012 eV-1cm-2 and 3 × 1012 eV-1cm-2 for L1 and S1, respectively. Fig. 3 exhibits the μFE of L1 and S1 relative to the gate voltage, obtained from the gate characteristics at various temperatures. The drain voltage was set to -0.1 V for MOSFETs in obtaining the gate characteristics. μFE,Max of L1 slightly increased from 10.9 cm2V-1s-1 at 373 K to 12.6 cm2V-1s-1 at 123 K with lowering the temperature. On the other hand, μFE,Max of S1 decreased from 5.3 cm2V-1s-1 at 373 K to 1.3 cm2V-1s-1 at 123 K with lowering temperature. Lowering the temperature results in a decrease in mobility constrained by Coulomb scattering, while mobility constrained by phonon scattering increases, owing to the diminished lattice vibration at lower temperatures. Therefore, as the channel length decreases, the temperature dependence of mobility is predominantly regulated by Coulomb scattering.

ABSTRACT. Silicon carbide (SiC) is distinctive as the only wide bandgap semiconductor capable of thermal oxidation, leading to the formation of a durable silicon dioxide layer that is chemically and thermally stable. The 4H-polytype of silicon carbide (4H-SiC) shows considerable promise for replacing silicon (Si) in metal-oxide-semiconductor (MOS)-based devices, particularly MOSFETs. Notably, the critical field of 4H-SiC exceeds that of Si by a significant margin, indicating markedly reduced drift resistance in a 4H-SiC MOSFET compared to a Si MOSFET at a given breakdown voltage. In the fabrication of a SiC MOSFET, the gate oxide is commonly grown in either a dry or wet oxygen environment using a conventional quartz oxidation furnace designed for Si, operating within the temperature range of 1100 °C to 1200 °C. Due to SiC's slower oxidation rate relative to Si, oxidation is typically conducted at the higher end of this temperature range.[1,2] Nevertheless, previous research consistently highlights a heightened defect density near the interface of oxide and SiC, commonly known as near-interface traps, under these circumstances. This occurrence is ascribed to the existence of carbon dimers [3], inherent oxide imperfections [4], and surplus Si [5]. The presence of interface trap density (Dit) notably impedes channel mobility due to Coulomb scattering [1,6]. As a result, this results in a MOSFET with increased on-resistance, counteracting the advantageous properties of 4H-SiC. Effectively addressing Dit is essential, and finding a simple approach to achieve this is paramount. In this study, we investigated the influence on the quality and reliability of SiO2 by dry and wet oxidation techniques, particularly focusing on incorporating dry oxidation as the final step, assessed through MOS capacitor fabrication. In this study, four samples (A, B, C, D) were prepared to compare the oxide properties. Detailed oxidation conditions for each sample are presented in Table I. We employed N-type 4H-SiC wafers with Si-face orientation (0001) and an 11 µm thick epilayer doped with 7.5 × 1015 cm-3 of nitrogen as substrates. After undergoing standard RCA chemical cleaning and treatment with a mixture of DI water and HF (100:1) to remove the thin SiO2 layer prior to oxidation, the wafers were oxidized in a quartz tube furnace under various conditions as depicted in Table I. The oxide layer thickness was determined using a spectroscopic ellipsometer. Following the oxidation process, post-oxidation annealing was conducted in flowing NO (2 slm) at 1150 °C for 1 hours. The samples underwent metallization with Al deposited by DC sputtering, and capacitor areas were defined through photolithography. Electrical characterization was performed using high-frequency and quasi-static capacitance-voltage (C-V) measurements. The wet oxidation process exhibited a higher oxidation rate compared to dry oxidation. Fig. 1 shows that as oxidation time increases, the oxide thickness also increases. When comparing samples A and B with similar thicknesses, sample B (subjected to wet oxidation) demonstrates a significantly lower Dit value by more than one order of magnitude. This suggests prolonged exposure to high temperatures, leading to unfavorable interfacial characteristics. Analysis of oxide breakdown field (Eox) values indicates similarity among three samples, excluding Sample D, where an abnormal Eox value suggests the necessity for remeasurement. The Dit value of sample C appears slightly lower compared to samples A and D; however, due to differences in exposure time to heat, it is difficult to attribute this solely to the effects of wet+dry oxidation. Our findings suggest that oxidation for a long growth time at relatively low temperatures (<1200°C) impedes the growth of thick SiO2 layers with excellent interfacial properties, while short growth times at high temperatures (>1200°C) yield superior interfacial characteristics. Therefore, it is inferred that oxidation on SiC at relatively high temperatures (>1300°C) with a high growth rate for a short duration might be beneficial for the interfacial properties of the oxide.

ABSTRACT. In the semiconductor oxidation process of Si, Chlorine plays a crucial role in removing metallic impurities within the Gate Oxide (GOX) [1-3]. However, in SiC processes, various other techniques are being introduced concerning the quality of GOX [4]. SiC devices primarily utilize implant sources like Al, which certainly introduces metallic impurities into the Gate Oxide during Thermal Oxidation. This paper aims to investigate the effects of Chlorine oxidation on SiC MOSFET devices. Additionally, considering the influence of lower pressure oxidation on oxide quality, as discussed at ICSCRM2023 [5], we aim to examine its impact on SiC MOSFET devices. We evaluated the Oxide Quality by altering the GOX conditions of SiC MOSFET produced products. Employing a DOE on GOX conditions, we represented Oxide Quality through QBD and secured the reliability of the effects by evaluating multiple devices under the conditions. Additionally, SIMS analysis was conducted to observe changes within the oxide. SiC MOSFET wafers processed under conditions featuring the lower pressure oxidation that was effective in improving QBD in SiC MOS did not show significant differences in QBD among conditions. While the quality of the oxide itself could be improved, substantial effects were not observed in SiC MOSFET devices with multiple processes. Conversely, conditions involving Chlorine showed over a twofold improvement in QBD (Fig. 1). Analysis (Fig. 2) revealed that gate oxides processed without Chlorine exhibited fluctuation in Si concentration from the SiC/SiO2 interface towards the SiO2 surface. In contrast, gate oxides processed through Chlorine oxidation maintained a consistent Si concentration within the oxide. This signifies the maintenance of uniformity in SiO2 across the entire gate oxide area and serves as evidence for improved QBD compared to gate oxides under different conditions showing Si concentration degradation comparatively due to Carbon defects. Therefore, chlorine added thermal oxidation can forming stable SiO2 layer and this effect is a gate oxide quality improvement as shown QBD improvement results in the SiC MOSFET device.

ABSTRACT. The Deep Level Transient Spectroscopy (DLTS) is an important analytical tool to characterize electrically active defects in semiconductor materials. After it was proposed by Lang [1] in 1974, the technique has been explored and developed in most of its aspects and has given scientists a straightforward means to access information of primary importance to understand the microscopic mechanisms underlying the electrical behavior of semiconductors. Thermodynamic quantities measurable by DLTS are essential data for TCAD-based electrical simulations and serve as reference for DFT calculations, thus enabling accurate prediction of electrical device performance and boosting the optimization of quantum mechanical models useful in solid matter physics. To date, we can rely on a variety of DLTS-based techniques to extract information on both majority and minority carrier traps, using electricity and/or light as charge carrier excitation source. In the Junction DLTS experiment minority carriers are electrically injected using a p-n junction driven into forward bias [2, p. 554]. The main drawback of this technique is that, while the properties characterizing the minority carrier trap – the trap concentration (Nt) and capture cross-section (σ) mainly – depend on the injected minority carrier density, the experimental determination of this quantity is not straightforward [2, p. 567]. It comes that in most of the cases it’s not possible to obtain a full characterization relying only on Junction DLTS experiments. TCAD electrical simulations can help in this sense. If the material and the structure of the analyzed device are known, it is possible to extract physical quantities of interest, such as the carrier densities, the depletion depth, the current density-voltage (J-V) characteristics etc. The simulated injected minority carrier density can be used in combination with Junction DLTS experiments to enlarge the range of information obtainable from this technique. A simple electrical model can be then improved by including the parameters of the characterized defect, and the procedure iterated to find a compromise between the model and the experiments. In this work we combined TCAD simulations with Junction DLTS experiments to extract capture properties of the well-known Shallow Boron defect centers [3, 4] (DLTS spectrum in figure 1a) in N-type 4H-SiC. A 4H-SiC P-i-N device used as sample for the study was simulated by Silvaco TCAD, with the reliability of the simulations tested by comparing simulated and experimental J-V curves measured at different temperatures (figure 2a). Capture rate DLTS measurements were performed by varying the forward bias filling pulse (figure 1b) and, taking advantage of the relation between capture rate and forward bias injected hole density [2, p. 636] (figure 2b) and according to the multiphonon emission model [2, p. 432] for σ(T), true capture cross-section (σ∞) and energy barrier (Eσ) for the B1 (Ev + 0.27 eV) and B2 (Ev + 0.30 eV) hole traps were derived. The capture parameters were combined with thermal emission Junction DLTS data – activation energies (Ea) and apparent capture cross-sections (σa) – to estimate the entropy factor [2, p. 426] and the Gibbs free energy of electronic activation of the defects.

ABSTRACT. Continuous operation for 600 min of the 4H-SiC MOSFET under positive bias stress at 300℃ is investigated. The electrical parameters of the 4H-SiC MOSFET during the high-temperature operation process are extracted by using a modified BSIM model. The threshold voltage of the MOSFET increases of 0.6 V just after 10 min of operation, however, after that, it changes insignificantly with the operation time. The extracted results show that the interface trap density at the SiO2/SiC remains stable after 600 min of continuous operation at 300℃. The low gate leakage current and proper characteristics of the 4H-SiC MOSFET indicate that the fabrication process of 4H-SiC MOSFET is promising to apply for high-temperature applications, up to 300℃.