ABSTRACT. Physical vapor transport (PVT) method remains the dominant approach for producing commercial 4H-SiC substrates, yet dislocation defects, particularly basal plane dislocation (BPD), persistently challenge device reliability [1]. Minimizing the defect density in PVT grown 4H-SiC boule becomes incrementally harder as growth diameters reach 150 mm or larger, highlighting the primary challenge of optimizing temperature gradient for maintaining uniformity and stability during extended growth periods. Disruption of the temperature gradient not only affects growth rates but also significantly increases the probability of continuous defect formation, leading to a deterioration in crystal quality. Some literature mentioned that an expanded hot-zone diameter decreases temperature uniformity at the boule center, fostering localized 2D island growth and an irregular convex surface, thereby unintentionally form the threading dislocations (TDs) [2]. Additionally, thermoelastic stress during step-flow growth towards the periphery of the SiC boule promotes defect interaction between BPDs and threading edge dislocations (TEDs) [3-8]. These phenomena finally cause a significant increase in defect density during large-diameter PVT growth. In previous work, it was shown that the temperature gradient strongly influences the defect density in the initial stage of PVT growth [9,10]. By the optimization of the temperature gradient in the initial stage, the defect density was dramatically decreased. Now we aim to investigate the mechanism of the defect formation in the initial stage of PVT growth based on the optimal temperature gradient conditions. This work will help in understanding the generation of defects in the initial stage of PVT growth and also provide insight into its formation mechanism. In the experiments, 6 inch 4H-SiC (000-1) 4°off-cut conductive substrates were prepared with surface finishing processes. One substrate (#1) was grown through the standard PVT process, while the other substrate (#2) was grown under optimal temperature gradient conditions during the initial stage of PVT growth. These substrates were carefully selected from the boules close to the seed crystal. Investigation of the grown substrates has been carried out in two steps. At first, substrates were characterized by X-ray diffraction omega rocking curve mapping to determine the residual stresses. As shown in Figure 1(a) and (b), residual stress in substrates varied with the initial stage growth conditions, showing tendencies towards either tensile (in the case of #1 sub.) or compressive (in the case of #2 sub.) stresses, and the magnitudes gradually changed toward the [-1-120] direction in both cases. Furthermore, the residual stress magnitude in the substrate grown under the optimal initial stage process (#2) is approximately 4-times lower than that of the substrate grown under standard conditions (#1). Second, X-ray topography (XRT) was used to measure BPD as well as TED densities and their lateral distribution. XRT was performed in 11-28 reflection to observe both BPDs and TEDs. Figures 2(c) and (d) show changes in the densities of BPD and TED in the selected regions, which are left (S3), central (S2), and right (S1) sides of each substrate, and mentioned in Figure 1(a) and (b). As expected from the stress mapping, it was evident that #1 substrate grown under standard conditions exhibited a significantly higher density of defects than of #2 substrate. This result highlights again the effectiveness of the optimal temperature gradient in suppressing defect formation at the initial stage of the growth process. Both substrates displayed contrary trends in the distribution of BPDs along the [-1-120] direction on the (000-1) surface. For instance, the substrate #1, grown without controlling the initial temperature gradient, exhibited a higher BPD density in S1 region than S3 region, associated with the direction of the tensile stress increases in Figure 1(a). On the other hand, the substrate #2, grown with the optimal temperature gradient during the initial stage of growth, showed a lower BPD density in the S1 region and slightly increased in the S3 region. In case of TED instead of BPD, it becomes noticeable that the trend flows exactly opposite to that of BPD. Meanwhile, it was noticed that TED density at the center (S2 region) of both substrates is higher than that of the BPD. This observation may be attributed to the comparatively lower temperature in the S2 region compared to the periphery of the substrate (S1 or S3). Our findings on the characteristics of defects in PVT grown substrates shall be remarkable as the substrate diameter increases, particularly during the initial stages of PVT growth. The growth rate in the S2 region can be enhanced due to the lower temperature, resulting in the reduced migration length of growth species and the promoted 2D island growth, which potentially increases the TED density at the initial stage and facilitate a transition from BPD to TED. [11, 2] Since this work primarily centers on the understanding of defect formation influenced by the temperature gradient during the initial stages of PVT growth, the observed tendencies may differ from those in the upper part of the boule where growth is being completed after a long time growth. Specifically, it is crucial to examine the growth mechanism under various temperature gradients and addressing the instability occurring at the seed-boule interface during the initial growth stages. For a more comprehensive discussion, detailed topographic images will be presented during the conference.

ABSTRACT. We employed polarized light observation under slightly off-crossed Nicols conditions to visualize in-plane shear stress distributions, enabling the identification of edge-component Burgers vectors of threading mixed dislocations (TMDs). This method proved effective for identifying dislocations with large edge-component Burgers vectors, such as <1-100>, known to cause significant leakage in power devices.

Utilizing a 6-inch commercially available SiC epitaxial wafer, observations were conducted. For comparison, synchrotron radiation X-ray topography was performed. Our findings demonstrate that TMDs with <1-100> Burgers vectors display stronger contrasts in polarized light compared to other dislocations, facilitating easier detection. These observations suggest that polarized light observation can serve as a non-destructive and rapid method for detecting potentially detrimental crystal defects in SiC devices.

This study underscores the potential of advanced imaging techniques to improve the quality control of semiconductor materials, thereby ensuring the reliability and performance of advanced power devices.

ABSTRACT. Effective singulation of SiC die, with reduced dicing street widths and subsequent increase in die per wafer is an important technological development for device production. Conventional saw dicing is known to introduce chips and abrasions which serve as sites for crack propagation, which can significantly weaken the individual SiC die, with a detrimental impact on yield by 9% on average across the industry. Plasma dicing of SiC offers an alternative avoiding edge chipping, surface particle damage, and tooling losses related to saw dicing and thermal stresses and particulates associated with laser dicing. Assuming a dicing lane width reduction to 30μm from 100μm (saw dicing), and a die size of 8mm2 (typical of a 1200V SiC device) results in a 3% yield increase across a 200mm wafer. This predicted yield improvement is compounded by the established 9% yield loss typical of saw dicing, predicting an overall yield improvement of ~12% if plasma dicing was utilized over saw dicing. The presented work demonstrates SiC etch optimization and die singulation using a high-density plasma RIE process with etch rates as high as 2.2 μm/min achieved.

ABSTRACT. We recently have focused on bonded substrate a novel substrate comprising an extremely thin monocrystalline 4H-SiC layer bonded to a polycrystalline 3C-SiC substrate. In this study, we fabricated a DMOSFET on a bonded substrate and demonstrated its characteristics for the first time. We fabricated 1.2 kV-class DMOSFETs fabricated on a 4H-SiC singlecrystalline substrate and a 4H-SiC bonded substrate. The fabrication conditions and device structure, including the drift layer, were identical for these devices. We investigated characterization of current–voltage measurements, reverse recovery and forward-bias degradation. The result showed that bonded substrates have significant advantages as substrates of MOSFETs owing to their low on-resistance and long-term reliability such as low reverse recovery current and suppression of forward-bias degradation.

ABSTRACT. Magnetometry plays a crucial role in a wide range of remote sensing applications. On Earth, it’s used for GPS-denied navigation, geological surveying, and submarine detection. For scientific missions in space, magnetometer-equipped spacecraft make measurements that help answer questions in the planetary science, Earth science, and Heliophysics communities. Typically, magnetometers are positioned on a long boom to minimize magnetic interference from other instruments and spacecraft subsystems. To ameliorate the formulation and implementation cost and reliability challenges associated with spacecraft booms, an appealing alternative approach is to use numerous small sensors on a shorter boom to perform gradiometry, to map and cancel self-induced magnetic noise [1].

To achieve this, new sensors with extremely low SWaP (size, weight, and power) and the ability to measure magnetic fields with absolute accuracy are required. Those would also allow for accommodation on small platforms like CubeSats, which enables new science.

Here, we discuss different kinds of optically pumped quantum magnetometers based on spin defects in solid-state systems, focusing on silicon vacancy quantum center (VSi) in silicon carbide (SiC). The basic principle relies on maintaining resonance of the involved spin system, by compensating and thus measuring external fields using cancellation coils. This simple approach offers a robust technique for dual mode vector and scalar magnetometry. In this work:

(1) We present different readout mechanisms [2] based on ODMR (optically detected magnetic resonance), EDMR (electrically detected magnetic resonance), and RFDMR (RF detected magnetic resonance). While ODMR shows higher sensitivity, EDMR offers a simpler, purely electrical approach that can be improved by optical pumping using UV light, improving EDMR sensitivity down to 30nT/√Hz.

(2) Additionally, we will discuss progress towards a novel approach with a hybrid version (RFDMR) based on a recently developed room-temperature maser using SiC [3,4]. This approach not only benefits from the advantages of each system—a narrow linewidth and an electrical readout—but also, due to the superradiance in the masing regime, allows us to narrow the linewidth beyond the state-of-the-art limit and use an electrical readout in a frequency range far above the noise of the modulation electronics.

(3) We show progress in SiC VSi defect engineering for magnetometer performance optimization, identifying the electron irradiation parameters leading to a sensitivity increase down to 40nT/√Hz. We also show challenges in excitation source stability, and the mitigation path leading to 1nT/√Hz with existing samples, as well as approaching sub-nT sensitivities by further irradiation granularity.

Overall, the recent progress in advancing performance metrics of quantum solid state sensors, specifically magnetometers, as well as the maturing of operation modes leading to reduced complexity and resource consumption, shows that this technology field stays highly promising and exciting. Competitive single-digit nanotesla performance for planetary science is within reach.

[1] Cochrane, C.J., Murphy, N., Raymond, C.A. et al. Magnetic Field Modeling and Visualization of the Europa Clipper Spacecraft. Space Sci Rev 219, 34 (2023) doi:10.1007/s11214-023-00974-y [2] A. Gottscholl, C.J. Cochrane, H. Kraus, Operation Modes of an Optically Pumped 6H-SiC Quantum/Solid State Magnetometer, IEEE Sensors (2024), doi:10.1109/JSEN.2024.3391191 [3] A. Gottscholl, M. Wagenhöfer, V. Baianov, V. Dyakonov, A. Sperlich, Room-Temperature Silicon Carbide Maser: Unveiling Quantum Amplification and Cooling, arXiv:2312.08251(2023) [4] A. Gottscholl, M. Wagenhöfer, M. Klimmer, S. Scherbel, C. Kasper, V. Baianov, G. V. Astakhov, V. Dyakonov, A. Sperlich, Superradiance of Spin Defects in Silicon Carbide for Maser Applications, Front. Photonics 3:886354. doi:10.3389/fphot.2022.886354

ABSTRACT. Quantum magnetometers based on spin transitions of solid-state point defects can achieve excellent sensitivity and spatial resolution at ambient conditions, in a convenient, stable material platform. The diamond nitrogen vacancy (NV) center has dominated this field, but several different atomic defects in silicon carbide (SiC) provide similar advantages in a host material far more amenable to large-scale growth, fabrication, and integration with existing semiconductor technologies. We explore the negatively-charged, h-site silicon vacancy (V2) in 4H-SiC, which, like the diamond NV center, is an intrinsic defect, with an intersystem crossing allowing for optical initialization and readout of a spin-3/2 ground state at room temperature [1-2]. However, lower optical contrast and shorter coherence times prevent it from equaling diamond-NV magnetometers. To fully employ this defect it is necessary to understand the limiting dephasing sources and extend its coherence times. Here, we compare V2 ensembles created by electron irradiation in natual-abundance (29Si = 4.7%, 13C = 1.1%) and isotopically-purified (29Si = 0.01%, 13C = 0.15%) SiC epilayers. By reducing spin-spin interactions with the nuclear-spin-carrying isotopes 29Si and 13C, both inhomogeneous (T2*) and homogeneous (T2) dephasing times are improved by more than a factor of 10 [3]. With this dephasing source suppressed, T2* and T2 decrease with increasing irradiation dose, showing that irradiation-produced effects are now a limiting factor. At the lowest doses, T2 approaches its spin-relaxion (T1) limited value. We also find that T2* and T2 vary with magnetic field strength (Figure 1a-b), the former due to state mixing at the spin level anticrossings, the latter due to electron spin echo envelope modulations (ESEEM). ESEEM arise due to interaction with spin-carrying nuclear isotopes [2], and we explore how their behavior changes in natural-abundance vs isopure SiC. Finally, we continue to explore ways to make full use of the different Δms=1 transitions available in this spin-3/2 system. Simultaneously monitoring both {1/2, 3/2} transitions can effectively double our magnetic-field sensitivity. Meanwhile, the {-1/2, +1/2} basis is insensitive to shifts in the zero-field splitting (ZFS), such as those due to static strain or electric fields, resulting in a longer T2* but no change to T2 (Figure 1c-d). Benefitting from both isotopic purification and careful implementation of this choice of bases, we demonstrate DC magnetic field sensitivites as low as 4 nT/√Hz [4] and expect to achieve few-hundred pT/√Hz.

This work was supported in part by the U.S. Office of Naval Research, the Defense Threat Reduction Agency, and an appointment to the NRC Research Associateship Program at the U.S. Naval Research Laboratory administered by the Fellowships Office of the National Academies of Sciences, Engineering, and Medicine.

[1] P. G. Baranov, et al., Phys. Rev. B 83, 125203 (2011). [2] S. G. Carter, et al., Phys. Rev. B 92, 161202 (2015). [3] I. Lekavicius, et al., PRX Quantum 3, 010343 (2022). [4] I. Lekavicius, et al., Phys. Rev. Applied 19, 044086 (2023).

ABSTRACT. Spin defects in wide bandgap semiconductor attract attention for quantum technologies since they act as quantum bit (qubit) and quantum sensor. Negatively charged silicon vacancy (Vsi) is known as a such quantum defect. For quantum sensing based on Vsi, optically detected magnetic resonance (ODMR) of the ground state is used for magnetic field sensing. However, ODMR of the excited state is applied for temperature measurement because the ground state ODMR does not have any temperature dependence. In our previous study, temperature sensing at a local area in a SiC pn diode has been demonstrated using Vsi created by Particle Beam Writing (PBW) technique. In addition, Yamazaki et al. developed the simultaneous resonated optically detected magnetic resonance (SRODMR) method by which the sensitivity of temperature sensing is improved. Since temperature at local areas in devices is important to understand the health of devices, Vsi locally created in SiC devices by PBW can be applied to a tool for the diagnosis of SiC devices. Of course, other information such as electrical current and electric field as well as temperature are required to establish a diagnosis methodology for SiC devices. In this study, we simultaneously measure magnetic field induced by electrical current and temperature in local areas in SiC devices. The sample used in this study has a structure consisting of an aluminum (Al) line formed on an oxide layer on 4H-SiC. Using PBW (0.6 MeV-He ions), irradiation spots were formed near the Al line. For the magnetic field, the results obtained from the experiment well agree with the results obtained by calculation. For temperature, the value for all dots is around 315 K and no significant difference between each peak was observed. This indicates that temperature slightly increases by electrical current, but temperature gradient is not observed.

ABSTRACT. In typical SiC semiconductor devices, SiC is thermally oxidized which leads to the formation of insulating amorphous SiO2 (a-SiO2) layers [1]. Unlike silicon, where a stable thermal oxide can be readily grown, the formation of a high-quality oxide layer on SiC is still challenging. Standard thermal oxidation processes often result in many interface defects that can introduce defect levels within the band gap of SiC and act as traps for carriers. By confocal microscope scanning, single photon emitters upon 532-nm illumination were found at the interface with unknown origin [2, 3] where the number of emitters can be reduced but not fully eliminated by post-oxidation treatments [4, 5]. In this study, we focus on the origin of the reported single photon emitters at the 4H-SiC/a-SiO2 interface which exhibit high-energy local vibration modes in the photoluminescence (PL) spectrum that can be associated with carbon clusters with short C-C bonds [2, 3]. We model the interface, introduce defects and calculate their optical properties by means of density functional theory (DFT). The atomistic model of the 4H-SiC/a-SiO2 interface is created by molecular dynamics simulation with several steps to obtain the final starting model. All the first-principles calculations are performed using DFT within the projector augmented wave potential plane-wave method, as implemented in the VASP. The screened hybrid density functional of Heyd, Scuseria, and Ernzerhof (HSE06) is employed to calculate the electronic structure which is able to reproduce the experimental band gap. The single Γ-point scheme is convergent for the k-point sampling of the Brillouin zone (BZ). The excited states were calculated by ΔSCF method. We applied 10.72×12.38 Å2 lateral size and SiC width of 20.26 Å to embed the defects. The thicknesses of the a-SiO2 and vacuum layers are 14.83 Å and 15.00 Å, respectively. The atomistic model of 4H-SiC/a-SiO2 interface is shown in Fig. 1(a). Apart from carbon clusters, the interface transition region also encompasses paramagnetic dangling bonds, Si-Si dimers, and oxygen-related defects. For the C-related defects (Cn, where n is the number of C atoms), the configurations exhibit increased complexity due to structural changes in the interface transition and the diverse combinations of defect atoms. We considered more than 120 defect configurations in our study with n=1…4. These distinct localized structures of defects lead to significant variations in the distribution of defect levels among them. Consequently, the vertical excitation energies also span a wide range (e.g., the vertical excitation energies for C-related defects range from 0.5 to 3.1 eV) [Fig. 1(b)]. Silicon dangling bonds (Sid) and Si-Si dimer defects, on the other hand, are primarily situated on the SiC surface, exhibiting a relatively uniform defect structure. The position of defect levels remains generally constant, resulting in a relatively fixed energy for vertical excitation. Particularly for Si-Si dimer defects, the defect levels are predominantly located near the valence band maximum, with the vertical excitation energy typically around 3.2 eV. Subsequently, we simulated the PL spectrum for carbon-related defects and Si-Si dimer defects that are relatively stable structures. For carbon-related defects, the zero-phonon-line (ZPL) is predominantly distributed in the range of 1.7 to 2.7 eV. As for Si-Si dimer defects, the ZPL peak fall in the deep blue region. These observations align with previous experimental finding on PL centers at the interface with ZPL peaks ranging from 1.5 to 2.5 eV upon illumination with 532-nm and 633-nm laser, respectively [6, 7]. We find that these PL centers can be well explained by carbon-clusters at the interface. We note that we have recently identified carbon-clusters in bulk 4H-SiC [8]. These carbon clusters appear due to incomplete oxidation of SiC at the interface in a complex environment consisting of silicon-oxygen bonds too. The concentration of these PL centers may be reduced to an isolated level resulting in quantum emission at the 4H-SiC/a-SiO2 interface [3] that show sharp high-energy local-vibration-modes (LVMs) between 120 and 200 meV. We find that many of the considered carbon-related emitters (around 100 configurations) exhibit high energy modes. Notably, the carbon-cluster consisting of four carbon atoms produce very similar PL spectrum to the observed one with a ZPL peak at around 2.1 eV [3] so the origin of those quantum emitters is tentatively identified. We note that PL spectra significant vary with the actual environment. Because these carbon clusters are formed during thermal oxidation of SiC which is a stochastic process with different environment, it is principally impossible to form indistinguishable color centers, thus it might be difficult to use them as a resource for quantum technologies. We note that most of these color centers occurs in their neutral charge state with bound exciton excited state [8] and they have singlet ground state. These defects at the interface introduce a myriad of deep levels in the band gap of SiC [Fig. 1(d)]. These defect levels, characterized by their diverse structures, become virtually pervasive throughout the entire band gap. In the context of quantum sensor applications, the broad distribution and varying magnitudes of deep levels from the interface defects can lead to spectral broadening and shifts in the emission peak of the shallow implanted defect qubits, potentially impeding the accurate initialization and readout in quantum sensor applications. Moreover, the defect levels may impact charge transfer processes and may temporal or permanent photostability issues of the quantum sensor. We conclude from this study that the concept of surface termination of 4H-SiC should be radically changed for quantum sensor applications. We acknowledge the support from EU Commission (SPINUS project, Grant No. 101135699), NKFIH Grant No. 2022-2.1.1-NL-2022-00004 (Quantum Information National Laboratory of Hungary). [1] P. Fiorenza, F. Giannazzo, and F. Roccaforte, Energies 12, 2310 (2019). [2] S.-i. Sato, T. Honda, T. Makino, Y. Hijikata, S.-Y. Lee, and T. Ohshima, ACS Photon. 5, 3159 (2018). [3] B. Johnson et al., Phys. Rev. Appl. 12, 044024 (2019). [4] R. Kosugi, W.-J. Cho, K. Fukuda, K. Arai, and S. Suzuki, Journal of Applied Physics 91, 1314 (2002). [5] T. Kobayashi, T. Okuda, K. Tachiki, K. Ito, Y.-I. Matsushita, and T. Kimoto, Appl. Phys. Exp. 13, 091003 (2020). [6] A. Lohrmann et al., Nature Communications 6, 7783 (2015). [7] A. Lohrmann et al., Applied Physics Letters 108, 021107 (2016). [8] P. Li, P. Udvarhelyi, S. Li, B. Huang, and A. Gali, Physical Review B 108, 08201 (2023).

ABSTRACT. In this work, we discuss the radiation damage studies of a new, large area, p-n junction silicon carbide device developed by the SiCILIA collaboration. We have studied the general performances of several devices, as a function of fluence, irradiated in different experimental conditions with different beams. A standard p-n junction silicon detector was also irradiated for comparison. The new detectors manifest excellent performance in terms of stability of the main parameters, linearity, defect distribution, charge collection efficiency, energy resolution, leakage current, etc. Experimental results evidence a radiation resistance of SiC devices more than two order of magnitude higher than Si devices. The new construction technology applied to silicon carbide material has made it possible to create very robust devices with excellent performance.

ABSTRACT. This study presents a systematic investigation of the influence of gold nanoparticles on the performance of a metal-semiconductor-metal self-powered 4H-Silicon carbide ultraviolet photodetector (SiC-UVPD) through nonsymmetric contact phenomenon under 254 nm UV-light exposure. Ultraviolet photodetectors attract great interest due to their broad range of applications such as optical communications, pharmaceutical, and chemical analysis, environmental sensing, flame detection, biomedical electronics, missile detection, and space communications. Self-powered photodetectors are desirable devices for green energy applications due to their unique advantages such as smaller footprints and wireless operation. Thus, improving the performance of these devices has become very crucial for the fabrication of efficient, sustainable, energy and environment friendly devices.

Metal nanoparticles on a semiconductor surface can enhance the scattering of the incident photons and increase the optical absorption around each particle on the active region of the semiconductor leading to a performance enhancement for the photodetector. Considering this, the SiC-UVPD was fabricated via a highly practical and cost-effective fabrication scheme. A physical mask and a sputter coater system were used to deposit asymmetrical electrodes with a 50 µm spacing. To investigate the influence of gold nanoparticles on the performance of the photodetector, the surface of the fabricated SiC-UVPD was coated with gold for 5 s, 10 s, 15 s, and 20 s deposition times. Following each deposition step, the SiC-UVPD was heated at 150°C for five minutes to transform the deposited gold film into nanoparticles. Fig. 1 shows a scanning electron microscopy image of the Au nanoparticles on the SiC-UVPD surface and a schematic diagram of the measurement setup of the self-powered SiC-UVPD. The size of the Au nanoparticles ranges from 30 nm to 40 nm for 15 s and 20 s deposition times, respectively.

To evaluate performance characteristics of the SiC-UVPD, current-time (I-t) measurements were performed through 20-s multiple cycles under two UV light at 0 V through a sourcemeter (Keithley 2634B), which is attached to a probe station and controlled with a Labview program. Fig. 2 displays the I-t plots of the SiC-UVPD following the applications of Au nanoparticles with different surface densities (from 5-s to 20-s Au deposition) at 0 V, revealing strong enhancements in photocurrent. In fact, the ION/IOFF ratio gradually increases with the increase of Au deposition time reaching to a maximum on/off current ratio of 934 with 15-s Au deposition under 254 nm of UV light. However, a slight decrease on the ION/IOFF ratio (870) is observed with 20-s Au deposition under 254 nm UV light. The fabricated SiC-UVPD exhibited a very good sensitivity of 9.34 x 104, great responsivity of 0.30 A/W, and excellent detectivity of 7.0 x 1011 cm. Hz1/2.W-1 under 254 nm UV light without any external power. In fact, the specific detectivity of the self-powered SiC-UVPD improved by 70 % following the application of Au nanoparticles. Combined with the practical and cost-effective fabrication, the self-powered SiC-UVPD can lead the path towards novel, high performance, emerging sustainable energy, and eco-friendly optoelectronic devices particularly for harsh environments.

ABSTRACT. In this work, for radiation hardened image sensor, SiC CMOS active pixel sensors (APS) with embedded UV photodiode was suggested and demonstrated. In our previous study on the SiC CMOS image sensor, after high gamma-ray radiation of 2 MGy, the radiation effect on the device was mainly caused at the surface of SiC photodiode. In this work, we introduced an embedded photodiode in 4H-SiC CMOS APS for preventing radiation effects at the interface. And then high quantum efficiency of 85% was achieved. We fabricated 4H-SiC APS with the embedded PD, and these devices were successfully demonstrated.

ABSTRACT. A Schottky diode, i.e. a metal-semiconductor junction, is among the simplest yet fastest electronic components. The underlying general theory has been developed by Schottky for the stationary, i.e. DC case, where electronic transmission processes through or over the barrier are associated with reliable absorption on the opposite electrodes, resulting in rectification. When operating it at high frequency, it is well known that the RC timescale sets an extrinsic limit. We present a series of experiments that address even higher frequencies using the electrical fields provided by intense light pulses, thus exploring the so far unattainable intrinsic limitations of Schottky rectification.

Using graphene as a metal and silicon carbide (SiC) as semiconductor, epitaxial graphene on 4H-SiC (0001) provides a monolithic and extremely robust Schottky diode. Its current-voltage characteristics can accurately be described by Schottky’s model . When driving such a diode at high frequency, an RC damping at around 400 GHz could be determined [1]. Notably, Schottky’s description is fully consistent from DC to this frequency range. Similar devices have been studied before under perpendicular incidence [2], where ultrafast coherent excitation-tunneling processes faster than femtosecond scales could be identified.

Our approach to study rectification beyond RC limitations is to replace the electrical voltage by intense light fields as they occur in ultrashort pulses, which now are applied from the sidewall (see Fig. 1). SiC devices using epitaxial graphene are extremely well suited for this case, because of their robustness and high optical transparency.

In a first series of experiments, we applied mid-IR pulses at frequencies of 14 THz up to 82 THz, hence well above the RC limits. In reverse bias, there is a clear electrical response to the applied light field, hence rectification. By comparison with Schottky’s model, we find good but not yet perfect agreement. This motivated us to revisit the tunneling process at fast timescales. When the transfer time of electron motion through the barrier is similar to the oscillatory motion of the barrier itself, a semiclassical correction to Schottky’s theory is straightforwardly derived that describes partly oscillatory motion of the electron and an incoherent recapture mechanism. With this correction and the DC parametrization of the diode, the rectification in our experiments can be accurately predicted [3].

We have now adapted the same experimental strategy to near-IR pulses, with a center frequency of 375 THz. Simultaneously, we have chosen a slightly lower Schottky barrier. The result is again a field driven current contribution, as identified by a carrier-envelope phase dependent contribution. It increases with an effective power law. In order to understand this behavior, the Schottky model with its balance of tunneling and absorption turns out to be inappropriate. Rather, a time-dependent Schrödinger equation, hence a fully coherent treatment catches the experimental characteristics. This crossover of the physical description can be understood by a Keldysh-parameter close to unity.

ABSTRACT. Review for Resonac’s SiC Epiwafer Development

H. Kanazawa1) 1) Device Solutions Business Unit, Resonac Corporation, 1505 Shimokagemori, Chichibu-shi, Saitama 369-1893, Japan E-mail: kanazawa.hiroshi.xhjhc@resonac.com

In January 2023, Showa Denko and Hitachi Chemical were integrated to form the functional chemical manufacturer Resonac. Semiconductor and electronic materials currently account for more than 30% of Resonac Group's sales among its lineup of chemical products, and are expected to achieve the highest operating income by segment. Resonac’s SiC activities for power devices have been started from 1998 and epitaxial wafer business is one of most focused business area in Resonac. SiC devices exhibit a lower specific on-resistance and higher breakdown voltage. However, due to the market requirement for further reliability robustness and the increase for power density of the power module, several defects and dislocations in the epilayer and substrate make this difficult to achieve. Especially, the trend of increase for current density in the device chips requires the reduction of basal plane dislocation (BPD), which is lead to the expansion of the stacking fault during a forward biased operation in a bipolar device. BPDs inducing the bipolar degradation [1] in the epilayer has been eliminated by improving the growing method with conversion to threading edge dislocations (TED) at the epi/sub interface [2], and the BPD detection technique has been also improved using photoluminescence (PL) and X-ray topography[3]. It is known to be difficult to completely determine the device yield using such detection methods, because four types of BPDs converted near the substrate, namely I. At the substrate/buffer layer interface, II. In the buffer layer, III. At the buffer/drift layer interface, IV. Without conversion, could not be identified. (see Fig. 1) We detected the short BPDs using a mirror electron microscope (MEM) technique [4], and we compared the BPD to TED conversion in epilayers grown with the conventional and improved methods. (see Fig. 2) Through the review of latest technical update for our epi-wafer, especially for our best grade of epi [High Grade Epi: 1st, 2nd and 3rd], the status of our Development of epi-wafer is presented.

If you want any acknowledgements for your abstract, they should go here.

[1] M. Skowronski and S. Ha, J. Appl. Phys. 99 (2006) 011101. [2] N. Ishibashi, K. Fukada, A. Bandoh, K. Momose, and H. Osawa, Mater. Sci. Forum 897 (2017) 55. [3] T. Tawara, T. Miyazawa, M. Ryo, M. Miyazato, T. Fujimoto, K. Takenaka, S. Matsunaga, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimot, and H. Tsuchida, J. Appl. Phys. 120, (2016) 115101. [4] M. Hasegawa, K. Ohira, N. Kaneoka, T. Ogata, K. Onuki, K. Kobayashi, T. Osanai, K. Masumoto and J. Senzaki, Mater. Sci. Forum 1004, 369-375 (2020).

ABSTRACT. Multiple commercial platforms are now available for silicon carbide (SiC) epitaxy on 200mm wafers. Improvements in 200mm wafer quality and quantity have accelerated the need to evaluate different platforms for quality, throughput, cost of ownership, and ultimately device yields. In preparation for high volume manufacturing at the John Palmour Manufacturing Center (The JP), Wolfspeed has been evaluating different reactor platforms across our current and future device portfolios. Conventional wisdom suggests that thicker epitaxial layers will be more challenging on thinner wafers with respect to shape and defectivity metrics. In this report we will share relative comparisons of thickness and doping uniformity, defectivity, and other parameters critical to meeting device requirements on 350um and 500um thick 200mm wafers. Initial results at 13um show thinner substrates will not be problematic for epitaxial growth, but stress-induced basal plane dislocations (BPDs) and other defects are expected to reduce usable area on wafers with increasing growth. Trends in wafer shape and defect evolution for epitaxial thicknesses of up to ~100um will be compared for doping levels relevant for high voltage devices. Additional metrology and comparisons will be provided where possible for potential offsets observed in both wafer thickness and/or platform dependencies.

ABSTRACT. The well-known basal plane dislocations (BPD) in SiC are high-voltage bipolar device killers that source Shockley-type stacking faults in the presence of an electron-hole plasma and cause forward voltage drifts in bipolar devices [1]. It has been imperative to develop ways to prevent the expansion of these extended defects where multiple research groups have been successful in mitigating their propagation from the substrate into the epitaxial layer [2-5]. Of course, BPD free substrates are the ideal solution, and while these substrates are being developed, most substrates contain ~200-1000 cm-2 BPDs. For most SiC device applications, the current mitigation processes that reduce these defects is sufficient. However, for applications which require high pulsed power current density or high surge current capability, the injected carrier concentration is significant enough to expand converted BPDs from the substrate into the epitaxial layer. In the last ICSCRM conference, we reported a new process to mitigate the BPD expansion at power densities up to 13 kWcm-2 UV excitation using a H2 etch before the buffer layer growth, followed by a H2 growth interrupt prior to the low doped epitaxial layer growth. Here, we will report results from comparisons of H2 etching to Ar annealing and the use of H2 versus Ar during growth interrupts to prevent BPD expansion with the goal of understanding the mechanism of the suppression of BPD expansion. SiC epitaxial layers were grown using a horizontal hot-wall CVD reactor with SiH4 (2% in H2) and C3H8 on 4° off-axis substrates toward the [11-20] that are known to have BPDs. A H2 etch or Ar anneal was performed before the buffer layer (BL; n-type ~ 2x1018 cm-3) growth while a growth interrupt in H2 or Ar was conducted prior to the intentionally low doped (n-type ~ 5x1015 cm-3) drift layer. Fig. 1 shows a schematic of the growth schedule. The H2 etch or Ar anneal was carried out at 1665 °C and 70 mbar for 50 min. During the growth interrupt, the sample was cooled to 1000 °C in either 80 slm H2 or 5 slm Ar at 100 mbar. Ultraviolet photoluminescence (UVPL) imaging was used to image the samples before and after UV stressing up to 13 kWcm-2. The film thickness was evaluated by Fourier transform infrared analysis, quality by X-ray diffraction and doping concentration via Hg probe CV measurements. As reported at the ICSCRM 2023 conference, the H2 etch and H2 growth interrupt prevented BPDs from expanding under UV stress of 13 kWcm-2 and it was believed that the H2 treatment specifically had inhibited this expansion. There has been a report where the role of H2 on preventing BPD faulting in implanted samples was not effective [6]. To confirm the role of H2, we performed a growth using the same conditions as the H2 etch/interrupt, however, an Ar anneal at 1665 °C was used instead of a H2 etch and the growth interrupt was conducted in an Ar atmosphere instead of H2. The sample was UV stressed up to 1000 Wcm-2 and it was found that four BPD expanded from the substrate into the epilayer, see Fig 2. For comparison, a sample grown with a double H2 etch (before the buffer layer growth and drift layer) and a sample grown with a H2 etch plus H2 growth interrupt did not produce faulting at the same power density. The primary difference in our sample is the in-situ H2 treatment vs implantation, which does not create implant damage. We will present detailed parametric results of samples grown with various etching/ annealing, growth interrupts, anneal times, buffer layer thickness, gas flow rates and interrupt temperature, both in H2 and Ar.

[1] J.P. Bergman, et. al., Mater. Sci. Forum Vol. 353-356, 299 (2001). [2] N.A. Mahadik et.al., Mater Sci Forum 858, 233 (2016). [3] R. E. Stahlbush, et al., Appl. Phys. Lett. 94, 041916 (2009). [4] M. Kato, et al., Sci. Rep., 12, 18790 (2022). [5] N.A. Mahadik et. al., Appl. Phys. Lett., 100, 042102 (2012). [6] M. Kato, et. al., Japanese J. Appl. Phys., 63, 020804 (2024).

ABSTRACT. In this paper, we have investigated the influence of growth-interruption during buffer layer growth on killer defect density in SiC epilayer grown over 4H-SiC (0001) substrates. We have observed that the growth-interruption method reduces total killer defect density by ~45(±5)%. Implementing growth-interruption in the buffer layer is a novel approach to mitigate epitaxial defects such as in-grown stacking faults (SFs), triangular defects, and basal plane dislocations (BPDs) in the drift layer and provide an extra margin to bipolar degradation by terminating BPDs early in the heavily doped buffer layer. The defect reduction mechanism in presence of hydrogen has been simulated using Kinetic Monte Carlo (KMC) simulations.

ABSTRACT. In this paper we review the FinFET technology, from concept , device design, fabrication to challenges and opportunities. The FinFET is a new concept in Silicon Carbide power devices [1-4]. In Silicon, the FinFETs are used in ULSI applications to increase the gate density (3nm gate) and improve the subthreshold slope. In Silicon Carbide, the FinFET has a very different purpose, that of significantly increasing the effective mobility [1-4]. The increase channel mobility results directly in a lower specific on-state resistance and aa a result higher device efficiency or indirectly could lead to reliability improvement, longer short-circuit endurance or lower Miller capacitance which results in faster and less lossy commutation.

Numerous studies have been dedicated to understanding the interface between the oxide and Silicon Carbide and improving the electron mobility at this interface [5-7]. It has been found that there are several mechanisms limiting the mobility, among which the most important is the Culombic scattering, followed by phonon and surface scattering [8]. Several methods involving oxide deposition and annealing (e.g. in Hydrogen [7]) have been investigated in order to minimize the interface charge and traps which are responsible for Coulombic scattering, The motivation of this work is to provide an alternative approach, based on FinFET structure to improve the effective mobility at this interface.

Fig. 1 shows schematically a FinFET designed for 1kV breakdown. Different pitches between adjacent trenches (i.e. fins) have been designed and fabricated. The FinFET effect is observable below 250nm. We define the mild FINFET region, around the 150nm line, where the two depletion regions associated with adjacent trenches meet and the charge in the depletion region is restricted to grow. In the strong FinFET effect full bulk inversion is established and the depletion region in the p well is no longer present. This is below 50nm. A SEM photograph of a fabricated FinFET with 144nm fin is shown in Fig.2 [3]. Fig. 3 shows the transfer characteristics [3], highlighting the higher subthreshold slope due to the increased effective mobility and lower threshold voltage of FinFET structures. Fig. 4 shows the difference in band diagrams of a FinFET compared to a classical structure. It is worth noting that the electron charge in the strong FinFET is significantly increased while in the middle of the bulk channel the transversal electric field is zero. The threshold voltage can decrease significantly (towards a normally-on structure) with lower fins, however, interestingly, the variation of the threshold voltage with temperature is milder for the FinFET when compared to a classical FET. This is proven by both experimental results and TCAD simulations which are in excellent agreement. The increased mobility in the FinFET (by more than 2X even in the mild geometry) resulted in a record FOM as shown in Fig. 6. Acknowledgement and References I would like to acknowledge the team at Mirise, Japan, H. Fujioka, H. Tomita, T. Nishiwaki, T. Kumazawa, M. Kumita, M. Okuda, H. Fujiwar and others for the work done on FinFETs and in particular the advanced fabrication of these devices. I would also like to thank Q.Wang for his contribution to FinFET modelling. [1] F. Udrea and H. Kang, UK 805288.6, priority date 29.03.2018, published 02.10.2019 [2] T. Kato et al., 32nd ISPSD, Vienna, 62 (2020). [3] F. Udrea et al., 33rd ISPSD, Nagoya, 75 (2021). [4] F. Udrea et al, 34th ISPSD, Vancouver, 253 (2022) [5] M. Cabello et al., Mater. Sci. Semicond. Process. 78, 22 (2018). [6] T. Kobayashi et al., Appl. Phys. Express 13, 091003 (2020). [7] T. Kimoto. Proc. Jpn. Acad., Ser. B 98 (2022) [8] K. Naydenov et al, . Engineering Research Express. 3 (2021)

ABSTRACT. SiC power MOSFETs are replacing Si devices in the blocking voltage range from 600 to 6500 V with substantial energy saving in various electric systems courtesy to their low on-resistance and fast switching. This trend has been supported by improved channel mobility using a nitridation technique such as NO Post Oxidation Annealing (POA) and now often by using nonplanar structures with higher mobility on non-basal planes [1]. However, the SiO2/SiC interface, POA, has a high density of interface traps (Dit) especially due to carbon-related defects. This is a major cause of reduced channel mobility and threshold voltage instability. Hence a clear industry trend [2] is to replace thermal SiO2 by quality deposited SiO2. Among dielectric deposition techniques, atomic layer deposition (ALD) is widely used due to best-in-class quality of the oxides at low deposition temperature, superior uniformity and conformality, precise control of thickness [3]. The capability to engineer the SiO2/SiC interface by in-situ surface treatment and plasma enhanced ALD (PEALD) of interfacial layers are expected to play a significant role in the manufacturing of high performance SiC MOSFETs. In this study, we utilize cutting-edge ALD technology from Beneq TFS 200 R&D and Transform® high-volume manufacturing cluster tools to fabricate SiO2 dielectric stacks for 4H-SiC MOS capacitors. Furthermore, we investigate in-situ plasma-based surface treatment methods and advanced PEALD techniques with Atomic Layer Annealing (ALA) [4] to tailor the SiC/dielectric interface. The standard fabrication process for 4H-SiC MOS capacitors involves three primary steps: i) plasma precleaning (PP) of the SiC surface to eliminate electrically active defects such as carbon clusters and oxycarbidic phases, ii) deposition of a plasma-based SiO2 interfacial layer (IL) to enhance leakage current, breakdown voltage, and quality of the SiC/SiO2 interface, and iii) deposition of a thick high-quality SiO2 thermal ALD dielectric layer. To investigate the role of the IL, we here used either a 5nm SiO2 by PEALD or a 5nm SiO2 by PEALD with ALA. Fig. 1 (a,b) illustrates measured CV characteristics for devices after N2 anneal, and (c) shows extracted hysteresis, (d) flat band voltage, and (e) trapped charge. The PP/IL/SiO2 samples with PEALD SiO2 IL exhibit a sharp CV profile with a narrow hysteresis of 0.5V and a VFB of 1.63V. Furthermore, devices with the PEALD SiO2 ALA IL (PP/ALA IL/SiO2) demonstrate a substantial reduction in hysteresis to 0.09V, accompanied by a nearly ideal VFB of 0.94V. These enhancements are attributed to the improved quality of the SiO2 IL by PEALD with ALA, which results in significantly lower charge trapping at the SiO2/SiC interface from - 3 × 1011 to 6 × 1010 cm-2 which is near the detection limit. Given potential charge trapping in the bulk of the dielectric layer, we revised the deposition conditions for the ALD SiO2 process itself by increasing the deposition temperature. Fig.2 illustrates the electrical characteristics of MOS capacitors fabricated with improved ALD SiO2 deposition conditions using PP only. These devices exhibit a steep CV curve (Fig.2a) and a hysteresis of 0.02V (Fig.2b), representing a 25-fold reduction compared to PP/IL/SiO2 devices. Additionally, the VFB is measured at 0.96V (Fig.2c). The current density-voltage curve (Fig.2d) shows a low leakage current of 2 × 10-7 A/cm2 @4.8 MV/cm (Fig.2e) and a high breakdown voltage of 11.5 MV/cm (Fig.2f), aligning closely with devices featuring SiO2 dielectric layers prepared by high-temperature oxidation process, particularly in terms of breakdown voltage [5]. Currently, devices with PEALD with ALA IL films and an additional low temperature nitridation step are being analyzed for revisited SiO2 deposition conditions, with targeted Dit values well below 1 × 1011 cm-2eV-1. These findings, along with ToF-ERDA elemental composition analysis, will be presented during the conference. Furthermore, the effect of post-deposition annealing with NO and N2 will also be discussed.

ABSTRACT. Developing an entire process flow for trench structures from the ground up is a time-consuming, expensive, and challenging endeavor, particularly when working with fabrication facilities that lack trench process design kit support. Therefore, our objective is to create a 1.2 kV SiC Trench MOSFET structure that employs the simplest possible process flow and validate its feasibility through TCAD simulation as well as unit process fabrication. This paper introduces the novel concept and fundamental characteristics of the compact 1.2 kV SiC Trench MOSFET with Bottom PWell (BPW), illustrating its optimization using process parameters derived from unit process development. The proposed device is featured by a shallow trench structure with a BPW that can be implemented by ion implantation without necessitating multi- MeV ion implanter.

ABSTRACT. Although SiC MOSFETs using silicon oxide (SiOx) as gate dielectric are commercially available, with several studies demonstrating their performance and reliability [1-2], the use of high-K (HK) materials for the realization of gate-stacks has demonstrated potential for the fabrication of the next generation of high-performing SiC MOSFETs. This is because HK-based devices offer significant advantages over SiOx-based technologies in terms of improved on-state resistance and minimal threshold voltage hysteresis (VTH,HYS) during switching [3-4]. The reliable and stable operation of SiC MOSFETs is often hindered by the high device-internal electric fields encountered under operating conditions and by the defectivity of the semiconductor-insulator interface leading to charge trapping effects. Reliability/stability characterization relies on accelerated testing occurring under highly accelerated gate bias stress conditions where absolute care must be devoted to avoiding triggering degradation mechanisms not representative of operational conditions. This study addresses the response of an HK-based SiC MOSFET device to high gate voltage stress, comparatively to a SiOx reference, to define the onset of instability mechanisms which are not encountered under operational conditions. The peculiarities of the planar SiC MOSFETs under consideration in this study are summarized in Table I. Additionally, Fig. 1(a)-(b) report the DIT measurements obtained on MOS-capacitors (n-epi) and a schematic representation of the conduction/valence band offset, respectively, representative for the two gate-stack configurations. Comparatively, the HK device exhibits a better semiconductor-insulator interface quality over the SiOx sample, while offering a lower band offset. The DUTs have been exposed to the stress/measurement routine summarized in Fig. 1(c). Here, a positive high voltage gate bias is applied to the DUTs for a total stress time of up to 10 s, while the threshold voltage (VTH) is monitored at regular intervals (10-100 ms) by fast ID-VGS sweeps [5]. The applied gate bias voltages have been calibrated to result in electric field stresses in the dielectrics in the 6 MVcm-1 to 9.5 MVcm-1 range (factors over maximum operating field conditions). Fig. 2(a)-(b) report the VTH monitoring results for the SiOx and HK samples, respectively. For the SiOx sample, electron trapping is observed to be dominating the VTH shift behavior up to a gate stress of 7 MVcm-1. Starting from stresses over 8 MVcm-1, a concurrent process is initiated, leading to a negative VTH variation. Such process is attributed to the trapping of positive charge occurring due to hole generation by impact ionization [6]. Despite the lower band offset exhibited by the HK dielectric, expected to promote hot-electron tunneling and subsequent hole generation, for the HK device the onset of negative VTH shift is observed at larger stress fields (exceeding 9 MVcm-1) and at larger timescales compared to the SiOx device. For stress fields up to 8.5 MVcm-1, the VTH shift behavior for the HK device appears to be still dominated by negative charge trapping, occurring at a fast timescale. Sudden negative VTH shift is observed at 9.25 MVcm-1 (9.5 MVcm-1) for stress times exceeding 2 s (200 ms), highlighting the capability of the employed HK material to inhibit hot-electron injection towards the gate polysilicon. Fig. 3 (a)-(b) show the hysteresis measurements of the sub-threshold characteristics of SiOx and HK devices, respectively, in their pristine state and after undergoing high gate voltage stress at different dielectric fields for 2 s of stress time. The VTH,HYS after the application of each stress is reported in Table II. The VTH,HYS measured for the HK device is significantly smaller than that of the SiOx sample at each stress condition. Additionally, devices stress at 9MVcm-1 have been subjected to a gate voltage stress procedure (TAMB) aimed at the restoration of VTH close to its pristine value. The insert of Fig. 3 and Table. II highlight how for the HK device, the VTH,HYS is fully recovered to its pristine state by the application of a gate bias stress alone.

ABSTRACT. The next generation of wireless infrastructure will depend on wide band gap semiconductors owing to their unique materials properties, including: their large band gap, high thermal conductivity, and high breakdown field [1-2]. To ensure the competitiveness of this next generation of materials, it is essential to make SiC MESFET and GaN HEMT microwave devices more suitable for a wide range of applications. The application of high-resistant HPSI (high-purity semi-insulating) 4H-SiC to microwave devices is absolutely indispensable. To ensure stable quality and high resistant values of HPSI-SiC single crystal, it is essential to suppress nitrogen incorporation during the crystal growth [3]. However, since the nitrogen flow is essential for polytype stability in the universal PVT method, it is important to obtain high-resistant HPSI-SiC ingots while maintaining the polytype stability without nitrogen flow. In this study, we tried to obtain SiC ingots with high resistance and polytype stability by applying hydrogen mixed gas flow to the PVT method. HPSI-SiC ingots could be obtained through the purification effect of the hydrogen mixed gas flow, which has a function to remove impurities in the hot zone [4]. Table I exhibited gas flow condition for three different SiC crystal ingots prepared with different gas ratio. One standard n-type SiC crystal for a power device application using the conventional growth condition was grown for a comparison. Two other SiC crystals were grown by Method A with a hydrogen mixed gas flow with a hydrogen/Ar ratio of 10%, and Method B with hydrogen/Ar ratio of 30%. UVF images could display the influence of gas flow on polytype stability in SiC crystal and the transparency of SiC ingot to determine nitrogen incorporation, as shown in Fig. 1. The conventional n-type SiC crystal ingot prepared with nitrogen flow had good polytype stability, but no transparency of the ingot due to nitrogen incorporation. On the other hand, SiC ingot grown by Method A exhibited good transparency but unstable stability containing polytype inclusion and nitrogen incorporation. Method B using higher content of hydrogen sucessfully produced SiC crystal having polytype stability and transparency of the ingot. The electrical resistivity of SiC substrates was measured for application to HPSI-SiC, as shown in Fig. 2 and Fig. 3. In SiC crystal prepared by the conventional method, resistivity value of 21~22 mΩ·cm was measured and a relatively higher value of 5.7E2~6E2 mΩ·cm was measured in SiC crystal grown by Method A. SiC crystal ingot prepared by Method B was showed a high resistant value applicable to HPSI-SiC application with resistivity level of 1.6E11~1.7E11 mΩ·cm. (High resistance value could be measured using the high resistance measuring device COREMA system.) The method using hydrogen mixed gas flow in the PVT process was proven to be obtain HPSI-SiC ingots showing polytype stability and high resistivity.

ABSTRACT. The epitaxial growth of wide-bandgap semiconductors such as GaN (gallium nitride) and SiC (silicon carbide) is achieved by MOCVD (metal organic chemical vapor deposition) or high temperature/hot wall CVD and is counted as mature technology. The increasing demand for these semiconductors for high power and high frequency applications resulted in high pressure on the equipment suppliers for high throughput and high yield. The possibilities and limits for MOCVD and high temperature/hot wall CVD are already reached out. Especially for electronic applications the requested epi-wafer area is much larger than that of LED, so that GaN-based layers or SiC despite their superior physical properties over silicon-based electronics are not competitive due to the high production costs in MOCVD or high temperature/hot wall CVD. Many research groups worldwide are working on alternative approaches to replace fully or partly MOCVD in the production chain. Fujioka et al are pioneers in demonstration of high-quality GaN-based layers by pulsed sputter epitaxy (PSE) [1,2,3]. Recently Dadgar et al also have presented promising data with their reactive magnetron sputtering process [4]. Hiroshi Kawarada is a pioneer in growing diamond thin films [5]. The growth of diamond request in the CVD process higher temperatures compared to SiC growth, which limits the choice of material to build up a CVD reactor. Kawarada et al use microwave plasma to grow their epitaxial diamond films at 700°C. Further activities to reduce the production costs of especially for SiC are to use other substrates than SiC. Promising results are achieved for 2H-SiC on AlN on sapphire [6] and on sapphire [7]. The combination of new production methods combined with common substrates instead of SiC can enable the entry of SiC-devices into the consumer electronics market. In this work we describe another epitaxial process. Here we present data of aluminum nitride (AlN), graphene interlayers and of SiC on AlN thin films on sapphire and of epitaxial growth of SiC on SiC grown by Next Level Epitaxy (NLE). The new process is using a surface temperature around 250°C by combining PVD (physical vapor deposition) and CVD (chemical vapor deposition). The growth procedure in NLE is similar to the MOCVD growth process with substrate cleaning, start layer and main layer. Compared to the reactive sputter processes and pulsed sputter epitaxy the NLE uses different plasma sources in various combinations. The NLE system is a homemade novel deposition system. In the current configuration, it has a capacity of up to 70 x 200 mm wafer at one time. As Al-source pure Al was used. As nitrogen source nitrogen gas, as Si-source silane and as carbon source for graphene and SiC methane which were introduced by a homemade ion gun. Additionally, argon, oxygen and hydrogen were used. During the process the surface temperature of the wafer was kept around 250°C. The used plasma sources are all designed as stripe sources. The wafer is placed on the carrier which is moving front and back in the growth chamber under the stripe sources. First the substrates were cleaned with a mixture of argon and oxygen and after with argon and hydrogen using the plasma. After the in-situ cleaning first a monolayer of aluminum was deposited followed by low plasma power and low growth rate AlN and after higher plasma power and higher growth rate AlN. The graphene layers were used as interlayer sandwiched between AlN and were compared with AlN grown in one step with the same total growth time. The experiments for SiC growth started recently. As seed for the SiC growth NLE-AlN on sapphire was used. Since AlN is counted as 2H-AlN it can act as seed for 2H-SiC and 4H-SiC. The growth of AlN by NLE is epitaxial on single crystal wafer as sapphire, silicon carbide or silicon. The experimental evidence is given by X-ray diffraction (XRD) of the phi-scan around the 101 peak. Here only the allowed peaks of the hexagonal AlN crystal are visible. The full width at half maximum (FWHM) rocking curve of 002-AlN is usually below 200 arcsec and with optimized starting conditions down to 35 arcsec. By atomic force microscopy (AFM) and scanning electron microscopy (SEM) smooth surfaces with no artefacts of columnar growth could be measured. The root mean square (rms) roughness values are 0.2-0.27 for a 5 µm x 5 µm scan area. The layers grown by NLE exhibit an excellent thickness uniformity. 1.3 µm thick AlN on 5x200mm silicon show just one single color, indicating the high thickness uniformity. Since the stripe source consist of just one gas inlet, simply described of one pipe with some holes across the pipe, the thickness uniformity as well as the doping uniformity are always excellent. In figure 1 the XRD graph of AlN grown in one step and of AlN grown with graphene or graphene like interlayer is shown. With graphene or graphene like interlayer a clear increase in 2theta intensity is visible. The inset graph of the rocking curve of the AlN layer with interlayer shows clear resolved thickness fringes and a sharp peak. The graphene layer was grown using a mix of argon and methane insert through the ion gun. First experiments of SiC grown with methane and silane on AlN on sapphire revealed mirrorlike surfaces. The layer looks transparent with little greenish touch. XRD measurements about the phase purity are ongoing and doping experiments started already.

The authors would like to thank Prof. I. G. Ng from NTU Singapore, Dr. S. Tripathy from IMRE Singapore, Dr. V. Zubialevich from Tyndall National Institute Ireland and Dr. N. Zainal from USM Malaysia and their teams.

[1] Y. Arakawa, K. Ueno, A. Kobayashi, J. Ohta, H. Fujioka, APL Mater. 2016, 4, 086103. [2] K. Ueno, A. Kobayashi and H. Fujioka, AIP Adv. 2019, 9, 075123. [3] Y. Nishikawa, K. Ueno, A. Kobayashi, H. Fujioka, Applied Physics Letters, Volume 122, 082102, 2023. [4] A. Dadgar, F. Hörich, R. Borgmann, J. Bläsing, G. Schmidt, P. Veit, J. Christen, A. Strittmatter, Phys. Status Solidi A2022, 2200609. [5] H. Kawarada, Journal of Physics D: Applied Physics, 56 (2023), 5, 053001. [6] T.-T Luong, B. T. Tran, Y.-T. Ho, T.-W. Wei, Y.-H. Wu, T.-C. Yen, L-L Wei, J.-S. Maa, E. Y. C, Electron. Mater. Lett., Vol. 11, No. 3 (2015), pp. 352-359 [7] A. Ito, H. Kanno, T. Goto, Journal of the European Ceramic Society,Volume 35, Issue 16, December 2015, Pages 4611-4615

Fig. 1. XRD of AlN grown in one step and with graphene interlayer. Inset graph shows rocking curve of AlN with graphene interlayer.

ABSTRACT. The demand for reliable Wide Band Gap (WBG) materials, such as SiC and GaN, for power devices and high-voltage products has been steadily increasing in recent decades to meet the intensive use in many application fields. SiC and GaN present the best compromise between the theoretical characteristics (high voltage blocking capability, high temperature operation and high switching frequencies) and the real commercial availability of the starting material (wafer) and the maturity of their technological processes [1]. They have enormous potential to miniaturize power electronic converters (facilitating operation at higher frequencies and temperatures) with much higher power conversion efficiency than can be achieved with state-of-the-art silicon power devices [2] [3]. The market expansion of SiC power devices in recent years has been so rapid that many suppliers are struggling to satisfy the demand for such devices, so far produced from wafers with a diameter of 150 mm. As a countermeasure, STMicroelectronics has started production of SiC wafers with a diameter of 200 mm. The main challenge in the conversion from 150 mm to 200 mm is to increase the size of the bulk crystals while maintaining productivity and crystal quality. An increase of 50 mm in wafer diameter corresponds to 78% more area and thus a corresponding increase in the number of devices per wafer. This change impacts the productivity of a front-end line and thus the cost of the final device can be reduced. The increase in production volume and cost reduction will lead to further massive implementation of SiC-based power devices in the automotive industry, which is now racing down the road to electrification [4]. In the field of the seed enlargement (from actual 150 mm to 200 mm substrates) twenty-four 200 mm SiC substrates were grown by the same process in the same reactor in order to evaluate the defect evolution from the substrate to the epilayer and its impact on the total usable area (TUA). For this purpose, the substrates were selected as follows: 12 standard 4H-SiC wafers, 6 wafers 4H-SiC with polytypical inclusion (6H/12R) ≤1% and 6 wafers with high BPD (among them there are 2 that also have polytypical inclusion). The growth of n-type 4H-SiC 200 mm epitaxial layer 4H-SiC on Si-face substrates (0001) at 4° off axis was performed on low-pressure, single-wafer, hot-wall chemical vapor deposition (LP-CVD) reactor. The homo-epitaxial growth process is carried out at temperatures above 1600 °C and involves the use of silane (SiH4), propane (C3H8), and ethylene (C2H4) as silicon and carbon precursors, respectively, an n-type dopant obtained from nitrogen (N2), and hydrogen (H2) as carrier gas. The presence of HCl, due to the system chemistry, is required to prevent the formation of Si droplets (Si-C bonds stronger than Si-Si ones). The epilayer specifications, required for medium/high voltage device technologies, are ~6.55 µm for thickness and ~1.8E16 cm-3 for doping. The uniformity of thickness distribution and doping concentration of epilayers were measured by Fourier transform infrared spectrometry (FT-IR) and mercury-probe CV (Hg-CV). Bow and warp metrology measurements were done by FRT (the measurement will be shown during the conference) and physical defect characterization analysis was performed by optical inspection tools with and without photoluminescence, Candela and KLA Altair, respectively. The Candela defect maps referring to a wafer with polytypical inclusion, in Fig.1, show a decrease in substrate defects during the epitaxial growth process. In addition to the conversion of BPDs (which are fatal to the device) to TEDs, a significant decrease in particle density in the epilayer and an increased number of defects in the polytypical inclusion zone (highlighted in red) can be observed. Specifically, in this area there is evidence of carrots, topo defects and most of detected buried triangles, consistent with the increased surface roughness. The Altair map of post epitaxy defects, right in Fig.1, displays a good match with the Candela map. Table I, instead, shows the data of 6 of the 24 wafers investigated. A lower Total Usable Area (%) value, around 70-72%, is observed for wafers with high BPD density and polytypic inclusion simultaneously (highlighted in green and light blue). The substrate BPD characterization by molten KOH method will be also presented during the conference. This information will be supported by EWS (Electrical Wafer Sorting) data that will presumably be presented at the conference with power MOS-type vehicle tests.

[1] K. Shenai, M. Dudley and R.F. Davis, ECS J. Solid State Sci. Technol. 2 (2013), N3055. [2] X. She, A.Q. Huang, O. Lucìa, B. Ozpineci, Review of silicon carbide power devices and their applications, IEEE Trans. Ind. Electron. 64 (10) (2017) 8193–8205. [3] R. Anzalone, M. Salanitri, S. Lorenti, A. Campione, N. Piluso, F. La Via, P. Fiorenza, C. Marcellino, G. Arena and S. Coffa, Material Science Forum (2015) 858, pp 197-200. [4] D. Raciti, R. Anzalone, M. Isacson, N. Piluso and A. Severino, Material Science Forum (2024) in press

ABSTRACT. Physical vapor transport (PVT) is current preferred general method in the industry for the growth of silicon carbide (SiC) crystals[1, 2], a seed crystal is placed in a high-temperature furnace, which is in contact with a sublimation raw material, and SiC vapor species are formed on the surface of the seed crystal until a crystal boule of the desired size is obtained that include diameter and thickness of crystal. Although the SiC crystals are thicker in usable thickness [3, 4], the BPD (basal plane dislocations) distribution shown a relatively high BPD at the seed end, and the decreases as the crystal grows. Therefore, the relatively low BPD ratio of the whole crystal was rarely results in fewer high-quality wafers. In this article, be devoted to the unique 200mm diameter SiC crystal growth technology [5] which achieved most obvious low BPD and uniform distribution of an entire crystal, as well as without high BPD at the seed end. The technology demonstrated a 200mm diameter SiC crystal, and the BPD difference of the two opposite carbon/silicon faces is low, which allows a more consistent crystal growth direction and can reduce the structural defects of the SiC ingots grown from the SiC seed crystal. Furthermore, due to SiC crystal has a silicon-face and a carbon-face opposite to the crystal boule surface. A difference D value between the basal plane dislocation density of the silicon-face stand for BPD1 and the basal dislocation density of the carbon-face represented by BPD2 to satisfies formula as follows: D=(BPD1−BPD2)/BPD1≤25%, the BPD difference D value between the silicon-face and the carbon-face is preferably 20% or less, more preferably 15% or less. The foregoing that the 200mm diameter SiC crystal grown by designed thermal field in the crucible whose source material sublimation particular process. Furthermore, A radial temperature gradient of the thermal field in the crucible is greater than or equal to 5° C/cm and less than or equal to 50° C/cm. In conclusion, the 200mm diameter SiC crystal was revealed a consistent crystal growth direction by controlling the BPD difference between the silicon-face and the carbon-face to produce significant high-quality SiC ingots with fewer defects. The results of comparison in relation to each different process and BPD distribution uniformity are shown in Figure 1 and Figure 2, respectively.

ABSTRACT. Stable and efficient production of high quality single crystal SiC is still a challenge due to the overall complexity of the production process. Most mature technique for SiC growth is PVT method, operating at above 2000°C, demanding precise temperature control and distribution within the graphite crucible encapsulated in an insulation felt. Therefore, such process is susceptible to the slight changes in the material (powder, graphite, felt…) properties (thermal, electrical, mechanical) used in the growth process. On the other side, extreme temperature and closed system design are limiting accessibility inside the crucible so that no direct feedback about the growth process is possible until it is finished. Here we would like to present newly established R&D initiative of PVA CGS focusing on rapid SiC growth process development based on advanced diagnostics and metrology implementation at early stages of the production. Such a long-term project is organized through a newly developed R&D business unit PVA Technology Hub equipped with 10 PVT (SiCma Gen. 4) units and whole preparation and postprocessing facilities. Such Demo Lab/Fab will work on development and integration of different diagnostic methods for material evaluation, process monitoring and crystal analysis in order to gain information about the process and quality of the crystal in early stages and thus reduce the process development time and costs. This way, growth process could be tuned for different materials in short times and at lower costs generating large amount of information. Analysis of the growth process starts with the evaluation of the powder properties such as size, shape, composition, doping… using different optical (microscopy, Raman spectroscopy) and electrical (resistivity) methods. In the next step, information about the powder together with graphite properties are used to setup Virtual Reactor simulation software in order to estimate optimal process parameters such as power and coil position by optimizing growth rate and quality. Considerable effort is focused on development of diagnostic method for an in-situ evaluation of the crystal growth and quality. A new measurement system is under tests, which should provide information about the crystal growth rate, seed temperature and possibly changes in the polytype during growth. Such measurements would provide possibility to tune the growth parameters up to desired growth conditions at very early stage of the growth (or early termination of faulty runs) and thus reduce process development time and cost. Major aspect of this project focuses on development of diagnostic methods applicable directly on the grown boule, before any processing. For this purpose, in-house established methods such as scanning acoustic microscopy [1] and scanning infrared depolarization spectroscopy [2] will be further adapted for SiC material. Acoustic microscopy is a mapping tool for volumetric inspection of materials, capable of detecting anomalies in density on few μm scales, while SIRD is an optical method for stress mapping. Additional inspection of the boule is performed using Raman spectroscopy and photoluminescence measurements by mapping an entire grown surface and providing information about the crystal quality (polytype, doping, purity, defect mapping…). Mentioned diagnostic methods should also be repeated on a wafer level, after the boule processing, providing additional data for cross-correlation and verification. [1] L. P. Bauermann et. al. Journal of Power Sources Advances 6 (2020) 100035. [2] M. Herms and G. Irmer, S. Spira, M. Wagner, Phys. Status Solidi A, 2100198, (1973).

ABSTRACT. Commercially available SiC-power-devices of MOSFETs and SBDs are recently fabricated on n-type 4H-SiC substrates with 6-inch in diameter. For improving device performance and device yield, the quality of large diameter SiC wafer is important [1-3]. In particular, for high-quality Epi growth, growth on a high-quality SiC substrate with a low density of crystal defects and suppressed polytype inclusion is required. Therefore, the control of temperature gradient and C/Si ratio of vapor source in front of growing crystal is important to obtain high quality SiC crystal growth. In this study, we aim to obtain high-quality SiC ingots through polytype stabilization and defect control through optimization of heat transfer at the growth temperature. In PVT process for SiC crystal growth, a non-optimized heat transfer design of the upper crucible could cause the instability in shape control resulting in dislocation formation and polytype inclusion within the grown SiC ingot. Therefore, we tried to optimize heat transfer design in the growth zone by controlling the lateral thickness of the upper crucible part, including the seed area. It was observed that the temperature on the edge area of the seed was relatively increased by increasing thermal radiation, which is the main heat transfer mechanism at high temperatures, and vapor species was easily delivered to the center area to finally make a slight convex shape of the SiC grown ingot [4]. Fig. 1 shows a schematic diagram of the conventional crucible design and modified crucible design with reduced wall thickness in upper part of crucible. As shown in Table I, the outer diameter of crucible was 210mm for the conventional design, and outer diameter of modified crucible design was reduced to 200mm and 190mm in order to find optimized heat transfer condition with changing crucible thickness. UVF images from UV lamp and shape images of 6-inch SiC ingots grown with the conventional method, and modified methods (200mm/190mm) were shown in Fig. 2. In terms of defect density, the modified crucible design with optimized heat transfer condition definitely exhibited lower level of defect density. Fig. 3 and Table Ⅱ showed etch pit density (EPD) images and defect density values of SiC crystals grown with conventional and modified designs.

ABSTRACT. SiC with high critical electric field strength, high hardness and high thermal conductivity, is commonly known as the wide-bandgap semiconductor, which are one of top choices for high -power and high-temperature devices. With the development of growth technology and commercialization of SiC substrate, the quality of SiC single crystals has been greatly improved and 8 inch SiC substrate is accessed with small batch production. Nowadays, the wide-scale use of these materials in automotive application requires low dislocation density. Access to 8 inch size of SiC substrate with ultra-low treading screw dislocation (TSD) and basal plan dislocation (BPD) density is the crucial market driver and a preferred interest for substrate suppliers and researchers in the past three years. In this study, the variation of the stress, carrier concentration and dislocation density on the interface between seed and boule has been evaluated. By lowering the temperature gradient toward the growth direction, TSD and BPD density has dropped continuously since 2022. TSD density is reduced to values as low as 0 cm-2 and BPD density is below 200 cm-2 in mass production. The best result shows that zero micropipe and ultra-low defect density 200 mm 4HN-SiC substrates are available with 0 TSD, 0 SF and BPD density is 7 cm-2. Based on the capability build-up of 8inch SiC, it takes some times for transition from 6 to 8 inch for R&D and industrial application.

ABSTRACT. It is critical to elucidate the mechanisms of macroscopic and microscopic surface planarization features of 4° off 4H-SiC (0001) wafer in our recently reported Dynamic AGE-ing® (DA), a thermal sublimation process. This provides an opportunity to investigate the possibility of solving surface morphology control issues in wafer fabrication and thermal etching/epitaxial growth processes. This method facilitates sublimation etching and epitaxial growth in a quasi-closed environment made with polycrystalline SiC, driven by a slight temperature gradient. The DA thermal sublimation etching and growth rates with and without the Si supply source are shown in Fig. 1. The red and blue lines are theoretical curves derived from thermodynamic calculations of the partial pressure of the C system in the SiC-Si and SiC-C phase-equilibrium environments, respectively. Since the theoretical curves and experimental values are close, the case with and without a Si supply source is defined as SiC-Si and SiC-C Phase equilibrium Environments, respectively. In the DA process, surface planarization is controlled by adjusting the temperature, pressure, and C/Si ratio of the vapor environment based on wafer roughness. There are two primary planarization mechanisms: microscopic planarization and macroscopic planarization. Microscopic planarization was observed under the SiC-Si phase-equilibrium environments condition, which is a low C/Si ratio atmosphere, and experimentally the smoothest micro steps with a height of 1 nm are formed[1]. On the other hand, macroscopic planarization effectively planarizes mechanical sliced, ground, and diamond-polished substrates with large roughness[2-3]. Macroscopic planarization occurs by DA etching under high temperatures above 2000°C and pressures above 1 kPa, or under SiC-C phase-equilibrium environments conditions for the C/Si ratio. These processes form giant step bunching with stable facets of several hundred and tens of nm in height, respectively[1-2]. DA has two possible planarization mechanisms: macroscopic planarization due to giant step bunching caused by the sweep of large, stable facet structures and microscopic planarization due to step debunching. Once formed, the giant steps must be broken down into minute step structures in a later process. However, designing optimal processes for different initial surfaces is challenging due to an incomplete understanding of these mechanisms. We compared surface morphologies before and after the DA process, considering initial roughness, and observed changes post-debunching to clarify these mechanisms. First, we verified the macroscopic planarization effect. DA etching was performed with SiC-Si and SiC-C phase-equilibrium environments on 4H-SiC, 4°off substrates, and diamond-polished substrates, and the results before and after DA etching are shown in Fig. 3. The diamond-polished substrate, DA etching with SiC-C phase-equilibrium environments removed the scratches, whereas DA etching with SiC-Si did not. These results suggest that giant step bunching has the effect of eliminating scratches and planarizing the surface. To investigate the mechanism of microscopic planarization, we observed the giant step bunching before and after SiC-Si phase-equilibrium environments DA etching on the substrate with giant step bunching using the laser mark as a landmark, as shown in Fig. 2. The giant step bunching was found to decrease before and after the DA process (Figs. 2. (a),(b)). Observation of the area around the laser mark shows that the giant step bunching is decomposed starting from the laser mark (Figs. 2. (c),(d)). This suggests that the giant step bunching extending [1-100] from edge to edge of the SiC substrate is cut by the laser mark, and the giant step bunching decomposition occurs from the edge of the giant step bunching. These indicate that giant step bunching with thermally stable facets will disappear or decompose by DA etching from the edge of the giant step bunching. Using these microscopic planarization mechanisms by debunching and macroscopic planarization mechanisms by giant step bunching, we could planarize the diamond-polished substrate, as seen in Fig. 3(g-h).

ABSTRACT. As market competition builds in the 4H-SiC power device space, a growing number of vendors are coming online to supply bare substrates and turnkey epitaxial wafers. With this growth, standardization of quality is becoming critical to ensure the industry continues to build a reputation of providing reliable devices for expanding global electrification. Despite the market seeing significant quality improvements in 4H-SiC turn-key epitaxial wafers ≤30μm [1], the industry has not aligned on epi defect nomenclature, nor has it aligned on what each defect type does to device performance or reliability. Work has been done in characterizing effects of defect types [2-3], but the SiC industry needs robust standards for 4H-SiC crystal defects to ensure quality compared to its Si predecessor. Past Microchip research showed how trapezoidal defects affect MOSFET on-resistance (RDSon), shown in Fig. 3, similarly identified in [2], and reported in [3], but a lack of robust standards challenges the industry on what defects impact Unclamped Inductive Switching (UIS), which require improved accuracy of SiC epi defect detection. UIS is a standard industry practice for production testing of avalanche energy rating of power devices [4]. While additional testing is implemented for quality control – adding cycle time and cost – more robust standards will sus out which defect types are causing UIS failures with fewer post fabrication test requirements. Also critical at hand to achieve is industry alignment on which 4H-SiC epitaxial defects kill devices, regardless of device design, to define Total Usable Area (TUA). When comparing TUA across suppliers, vendors don’t provide standardized TUA defect data maps as shown for example in Fig. 1. Current vender-supplied epi defect data lacks the high resolution capabilities of Ultraviolet Photoluminescence (UVPL), as shown in [1]. This complicates pinpointing the impact of specific defects of in-line UIS yield prediction. Though there is precedent of good data sets for correlations, work is needed to improve the accuracy of defect detection, as illustrated in Fig. 4, such that defects are easily discernible. These challenges hinder wafer level and packaging yield predictability. In this research we attempt to show correlation between UIS yield and material quality as the cause of variation. It’s shown that defect maps in many cases lack robustness for strong correlations with epi-wafer defect maps from vendor to vendor as shown in Fig. 1 and Fig. 4, and robust capabilities exist as shown in Fig. 3, but are not standard, to pinpoint and quantify effects of defects on device parameters. Data presents large variations in UIS failure distribution across 3 different wafer supply vendors, as shown in Fig. 2. As epi layers become thicker for high voltage, yield predictions become even more critical as the costs increase. This is why the SiC industry needs reliable TUA data of each incoming wafer for reliable UIS yield prediction. As shown in Fig. 1, the nomenclature of what defects to report are far from aligned. A lack of robust epi defect data only adds further qualification and production testing time. [1] R. Stahlbush, N. Mahadik, Defects in 4H-SiC Epi Affecting Yield & Reliability, IRPS (2022). [2] H. Das, Material Science Forum, ISSN: 1662-9752, Vol. 1062, pp 406-410. [3] S. El Hageali, H. Guthrey, J. Soto, JAP, Vol. 134, Issue 7 [4] K. Chinnaswamy, P. Khandelwal, M. Trivedi, and K. Shenai, “Unclamped inductive switching dynamics in lateral and vertical power DMOSFETs,” IEEE Industry Applications Conference. 1085 (1999)

ABSTRACT. The 4H polytype Silicon Carbide (4H-SiC) is a wide bandgap semiconductor, and it is receiving increasing scientific and technological attention due to its electrical, mechanical, and thermal properties suitable for high-power devices operating in harsh environments [1]. In particular, aerospace and nuclear applications have shown great interest in proton irradiation effects on SiC, but it remains unclear how the induced defects could be modified and which is their impact on the SiC physical properties [2]. This work reports on photoluminescence (PL) measurements of color centers associated with defect creation from proton irradiation experiments. The study focuses on how these color centers change following heat treatments, and measurements have been carried out at low temperatures (11 K) and room temperature (300K). In this study we used 4H-SiC substrate with a n-doped epitaxial layer of 1.5e16 cm-3 and a thickness of 6 µm. The samples were irradiated with H+ ions at an energy of 200 keV and with a dose of 1e14 cm-2. Initially, ToF-SIMS was used to verify the implant depth, which was observed at ~940 nm, measuring the thickness of the crater formed after dual beam sputtering. Thermal processes in a nitrogen environment with temperatures between 773K and 1323K for 30 minutes were carried out on similar samples. Photoluminescence (PL) measurements were performed on these samples at room temperature and 11 K. A He-Cd laser, with a wavelength of 325 nm (3.81 eV), modulated at a frequency of 55 Hz and with a pump power of 0.7 mW, has been used. Figure 1.a shows a comparison of the emission spectra obtained at RT. These spectra show the first peak at 382nm corresponding to the typical bandgap emission of 4H-SiC, which settles at 3.23V [3]. In addition to this main emission in the UV, there is the green-yellow light emission related to the recombination of the acceptor-donor pairs due to the injection of minority carriers [4]. The difference in the spectra of Fig. 1a between 425 nm and 625 nm (see the inset in the figure) is evident. In this range, as the annealing temperature increases up to 1073 K, the recombination peak emitting green light shifts from 525 nm to 500 nm. This indicates that the green luminescence promoted by p-type doping due to the implantation of H+ ions is responsible for more than one deep recombination level [4]. Moving to higher annealing temperatures, the levels created by the activation of the H+ dopant are destroyed and the spectrum, due to ion diffusion, slowly recovers. The PL spectra acquired at low temperature (11 K) are shown in Figure 1.b. The typical bandgap emission of 4H-SiC also appears in the ultraviolet at 390 nm, followed by the two peaks at 404 nm and 420 nm, respectively no-phonon lines, one-phonon replicas, and two-phonon replicas [5]. From 425 to 525 nm, the largest differences between the spectra are again confirmed, with an opposite trend than RT measurements. Here a higher intensity of blue luminescence is recorded for annealing at temperatures different from 1073 K. For this heat treatment, the spectrum is much closer to the 4H-SiC as-grown sample. In addition, there are known emission peaks at 1077 nm and 1032 nm, due to VSiVC di-vacations, more evident in the case of heat treatment at 1073 K [6]. Considering the results obtained, the optimum temperature for the activation of H as a p-type dopant appears to be between 873K and 1073K. The results obtained, both in implantation depth and modulation of the color defects centers with the annealing temperature, open the way to control recombination into the epitaxy. This could lead to the fabrication of more performing and faster SiC power devices.

Fig. 1: a) Comparison of the PL spectra measured at RT. b) Comparison of PL spectra measured at 11 K.

[1] T. Kimoto, K. Danno, J. Suda (2008). Phys. stat. sol. (b) 245, No. 7, 1327–1336 (2008). [2] L. Zhao, Y. Tang, Y. Bai, M. Qiu, et. Al. Electronics 11, 1341 (2022). [3] G. Feng, J. Suda, and T. Kimoto, Appl. Phys. Lett. 92, 221906 (2008). [4] S. Omar, H. Song, T. S. Sudarshan, M.V.S. Chandrashekhar. Mat. Sc. Forum 717–720 (2012). [5] A. Kakanakova-Georgieva, R. Yakimova, A. Henry, et. al. J. Appl. Phys. 91, 2890(2002). [6] R. Karsthof , M. Etzelmüller Bathen, A. Galeckas, L. Vines. Phys. Rev. B 102, 184111 (2020)

ABSTRACT. Silicon carbide (SiC) is an attractive semiconductor for use in high-power, high-temperature, and high-frequency electronic devices because of its wide bandgap, high breakdown electric field, high thermal conductivity, and device-applicable mobility of carriers [1]. Among the defects in SiC, stacking faults (SFs) may propagate into the epilayer from the substrate or generated at epilayer/substrate interface. Furthermore, SFs can be expanded by high-temperature annealing and current flow, particularly during bipolar device operation. For high power SiC power devices, the epilayer requires a long carrier lifetime to achieve sufficient conductivity modulation in the forward conduction mode [2]. It is well known that the forward voltage drop of bipolar devices increases due the reduction of minority carrier lifetime induced by SF expansion [3]. Also, SFs cause increasing leakage current and reducing the blocking voltage of SiC devices due to the localized reduced bandgaps [4]. Therefore, the carrier lifetime is an important physical property that strongly affects the performance of SiC power bipolar devices. Although carrier lifetime has been studied from the perspective of deep defects, no study has yet been reported on differences in carrier lifetime depending on the individual SF types. In this work, we carried out measurements of carrier lifetime for whole epitaxial wafer and investigated effect of SFs on the minority carrier lifetime using the room temperature time-resolved photoluminescence (TRPL) acquired at micro steps from the photoluminescence (PL) maps. PL spectrum and carrier lifetime maps were acquired from the defect map obtained by using MiPLATO-SiC (EtaMax, Suwon, Republic of Korea) equipped with spectrometer and TRPL module shown in Fig.1(a). Carriers were excited by using a 30kHz 355nm pulse laser source with photon density of low-level injection, and photons were detected by using a single-photon counting photomultiplier tube. An optical filter was set to approximately 390 nm to detect the band edge TRPL signal of 4H-SiC epi wafer. Commercially available 4H-SiC epitaxial wafer (100 mm-diameter and thicknesses of 13 μm) was used in this study. For the TRPL signals from SFs, the optical filter in 400-500 nm wavelength bands was additionally used. Fig.1(b) and (c) show typical whole wafer mapping and TRPL decay curves at the line scan from the center to the right edge. It is known that types of SFs can be classified according to the characteristic emission wavelengths of the PL peaks [5,6]. Specific SFs classified based on the emission wavelength were investigated as shown in Fig. 2(a). It was revealed that different carrier lifetimes from two adjacent SFs with different characteristic emission wavelengths (Fig.2(b)). The present results clearly showed the different band-edge PL decay depending on the type of SF. Furthermore, very surprisingly, different carrier lifetimes were detected depending on the regions from the single bar type SF with subtle differences in PL peaks.

ABSTRACT. SiC substrate is a key enabler for high voltage and high current technology. Most of the SiC commercial device use a planar-gate design on multiples nodes. To continue the shrinkage and enabling better performances, the trench-gate architecture (typically used in Silicon IGBT technology) is becoming a preferred choice by semiconductor manufacturer. One of the main usages of SiC power technology is for Automotive purpose: in this paper we investigate and propose techniques of monitoring with SEM that will enable exceptionally reliable devices through high quality process control. Compared to the Si technology, we need to face the additional difficulty of handling wafers having lower thickness and high warpage. Furthermore, the trench-gate design poses new challenges since the gate is defined along one (or both) the SiC trench sidewall. Therefore, relying on the etch process chamber quality and robustness over time (See figure). On the defectivity side we explore the defects created during the process that fall inside the trench, which later create a problem after Oxide & Poly gate deposition. In this work we used few 100mm and 150mm SiC epi-wafers where stripes have been defined by common i-line photolithography. After the SiO2 HM Etching (2), SiC trenches with rounded bottom were etched (3), this was followed by the Hard Mask removal (4) and finally by a wet cleaning step (5). We explored the defects evolution across each processing step to understand how the devices evolved into these critical steps (as shown in figure 2). To accelerate the process development and reduce the random defectivity, we propose to inspect the wafer with high resolution SEM using API (Automatic Process Inspection) methodology. Using this method, we demonstrate what is the main process variation contributor at each step of the process (figure 2). The eTilt imaging (enabled by tilting the electron beam at a certain angle from the column) helps understand where the particle is located and whether it is critical. As shown in figure 3, most of the particles are located on the HM After HM removal, we see that majority of the defects were some small particles or residues due to process variation. We propose to add a cleaning process to remove them. Main defect contribution after clean was qualified as deformed pattern as shown in figure 5. Defects seen on figure 5 (b) can be linked to the variation of the Hark Mask and defects seen at his layer (figure 5 [a]) which can have an impact at the 3D level as shown with the Tilt view on figure 5 (c). This suggests that the patterning of the trench gate would require a better roughness control to avoid this type of problems. To conclude, in this study we explored the defects from the trench gate patterning process and extracted an overview of the defect contribution of each process step. Furthermore, we have shown how we can reduce it using API methodology to screen the wafer with high resolution SEM and how to avoid high false alarm from optical inspection tools due to process variation. Additionally, the wide range of imaging type enables a better understanding of the defect impact which is critical to differentiate between killer and non-killer defects.

ABSTRACT. The mass production process of SiC wafers involves many variations in crystal quality (lattice dislocation arises from doping variations, thermal stress, and extended defect concentrations [1]). Although the CMP process guarantees the final surface flatness, sub-surface damage (SSD) from machining remains in SiC crystals, which are hard and brittle materials. Therefore, it is necessary to visualize the SSD and optimize the processing conditions to suppress the variation in processing quality. If epitaxial growth is performed with SSD remaining on the wafer surface, new crystal defects, such as stacking faults, will be induced from the interface, affecting device yield [2-3]. Generally, hydrogen etching is performed before epitaxial growth in the CVD process as a method to remove SSD. However, when there is a significant variation in the thickness of the SSD layer from wafer to wafer, it is necessary to either extend the CVD process window or select only wafers that can be used in the CVD process in advance. CVD process by selecting only those wafers that can be used in the CVD process. Considering device yield, quality control through visualization of wafer processing quality before epitaxial growth is required. We have proposed a laser scattering method as a nondestructive inspection method that can visualize the depth and distribution of SSD layers remaining on the wafer after CMP processing at high speed [4]. Using the same process, we have clarified that differences in processing methods among wafer vendors significantly impact the depth and distribution of residual SSD. In this study, from the viewpoint of actual wafer quality control, we investigated how much processing quality variation exists not only among vendors and wafers supplied from the same vendor at different manufacturing times for commercially available SiC production grade wafers. It is thought to be useful as a visualization tool for optimizing processing conditions during wafer fabrication and for sorting good wafers to improve device yields (Fig. 1.). Fig. 2. shows the scattered light intensity mapping images and SSD depths at different for epi ready 6-inch SiC wafers purchased from two mass-production wafer vandors. There were differences in SSD distribution and depth between vendors. Even when wafers were purchased from the same vandor, there were variations in SSD depth and distribution at different times of purchase. Fig. 3. shows the results of quality variation measured by LLS for production grade 6-inch SiC wafers purchased monthly from the same manufacturer. In the June purchased, SSD like traces of wire cutting were observed. In July, SSDs were present, as if strong pressure had been applied to the entire wafer surface during the grinding and polishing processes. In the November purchase, the wafer quality improved significantly. To improve quality and cost, mass-production wafer makers are changing production processes. Visualization of SSD allows them to recognize that process improvements have a significant impact on the processing quality of wafers, allowing them to improve quality more efficiently. Fig. 3. (b) shows that among the samples purchased in July, which tended to have large SSDs overall, there were samples that were equivalent to those purchased in November, when quality was improved. For device manufacturers, visualization of wafer SSD is very effective in recognizing the degree of quality variation and implementing appropriate yield measures.

Acknowledgments: The authors are grateful to Toyota Tsusho Corporation for funding and technical support, YGK Corporation for equipment support. [1] B. Gao, Koichi Kakimoto., Cryst. Growth Des. 14, 1272−1278(2014) [2] K. Ashida, D. Dojima, Y. Kutsuma, S. Torimi, S. Nogami, Y. Imai, S. Kimura, J. Mizuki, N. Ohtani, and T. Kaneko, MRS Adv., 1, 3697-3702 (2016). [3] K. Toda, D. Dojima, K. Kojima, H. Mihara, S. Mitani, and T. Kaneko, Solid State Phenomena, 344, p. 9-14, (2023). [4] D. Dojima, et al., Solid State Phenom. 343 (2023) 43-50

ABSTRACT. The synthesis of dislocation-free 4H-SiC and GaN wafers remains challenging at the manufacturing level, with ongoing research into high-quality crystal production processes. There is an urgent need to provide these high-quality wafers for use in power semiconductor devices, along with the development of nano-level dislocation analysis methods. Typically, dislocations in compound semiconductors are analyzed using photoluminescence (PL) and X-ray topography which require no sample preparation but offer lower spatial resolution generally on the order of around 1 µm. This limitation makes it difficult to detect minute dislocations on the nano-scale. In this study, we present an analysis of dislocations in compound semiconductors using a low accelerating voltage SEM combined with cathodoluminescence (CL). This method allows for detailed nano-level dislocation analysis. The operating principle of CL is shown in Figure 1, where CL data is generated by the electron beam of SEM, enabling precise localization. Recent advancements in SEM technology have achieved spatial resolutions of less than 1.0 nm under low-voltage conditions. By selecting suitable observation conditions, various types of information, such as material typography and composition, can be selectively obtained. We have developed a new objective lens, the Super Hybrid Lens (SHL), comprising both magnetic and electrostatic lenses, installed in the JEOL JSM-IT800<SHL>. This lens achieves a small probe size even at low accelerating voltages, for example, 0.7 nm at 1 keV. The SEM's high-brightness Schottky emission electron gun and the Monarc Pro CL detector (Gatan), used under low-voltage conditions, make the system ideal for CL applications. Figure 2 shows CL images of a dislocation in a 4H-SiC wafer indicating the difference in electron penetration depth at different accelerating voltages. The dislocation width is approximately 200 nm at 3 kV. However, at higher voltages such as 10 kV, the contrast was decrease likely due to the increased electron beam penetration. Optimizing the conditions for CL imaging is crucial for achieving fine contrast and high-resolution images of the dislocations.

ABSTRACT. Bipolar degradation of SiC devices caused by the expansion of single Shockley stacking-faults (1SSFs) from basal plane dislocations (BPDs) in the 4H-SiC crystal. Previous studies have shown that the expansion of 1SSFs can be suppressed by proton implantation into the epitaxial layer, and bipolar degradation may be suppressed with the introduction of point defects or the reduction of carrier lifetime. In this study, we introduced hydrogen and point defects into the epitaxial layer using hydrogen plasma treatment (HPT). HPT introduced hydrogen and point defects as observed through SIMS and DLTS. Thus, plasma treatment remains a viable option for the suppression of the bipolar degradation.

ABSTRACT. As a Wide bandgap semiconductor (WBGS) material, silicon carbide (SiC) boasts a wide bandgap (~3.3 eV), a high critical electric field (~3 MV/cm), and excellent thermal conductivity (~4.56 W/cm°C). These features make it superior to silicon, currently used in power module devices, garnering significant attention in the power semiconductor field. Additionally, its low thermal resistance and high breakdown voltage reduce switching losses, making it suitable for industries such as electric vehicles and renewable energy.[1] However, various defects generated during the 4H-SiC process limit device performance, with deep level traps being a major obstacle. Specifically, deep level trap like Z1/2 and EH6/7 reduce carrier lifetime, deteriorating switching characteristics and leading to issues like increased leakage current.[2,3] Therefore, it is important to improve reliability and performance by reducing the reverse leakage current through research on reducing defects in 4H-SiC based devices.[4] In this work, we investigated the electrical characteristics and deep-level defects of 4H-SiC-based MPS and PiN diodes, focusing on the impact of the P-region. The structure of the diodes was examined using FiB SEM, and deep-level trap in MPS and PiN diodes were identified via deep level transient spectroscopy (DLTS) analysis. In Fig. 1, the proportion of the P-region in each diode was identified. The electrical properties, such as J-V and 1/C²-V, were investigated in Fig. 2. As the P-region increases, Fig. 3 shows that the peaks near 150 K and 450 K increase, while the peak near 300 K decreases. We summarized the activation energy and trap concentration in Fig. 4. The SH1* peaks near 150 K increase as the proportion of the P-well increases. This could be due to more significant damage from Al implantation for P-well formation, which is related to Al acceptors. The trap density of Z1/2 peak near 300 K decreases from 4.5×1011 cm-3 to 3.4×1011 cm-3. The Z1/2 is derived from carbon vacancies (VC) and is known as a major carrier lifetime killer defect in SiC. By Al implantation in SiC, carbon interstitials (Ci) might be formed by collisions, and subsequent heat treatment causes Ci to occupy the VC [5]. Additionally, the RD1/2 peak near 450 K increases; it could be generated by high-energy ion-implantation or irradiation and consists of a nonaxial C-Si divacancy. While previous works typically analyze the effects of various implant doses and dopants in 4H-SiC [2,3], our study conducts an in-depth analysis of the impact of the implantation process and Al dopant on major killer defects in 4H-SiC-based diodes. By varying the proportion of the p-well region, we investigated the changes in deep level defects in both MPS and PiN diodes.

ABSTRACT. SiC power devices have garnered increasing interest in the power electronics industry due to their superior performance at high operating temperatures and lower switching losses compared to traditional Si-based power devices. It is forecasted that SiC power devices will account for half of the growth in the power semiconductor market over the next decade. As the adoption of SiC power MOSFETs continues to expand into power supplies and electric vehicles, applications requiring excellent reliability are also growing in tandem [1].

During the manufacturing process for SiC MOSFETs, various issues related to raw materials may arise. One such issue is the occurrence of high-level warpage in SiC wafers. As the processes progress within the Fab, the warpage of the wafer gradually increases (Fig. 1), significantly impacting productivity due to equipment issues and variation in unit process data.

In this experiment, we propose two methods for improving SiC wafers with high-level warpage. The first method involves Single Side Polishing. Typically, wafers entering the Fab undergo Dual Side Polishing to ensure they are introduced in a flat state [2]. However, when a flat wafer undergoes processing in the Fab, it gradually transitions into a compressive state, potentially causing issues during the process. By implementing Single Side Polishing, wafers are introduced into the Fab in a tensile state (Fig. 2), resulting in a lower warpage level even after undergoing compression during processing (Fig. 3).

The second method involves densification through low-temperature annealing. As mentioned earlier, as the process progresses, the initially flat wafer transitions into a compressive state, gradually increasing the warpage level. Conducting low-temperature annealing causes thermal release within the wafer due to the applied heat, resulting in a decrease in the wafer's warpage level [3] (Fig. 4).

In summary, Single Side Polishing and low temperature annealing for densification can effectively reduce the warpage level of the wafer, which becomes increasingly compressive as the process progresses. By addressing high-level warpage with these methods, it is possible to rectify issues occurring during the process, leading to improved productivity.

ABSTRACT. The effect of a sulfurization treatment carried out at 800°C on silicon carbide (4H-SiC) surface was studied by detailed chemical, morphological and electrical analyses. In particular, X-ray photoelectron spectroscopy confirmed sulfur (S) incorporation in the 4H-SiC surface at 800°C, while atomic force microscopy showed that 4H-SiC surface topography is not affected by this process. Notably, an increase of the 4H-SiC electron affinity was revealed by Kelvin Probe Force Microscopy in the sulfurized sample with respect to the untreated surface. The electrical characterization of Ni/4H-SiC Schottky contacts fabricated on sulfurized 4H-SiC surfaces revealed a significant reduction (0.3 eV) and a narrower distribution of the average Schottky barrier height with respect to the reference untreated sample. This effect was explained in terms of a Fermi level pinning effect induced by surface S incorporation.

ABSTRACT. Various annealing conditions using Al-based (Ti/Al/Ti/Au=70nm/100nm/5nm/120nm) and Ni-based (Ti/Ni/Ti/Au=20nm/90nm/5nm/120nm) metal contacts to n-type and p-type ion-implanted 4H-SiC epi layers have been studied in the effort to optimize simultaneous ohmic contact formation with the lowest specific contact resistance (SCR) values. Values of 1.091×10-4 Ω∙cm2 and 1.158×10-5 Ω∙cm2 were achieved using Al-based Ohmic metal contacts for p-type and n-type 4H-SiC, respectively, at an annealing temperature of 950°C and under vacuum for 90 sec. Ohmic formation mechanisms were analyzed using X-Ray Diffraction (XRD) surface analysis method, indicating Ti3SiC2 alloys to be the key intermediate layer formed at SiC/Ti interface, responsible for Ohmic properties to p-type SiC. The paper summarizes the metal process combinations possible in forming simultaneous ohmic contacts to both n and p-type 4H-SiC, offering various options in either using the same metal materials and/or common annealing conditions.

ABSTRACT. We fabricated a Si-face 3C/4H-SiC heterojunction and applied a Ti/Al-based stack for ohmic contact, previously reported as effective for p-type doped 3C-SiC. We evaluated the contact resistance of this stack when applied to the heterojunction. Specific contact resistance was found to be 1.0 × 10-4 Ω・cm2, confirming effectiveness of the stack.

ABSTRACT. This study focuses on analyzing the electrical performance and characteristics of Schottky Barrier Diodes (SBDs) on the carbon face (C-face) epitaxial layer. The C-face epitaxial layer is grown on monocrystalline 4H-SiC and has a thickness of ~ 11 μm. It displayed minimal surface roughness, with an Rq of ~ 0.3 nm. The C-face termination epitaxy was examined using grazing-angle X-ray photoelectron spectroscopy (XPS) analysis. SBDs were fabricated using a Ti/Al metal stack. Schottky Barrier Height (ΦB) of about 1.2 eV was extracted from I-V measurements. Temperature-dependent I-V measurements demonstrated a forward voltage decrease as the temperature rises when the forward current is < 1 μA. However, for forward currents > 1 μA, the forward voltage increases with temperature. This rise in forward voltage could lead to a reduction in reverse recovery time and thus enhancing the switching speed. Additionally, the diode exhibits remarkable immunity to reverse leakage current up to 200 °C, surpassing the performance of the 6.5KV JBS diode on Si face 4H-SiC.

ABSTRACT. Ohmic Contact Formation is a fundamental yet complex process in the manufacture of semiconductor devices. It involves the creation of metal contacts on the semiconductor material, facilitating efficient current flow. For SiC devices, OCF is a challenging endeavor due to the material's inherent properties. The conventional approach typically involves the application of nickel or titanium layers. This process facilitates the transition from Schottky to Ohmic contacts, which is essential for efficient device operation. For thick SiC substrates rapid thermal processing (RTP) is established as a standard process generating good and well controlled silicide interfaces. As SiC devices decrease in thickness the use of RTP is limited and thermal annealing processes by pulsed laser sources are applied. This study aims to investigate the impact of different laser parameters on the formation of NixSiy layers and identify qualitative correlations of different analysis results. All tests were conducted on 350 µm thick 4H-SiC wafers covered with a 70 nm NiAl. The wafers were processed under inert atmosphere with varying laser conditions. These setups were established with two different diode pumped solid state laser sources with a wave length of 355 nm that differ in pulse duration. Laser source A utilizes short nanosecond pulses of approx. 30 ns and Laser source B long nanosecond pulses with a pulse duration of approx. 80 ns. Both laser sources were then projected onto the wafer surface with two different beam shapes. The first optical setup resulted in a gaussian beam and a second optical setup a flat top beam (Figure 1). Parameter sweeps of laser power and pulse overlap were conducted for the four combinations of pulse duration and beam shape and subsequently compared to each other. The analysis methods performed on all parameter fields consist of surface / sheet resistance measurements to assess the electrical performance, x-ray fluorescence spectroscopy to asses a potential ablation of the Ni, x-ray diffraction spectroscopy for information on the distribution of chemical phase, surface roughness measurements and scanning electron microscopy of cross sections of the individual pulses and overlap areas prepared by focus ion beam milling to measure the layer thickness and investigate the distribution of the chemically released carbon. Representative results of these measurements for laser B and a flat top shape can be found in figure 2 to 4. Major findings of the study consist of a high tolerance of the electrical performance towards high laser fluencies, a direct correlation of the energy density of the laser with the thickness of the resulting NixSiy layers (Figure 5) for flat top beams and the impact of pulse overlap on the formation of carbon rich layers at the interface of the SiC with the NixSiy - indicating a process window for optimum quality based on pulse overlaps below 30%.

ABSTRACT. In this paper, we propose a 650V – 1.3kV voltage-controlled Si-SiC hybrid power switch with both lower ON voltage than the current IGBTs and also significantly shorter tail of the collector current during turn off. The underlying principle, forced carrier extraction, relies on introducing an extraction plug to the standard IGBT architecture. This enables the attachment of a SiC Forced Extraction Device which fulfills the freewheeling role and also provides a relatively low resistance path for the removal of electrons from the drift region. The approach yields a three terminal power switch (FE-IGBT) that will employ the standard gate driving circuitry of the current IGBT market. It exhibits a much faster turn-off time, orders of magnitude lower than the standard IGBT architecture, with 10% to 18% lower turn-off energy.

ABSTRACT. This paper analyzes the temperature and gate voltage (VGS) impact on the drain-source on-resistance (Rds,on) of a vertical 1.2 kV Silicon Carbide (SiC) Schottky barrier diode embedded MOSFET (SBD-embedded MOSFET).When VGS is 10 V, the channel is not fully activated. As the temperature increases, Rds,on is possibly dominated by the resistance of the channel (RCH) in the beginning then by the residual resistance (Rs). Rs is defined as Rds,on minus RCH. The longer the channel length, the more pronounced the impact of RCH on Rds,on. When VGS is 20 V, the channel is fully activated and Rds,on is possibly dominated by Rs. Rds,on of a MOSFET with a larger active areas is less sensitive to temperature changes.

ABSTRACT. This paper proposes a structure with locally etched gate in a DMOSFET which has a linear-type cell. By adjusting the etched gate width and length in the structure, we can observe a tendency in Ron,sp, Qgd,sp and HF-FOM [Ron,sp × Qgd, sp]. These observations are of significant importance not only for the analysis of static properties, but also for the analysis of dynamic properties. In particular, it impacts the delay time and transition time [1]. Fig. 1. shows the 2D and 3D structures of (a) DMOSFET and (b) locally etched gate MOSFET (LEG MOSFET) and the parameters are described in the Table I. The B-B' region of LEG MOSFET is the locally etched region. LEG MOSFET’s unetched region has the same structure as the DMOSFET (A-A'). In the layout of the structure, a dashed line means one unit cell, the colored area is one-fourth cell. We simulated the colored area through Sentaurus TCAD. In the process of designing the proposed structure (LEG MOSFET), we went through three steps. 1) determination of JFET concentration, 2) determination of etched gate length (LEG) through 2D simulation and 3) determination of etched gate width (WEG) through 3D simulation. If locally etching is applied, it is important to set the JFET concentration and etched gate length. Because the electric field may be crowded at the corner (Fig. 1. B-B' Cross Section). Fig. 2. shows a Eox, Ron,sp and Vth as a function of JFET concentration. This indicates that the electric field increases with an elevated concentration of JFETs. The JFET concentration is determined the one with the smallest Eox among values whose Ron,sp is smaller than 10 mΩ∙cm2 and Vth is larger than 5 V. JFET concentration (1×1016 ) was excluded because the on-resistance was larger than 10 mΩ∙cm2, and among the remaining cases the oxide field was the smallest at JFET concentration (3×1016), so this was determined. Fig. 3. shows the results of Eox, Ron,sp, Qgd,sp and HF-FOM as a function of LEG. As the LEG increases, the Eox increases due to the electric field crowding effect at corner of oxide. But at a certain point, the corner is protected by depletion region which formed at the junction between the Pbase and the N-Drift. As a result, Eox can decreases. Specifically, When LEG is larger than 0.7 μm, Ron,sp increases rapidly. Because the shortened LEG results in a reduction in the length of the accumulation region that facilitates the vertical dispersion of electrons when a channel is formed [2]. We determined LEG to be based on EOX being less than 3MV/cm. But, In the case of 0.7 μm, this value was exclueded due to peaked Ron,sp, so determined LEG 0.6 μm. To demonstrate the effect of WEG, the simulation was performed in 3D. As shown in Fig. 4, It can be observed that the oxide field remains relatively unchanged as the WEG increases. This is due to the fact that the field is crowded in the corner for all WEG. ( Fig. 1.(b) ) Also, it can shows that an increase in WEG is accompanied by a reduction in Qgd,sp, while the Ron,sp exhibits an upward trend. As the WEG increases, the area of the DMOSFET shrunk. This shows that Ron,sp and Qgd,sp are a trade-off relationship. The best HF-FOM was achieved with a WEG of 2.3 μm. An increase about 65% of HF-FOM compared to DMOSFET, which has WEG zero. Table Ⅱ. summarizes the results. This work was supported from the National Research Foundation of Korea (RS-2024-00423646) was appreciated.

ABSTRACT. Reverse-bias current and forward surge-current capability of SiC Schottky diodes are two important parameters that motivated a departure from pure SiC Schottky-barrier diodes (SBD). The predominant modifications in commercial SiC Schottky diodes, which address observed issues with these two parameters, include the junction barrier Schottky (JBS) diode for reduced reverse-bias current and the merged P+N Schottky (MPS) diode for improved non-repetitive surge current [1]. A key feature of both structures is the integration of implanted P-type regions, with specific geometric properties, to achieve the desired forward and reverse characteristics. The P-type regions in both JBS and MPS diodes require the use of ion implantation, along with precise photolithography to achieve designed width of and spacing between the P-type regions [2].

However, a modern SiC SBD without ion-implanted P-type regions was recently patented [3] and successfully fabricated. The edge termination in this diode is achieved by tapered negative charge, created by acceptor ions at the outer edge of a P-type ring, as illustrated in Fig. 1. The P–N junction between the P-type termination ring and the N-type drift region is formed by epitaxial layers. Consequently, this junction is free of defects and can completely block the reverse-bias current at the perimeter of the diode. Typical forward- and reverse-bias current–voltage characteristics are shown in Figs. 2, 3, and 4 for 650V, 1200V, and 1700V diodes, respectively.

An experimental and theoretical study of the reverse-bias current showed that, at temperatures above 60˚C, the reverse-bias current is dominated by the two fundamental current mechanisms: (1) tunneling and (2) thermionic emission [4]. As a result, measured reverse-bias currents at these temperatures did not exhibit chip-to-chip variations and matched the fundamental model and the parameters for tunneling and thermionic currents. Increased currents above the theoretical level were observed at room temperature, which was due to leakage through point defects in the main area of the Schottky contact.

The forward surge-current capability of SiC Schottky diodes is usually classified in two ways: (1) repetitive and (2) non-repetitive peak current of a 10ms half sine wave. For a given case temperature, the non-repetitive surge current of MPS diodes is higher than in the case of pure SBD’s, because integrated P+–N junctions turn on at high surge currents to reduce the forward voltage and to enable higher surge currents for the power dissipation that destroys the diode. However, the integrated P-type regions reduce the area of Schottky contact. To compensate for the increased on resistance due to the reduced Schottky-contract area, the SiC substrate in both JBS and MPS diodes is thinned. In terms of thermal characteristics, this thinning reduces both the thermal resistance and the thermal capacitance. A recent experimental and theoretical analysis demonstrated that the adverse effect of the reduced thermal capacitance is dominant, resulting in faster chip-temperature increase during the surge current [5]. The SiC substrate was not thinned in the fabricated SBD’s, and the much higher thermal capacitance maintained the chip temperature within the specified 175oC at much higher repetitive peak surge currents in comparison to MPS diodes.

[1] B.J. Baliga, Modern Silicon Carbide Power Devices. (World Scientific, Singapore, 2024). [2] F. Roccaforte, P. Fiorenza, M. Vivona, G. Greco, and F. Giannazzo, Materials 14, 3923 (2021). [3] S. Dimitrijev and J. Han, U. S. Patent No. 10,971,580 (6 April 2021). [4] J. Nicholls, S. Dimitrijev, P. Tanner, and J. Han, Sci. Rep. 9, 3754 (2019). [5] J. Damcevska, S. Dimitrijev, D. Haasmann, and P. Tanner, Sci. Rep. 13, 19189 (2023).

ABSTRACT. This work investigates the optimization of electric characteristics through the application of artificial neural networks using machine learning methods for 1200V 4H-SiC vertical double diffusion MOSFETs (VD-MOSFETs), aiming to predict threshold voltage. Numerous experiments with various P-Well concentration or gate insulator thickness were established 100 databases to train machine learning method. A prediction characteristic has been established with an accuracy exceeding 95% with a maximum error of 4.7%. ANN model of a machine learning method is able to achieve high accuracy for the performance prediction of 4H-SiC VD-MOSFET devices.

ABSTRACT. In the field of next-generation high-power electronics, wide-bandgap materials are considered key due to their excellent properties in harsh environments [1]. Among the ultrawide bandgap materials, Ga2O3 is expected to surpass the trade-off relationship between breakdown (BV) and on resistance (Ron,sp). However, the Ga2O3 vertical Schottky barrier diode (SBD) still cannot achieve the theoretical breakdown electric field. To improve electric field management, device designs incorporating field rings, junction termination extension, field plates, and mesa structure could be used to reduce the leakage current in the reverse bias state [2]. The edge termination technique has been demonstrated to extend the breakdown voltage close to the ideal value that is determined by the material properties [3]. The SBDs were fabricated on Si-doped β-Ga2O3 grown by halide vapor phase epitaxy (HVPE) on a Sn-doped (6×1018 cm-3) (001) β-Ga2O3 substrate. In the SBD with mesa structure, the circular mesa with a diameter of 162 μm and a depth of 500 nm was formed around anode electrodes. The Ti/Au metal stack on the polished back side of the substrate acted as a cathode while Ni/Au/Pt layers on the epitaxy acted as the anode electrode. After the fabrication process, current-voltage (I-V) measurements were performed before, during and after the heating as shown in Figure 1. From the results, the Ron,sp at 1 V measured initially before heating are 6.9 mΩ•cm2 and 7.9 mΩ•cm2 in planar and mesa SBDs, respectively. Moreover, the current characteristics are changed after the heating in both planar and mesa SBDs. The changes caused by heating is more significantly in planar SBDs. In addition, the leakage current at -165 V is reduced by approximately 99.9% in the mesa structure. The reverse bias characteristics of the SBDs, where the SBDs with mesa structure have approximately 2.75 times higher BV than SBDs without a mesa structure. Deep level defects were investigated by deep level transient spectroscopy (DLTS), and the SBDs with different structure have similar trap energy levels shown in Figure 2. In general, the trap density is larger in the SBD with mesa structures, however, the trap near the Ec - 1.2 eV is only detected for the SBD without the mesa structure and this defect is related to unstable defects [4]. Furthermore, we extended the study by performing the scanning electron microscopy-electrical dispersive spectroscopy to get defect information of the SBDs by heating which could be related to the DLTS results. We will discuss these results considering the enhanced electrical performance of SBDs with mesa structures in high temperature environments.

ABSTRACT. Static and dynamic electrical characterization are carried out on 4H-SiC BJTs at Ampere Lab. The BJT were fabricated on a 4H-SiC wafer with an epilayer layer of 120 µm thick and doping concentration of 8x10+14 cm-3. A maximum breakdown voltage of 11 kV was obtained in vacuum conditions. Three distinct configurations of BJTs with their respective finger length and active area are incorporated to optimize the electrical parameters. A maximum current gain B is about 15 for all configurations of the BJT. Switching measurement will be presented in the final paper.

ABSTRACT. Concerning the ramp in production and supply of Silicon Carbide devices targeting the automotive industry, the availability of large area transistors has become paramount specifically for the traction inverters application. This is motivated by the reduction of the number of dies per switching cell. Commercial 1200V single die transistors are currently limited to a rated current slightly above 100A at a working temperature around 125°C [1]. The automotive industry is currently targeting 1200V transistors with a current rating above 200A. Despite its superior characteristics in terms of band gap, intrinsic carrier generation rate, thermal conductivity, and critical electric field compared to silicon, 4H-SiC technology still faces maturity issues due to the presence of various crystalline defects. Understanding the distribution of defects in SiC substrates and how they interact with epitaxial growth is crucial for the development and manufacturing of high-quality substrates that will enable large area devices (compatible with the targeted fabrication yields). Previous works have evidenced the link between basal plane dislocations (BPD) and various defects affecting the functionality of power devices [2-5]. Stacking faults (SFs) in the epitaxy drift layer have been found to be connected with dislocations (BPD or threading screw dislocations-TSD) in the substrate. These correlations indicate that the use of a high-quality substrate is effective in reducing in-grown SFs in epilayers. In parallel, BPDs of the substrate have been correlated with SF complexes also called carrots. The best solution is to lower the crystal defect density of the substrate. The elimination especially of basal plane dislocations is still the ultimate target for SiC single crystal substrates [6]. The SmartCut™ technology combines a thin (350-800 nm) single crystal SiC layer with a thick (350 μm) low-resistivity polycrystalline SiC (pSiC) carrier wafer using layer transfer [7]. Besides the combination of a highly doped pSiC material with commercial single crystal 4H-SiC material (20 mΩꞏcm), this technology enables the stacking of two SiC based materials with dissimilar crystal quality. Advanced (Adv) SiC engineered substrate samples have been prepared through the layer transfer of a BPD free layer obtained by epitaxy growth on commercial single crystal 4H-SiC substrates. BPD density below 0.1/cm² has been measured through surface etching of the thin transferred SiC layer by potassium hydroxide [8]. To evaluate the performance of this new technology, a set of 15 SmartCut™ wafers was prepared, which encompassed three Adv SiC Engineered Substrates. Prior to the epitaxial layer growth, the wafers underwent preliminary evaluation through laser scattering and photoluminescence (PL) non-destructive inspection tool Candela CS920, which adopts a =355 nm laser. Following 14 m epitaxial growth carried out at 1650°C chemical vapor deposition (CVD) process [9,10]. The wafers underwent defects inspection and were subjected to Electrical Wafer Sorting (EWS). Figure 2A illustrates the distribution of defects across the entire batch, with examples of defects detected by scatter light method and photoluminescence, presented in the figure's lower section. Inspection data denotes a preponderance of defects in the reference SiC engineered substrate (Ref) wafers, with Stacking Faults (SFs) accounting for (51.4±11.2) % of the total defects identified. In contrast, the Adv SiC Engineered Substrates showed a significantly lower SFs incidence of (31.4±9.9) % which corresponds to a relative improvement of roughly 70% of stacking faults. The yield improvement is further evidenced by the Total Usable Area (TUA), which is determined by analyzing the die areas free from defects within a (5mm×5mm) grid. Figure 2B also illustrates TUA both before and after epitaxial growth. For Ref substrates, the initial TUA is (92.7±3.1) %, which is reduced to (84.4±6.4) % following epitaxial growth. In contrast, the Adv SiC Engineered Substrates start with a pre-epitaxial TUA of (95.6±1.2) %, which marginally decreases to (90.3±1.6) % post-epitaxial growth, thus confirming a higher yield when compared to the Ref substrates as well as to standard epitaxial growths on 4H-SiC conventional substrate illustrated by the green band. The small number of wafers used in such activity hampers an effective statistical evaluation of the technology here proposed, however, the evidence of the decreasing of photoluminescence defects signal (SFs) is more than an indication that the Adv SiC technology proposed is damping down the propagation of dislocations through the epilayer. Additional encouraging indication is depicted in Fig3, where Electrical Yield is reported comparing Ref and the Adv SiC engineering. The results exhibit comparable device performance, that will be shown during the conference, with a slight improvement in relative yield by using Adv SiC technology. Such final evidence leads us to strengthen the basic concept of taking care of the crystal quality of the material used, in order to obtain a valuable epitaxy with low defect density and a consequential competitive electrical yield in power device having increasingly larger size and higher voltage.

This work has been carried out within TRANSFORM project which has received funding from the Key Digital Technologies Joint Undertaking (KDT JU) under Grant Agreement No101007237. The JU receives support from the European Union’s Horizon 2020 research and innovation program and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain.

ABSTRACT. Rapid progress in the growth of 4H-SiC epitaxial layers allow device scientists/engineers to tighten the specifications of doping and thickness uniformities of SiC epitaxial films. Further, reducing the cost of SiC epitaxial layers is a continuing goal. A compelling good approach is to choose a multi-wafer warm-wall epi reactor which has been shown to have very high wafer throughput[1]. In all reactors including a warm wall reactor, the precursors such as silane, DCS or TCS, C3H8 or C2H4, and nitrogen are heated by passing over hot reactor components to achieve the efficient decomposition of these chemical precursors. However, the precursor molecules crack before reaching the substrate and can form parasitic SiC coatings. Such coatings change the emissivity of reactor parts, changing their temperatures. The allowed vapor pressure in the gas phase is also a function of the chemical composition of these deposits. Subsequently, the effective Si/C ratio at the wafer varies changing the nitrogen incorporation efficiency on the SiC epitaxial wafer. This trend follows a higher order polynomial [2] but can be used to adjust the intentional dopant flow for a desired layer doping. Here, we discuss an approach on how to minimize the effect of changing Si/C ratio on absolute layer doping and thickness even though the dopant incorporation efficiency varies due to parasitic coating for the full growth campaign. Our approach analyzes the data, identifies the pattern, then the pattern is used to make predictions or decisions. The vapor pressure of Si varies due to cumulative coating (increased surface area of dendrite-like structure) and leads to reduced growth rate as function of cumulative coating as shown in Fig. 1(a). The nitrogen incorporation was analyzed as a function of cumulative coating on the reactor parts followed by a multi-order polynomial fit as shown in Fig. 1(b). The derived models were used to make the decisions for predictive doping by adjusting the flow rates of nitrogen precursors during upcoming campaigns at specific cumulative thickness of reactor parts coating. The same approach was also used for the adjustment of growth time to obtain the targeted epi layer thickness as a function of cumulative coating. Consequently, the predictive doping control resulted in the improvement of doping Cpk from 0.37 to >1.67 and the predictive thickness control resulted in the improvement of thickness Cpk from 0.75 to 1.61. This implies that the process is six sigma qualified and expected overall nonconformance was 0.001% for doping, as shown in Fig. 2. Moreover, the average 200 source contrast projected chip yield using a Lasertec system 88-HIT and the machine learning based PLDIZ recipe was >94% by considering the Particle, Bump, Micropipe, ComplexSF, Polytype Inclusion, Particle Inclusion, and ScratchTrace as device killer defects. The average BPDs are <25 on a 150mm wafer using a 1µm thick buffer layer.

For this effort, we acknowledge the support by Coherent SiC epi process engineers (Philip Frey, Rajat Jain, Troy Tomlinson, Mark Strzelecki and Rick Vega), our SiC epi equipment team (Martin Wilcox, Brad Howsare, Steve Nemeth, and Juan Sosa), and our SiC substrate team. We gratefully acknowledge partial funding for this work under AFRL under contract number “FA8650-17-2-1727 P00015”, Jane Thompson contract monitor.

References: [1] Wolfspeed orders multiple Aixtron G10-SiC systems to support ramp-up of 200mm epi production, (n.d.). https://www.semiconductor-today.com/news_items/2024/apr/aixtron-190424.shtml (accessed July 12, 2024). [2] L.B. Rowland, A.A. Burk, C.D. Brandt, Nitrogen Doping Efficiency During Vapor Phase Epitaxy of 4H-SiC, Mater. Sci. Forum 264–268 (1998) 115–118. https://doi.org/10.4028/www.scientific.net/MSF.264-268.115.

ABSTRACT. Monocrystalline 4H-SiC is a promising semiconductor material due to its large bandgap, thermal conductivity, and high-temperature strength making it suitable for high-performance power devices in extreme conditions [1]. The quality of 4H-SiC film growth, which depends on the substrate wafer obtained by the physical vapor transport (PVT) method at roughly 2400 °C is crucial for effective device performance. [2]. However, achieving optimal growth conditions is challenging due to high operating temperatures and monitoring difficulties in the growth chamber, leading to structural defects such as micropipes, and various dislocations in the crystal growth process [3]. In this study, the deposition and growth process of silicon carbide (SiC) on a 4H-SiC (0001) substrate with off-cut angles of θ = 0, 2°, 4°, 8°, and a broad range of temperatures, is studied using molecular dynamics (MD) simulations with LAMMPS [4,5]. The goal of the MD simulations is to uncover the fundamental microscopic mechanisms behind the nucleation and growth of various SiC polytypes, the formation of dislocation defects, and the influence of temperature and substrate angle on film stress and surface morphology. The computational setup illustrated in Fig. 1(a), involves depositing a total of 120,000 SiC atoms for a total duration of 60 ns. During the deposition process, nucleation of the 4H-SiC crystal begins after an amorphous layer of atoms completely covers the substrate surface. The crystal growth then progresses from the substrate surface toward the film surface by rearranging the amorphous atoms into the 4H-SiC crystal structure. After all atoms are deposited, the structure type is characterized as shown in Fig. 1(b) where the amorphous layer varies between 0.1 nm and 3 nm with the thickness depending strongly on the substrate temperature and favoring relatively small off-cut angles of the substrate. We find that there is a strong sensitivity to the substrate angle and temperature by the analysis of the dislocation density in Fig. 1(c). Small off-cut angle substrates yield a closely aligned lattice of the deposited film which reduces the formation of dislocations while higher off-cut angle substrates increase the formation of dislocations. Additionally, higher temperatures can promote dislocation mobility and glide, leading to annihilation which helps to reduce the overall dislocation defect region. We establish that the residual stress depicted in Fig. 1(d) increases almost linearly with deposition time and shows a significant dependence on the off-axis angle. Notably, θ = 0 and θ = 4° exhibit similar residual stresses across all temperatures considered which points to the fact that the stress distribution in a 4° is more uniform and reduces localized stress concentrations that can cause defects. To further explore the impact of the substrate morphology on the deposition and growth of the SiC crystal, additional simulations are carried out using a substrate with surface steps and off-cut angles of θ = 0, 2°, 4°, 8°, as shown in Fig 2. These simulations employed the same computational setup as described in Fig. 1(a). The major results show that the surface steps play a nontrivial role in determining the structural and mechanical properties of the grown 4H-SiC film, and precise control over the substrate angle and temperature is necessary to optimize dislocation density, residual stress, and film quality.

[1] A.A. Lebedev, and V. E. Chelnokov, Semiconductors 33, 999–1001 (1999). [2] H. Tsuchida, I. Kamata, T. Miyazawa, M. Ito, X. Zhang, and M. Nagano, Mater. Sci. Semicond. Process. 78, 2-12 (2018). [3] B. Raghothamachar and M. Dudley, in Wide Bandgap Semiconductors for Power Electronics: Materials, Devices, Applications (P. Wellmann, N. Ohtani, R. Rupp, eds.) pp 169-197, 2022. [4] S. Plimpton, J. Comput. Phys. 117, 1-19 (1995). [5] K. Wu, Q. Mei, H. Liu, S. Zhou, B. Gao, C. Li, S. Liu, and L. Wan, Crystals 13, 715 (2023).

ABSTRACT. While NO nitridation passivates defects at the SiO2/SiC interface, the high density of defects remains in SiC MOS structures. We recently reported a process that achieves further reduction in the interface state density (Dit). The process comprises the following steps: (i) plasma nitridation of the SiC surface, (ii) SiO2 deposition, and (iii) post deposition annealing (PDA). Although CO2-PDA is performed aiming to reduce defects in SiO2 in the recent study, the role of PDA was not yet investigated in detail. In this study, we investigated the impacts of PDA temperature and ambient on SiC MOS interface properties and reliability. Low Dit values and the high reliability were achieved by CO2-PDA at 1250℃. It was found that the key to obtaining superior electrical properties would be attributed to the high temperature annealing and compensation of oxygen vacancies in SiO2 by CO2.

ABSTRACT. Almost all state-of-the-art semiconductor interconnects use solid metals welded together through thermo, thermo-sonic, ultrasonic, or thermo-compression bonding. These interconnects are degraded by thermo-mechanical stress and are a primary cause of failure in power semiconductor devices. For SiC MOSFETs, power cycling lifetime may be only 20% - 30% of the lifetime of Si IGBTs when packaged with identical interconnect technologies.

In this work, we replace solid metal interconnects with liquid metals. The latest results demonstrate a factor of 80x increase in the power cycling lifetime of SiC MOSFET chips when compared to SAC-305 solder and Aluminium wirebonds. No solid interconnection materials remain in the power module.

The presentation will detail the construction of the liquid metal based SiC MOSFET packages, the power cycling and thermal resistance test routines, and estimations for the system level impacts. This may include up to 80% reductions in system weight, and 60% reductions in system cost.