ABSTRACT. Silicon carbide (SiC) epi-wafers, with thick epitaxial layers required for high-voltage applications, are prone to warping and having basal plane dislocations (BPDs) form due to the lattice mismatch between the epilayer and substrate during the manufacturing process. These problems must be solved to improve yields, particularly for large-diameter wafers. Our previous study revealed that BPDs are generated mainly from triangular defects in SiC epi-wafers at epilayer thicknesses of 50 μm or more. In this study, we classified the observed BPD half-loops into two types and aimed to elucidate how the BPDs formed, from the perspective of the behavior in the wafer and numerical stress analysis. Fig. 1 shows synchrotron x-ray topography images and their schematics of the 4° off 150 mm-diameter epi-wafer with a 200-μm thick n− epilayer (Nd−Na=~2×1014 cm−3) after polishing the n+ substrate (Nd−Na=~5×1018 cm−3) leaving ~3 μm. As the transmission image (g=11¯20) in Fig. 1(a) shows, BPD half-loops were generated by triangular defects in the epilayer and extended wide on the basal plane. Noteworthy, however, is the relatively small density of BPD having propagated from the substrate into the epilayer (<0.07 cm−2). Many of the BPD half-loops from the triangular defects reach the crystal surface on the substrate side, indicating that the BPDs propagated beyond the epilayer/substrate (epi/sub) interface into the substrate. Also worth noting is the fact that the BPD half-loop is narrower at the epilayer surface and widens as it approaches the epi/sub interface. Fig. 1(b) shows a reflection topography image with a penetration depth of ~12 μm taken from the C-face (g=11¯2¯8). As shown in the figure inset, the BPDs propagating perpendicularly or obliquely to the step flow direction exhibit dark contrasts, which correspond to edge-type BPDs with an extra half-plane above the BPD core (epilayer side) [1]. Some of the BPD half-loops have segments with edge components near the epilayer surface and the inside of the substrate, with an extra half-plane below and above the BPD core, respectively, as the schematic of Fig. 1(c) shows. These BPD half-loops propagating into the substrate are hereinafter referred to as Type-A. Conversely, BPD half-loops of the opposite sign were also observed, as shown in Fig. 2. The transmission topography image (g=11¯20) shows that BPDs of this type form interfacial dislocations (IDs) at the epi/sub interface and are narrower than that of Type-A BPDs. Confirming the dislocation contrast in the reflection topography image taken from the C-face (Fig. 2(b), g=11¯2¯8), the IDs appear as bright contrasts, corresponding to edge-type BPD with an extra half-plane below the BPD core (substrate side). Such BPD half-loops forming IDs are referred to as Type-B. For these two types of BPD half-loops, their widths in the [1¯100] direction at the epi/sub interface in epi-wafers with epilayer thicknesses of 50, 100 and 200 μm are examined based on the topography image and plotted as shown in Fig. 3. BPD formation from triangular defects was observed only for an epilayer thickness of 50 μm or more. As for the Type-A, it is evident that the BPD width increases with epilayer thickness, about 10 mm wide for a 200-μm epi-wafer. Conversely, for Type B, although the width appears to increase gradually with epilayer thickness, the tendency is far less compared to Type A. The stress caused by the differing coefficient of thermal expansion between the n− epilayer and the n+ substrate is considered one of the driving forces for generating and increasing the width of the BPD half-loops. Fig. 4 shows the calculation results of the stress σrr acting on the BPD located 5 μm below and above the epi/sub interface (substrate side), using a two-dimensional axisymmetric model based on the finite element method, assuming coefficients of thermal expansion for the epilayer and substrate of 5.70×10−6 and 5.22×10−6 K−1, respectively [2]. Here, a uniform temperature distribution is assumed. The lattice constant of the epilayer is assumed to be larger than that of the substrate, resulting in compressive (σrr < 0) and tensile (σrr > 0) stresses on the epilayer and substrate. As the epilayer thickens, the tensile stress on the substrate increases while the compressive stress (<0) declines. These stresses can qualitatively explain the driving forces of the two types of BPD half-loops that form. The observed widening of Type-A BPD in the substrate across the epi/sub interface can be attributed to the tensile stress acting on the substrate. The tendency for the Type-A BPD half-loops to widen with increasing epilayer thickness is also consistent with the stress calculation. Conversely, Type-B BPD tends to mitigate the compressive stress in the epilayer and any slight change in width observed with respect to epilayer thickness can be attributed to reduced compressive stress with respect to the epilayer thickness. Since other possible driving forces, such as thermal stress caused by the radial temperature distribution and local stress near the nucleation point (triangular defects), can affect the formation and width of BPD half-loops, these effects also need to be considered, e.g. to discuss the in-plane distribution of BPD half-loops.

ABSTRACT. Silicon Carbide (SiC) based devices have become mainstream for power applications rated from 1-3.3kV [1]. However, grid scale, defense and pulsed-power applications require higher voltage rated devices such as insulated gate bipolar transistors (IGBTs) with very high reliability operation and high surge current capability. Basal plane dislocations (BPDs) can cause stacking fault (SF) expansion during IGBT operation, which results in forward voltage degradation, and higher reverse leakage currents. Developments in epitaxial growth over past two decades have successfully achieved almost BPD-free epitaxial layers by converting BPDs to threading edge dislocations. However, under surge current conditions, very high carrier injection can occur and cause BPDs to propagate from substrates into the epitaxial layers causing device failure [2]. In this work, we investigate BPD faulting under very high carrier injection in engineered SiC substrates SmartSiC™ and compare it to monocrystalline substrates, and also analyze any associated stacking fault expansion in epitaxial layers deposited on both the substrates. For this work, 10 µm thick, 1x1016 cm¯³ n-doped epitaxial layers with 2 µm thick, 1x1018 cm¯³ n-doped buffer layers were simultaneously grown on a 150 mm diameter engineered substrate and a commercial monocrystalline SiC substrate. The SmartSiC™ substrate consists of less than 1 µm thick monocrystalline SiC layer transferred on to a thick polycrystalline SiC substrate using the Soitec SmartCut™ layer transfer process process. Full wafer ultraviolet photoluminescence (UVPL) imaging was performed using a 4W, 355 nm UV laser coupled to a custom microscope setup. Above bandgap UV excitation creates electron-hole pairs in SiC, which simulates current injection during device operation. Ultra-high carrier injection was performed in several 2.5x2.5mm² areas in both wafers by UV excitation with 100–10,000 Wcm¯² power densities. The stress duration varied from 5-30 mins for different stress conditions. UVPL imaging was followed after each stress condition to evaluate BPDs in the epitaxial layers. Upon UV illumination at 100 Wcm¯² for several minutes, no BPDs were observed for all regions analyzed. Successive UV stressing at 1500 Wcm¯² caused BPD faulting in the monocrystalline substrate and propagation into the epitaxial layer, which was directly observed from the UVPL images. Upon stressing few regions in the engineered substrates at 1500 Wcm¯², no BPD faulting or expansion was observed in any of the regions. Following this, some regions in the engineered substrates were stressed at over 10,000 Wcm¯², which also did not cause any BPDs to expand into the epitaxial layer. To understand potential reasons that apparently makes the engineered substrates less prone to BPD faulting, estimates of carrier densities were simulated for the UV stress conditions. Typical carrier lifetimes were assumed as: 1µs for drift layer, 200ns for buffer layer, 100ns for monocrystalline substrate and 50ns for thin transferred substrate. During carrier injection, the engineered substrate has fewer carriers due to limited thickness of the transferred layer and lower carrier lifetime, which mitigates the possibility of recombination at BPD partials causing any expansion. The thin transferred layer also has fewer BPDs. For the monocrystalline substrate, the carrier density is sustained for several micrometers at ~5x1017 cm¯³, which is sufficient to cause BPDs to fault and expand into the epilayer. An additional component for BPD glide is wafer strain. The engineered substrate could potentially have lower strain due to high flatness. Precise lattice strain and tilt maps from x-ray rocking curve mapping [3] comparing both the wafers will be also be presented.

[1] Z. Chen and A. Q. Huang, Mater. Sci. Semicon. Process. 172, 108052 (2024) [2] N. A. Mahadik, et. Al., Appl. Phys. Lett., 100, 042102 (2012) [3] N. A. Mahadik, et. Al., Sci. Rep. 10, 10845 (2020)

ABSTRACT. Silicon Carbide (SiC) is a wide bandgap semiconductor that has significant promise for power devices. Its characteristics, including high breakdown field, and high thermal conductivity, which enables SiC devices to operate in severe conditions such as high temperature, voltage, and frequency [1]. Devices operating up to 3.3kV are commercially available, and are mainly used for automotive and traction control applications. However, higher voltage rated (>6.5kV) SiC devices are needed for hybrid systems, shipboard power, grid systems, and defense applications. These devices are fabricated on SiC wafers with thick epi-layers to achieve required breakdown voltages [2]. However, as the epi-layer becomes thicker, density of defects formed during growth increases [3], which significantly degrades device performance. Recently, Mahadik et. al. have reported a complex stacking fault that originated in the substrate then propagated into 180 μm thick epi-layer, and generates several Shockley-type stacking faults (SSFs) upon carrier injection by UV excitation [4] via the recombination enhanced dislocation glide mechanism [5,6]. Another observed defect in epi-layers is the interfacial dislocation (ID) with associated half loop arrays (HLAs) [7]. Here the gliding motion of originally screw oriented basal plane dislocations (BPD) under mismatch stresses, induces bending at the growth front that makes them prone to be converted to threading edge dislocations (TEDs). As the gliding velocity of BPD exceeds the growth rate of the epi-layer, sections of the mobile BPD manage to protrude through the surface, forming HLAs each consisting of two TEDs and a BPD segment. In this paper, 4H-SiC with 180 μm epilayer was characterized by ultraviolet photoluminescence (UVPL) imaging and High-resolution X-ray topography (XRT). Fig. 1(a) shows XRT image before UV exposure, where screw BPD originated from the substrate replicated in epilayer forming BPD loop and ID. However, no HLA is observed associated with the ID. The formation mechanism of such defect is that the screw BPD segment first get replicated into epilayer (Fig. 1(b)) then glide under the misfit stress (Fig. 1(c)). Due to the change of the line direction, the BPD segment at the growth front will not be screw type so that partials can constrict enabling conversion to TED acting as pinning point (Fig. 1(d)). In this case, differing from the formation of HLAs, the relative gliding speed of the BPD is lower than the growth rate of the epilayer due to lower stress, so it propagates as a loop in the epi-layer and forms ID at the epi/sub interface (Fig. 1(e) and 1(f)). Fig. 1(g) shows UVPL image of the BPD loop in epi-layer, where several stacking faults formed during growth are highlighted by the yellow arrows. After the UV stress, not only initial SSF is expanded, as indicated by the yellow circle in Fig. 1(h), but also 15 new SSFs are formed from a complex interaction of expanding BPD loop with preexisting threading mixed dislocations. This will have more detrimental effect on devices. Details of the formation and the complex expansion mechanisms will be presented.

[1] A.A. Lebedev and V.E. Chelnokov, Semiconductors 33, 999–1001 (1999). [2] P. Luo and S. N. E. Madathil, IEEE Transactions on Electron Devices, 67 5621-5627 (2020) [3] H. Tsuchida, et. al., Mater. Sci. Semi. Process. 78, 2 (2018) [4] N. A. Mahadik, et. al., Scripta Materialia 235, 115598 (2023) [5] J.P. Bergman, H. Lendenmann, et. al., Mater. Sci. Forum 353–356, 299–302 (2001) [6] A. Galeckas, J. Linnros, P. Pirouz, Appl. Phys. Lett. 81, 883–885 (2002) [7] N. Zhang, Y. Chen, Y. Zhang, M. Dudley and R. E. Stahlbush, Appl. Phys. Lett. 94, 122108 (2009)

ABSTRACT. Bipolar degradation is one of the key issues that should be considered in silicon carbide (SiC) MOSFETs. The growth of the highly nitrogen-doped epitaxial layer as recombination-enhancing buffer is well-known practical method for preventing the bipolar degradation. In recent years, the suppression of the stacking fault (SF) expansion into SiC by proton (H+) implantation has been reported. It would be an attractive candidate as a solution for the bipolar degradation, but there are few reports about mechanism of suppression. Thus, in this work, we have investigated the effect of proton implantation on the suppression of SF expansion. We fabricated a vertical SiC-MOSFET which proton was partially implanted into the middle depth of the drift layer by appropriately shielding an active area of the device using silicon pieces. And we performed photoluminescence (PL) inspection after the continuous current stress test for body-diode in SiC-MOSFET. From the shape of expanded SF observed in the PL image after the continuous current stress test, we infer that the proton implanted layer could act as a lifetime killer. And it also suggests the recombination-enhanced buffer at any depth of the drift layer can be introduced by proton implantation. In conclusion, proton implantation would be a promising method for fabricating highly reliable SiC-MOSFETs in the future.

ABSTRACT. This study involves energy-filtered ion implantation (EFII) to explore pinning effect using Nitrogen ion for suppressing REDG caused by BPDs/converted BPDs/SF and precise doping of the entire drift region in one step. This presents a significant advantage over the earlier methods in immobilizing the nucleation sites in the entire implantation region, enhancing the reliability and production feasibility of power devices for mass production. This study employs optical excitation method using UV to investigate 1SSF expansion, which is the basic cause for bipolar degradation, governed by the recombination-enhanced dislocation glide (REDG) mechanism.

ABSTRACT. We developed a new self-aligned process to suppress short-channel effects (SCEs) in SiC UMOSFETs with a short channel length (Lch). By this process, n+ source, p+ contact, p+-shielding region at the bottom of the trench, and SCEs suppression structure (SCEs-SS) were formed symmetrically to the trench without increasing the concentration at the channel surface. SiC UMOSFETs with Lch = 0.28 μm has been successfully realized without SCEs such as drain-induced barrier lowering and punch-through. As a result, specific on-resistance (RonA) was reduced by 14 % from Lch = 0.46 μm, and the trade-off between short-circuit withstand time (tSC) and RonA was improved owing to the low channel resistance / JFET resistance ratio. The developed self-aligned process is expected to contribute to the realization of SiC UMOSFETs with extremely low RonA and high tSC.

ABSTRACT. SiC MOSFETs designed with various hexagonal unit cell layouts are shown in Fig. 1(a-c). These unit cell layout designs are identical in all aspects except for the existence/non-existence or the shape of Shield and Bridge regions, formed by the PWELL implantation. A Shield region links adjacent PWell hexagons. Design A in Fig. 1(a) has no Shield region. Design B in Fig. 1(b) has two variants (B1 and B2) of a triangular Shield region. Design C in Fig. 1(c) has two variants (C1 and C2) of a tetrapod-shaped Shield region. In addition, Design C has Bridge regions of different widths that connect the Shield region with the adjacent PWell hexagons. Table I summarizes the various unit cell designs with the Bridge widths (normalized to Design B1) and the channel densities (normalized to Design D). Design D in Fig. 1(d) has a conventional stripe layout. Fig. 2 shows top-down SEM images of the unit cells of the fabricated SiC MOSFETs with Design B2 and Design C2. The intricate interaction of the processing steps for PWell and N+ Source region formation with the as-drawn sub-micron bridge and shield features result in additional features not present in the mask layouts. For instance, the N+ source regions may also be formed within the shield/bridge regions, as observed from the SEM images in Fig. 2. Further, these N+ source regions may or may not be connected to the N+ source region within the main PWELL hexagons, which results in changes to the effective channel width. All the SiC MOSFETs investigated in this work were rated at 650 V and had a chip size of 3.06 mm2. Apart from the layout variations described above, all the MOSFETs were fabricated using Navitas’s GeneSiCTM “trench-assisted planar” SiC MOSFET architecture, which is distinguished by the PPLUS regions formed below a trench etched into the SiC in the Source regions. All Designs, except Design D from Wafer A, show VTH of ~ 3 V (Fig. 3). Design B1/B2 and Design C1/C2 with the shield/bridge regions show a median RDS,ON around 102~106 mΩ (Fig. 3). Direct comparison of Design C1/C2 to Design D from Wafer B shows 13.6% reduction of RDS,ON, which is due to the hexagon PWell geometry with > 2X channel densities. Design A with no shield shows the lowest RDS,ON of 92.7 mΩ. Design C1/C2 show 2-3% lower RDS,ON than Design B1/B2, due to the unique tetrapod-shaped shield region of Design C1/C2 reduces the JFET effect, in addition to a 10% higher channel density (calculated from the mask layout). Design D from Wafer A has a 10% higher VTH as a result of a longer effective channel length, when compared to the hexagonal layouts. The drain leakage plot at the bottom of Fig. 3 shows the spatial distributions of the IDSS measured at 650 V, where 0 and 60 on the horizontal axis indicate the center and edge of the wafers, respectively. Design D shows the best IDSS performance, while Design B1/B2/C1/C2 having the shield/bridge regions show significantly lower IDSS compared to Design A, which is unshielded. Fig. 4 shows a plot of the RDS,ON vs. TC. Temp-co was calculated by using the RDS,ON‘s at RT and 150ºC. Design A with no shield region shows the lowest temp-co. of 1.08, which is far better (by ~17%) than Design D from Wafer B with the same VTH of 3V, and this is due to the reduction of the JFET resistance in Design A compared to Design D because of the lack of the shield/bridge regions. Design B2 and C2 have temp-co’s of 1.21 and 1.20, respectively, which are ~10% higher than Design D from Wafer B. Fig. 5 shows the HTGB results (up to 500 hr) on select designs (Design B2/C2/D). Design B2/C2, which are better designs than Design A due to existing shield/bridge regions, have less VTH shift than Design D with better statistical tightness. This suggests the shield/bridge regions of Design B2/C2 provide better protection to their gate oxide stacks in comparison to Design D. It should also be noted that there is a four-sided JFET depletion effect in the shielded/bridged devices (Design B2/C2) as compared to the stripe layout (of Design D) which only has a double-sided JFET depletion effect. This leads to a smaller EOX (at the center of the JFET region) under high drain bias. Design B2 is slightly better than Design C2 from HTGB perspective due mainly to the larger area of its shield region.

ABSTRACT. A new topological layout was explored to increase the channel density of 1.2kV 4H-SiC MOSFETs. The novel 'Ladder' MOSFET features an additional JFET and channel region inserted orthogonally in the layout (see Fig. 1). Unlike previous approaches to increase channel density [1], the proposed Ladder design maintains a stripe pattern. To fairly compare, the same design rules were applied for both MOSFETs. However, the half contact width (WC) slightly differs due to limitations within these rules, with it being 0.7 µm and 0.9 µm for the Nominal and Ladder MOSFETs. Consequently, the cell pitches for the Nominal and Ladder MOSFETs are 5.4 µm and 5.8 µm. The channel density, calculated by dividing the channel region area by the total unit cell area, was calculated to be 0.30 and 0.41 for the Nominal and Ladder MOSFETs, respectively. 3D Synopsys Sentaurus TCAD simulations were employed to conduct a comparative analysis between the Nominal and Ladder MOSFETs. Utilizing SProcess, 3D doping profiles were generated under identical implantation and process conditions, as depicted in Fig. 2 for both the Nominal (a) and Ladder (b) MOSFETs. Subsequently, forward and transfer characteristics were simulated using SDevice. The specific on-resistance (Ron,sp) was determined to be 3.96 mohm⋅cm2 and 3.60 mohm⋅cm2 at Gate Voltage (VG) = 20V and Drain Voltage (VD) for the Nominal and Ladder MOSFETs, a 10% reduction in Ron,sp. Threshold voltage (Vth) was found to be 2.53 V and 2.33 V for the Nominal and Ladder MOSFETs, respectively, when assessed at VD = 0.1 V and ID = 1 mA. As shown in Fig. 3 and 4, the newly developed 3D simulation methodology was effective in predicting trends in the static electrical characteristics for different MOSFET topological layouts. Detailed descriptions of the 3D simulations will be discussed in the full paper. To further compare, both Nominal and Ladder MOSFETs were fabricated on 1.2kV rated epi-layer with 360 µm 4H-SiC substrates at Clas-SiC Wafer Fab in the United Kingdom, employing an identical process flow and implantation recipes. A self-align process was implemented to form the Pwell/Channel. Subsequently, the wafers were diced, and from each, 15 Nominal and 10 Ladder MOSFETs were selected for packaging in TO-247s. Comprehensive measurements of static electrical characteristics were conducted. At a VG = 20V and Drain Current (ID) = 15 A the Ron,sp for the best performing Nominal and Ladder MOSFETs was determined to be 3.84 mohmcm2 and 3.40 mohmcm2, showcasing a notable 12.94% reduction in Ron,sp for the Ladder MOSFET. The typical output characteristics of these selected MOSFETs are illustrated in Fig. 5. Overall, Ladder MOSFETs exhibited an average reduction of 15.39% in Ron,sp compared to their Nominal counterparts, as evidenced in Fig. 6. Additionally, the average threshold voltage (Vth) at ID = 5mA and when VG=VD was measured to be 2.49 V and 2.29 V for the Nominal and Ladder MOSFETs, respectively. The enhancement in Ron,sp achieved through the utilization of the Ladder MOSFET design is consistently sustained even at elevated temperatures, as depicted in Fig. 7. It is interesting to observe that the temperature coefficient of the Ladder MOSFET is smaller than that of Nominal MOSFET, which may be attributed to wider contact opening.

ABSTRACT. There are some technological issues in SiC MOSFETs that are still unsolved. One of the main problems is the high density of traps/defects at the SiC/SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. The h igh density defects at the SiC/SiO2 interface is a relevant problem since it can influence the overall performance of the device, causing detrimental impacts on threshold voltage stability, channel mobility and leakage current amplitude. Due to the fundamental importance of the SiC/SiO2 interface characterization, several techniques have been employed to investigate defects properties related to this region. In this work non-classical C-V measurements are performed. Capacitance is measured between Gate and Source terminals while a fix DC voltage is imposed on the Drain. this latter is considered among positive values in a first case, while it is chosen as a negative voltage in the second case. The arising capacitances in both cases show an unexpected behavior which can related to interface properties. To this aim numerical analysis is performed in Sentaurus TCAD environment.

ABSTRACT. Power electronics are a key enabling technology in the process towards a fully electrified society. Modern power conversion is integral in delivering efficient electric vehicles (EVs) and their fast charging stations, advanced motor drives and the integration of renewable energy into a modern grid. In these applications, well-developed converter topologies are key. Ideally, these would contain semiconductor switches that have both excellent blocking capabilities in both directions and bidirectional current conduction in the on-state. However, none of the common semiconductor switches, e.g. thyristors, IGBTs and MOSFETs, can provide these functionalities alone, such that multiple discrete device topologies are typically deployed, consuming more space and creating an increase in resistance compared to a standalone solution. Recently however, the silicon-based B-TRANTM was proposed, which has bidirectional capabilities and low conduction loss. A 4H-SiC B-TRAN (TM) has the potential to extend the blocking voltage up to 15 kV. In this investigation, vertical PiN diodes and lateral JFETs were simulated, fabricated and characterized on both the C-face (000-1) and Si-face (0001), as required to produce a SiC B-TRANTM. The carrier lifetime of the thick drift region was optimized to enable sufficient carrier diffusion for conductivity modulation.

ABSTRACT. The use of silicon carbide (SiC) power devices in space is limited by their sensitivity to the radiation environment, which increases the risk of single event effects (SEEs). This work focuses on the basic mechanisms of damage induced by heavy-ion irradiation in 4H-SiC unipolar devices.

ABSTRACT. High-energy electron irradiation on MOSFETs can improve the reverse recovery characteristics of body-pin diodes because the point defects created in the drift layer shorten the carrier lifetime. However, it is known that electron irradiation causes an increase in the on-resistance of MOSFETs and a negative threshold voltage shift. In this study, we analyze electron-irradiated SiC power MOSFETs, focusing on their effects on the drift layer resistance and MOS channel characteristics such as the threshold voltage, subthreshold swing, and transconductance.

ABSTRACT. SiC MOSFETs were fabricated after proton irradiation of SiC epitaxial wafers, and the effects of proton irradiation on the electrical characteristics were experimentally investigated to demonstrate the improvement of recovery characteristics and suppression of bipolar degradation.

ABSTRACT. Superjunction (SJ) power devices have shown to be more efficient than their planar counterparts, with 600 V Si SJ-MOSFETs showing a 20% lower specific on-resistance (Ron,sp) than equivalent planar MOSFETs.[1] A superjunction is a drift region structure comprised of alternating p-doped and n-doped columns that charge-balance in the depleted state.[2] This permits higher doping in the epilayer, reducing Ron,sp for equivalent thickness devices. Since SiC is capable of improving Ron,sp by a further 10-fold due to its higher critical electric field, SiC superjunction devices could potentially have advantages in the high-voltage (>1.7 kV) range. However, current SJ fabrication methods are designed for Si and are practically inapplicable to 4H-SiC device fabrication.[3] Trench filling epitaxy (TFE) is where deep trenches are etched into n-doped (p-doped) SiC and epitaxially refilled with p-doped (n-doped) SiC, and is a feasible approach to SiC-SJ fabrication even for a drift region up to 50 μm thick. However, further development is needed for TFE to be used in practice. One challenge of TFE is the occurrence of pattern and etch imperfections prior to epitaxy, such as microtrenches, surface roughness or trench/ mesa width disparity. Annealing trenches under various atmospheres can round mesas and smooth surfaces, making it a useful trench conditioning method to alleviate inevitable patterning flaws.[4,5] Here, we present a systematic study of annealing 4H-SiC trenches in Ar, H2 and HCl at varied temperature and duration, to derive structure-condition relationships that will drive TFE process design. Focus is placed on H2 and HCl due to their relevance in chemical vapor deposition (CVD) as this enables trench modification in situ as a preconditioning step, prior to CVD epitaxy. In this work, trenches were processed on the Si face of n+ 4H-SiC (0001) substrates off-cut by 4° in the [11-20] direction. These were masked using 500 nm SiO2 with TEOS as a precursor by low pressure (LP-) CVD, then a sputtered Ni layer was patterned by photolithography. Using a F-based ICP etch in an Oxford Instruments PlasmaPro 100 Cobra etcher, trenches of ~5 μm depth were produced in the SiC [11-20] substrate directions using the SiC/SiO2/Ni mask. Resulting trenches were as low as 1.5 μm wide with corresponding mesas of 2.5 μm, which is termed a 4 μm pitch. Pitches of 8 μm and 20 μm pitch were also investigated. Annealing was performed in an LPE ACiS M8 RP-CVD reactor between 1550°C and 1650°C for up to 4 hours. By comparing scanning electron micrographs (SEM) of trench cross-sections cleaved along the [1-100] direction, the effect of annealing on trench profile can be examined. At 1550°C, Ar (30 slm) and HCl (0.1 slm, with H2 100 slm carrier flow) have no effect on the trench shape but H2 (100 slm) causes a duration-dependent faceting of the mesa corners (see Fig. 1). This appears as a ‘truncation’ of corners at 30-60° from the (0001) surface along the [1-100] direction. This angled facet extends in length at a rate of ~0.3 μm h-1 at the mesa top but only by ~0.1 μm h-1 at the trench bottom, which may be caused a differential etching rate of SiC by H2 depending on the trench depth or sidewall slope. This faceting is also observed in trenches refilled by CVD at 1550°C with H2 carrier gas, which we propose will encourage fusing of the epilayer over trenches to produce a flat end surface required for planarization and further processing. Corner faceting at the trench bottom can also remove microtrenches after 10 min for trenches of 4 μm pitch (Fig. 1). In addition to faceting, H2 also anisotropically etches mesas depending on the trench depth and the trench direction relative to the 4H-SiC crystal orientation. See image 2b), “wheel” structures were also on the same back, so that any effect of crystallographic direction could be investigated. For trenches aligned to the [11-20] direction, mesa tops are laterally etched ~0.2 μm h-1 faster than at the trench bottom, which may be

due to a microloading effect, whereby the concentration of H2 gas is lower at the trench bottom. Similarly, the trench depth decreases by ~0.3 μm h-1, indicating that mesa tops are vertically etched faster than trench bottoms and that H2 etching is directionally isotropic at a given depth. Examination of the lateral etch rates for trenches aligned 0-180° to [11-20] shows that the rate is slowest in the 〈11-20〉 (a-plane) and 〈1-100〉 (m-plane) directions, compared with intermediate angles (Fig. 2). This is an important consideration for both process and device design. From atomic force microscopy (AFM), it is found that the RMS surface roughness is <40 nm for all H2 annealed samples after 10 min, indicating smoothing is fast and does not further improve with annealing duration at 1550°C. In the full submission, we report all of the effects found with the various gases and temperatures. This is then combined with TFE to highlight the potential uses of the pre-TFE treatment as an aid to complete refill of the trenches, enabling SiC superjunction technology.

ABSTRACT. Single photon emitters (SPEs) in solid are a building block of quantum applications, such as quantum computing and information technologies. Silicon carbide (SiC) is regarded as a promising host of SPEs due to its wide bandgap and mature process technologies. In addition to SPEs in bulk SiC, such as V_Si and V_SiV_C, those at SiO_2/SiC interfaces are also attractive because of their bright luminescence. However, having control over the density and the optical properties of the interface emitters is challenging. In a previous study, we reported a method to form spatially well-isolated SPEs at the SiO_2/SiC interface by post-oxidation CO_2 anneal. In this study, we further investigated the impact of CO_2 anneal on the emitter density and compared it with Ar anneal.

ABSTRACT. SiC color centers have gained increasing attention due to their capability to operate as single photon sources, rendering them a promising platform for photonic quantum technologies. These color centers in SiC possess advantageous properties, even in comparison to the extensively studied nitrogen-vacancy center in diamond. Furthermore, the well-established semiconductor 4H-SiC readily provides advanced processing technologies to further enhance its utility.

ABSTRACT. Please see the uploaded extended abstract.

ABSTRACT. Spin defects in semiconductors are attractive candidates for a qubit, which is an essential element for quantum technologies, such as quantum communication, computing, and sensing. As a host of spin defects, silicon carbide (SiC) is promising owing to its wide bandgap, well-established crystal growth, doping control, and process technologies. Various spin defects in SiC including silicon vacancy (V_Si) and nitrogen-vacancy (N_CV_Si) complex were already reported. Recently, a theoretical study predicted the neutral oxygen-vacancy (O_CV_Si) complex as a candidate qubit with a high-spin ground state (S = 1) with near-infrared photoemission (1004–1117 nm). Its calculated high Debye-Waller factor (13.4%) is favorable for a spin-to-photon interface. However, a systematic study on other types of oxygen-related defects is still lacking. In this study, we systematically investigated the stability, structure, energy levels, and spin properties of oxygen-related defects in 4H-SiC taking the relevant charge states into account.

ABSTRACT. In this work, we study the impact of temperature on the static electrical parameters of 1200V power 4H-SiC diodes with various designs and architectures (Schottky, JBS, hexagonal and stripe cells) fabricated on 150 mm bulk 4H-SiC and 3C-poly SiC based substrates (SmartSiC). I(V) measurements were carried out in both reverse and forward modes to assess the impact of designs and substrates. Non-destructive avalanche mode was reached with similar performance (leakage, VAV) observed for both substrates (due to identical drift layer and device structure). JBS devices fabricated on SmartSiCTM exhibited a high current conduction and less resistance in the ohmic regime (compared to bulk). The observed conduction gain was further investigated at high temperatures (up to 200°C). Based on the extracted resistances, we can infer that all diodes designs (regardless of the epi or the substrate) follow the same predictive R(T) model proposed. Partitioning model was also proposed for evaluating the impact of substrate thinning on the specific differential resistance.

ABSTRACT. Several 1.2kV 4H-SiC devices of various cell architectures have been successfully fabricated by employing different P+ implantation conditions, resulting in varying levels of Basal Plane Dislocation (BPD) densities for each of the different device designs. It was found that by utilizing devices designed with an orthogonal P+ source layout as opposed to the traditional P+ stripe pattern or by utilizing the unipolar current of the JBSFET, the long-term reliability under continued 3rd Quadrant current stress can be greatly improved even in devices with medium to high BPD densities.

ABSTRACT. Gate switching instability (GSI) is usually investigated using a gate driving circuit that switches between a negative low level and a positive high level to generate the gate switching stress (GSS). This allows to determine various GSI-dependences like high level voltage, low level voltage, frequency, rise time and fall time [1]. However, these results do not allow clear selection between proposed mechanisms to describe the root cause, because recombination at interface traps, high positive electric field and internal field enhancement all happen within the same time period at the rising edge [2,3]. So, how to modify the experiment to separate these events in time to allow independent investigation? The effect of overshoots and undershoots on GSI by adjusting the gate resistor was investigated in [4]. A further kind of undershoot not connected to a rising or falling edge, may result from the switching transient of the complementary switch in a half bridge, which typically happens while the device is in off-state. How would this undershoot in the off-state effect GSI? A setup to generate three level gate stress pulses was built to address these questions. We use a relay to switch between stress phase and measurement phase. During the stress phase source and drain are shorted and driven by a gate driver IC with 20% duty cycle at 500 kHz. The gate is driven at the same frequency and duty cycle by a second independent channel of the IC. Voltages and delay between the driver channels are set such that we obtain the stress voltage sequence shown in Fig 1. Note that the intermediate voltage at +4 V is such that the interface is expected to be in inversion. The legend indicates the delay between rise time of the negative pulse and rise time of the positive pulse of each curve shown. We used commercially available devices (IMBG120R234M2H) with a small gate capacitance to allow fast switching without oscillations despite the relay in the drive path. Both stress and measurements were done at room temperature. To separate the threshold voltage drift (Vth-drift) due to GSI from the Vth-drift originating from the constant voltage stress (BTI), we included an aggressive preconditioning before each Vth-measurement by applying the low level for 1 s and applying the high level for 1 s and repeated that 5 times. The Vth was measured with gate and drain shorted and forcing -0.9 mA at the source contact. The Vth measured with positive pulse sequence from Fig 1b does not show any drift, as shown in Fig 2a, indicating that the preconditioning is sufficient to avoid Vth-drift from BTI. The curve from the negative pulse sequence shows a significant drift, indicating that even with low positive voltages, GSI is triggered effectively. The three level stress pulse sequences all show very similar Vth-drift curves. A close-up of these curves in Fig 2b shows that the Vth-drift slightly increases with reduction of the delay between negative and positive pulse in the three-level stress sequence. The internal field enhancement happens when going into inversion and, according to [2], is expected to cause an enhanced Vth-drift corresponding to an increase of 10 V~20 V for <100 ns in the gate source voltage for BTI. Because the Vth-drift depends only slightly on the delay before a +16 V boost of the gate-source voltage, we conclude that a major part of the Vth-drift cannot be explained by the internal field enhancement. Fig 3a shows the oscilloscope traces of the applied stress voltage sequences to investigate the effect of an additional negative pulse during the off-state. The trace without negative pulse is used as a reference. Fig 3b shows that the negative pulse significantly increases the Vth-drift and that the delay between the pulses, does not make a significant difference. Further investigations are needed, but it seems that in circuit design focused on optimizing for low GSI, we need to take care to reduce the negative amplitude of transients in the off-state.

ABSTRACT. We investigated how proton implantation has an effect on electrical characteristics of 4H-SiC MOSFETs. Bipolar degradation in silicon carbide (SiC) is the key issue for utilizing the bipolar operation in SiC power devices. Suppression of bipolar degradation with proton implantation technique has been reported recently. If we can apply such a new technique to SiC MOSFETs, it would provide the way to take advantage of the body diode of SiC MOSFET. Thus, we fabricated and evaluated huge numbers (about 4,000 chips) of proton implanted 4H-SiC MOSFETs to verify statistically its effectiveness on the suppression of the bipolar degradation as well as to consider its technological applicability to their mass production process. We found that the implantation of proton as much as 1e14 cm-2 has almost no effect on the 1st and the 3rd quadrant static characteristics of the SiC-MOSFETs at room temperature. Furthermore, our statistical investigation revealed that the suppression ratio of the increase in on-resistance is more pronounced by higher dosage of proton.

ABSTRACT. Bipolar components (diodes, transistors, thyristors) are essential for very high-voltage power electronics. Recently, an optical high-voltage 4H-SiC BJT (Bipolar Junction Transistor) has been designed, fabricated and characterized. The BJTs were fabricated on a 4H-SiC wafer using a 120 μm thick epilayer with a doping concentration of 8×1014 cm−3 [1] and were designed to withstand a voltage of 10 kV. After electrical characterization, a breakdown voltage of about 11 kV was obtained [2]. PiN diodes have been integrated in the mask layout as part of this project to optically trigger high-voltage bipolar components (Fig. 1, right). In order to verify the effectiveness of their peripheral protection, different geometries were considered: MESA only, MESA combined with JTE, with and without supplementary 6 JTE rings, with round and square shapes. These diodes have been characterized in a vacuum chamber up to a reverse voltage of 1000 V and exhibit a low leakage current as shown in Fig. 1, a prerequisite for OBIC characterization measurements in reverse. This paper aims to demonstrate how the micro-OBIC technique [3] can be used to assess the efficiency of peripheral protection by analyzing the 2D distribution map of the currents within the device structure, particularly at the junction periphery. 2 types of circular diodes were chosen for illustration: a MESA diode and a MESA diode with JTE and 6 rings. Micro-OBIC measurements were carried out in air, limiting the reverse voltage applied to avoid breakdown. The OBIC 2D-maps are shown in Fig. 2, where the junction is clearly evidenced. At the same time, finite element simulations were carried out with SentaurusTM [4] in transient mode, taking into account the diode structure (Fig. 3) and the characteristics of the laser optical beam. Simulations of this kind are rare [5] and time-consuming. Fig. 4 shows currents as a function of diode diameter for the diode protected with the MESA. As it can be observed, both the experimental and simulated OBIC behavior are almost identical: the optically induced current increases and widens at the junction if the reverse voltage increases. Acknowledgements for French ANR contract HV-PhotoSwitch (ANR-18-CE05-0020-01).

ABSTRACT. For the development and improvement of the next generations of SiC devices, new methods are needed to accurately measure device properties, such as doping concentration, local potential and electric fields. In this paper we investigate a derivative effect of the secondary electron doping contrast (SEDC) in the scanning electron microscope (SEM) [1-3], namely that we can visualize the local potential in a cleaved cross-section of the power device. The potential can then be manipulated by using in-situ nanoprobing to apply a voltage to the p-n contacts.

The SEDC is caused by potential differences due to the doping of the sample. The primary electron of the SEM scatters inelastically with the valence electrons in the semiconductor. Some of these valence electrons gain enough energy, so that they can escape the semiconductor becoming secondary electrons (SEs) and be detected. As shown in Fig. 1, the minimum kinetic energy required is equal to the potential difference between the detector level E_detect and the valence band edge E_v. This potential difference \Delta E_effective is smaller for p-doped areas than it is for n-doped areas, resulting in more SEs being detected, which is why p-doped areas appear brighter than n-doped areas in the SEM. Variations in the local doping concentration cause small potential differences, resulting in a small change in detected SEs and thus a small gray value difference in the resulting SEM image. Therefore, the SEDC can also be seen as potential contrast [3, 4].

To manipulate the potential further, we can use in-situ nanoprobing. On our sample, the p-doped area was implanted on top of an epitaxially grown n-doped area. An external voltage is applied to the p-doped area. An overview SEM image of this setup with the nanoprobing needle touching the sample metallization is shown in Fig. 2. A SEM image with 0 V applied at the junction is given in Fig. 3 (a) and for comparison images with -4 V and +4 V applied are shown in (b) and (c) respectively.

Line profiles were taken across the p-n junction for all measured images between -4 and +4 V and are given in Fig. 3 (d). With a larger negative bias, the signal in the p-doped region increases, whereas it decreases with a larger positive bias. The line profiles of the images taken with +3 and +4 V are almost identical, because the diode opens at about +3 V, shorting the two terminals. The measured gray value can thus directly be translated into a local potential, which may be compared to TCAD simulations. The increase in width of the space charge region can also be observed. The technique presented in this paper maps the local potential of the sample. Therefore, it can improve the development of SiC devices in areas where the knowledge and management of the electric field distribution is crucial, such as improving the edge termination, increasing radiation hardness and protecting the gate oxide. Additionally, the technique would allow TCAD simulations to be calibrated.

This work was funded by the Austrian Research Promotion Agency (FFG, Project No. 905107).

[1] M. Moser et al., Materials Science Forum, Vol. 1089, pp. 23–29 (2023). [2] C. Sealy et al., Journal of Electron Microscopy, Vol. 49(2), pp 311-321 (2000). [3] J. Cazaux, Journal of Electron Microscopy, Vol 61(5), pp 261-284 (2012). [4] R. Rosenkranz, Journal of Materials Science: Materials in Electronics, Vol 22, pp 1523-1535 (2011).

ABSTRACT. We have developed a solution-grown bulk SiC crystal growth method [1]. This method can grow SiC crystals of high quality because the process is close to thermal equilibrium. Moreover, by forming macrosteps on the surface, the threading dislocations in the crystal are converted into basal plane defects, and these defects are ejected out of the crystal during the growth process, thereby reducing the dislocation density [2-4]. If macrosteps are developed too much, they will conversely cause macrodefects such as inclusions [5]. In other words, it is important to maintain a moderate macrostep height. In controlling the macrostep height, the flow distribution in the solution is important [6]. In order to achieve a proper flow distribution over the crystal growing surface, it is necessary to intermittently change the crystal growing conditions to periodically realize multiple flow states on the crystal growing surface. We call this method “switching flow method”. However, there are so many crystal growth parameters that it is almost impossible to optimize the combination of multiple sequences by hand. For such complex control, we have used machine learning techniques to build a digital twin of the actual crystal growth apparatus in a computer and repeatedly run virtual experiments with it to optimize the parameters [7] In this study, we used this technique to optimize the growth conditions and attempted to grow 8-inch crystals. Top-Seeded Solution Growth (TSSG) method used in this growth. In this method, crystals are grown in a Si-based solvent in a carbon crucible at high temperature. A temperature distribution and a flow distribution are controlled by the position and rotation of the crucible and seed crystal, the power of the RF power supply, and so on. The experimental conditions for 8-inch crystal growth were optimized as follows: (1) The temperature and flow distributions under the optimum good condition of 6-inch crystal growth we have achieved are calculated by simulation. (2) The distributions of the optimized 6-inch growth are represented in latent space by the Variational Auto-Encoder (VAE) method. (3) Using an 8-inch setup, simulations are performed under various crystal growth conditions, and the simulations are represented in latent space in the same way. (4) The conditions for 8-inch growth that can obtain the same distribution as the optimum 6-inch condition are sought by changing the conditions in latent space. [7] The seed crystals were 8-inch crystals turned off once at [11-20]. Si-Cr solvent was used as the solvent.

ABSTRACT. The top-seeded solution growth (TSSG) method for SiC crystals is proposed as a promising alternative to the conventional physical vapor transport (PVT) method, offering a scalable approach to obtaining SiC crystals of superior quality. The primary advantage of the TSSG method lies in its ability to achieve defect conversion through macro steps, effectively eliminating the original TSD and TED defects present in the seed crystal.[1] However, the successful elimination of defects requires appropriate step height and slope.[2] In our previous research, we observed that step height and slope have a significant impact on the formation of solvent inclusion.[3-4] Solvent inclusion is the heterogeneous substance contained within the grown crystals. It not only causes damage to the electrical and mechanical properties of crystal but also becomes a source of dislocation defects, spreading harmful effects to epitaxial layers. Solvent inclusions in SiC crystals include two types: cellular structure and overhanging structure. To suppress two types of solvent inclusion defects in SiC solution crystal growth, this study first established a local three-dimensional phase field (PF) model capable of simulating both cellular and overhanging structures simultaneously. Secondly, the local PF model was coupled with the global computational fluid dynamic (CFD) model. The local velocity and supersaturation near the crystal surface from the global CFD model were applied to multiple local three-dimensional PF models. Various crucible and seed rotation patterns are compared to design the optimal growth process. This simulation method enables the evaluation of the global crystal surface morphology and the proposal of practical optimized growth processes. To verify the simulation results, 1.6-inch SiC TSSG growth experiments were conducted. Firstly, the outward flow and inward solution flow patterns are compared. The temperature and solution flow velocity distribution of outward and inward flow from CFD simulation are shown in Fig. 1. (a) and (b) respectively. Four points on the crystal surface are selected, and the CFD calculation results at these four points are input to the PF model to calculate step morphologies. Results indicate that outward flow tends to produce cellular and overhanging structure type inclusions in the parallel flow area, while inward flow suffers from the issue of low crystal growth rate. Secondly, cases with various seed rotation speeds are compared by this simulation method and TSSG experiment. Both results indicate that the optimal rotation speed is 30 rpm in the outward flow pattern. Finally, this simulation method is used to design a switching flow pattern, which can suppress the formation of cellular and overhanging type inclusions on the overall crystal surface, and maintain a high growth rate at the same time. The PF simulation results of switching flow case for various time steps are presented in Fig.2. The PF results demonstrate that the step morphology changes as the flow pattern changes. The first 100000 timesteps is inward flow and anti-parallel flow, the step movement rate is slow, the step morphology in Fig.2 (b) is similar with initial state. The solution flow pattern changes to outward flow and parallel flow in 100000 ~ 200000 timesteps, the step morphology in Fig.2 (c) become instable, the overhanging structure and cellular structure are formed. When timestep in 200000 ~ 300000, solution changes to inward flow and anti-parallel flow again, the overhanging structure is suppressed, and cellular structure changes to zig-zag shape. Fig. 3. shows the crystal morphology in the experiment with the switching flow pattern. The experiments verified that the optimized growth process proposed by the simulation effectively reduced the inclusion density and kept a high crystal growth rate. This method can also be applied to optimize the liquid phase growth process of other crystals.

[1] S. Yamaguchi, N. Naganawa and M. Nakamura, J. Appl. Phys. 58(6), 060901 (2019). [2] S. Xiao, S. Harada, K. Murayama, M. Tagawa, and T. Ujihara, Cryst. Growth Des. 16(11), 6436-6439 (2016). [3] H. Zhou, H. Miura, Y. Fukami, Y. Dang, K. Kutsukake, S. Harada, and T. Ujihara, Cryst. Growth Des (2024). [4] H. Zhou, H. Miura, Y. Dang, Y. Fukami, K. Kutsukake, S. Harada, and T. Ujihara, Cryst. Growth Des. 23(5), 3393-3401 (2023).

ABSTRACT. This study reports on the challenges and advancements in developing 200 mm-diameter 4H-SiC crystals utilizing the high-temperature chemical vapor deposition (HTCVD) method, significantly enhanced by process informatics (PI). While enlarging the diameter of SiC crystals presents substantial cost benefits and other advantages, it introduces complex challenges in process optimization and control. Particularly, larger-diameter crystals require stringent control over temperature fields to avoid stress-induced cracking. To overcome this issuse, we have introduced and developed PI technologies—including optimization, machine learning, and computational aided engineering (CAE). By applying our proprietary algorithms for optimizing the structural parameters of the growth furnace, we successfully achieved a 200 mm-diameter 4H-SiC crystal with a maximum growth rate exceeding 1.5 mm/h and a growth length over 10 mm, without any cracks, all within a remarkably short development period.

ABSTRACT. To assure reliability of SiC power devices, suppression of bipolar degradation is one of the most important issues. Since bipolar degradation occurs when electron-hole pairs recombine at BPDs, reduction of BPD densities in SiC crystals is effective to suppress it. It is known that most of BPDs in SiC substrates are transformed into harmless threading edge dislocations (TEDs) when epitaxial drift layers are formed. However, bipolar degradation still occurs when carriers reach BPDs in the substrate regions. [1-2] Hence there is a demand to develop techniques to produce SiC substrates with low BPD densities. In this paper, we, NGK INSULATORS, LTD., which is a Japanese ceramics company, present a novel method to grow 4H-SiC crystals with low BPD densities using its ceramic processing technology. Fig. 1 shows a schematic of our crystal growth process. SiC powders with additives that produce liquid phase upon heating and promote crystal growth, and a 6-inch SiC substrate (seed crystal) are contained in a graphite crucible. The crucibles are heat-treated at temperatures above 2000℃ in the mixed atmosphere of argon and nitrogen using a furnace with graphite heaters. The mechanism of the crystal growth is presumed to be the dissolution of SiC particles into the liquid phase and recrystallization onto the substrates. One of the primary advantages of this method is the ability to process multiple substrates simultaneously, which leads to a high productivity and a low cost. The resultant SiC sample is schematically shown in Fig. 2. SiC crystals with a thickness of ~100 – 200 m are grown onto SiC substrates. Fig 3(a) and (b) show X-ray topography images of the seed crystal region and the grown crystal region, respectively. These images clearly show that BPDs indicated by black, string-like contrasts are significantly reduced in the grown crystal region. Molten salt etching of the sample showed that the BPD density of the grown crystal region was typically ~1/5 to 1/10 of that of the seed crystal region. Detailed investigation on the behavior of BPDs and other defects associated with the crystal growth is reported in a separate paper in this conference. To prevent the inclusions of polytypes other than 4H in the grown crystals, it is necessary to maintain a low heating rate until reaching the maximum temperature. Fig. 4(a) and (b) show the polarized microscope images of the samples prepared under high and low heating rate conditions, respectively. The former sample contains some 6H regions, while the latter sample consists only of 4H. To investigate the origin of 6H regions, the cross section of the 6H regions was observed using scanning electron microscopy (SEM). As a result, inclusions of the additives were confirmed near the edge of the 6H regions. These results suggest that a high heating rate leads to insufficient melting of the additives in the early stage of the crystal growth, inhibiting the epitaxial growth of 4H through the formation of additive inclusions. The nitrogen concentration in the grown crystals, which determines their resistivity, varies with the N2 partial pressure in the atmosphere during crystal growth as shown in Fig. 5. The nitrogen concentration can be controlled from 2×1018 to 1×1019 /cm3, a range equivalent to that of current standard SiC substrates. The typical properties of 6-inch SiC substrates (seed crystals) and grown crystals are summarized in Table 1. It is confirmed that our crystal growth method significantly reduces BPD densities of SiC substrates while maintaining substrates’ polytype, off-angle, and resistivity. The impacts of the low BPD densities on device performances are under investigation and will be reported in the future.

ABSTRACT. Material development and optimization inherits the need to understand and control processing-structure-property relationships. Of particular interest is SiC, which is utilized in power electronic devices due to its exceptional properties such as a wide bandgap, high breakdown voltage, and high thermal conductivity [1]. The most common method to produce SiC single crystals is through physical vapour transport (PVT) where the SiC boules are grown within a closed reactor. Process temperatures around 2000 °C as well as pressure close to 5 mbar make it not only challenging to acquire experimental data, but also complicates the quantification of physical material properties of the system.

In order to improve process knowledge and to reduce the need for expensive experimental trials, crystal growth simulations are frequently utilized. Reliable models not only facilitate the production of high-quality crystals as well as high output and resource-saving processes, but they can also aid in optimizing growth conditions or scaling the process appropriately. However, models must consider complex coupled physics phenomena, accurately representing the key aspects of the growth environment within reasonable computational efforts. A further challenge arises from uncertainty in the materials parameters of the furnace which need to be calibrated precisely to achieve reliable simulation results. Novel techniques from machine learning (ML) offer great opportunities in this respect.

We present an approach providing a computational and time efficient active learning algorithm, that sequentially builds a ML model that can replace the COMSOL multiphysics finite element method (FEM) calculation to access relevant quantities in the reactor such as the temperature. Training data are generated by sequential Design of Experiment (DoE) leveraging Gaussian Process Regression (GPR). The COMSOL calculations are carried out sequentially and simultaneously the GPR model is utilized to determine the next set of parameters that would reduce the uncertainty of the ML model the most. The workflow is illustrated in Fig. 1. As a result of the absence of exact values for the physical material properties, input parameters for the ML model not only include the process parameters itself, but also material parameters and coefficients representing uncertainties, e.g. for radiation emissivities, thermal or electrical conductivities. These parameters are varied in a predefined range established by prior knowledge. The ML model was trained for one location close to the seed crystal, which can be measured experimentally. After gathering the training data through sequential DoE, ML models in combination with Bayesian inference, particularly with Markov Chain Monte Carlo (MCMC), are used to calibrate the unknown physical material parameters. Fig. 2. (a) shows the experimentally measured temperatures and the simulation results of the calibrated PVT simulation. The MCMC sample distribution for one parameter is shown in Fig. 2. (b). Furthermore, due to the high accuracy of this ML model, it can be used for different downstream tasks, like sensitivity and uncertainty analyses. Further potential applications and benefits of this approach in crystal growth facilities will be discussed.

ABSTRACT. 1. Introduction Tantalum carbide (TaC) due to its outstanding thermal stability, purity and chemical resistance, has been increasingly accepted by the SiC and GaN industry, as the features can significantly improve the durability of graphite reactor parts and diminish the possibility of contamination.[1] Typical SiC or GaN epitaxial growth happens at 1100 to 1750°C and the physical vapor transport (PVT) of SiC crystal growth happens around 2400°C. The special features of TaC coating can effectively protect graphite underneath and bring considerable enhancement in operating cost, product quality and thus economic benefits. In fact, just like all thin film deposition and coating process, TaC coating on graphite requires consideration of CTE matching, and different graphite grades bring in a large CTE spectrum. Decades of experiences and the proprietary coating process enable us to deposit uniform TaC coating on a wide range of graphite grade of CTE between 5.5 to 8.9×10-6/°C with exceptional adhesion and protection. In this study, we combined high temperature in-situ SEM and high temperature etching test to assess the impact of CTE matching to the coating reliability.

2. Surface crack due to CTE mismatch The graphite substrates, due to their applications and suppliers, can have large variation in CTE, which lead to significant CTE mismatch with TaC coating. CTE mismatch can result in surface cracks on TaC surface with crack width and density reflecting the degree of mismatch (Figure 1). Crack behavior was studied using in-situ high temperature Scanning Electron Microscopy (SEM) on a 10 × 10 × 1.5 mm coupon made from graphite B with CTE of 6×10-6/°C. The SEM images show that the crack width decreases with increasing temperature (Figure 2). For example, a 2-μm crack shown in Figure 3 shrunk to <1 µm at 1100°C, and would be expected to close completely at higher temperatures. This ‘healing’ behavior is a major factor explaining the wide tolerance of CTE mismatch between graphite and Momentive Technologies’ coating products.

3. Resistance to NH3 etching at high temperature Thin rods made from graphite grades B and B2 with CTE of 6.0×10-6/°C and 7.6×10-6/°C, respectively, were coated with 30 μm TaC. The rod specimens were then heated in NH3 at 500 torr to 1400°C and later to 2000°C. The rod resistance (Figure 3) was closely monitored to detect any graphite etching by hydrogen released from NH3. Both tests showed negligible change in resistance and no significant change in coupon weight before and after the experiments. Results indicate good protection of the graphite substrate due to the TaC coating at a high temperature and aggressive chemical environment. It also supported the hypothesis of crack healing at high temperature from the in-situ SEM study conducted as a part of this investigation.

4. Conclusion Momentive Technologies’ unique process enables uniform and dense TaC coatings and is tolerant of a wide range of CTE mismatch with various graphite grades. While cracks induced by CTE mismatch between coating and substrate are inevitable, these TaC coatings provide effective protection at temperatures over 2000°C and in aggressive chemical environments. Investigation using in-situ SEM imaging revealed that TaC coatings with cracks at room temperature would seal the graphite at elevated temperature. This mechanism was further supported by TaC coated graphite resisting against corrosive gases associated with SiC and GaN epitaxy processes at high temperatures. The results of this work also bode well for successful application of TaC coating in SiC PVT crystal growth.

References [1] Lee, Doe Hyung, et al. "Effect of TaC-coated crucible on SiC single crystal growth." Materials Science Forum. Vol. 778. Trans Tech Publications Ltd, 2014.

ABSTRACT. This paper introduces a novel method to exfoliate the entire thickness required for the drift layer from ultra-high-quality Semi Insulating (SI) 4H-SiC material. It enables precise control of doping concentration or custom doping profiles using Energy filtered Ion Implantation (EFII) technology [4] and bonding this layer to a highly conductive substrate. This approach is anticipated to remove the necessity for epitaxy in conventional SiC power device production lines, whilst epitaxy has higher maintenance cost and complexity in scaling up to 200mm and beyond in SiC technology. This study outlines the key steps for exfoliating a 4μm thick layer of SiC from substrates and bonding it to low-cost, highly conductive monocrystalline SiC.

ABSTRACT. The integration of high temperature refractory ceramic materials, for example silicon carbide, into silicon semiconductor process technology chains requires low thermal budget processing if the refractory material have to be introduced in the front- and back-end processing of silicon integrated circuits. The available growth technologies offer temperatures down to 750°C and are based on reactive sputtering [1], chemical vapor deposition [2] or molecular beam epitaxy [3]. At growth temperature between 700 and 1000°C the growth rates are limited and the growth duration of micrometer thick layers determines the thermal budget. To overcome this issue an alternative method can be applied. It consists in a combination of sputtering a silicon-carbon multilayer stack and subsequent rapid thermal annealing (RTA) [4]. Here we investigate the influence of the Si-C bilayer thickness to achieve transformation of the Si-C bilayer stack into SiC. The Si-C bilayers were deposited using magnetron sputtering of Si and C targets. Alternating layers of Si and C are repeatedly deposited onto a silicon substrate until achieving an overall film thickness of 1 µm. The thickness of the single silicon and carbon layers were 5, 10, 20 and 50 nm resulting in bilayer thicknesses  of 10, 20, 40 and 100 nm, respectively. The RTA was carried out in a temperature range between 500 and 1100°C in pure argon atmosphere with annealing times ranging from 1 to 5 min. The heating rate was set to 10 K/s. The cooling rate was kept at 4 K/s. The structural investigations were performed by X-ray diffraction (XRD) accompanied by Fourier transform infrared spectroscopy (FTIR). The X-ray diffraction patterns were analysed by Rietveld method to extract the structural properties. Morphological investigations were carried out with scanning electron microscopy (SEM). Fig. 1 shows a cross section SEM image of as deposited and annealed at 1100°C for 5 min samples reactive with a bilayer thickness  = 100 nm in the as deposited state. The dark grey layers in Fig. 1a correspond to carbon, whereas the light grey layers stem from the deposited silicon in the multilayer stack. As it is evident in Fig. 1b after annealing the total layer thickness shrinks. The densification of the layer stack is caused by two factors. Firstly, during ramping the substrate temperature to the final annealing temperature recrystallization of the deposited layer occurs. Secondly, at the interfaces between the silicon and carbon layers SiC was formed by interdiffusion and reaction of silicon with carbon in the interdiffused regions. This was evidenced by a contrast analysis in higher magnification images. These processes lead to densification of the multilayer stack. The shrinkage of the total layer thickness of the multilayer stack was confirmed by FTIR measurements, where a blue shift of the thickness oscillations was observed. In Fig. 2a the set of XRD diffraction spectra recorded in thin film mode for different bilayer thicknesses annealed at 1100°C is shown. Starting with a bilayer thickness of  = 40 nm Si related diffraction spots are appearing caused by not consumed Si in the Si-C to SiC transformation process. The maximum of the SiC intensities appears at  = 20 nm with no Si peaks indicating on a complete Si-C to SiC transformation. Therefore, it can be concluded that the critical bilayer thickness for a complete transformation is between 20 and 30 nm. Furthermore, the identified diffraction peaks allow to conclude that 3C-SiC was formed. The phase composition is summarized in Fig.2b. The onset of the SiC formation was determined to be around 700°C. The annealing temperature dependence of the lattice constant of the formed 3C-SiC of the Si-C bilayer structure with  = 20 nm obtained by Rietveld refinement is shown in Fig. 3a. For annealing temperatures below 1000°C the SiC was tensile stressed, whereas for higher annealing temperatures compressive stress was obtained. This result was corroborated by FTIR measurements where a change of the 3C-SiC TO vibration frequency from 785 and 800 cm−1 was observed if the annealing temperature increases from 800 to 1100°C. Fig. 3b displays the silicon and 3C-SiC grain size obtained by Rietveld refinement after RTA annealing in dependence on the bilayer thickness. The grain size is limited to values smaller than the single layer thickness. A model of the transformation process will be presented.

[1] Q. Wahab, R.C. Glass, I.P. Ivanov, J. Birch, J.E. Sundgren, M. Willander, J. Appl. Phys. 74, 1663 (1993). [2] I. Golecki, F. Reidinger, J. Marti, Appl. Phys. Lett. 60, 1703 (1992). [3] S. Kaneda, Y. Sakamoto, C. Nishi, M. Kanaya, S. Hannai, Jpn. J. Appl. Phys. 25, 1307 (1986). [4] R. Grieseler, I. Gallino, N. Duboiskaya, J. Döll, D. Shekhawat, J. Reiprich, J.A. Guerra, M. Hopffeld, H.L. Hauke, P. Schaaf, J. Pezoldt, Mater. Sci. Forum 1062, 44 (2022).

ABSTRACT. High warpage of 4H-SiC wafers after the wafering process is a serious problem in the device fabrication process, leading to yield loss due to vacuum chuck error during CVD epitaxial growth and non-uniform resist thickness in the lithography [1]. Therefore, a new method to control wafer warpage is needed. The Twyman effect originates from the difference in machining process quality between the Si-face and the C-face and lattice dislocation from variations in doping, thermal stress, and defect density [2]. The finishing quality of the Si-face leads to the generation of crystal defects at the interface during epitaxial growth in the device fabrication process, so chemical mechanical polishing (CMP) is performed with as little sub-surface damage (SSD) remaining as possible. In contrast, the C-face does not require epitaxial growth, so it does not require the same level of processing accuracy as the Si-face. From this, we hypothesize that various vendors use the balance between the degree of processing on both sides to control wafer warpage, with each vendor using a different strategy for empirical optimization. In that case, the degree of change in wafer shape may vary during device manufacturing processes that apply thermal processes such as CVD epitaxy and annealing after ion implantation. To address this, a method to quantitatively visualize the balance of processing quality on both sides and a new method to optimize wafer warpage independently of the conventional Twyman effect is needed. We have developed a laser light scattering (LLS) technique, which obliquely irradiates a laser beam onto a SiC wafer to obtain the LLS intensity distribution corresponding to SSD depth and surface roughness [3]. Applying this method not only to the Si-face but also to the C-face allows quantification of the processing quality balance for each vendor. One technique to exogenously control wafer warpage is to induce tensile stresses that bend the wafer by depositing different materials on the backside of the wafer [4]. In contrast, our innovative approach proposes controlling processing quality and independent warpage by depositing optimal homoepitaxial growth layers on both sides of the SiC wafer. We developed Dynamic AGE-ing (DA), a thermal sublimation etching and growth technique that anneals SiC wafers in a quasi-closed space, enabling precise etching on one side and growth on the other. In this study, we evaluated the processing quality of Si- and C-faces of 4H-SiC wafers made by various vendors using the LLS method, determined the relationship with warpage (BOW), and verified the possibility of correcting warpage of SiC wafers by the DA process. The samples were CMP-finished 6-inch 4ooff 4H-SiC (0001) wafers purchased from several vendors. First, the samples were measured for LLS intensity. For detailed LLS measurement conditions, see Ref. [5]. The same samples were measured for BOW and Warp using the NIDEK Slanting incidence Interference method Flatness Tester. Next, the mode values of LLS scattering intensity on Si- and C-face were determined. Fig. 1 shows the relationship between the BOW and the mode frequency of LLS intensity for each of the Si- and C-faces of wafers from several vendors. The graph shows that the same trend is observed for the same vendors, and there is a difference in the LLS scattering intensity between the Si- and C-face for each vendor. This suggests that different vendors have different strategies for controlling the wafer warpage and may adjust the processing quality of the backside of the wafer to control the wafer warpage. Fig. 2 shows the LLS images of the Si- and C-faces of CMP-finished wafers and the results of wafer warpage measurements from two vendors. As can be seen in the LLS image, the wafers have close BOW values even though they have different LLS intensities, which signify processing quality. This means that the BOW is affected by the balance of the difference in processing quality between the Si-face and the C-face, but not by the processing quality of each. As shown in the experimental process in Fig. 3 DA etching and DA growth were performed from the Si-face of the vendor C wafer. As a result, about 6 µm of the epitaxial layer was deposited on the Si-face and about 12 µm on the C-face, with carrier concentrations ranging from 1.0-3.0 × 1017 cm-3. Fig. 3 shows the results of sublimation etching and sublimation epitaxial growth of a wafer with a high warpage. After sublimation etching, the sign of the BOW changed from positive to negative, and then after sublimation epitaxial growth of the same wafer, the sign of the BOW changed back to positive again. This suggests that by using DA, it is possible to control the removal of SSD on the Si-face and the warpage of the wafer by balancing the growth layers on the Si- and C-face, no matter what the conditions of the wafer are.

ABSTRACT. This study explores the effect of a diamond-slurry-polished silicon carbide wafer surface on the resulting quality of a deposited SiC epitaxial layer. Diamond abrasives are well known in the manufacturing of silicon carbide wafers and are used at various process points from ingot shaping to wafer isolation to lapping and fine grinding. Because of its extreme hardness, diamond provides a mechanical removal action on a silicon carbide surface in both fixed bond systems and in a slurry as a free abrasive. We have demonstrated that an etched diamond surface can be produced on diamond as fine as 0.25 microns in diameter and that the nano-scale features of this diamond can significantly enhance the material removal rate and surface finish of the Si-side of a SiC wafer. By replacing or minimizing the use of the chemistry-based slurry with a mechanical abrasion process, significant savings can be realized by overall reduction in slurry usage as well as in waste disposal costs.

The key question this study addresses is: can a diamond-polish provide an acceptable surface quality for producing an acceptable epitaxy layer. In order to determine the extent of surface damage reduction from previous processing, several 150mm SiC wafers were polished with four diamond slurries of sizes 1um, 0.75um, 0.5um and 0.25um abrasive mean size. A control wafer was also polished using conventional chemical-based CMP slurry. The polishing was performed on a IPEC 472 CMP machine using a Power 1000 polishing pad. In addition to material removal rates and surface finishes as shown in Fig. 1, a non-contact, nondestructive microscopy technique was investigated for further wafer quality characterization. Preliminary results indicate decreasing residual damage with decreasing abrasive size. As shown in Fig. 2, the cross-sectional response image produced from the finest diamond polished slurry appears similar to the image of CMP polished wafer. Surface features were also measured using a Lasertec SICA analysis method.

The polished wafers were then subjected to a standard epitaxy process whereby a 10um layer of SiC was deposited on each of the wafers. Lasertec SICA scans were then performed on the epi-processed wafers. This poster describes the quality of the epi-layer on the wafers polished using a submicron diamond slurry as compared with the epi-layer on the wafers polished using conventional CMP slurry. If an acceptable epi-layer can be produced on a diamond polished wafer, considerable cost savings can be realized using the diamond slurry instead of the conventional, chemical-based CMP slurry.

ABSTRACT. We investigated surface irregularities on a 4H-SiC homoepitaxial layer caused by partial dislocations (PDs) encompassing stacking faults (SFs) existing under the surface using Raman scattering microscopy. The surface irregularities were classified into two types in terms of their Raman scattering spectra; one showed a reduced scattering intensity of the transverse optical (TO) E2 mode at 776 cm−1, whereas the other showed almost no changes in the TO scattering intensity but exhibited a distinct shift in the peak position of the longitudinal optical phonon-plasmon coupled (LOPC) A1 mode at 964 cm−1. We analyzed these behaviors of Raman scattering spectra and tried to extract unique information from 4H-SiC homoepitaxial layers grown on PDs of SFs, not attainable with other characterization methods.

ABSTRACT. We investigated the nature and distribution of the crystallographic defects formed during the initial stage of PVT growth of 4H-SiC using photoluminescence (PL) imaging and spectroscopy by examining a slightly off-oriented 4H-SiC (000−1) wafer prepared from the grown crystal/seed interface of a PVT-grown 4H-SiC crystal, where the substantially enlarged interface region between the grown crystal and the seed crystal appeared on the wafer surface. On the basis of the obtained results, we discuss the formation mechanisms of crystallographic defects, particularly those showing characteristic PL features, at the initial stage of PVT growth of 4H-SiC crystals.

ABSTRACT. In the field of power electronics, precise control of dopant incorporation during epitaxial growth of 4H-SiC is essential for device performance and stability. This study elucidates the complex interdependencies among key process parameters: C/Si ratio, system pressure, temperature, growth rate as well as reactor parts on nitrogen dopant incorporation into homoepitaxial layers on 4H-SiC (0001) substrates. Our investigations confirm that the CVD process parameters significantly influence nitrogen doping efficiency and can be tuned to enhance or cancel the effects of each other. In this way we demonstrate that precise tuning of these parameters can achieve targeted doping profiles. Furthermore, these results indicate a foundational role of the effective C/N ratio in governing dopant behavior under diverse growth conditions, as the local C- and N-coverage is significantly affected by every process parameter.

ABSTRACT. Reduction of basal plane dislocations (BPDs), which cause the forward-current degradation in bipolar devices [1], in SiC substrates is a significant challenge to improve the reliability of SiC devices. To tackle it, we have been developing a novel crystal growth method that enables the reduction of BPDs of multiple substrates at the same time, which has the potential to produce substrates with low BPD densities at a low cost. In this study, we discuss the behaviors of BPDs and other defects in this crystal growth method. In our method, the multiple graphite crucibles which contain a 4H-SiC substrate (seed crystal), SiC powder, and additives that produce liquid phase upon heating are put in a furnace and heat-treated at temperatures over 2000 ℃ in the mixed atmosphere of Ar and N¬2 as illustrated in Fig. 1. By this process, 4H-SiC single crystals with a thickness of ~100 – 200 um are grown onto the seed crystals. The crystal growth is presumed to occur including the following steps: melting of the additives at high temperatures, dissolution of the SiC powder into the liquid phase, and recrystallization of SiC onto the seed crystal. The obtained crystals were polished, and molten salt etching was performed to determine defect densities. The densities of BPDs, threading edge dislocations (TEDs), and threading screw dislocations (TSDs) of the seed crystal and the grown crystal were measured at five regions including center and periphery of the substrate. As shown in Table I, BPD densities of the grown crystal were significantly lower than those of the seed crystal at all regions, whereas TED and TSD densities of the two crystals showed relatively small variation ratios. We investigated in the behavior of micropipes (MPs) as well. The optical microscope image in Fig. 2 showed that MPs present in the seed crystal propagated into the grown crystal. These results indicate that our method is effective for reducing BPDs of seed crystals, while having relatively little effects on other defects, such as TEDs, TSDs, and MPs. To estimate the global BPD density of a 6-inch substrate, X-ray topography (XRT) was performed on the seed crystal and grown crystal. (The sample used for this analysis is different from the one used for obtaining data in Table I.) The XRT images were divided into a 10 mm × 10 mm grid, and the BPD densities at each grid were calculated and mapped by an image processing software. As shown in Fig. 3 (a) and (b), BPD densities in the grown crystal were lower than those in the seed crystal over the whole substrate area. To further understand the behavior of BPDs, the sectional XRT images were obtained as shown in Fig. 4 (a) – (c). The string-like contrasts that represent BPDs gradually decreased as the crystal growth proceeded. The total length of the string-like contrasts in each sectional image was calculated with an image processing software as shown in Fig. 4 (d). It indicates that most of BPDs disappeared during crystal growth of 100 um in thickness. For verifying the reason why BPDs disappeared, the grown crystal was observed by synchrotron XRT, and BPDs were found to be terminated by TEDs. That shows that the BPDs were converted into TEDs during the crystal growth. This conversion is typically reported in an epitaxial growth with chemical vapor deposition (CVD) method, and the conversion ratio is influenced by the size of the steps [2]. We expect that the steps formed by our method have similar structures to those of the CVD method, but the details have not been clarified. We are currently exploring the measures to enhance the conversion efficiency.

ABSTRACT. Silicon Carbide (SiC) is a promising wide bandgap semiconductor material extensively utilized in advanced high-power and high-frequency applications such as power devices, solar inverters, and electric vehicles (EVs). For efficient mass production of top-quality SiC epi-wafers, it is vital to ensure the uniformity of growth rate and doping incorporation during Chemical Vapor Deposition (CVD) of SiC epitaxial layers. However, high operating temperatures and aggressive environment in SiC deposition reactors make obtaining detailed experimental data on the processes particularly challenging. Under these circumstances, computer modeling becomes a powerful tool for investigating the bottlenecks in the existing technology and finding modifications beneficial for SiC epilayer quality and reactor throughput. In the presented modeling analysis, we focus on the factors affecting nitrogen doping level, its uniformity, and run-to-run reproducibility using a model of SiC doping by nitrogen presented in the work [1] and incorporated in CVDSim3D software [2]. Parasitic deposition on the internal surfaces of SiC epitaxial reactors affects multiple process characteristics including the growth rate, dopant incorporation, and uniformity. Apart from the obvious issue of the precursor losses, parasitic deposits upstream from the wafer, including the deposits different from SiC, affect precursor concentrations and C/Si ratio over the wafer. Moreover, gradual change of the amount and nature of the deposits from run to run is a well-known factor causing the drift in the resulting growth rates and N doping. To illustrate, we use a generic rendering of a widely used horizontal reactor shown in Fig. 1 along with the temperature distribution in a central cross-section. Typical process parameters of temperature equal to 1650 °C and pressure of 100 mbar have been selected. The precursor flow rates were taken so that C/Si ratio at the inlet exceeds 1 and N2 was considered as the dopant source. Often, internal surfaces of the reactor are coated with SiC. Simulations were conducted in order to see if the chemical composition of the deposits on the reactor walls can shift after several runs towards graphitized SiC. It has been found that deposition of graphitized SiC is possible on the parts of the reactor where the temperature varies in the range about 1000÷1500 °C. Evolution of the deposits affects C/Si ratio which, in turn, will have a noticeable effect on the nitrogen doping. To keep the reactor walls free of deposits, TaC coating can be used. In this case the problem of run-to-run reproducibility is resolved. However, the doping uniformity will exhibit strong non-uniformity as reduced upstream deposition will cause strong edge effects on the wafer itself. Numerical modeling can be used to find the optimal balance between the reproducibility and uniformity via the use of combination of the wall coatings of different compositions, see Fig.2.

[1] M. V. Bogdanov, et al, presented at ICSCRM-2017. [2] https://www.str-soft.com

ABSTRACT. Wide bandgap (WBG) materials such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3) are gaining significant attention for their use in electronic devices operating under high-frequency, high-power, and extreme temperature conditions due to their inherent large bandgap. Among these WBG materials, Ga2O3 is particularly noted for its effectiveness in deep ultraviolet photodetection and its durability under harsh conditions, attributed to its large bandgap of 4.9 eV and a high breakdown field of 8 MV/cm[1]. However, Ga2O3 based high-power devices suffer from a severe self-heating effect due to low thermal conductivity of Ga2O3 (~0.2 W/cm∙K). Thus, it is often deposited on substrates with better thermal properties, such as sapphire and SiC. In particular, SiC is frequently used as a substrate due to its excellent thermal conductivity (~5 W/cm∙K). Ga2O3 films can be manufactured using several techniques, including Molecular Beam Epitaxy (MBE), RF sputtering, Aerosol Deposition (AD), and Pulsed Laser Deposition (PLD). Furthermore, it is well known that the difference in substrates or different methods of preparing film has different effects on the quality of the film. In this study, we fabricated Ga2O3/SiC heterojunction diodes by depositing Ga2O3 films on SiC substrates using RF sputtering (sample A), PLD (sample B), and AD (sample C). The characteristics of these heterojunctions were analyzed using current-voltage (I-V) measurements, X-ray photoelectron spectroscopy (XPS), and deep level transient spectroscopy (DLTS). In I-V measurements of Ga2O3/SiC heterojunction diodes which was fabricated by different methods, we found significant variations in performance based on the deposition methods. Sample C showed remarkably low on-resistance of 910 mΩ·cm² and highest rectification ratio of 2.5 × 1011 whereas sample A showed specific on-resistance of 21,600 mΩ·cm² and lowest rectification ratio of 1,000. In the XPS analysis, we characterized the chemical composition and bonding states of the Ga2O3 films. We examined the O1s peaks to analyze the change in oxygen vacancies by the deposition method, which are reported to influence the conductivity of Ga2O3 film. For a quantitative analysis of the concentration of oxygen vacancies, the intensity ratio of OII/(OI+OII) on sample A, B, C was calculated to be 17.65 %, 19.76 % and 23.45 % respectively. This reduction in vacancies is can significantly impact the n-type conductivity which was shown in I-V measurements. Furthermore, we investigated the variations in deep level defect states in the samples through Deep Level Transient Spectroscopy (DLTS) measurements. Notably, the Z1/2 defect, which is a predominant defect in SiC was observed in all samples[2]. Additionally, defects in Ga2O3 such as E2, E4, and E6 were also detected[3]. This indicates that measuring DLTS on Ga2O3/SiC heterojunction diode can simultaneously detect defects in both SiC and Ga2O3. However, the types of defects and their concentrations varied according to the deposition method. This variation in defect states suggests that the deposition technique significantly influences the electrical characteristics of the Ga2O3/SiC heterojunctions, potentially impacting device performance and reliability.

ABSTRACT. One of the point defects of interest for the emerging quantum technology in 4H-SiC is the silicon vacancy (VSi). The dipole of the VSi is aligned along the c-axis and requires optical excitation perpendicular to the c-axis [1]. The conventional substrate for 4H-SiC homoepitaxy is c-plane with 4°off-cut towards the <11-20> direction, this makes it difficult to get optical access to any of the directions perpendicular to the c-axis. One solution to the issue of optical access is to use non-conventional substrates with an alternative orientation. A-plane substrates are promising candidates as earlier studies have reported good results for homoepitaxy on such substrates [2,3].

Beside conventional 150 mm c-plane wafers, circular a-plane substrates of 35 mm diameter have been used for this study. One side of the substrates was chemical mechanical polished (CMP) prior to epitaxial growth. The epitaxial growth has been performed in planetary reactors, and the majority of the epitaxial growth runs have been made with a combination of 35 mm a-plane wafers and 150 mm off-cut c-plane wafers. Both nitrogen doped and nominally undoped samples were grown. It was possible to achieve homoepitaxy on the entire 35 mm a-plane wafers. In Fig. 1, x-ray topographs using three different diffraction vectors are presented in Fig. 1 showing that the epitaxial layers do not have any polytype inclusions or any unexpected defects. The quality of the homoepitaxy was also confirmed using microwave photoconductivity decay (µ-PCD). The atomic force microscopy (AFM) scan in Fig.2 a) shows that the epilayer grown on 4° off-cut c-plane substrate has the characteristic steps from the step-flow growth. The step-flow growth makes the surface of the epilayer relatively rough with surface roughness in the range of a few nm. While in Fig. 2 b) the epilayer grown on a-plane substrate has a much lower surface roughness in the range of several hundred pm. The improvements in surface roughness in the epilayers grown on a-plane substrates comes from the lack of step formation on the surface. In Fig. 3 a) thickness measurements by Fourier transform infrared spectrometry (FTIR) are presented. The thickness for the c-plane and a-plane samples are very similar. It can be noted that the a-plane samples are consequently slightly thicker than the c-plane samples from the same growth run. It has still not been concluded whether this is due to the difference in the growth modes of the two samples or if this is an artefact from the large difference in the size of the substrates. In Fig. 3 b) the doping is presented for the same two runs discussed in Fig. 3 a). The doping measurements are done by capacitance-voltage (CV) probe using Hg as contacts. As can be seen the nitrogen incorporated at a much higher degree on the a-plane samples compared to the c-plane samples from the same growth run. This is in line with the site-competition theory of dopant incorporation in SiC [4] that claims that nitrogen competes with carbon for available carbon sites at the step edges (a-plane) of the step-flow growth mode. In the case of a-plane growth there are more available carbon sites available at the growth front as the entire growth front is a-plane. In this study the differences between homoepitaxy on c-plane and a-plane substrates will be discussed in detail. The µ-PCD measurements will be discussed in more detail together with additional discussions about the difference in surface morphology.

ABSTRACT. Fabricating a smooth and abrupt SiC/SiO2 interface for highly reliable SiC MOSFETs remains challenging due to C cluster formation near the interface. Despite efforts to reduce C clusters, their kinetics remain unclear. Numerical simulations provide insight, but there are limitations in first-principles calculations and MD simulations due to computational requirements and accuracy issues with empirical potentials. To address this issue, a highly accurate interatomic potential (PreFerred Potential; PFP) based on graph neural networks has been employed. SiO2 models with varying C and O atoms were created, exploring O-containing conditions denoted by the substitution coefficient (s). The generated structures were classified into gas molecules, monocarbon structures, dicarbon structures, and C clusters. C-cluster formation increased in O-poor conditions and decreased in O-rich conditions. At s = 2, where every two O atoms are replaced by one C atom, the mono-carbons increased and the C cluster decreased as C atoms bonded to Si atoms due to the lack of O atoms. These trends are consistent with previous results from formation energy calculations of mono-carbon and di-carbon defects in SiO2 and experimental observations that C clusters are concentrated at the SiC interface, not near the SiO2 surface. Structural analysis reveals a preference for chain-like C cluster configurations. These insights into the influence of the environment on C cluster formation provide the basis for understanding C defect reduction processes such as NO and H2 treatments.

ABSTRACT. 4H-SiC is of interest for high power electronics due to its large bandgap, high breakdown field strength and high thermal conductivity [1]. However, aluminum implantation still presents some uncertainties. This is partly because Hall-measurements of acceptors in 4H-SiC require high temperature measurements, as well as a careful analysis and evaluation of the measurement results to extract an accurate ionization energy, doping concentration, and concentration of compensating defects. To be able to predict the behavior of devices, it is desirable to accurately model the behavior of implanted aluminum dopants. Existing literature suggests that a single acceptor level is insufficient to explain the temperature dependence of the hole concentration in 4H-SiC doped via aluminum implantation [2, 3]. Additionally, ion implantation introduces a not yet fully understood concentration of compensating defects [4]. In this work we fabricated Hall test structures with implanted aluminum concentrations ranging from 1e16 cm-3 to 5e19 cm-3 in n-type epitaxial layers with a nitrogen concentration of approximately 1∙1016 cm-3. Activation was performed at 1700 °C for 30 minutes. The test structures were characterized via Van der Pauw and Hall measurements for temperatures ranging from 300 K to 650 K, yielding temperature and doping concentration dependent values of the mobile hole concentration and hole mobility. Preliminary results for a subset of the manufactured samples are shown in Figure 1. To analyze the data, the neutrality equation and the equations for hole mobility in 4H-SiC were fitted simultaneously to the experimental data [5, 6]. The fit parameters obtained in this process represent the material parameters with respect to ionization energy (EA1 and EA2) and defect concentration (NA1 and NA2) for two acceptors in the bandgap, the concentration of unknown compensating defects (NComp), as well as the deformation potentials for phonon scattering (Dac and Dnop). The preliminary results of said data analysis are listed in Table I. Taking the sample with an intended aluminum concentration (NNominal) of 8e16 cm-3 as an example, Figure 2 shows that the concentration of the acceptor NA1 and the concentration of compensating defects NComp are linearly dependent across a wide range of values when fitting only the temperature dependent charge carrier concentration. Therefore we emphasize the need to fit both mobility and hole concentration values when analyzing Hall measurement data of aluminum implanted 4H-SiC. This approach serves as an alternative to reducing the available solution space during fitting by making assumptions about the acceptor concentrations or the compensation concentration. In this work we focus on a broad range of doping concentrations and a detailed analysis that combines several key aspects about the fitting procedure that were previously described separately in the literature. We are combining the consideration of excited states [7], a second acceptor level [2, 3], and the simultaneous fit of hole concentration data and Hall mobility data [5, 6]. The goal is to determine the ionization energy of both acceptors in the material, as well as the concentration of compensating defects introduced during ion implantation and how these parameters scale with the total implanted dose.

[1] T. Kimoto, Jpn. J. Appl. Phys. 54, 040103 (2015) [2] J. Weisse, et al., Material Science Forum 963, (2019) [3] H. Matsuura, et al., J. Appl. Phys. 96, 2708–2715 (2004) [4] J. Weisse, et al., Material Science Forum 924, (2017) [5] A. Parisini and R.Niptoi, J. Appl. Phys. 114, 243703 (2013) [6] J. Pernot, S. Contreras and J.Camassel, J. Appl. Phys. 98, 023706 (2005) [7] H. Matsuura, Physical Review B 74, 245216 (2006)

ABSTRACT. Bipolar degradation is one of the key issues in which SiC-MOSFETs are facing for decades. It is known that bipolar degradation causes not only MOSFET forward voltage degradation (VDSon degradation), but also leakage current degradation (IDSX degradation). However, studies on IDSX degradation are very few. Its detailed origin is still unclear, and it must be clarified to fully understand the degradation phenomena. In this study, high current stress to the BD was performed on large numbers of 3.3kV SiC-MOSFETs and IDSX degraded chips were identified. These degraded chips show a clear abnormal leakage current compared to a good chip. Furthermore, failure analysis was conducted to identify the origin of abnormal leakage. It was found that abnormal leakage to be occurring at the periphery of extended stacking faults originating from the micropipe, or at the micropipe itself. These results suggest micropipe as a killer defect for both VDSon and IDSX degradation.

ABSTRACT. Stacking of SiC substrates of different crystalline quality and/or doping level through wafer bonding is of particular interest to build substrates for specific applications. Although a direct SiC/SiC bonding may result in an unstable interface, a good adhesion between the SiC substrates can be ensured by an intermediate layer of conductive material playing a role of a “glue”. In this work, we investigate the possibility to use silicon, titanium and tungsten as bonding materials. Bonded structures were prepared using atomic diffusion bonding (ADB) applied at room temperature. Then, the SmartCutTM process was applied resulting in a transfer of a 600nm-thick SiC layer on the SiC substrate. We compare the structure evolution of nanometer-thick Si, Ti and W layers in relation to the SiC substrates after a high temperature annealing.

Scanning electron microscopy (SEM) imaging was applied for large scale plan-view observations of the upper surface of the sandwiched layers, once the top substrate has been removed by cleavage. Cross-sectional transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM) imaging and X-ray diffraction were used for layers’ structural characterization at local and macroscopic scales. For all three materials, we demonstrate that the homogenous continuous film created after low temperature deposition transforms into a discontinuous structure following high temperature annealing. Fig. 1 and Fig. 2 show respectively, the SEM and TEM images of the interface after annealing for the three materials studied.

We show that annealing of the structures at temperatures below the melting point, between 900°C and 1400°C, causes fragmentation of the thin silicon layers together with silicon redistribution at the interface. We attribute such a finding to the development of the Si dewetting from the SiC internal surfaces. Upon annealing above the silicon melting temperature, we evidence a greater development of step bunching on the internal surfaces of both SiC substrates in comparison to the free SiC substrate surface. When Ti intermediate layers are used, they preserve the form of a quasi-continuous layer with the formation of a few thick nodules, whatever the temperature is applied. This indicates that Ti wets effectively the SiC surface as opposed to Si. On the other hand, Ti strongly promotes SiC surfaces reconstruction by step bunching at high temperatures, an effect similar to that observed with Si layers. The samples with the layers of tungsten reveal again the effect of solid-state dewetting upon annealing at high temperatures up to 1700°C. As a result, the initially continuous film decomposes into isolated nodules. The formation of tungsten carbide with an epitaxial relation to SiC substrates was also demonstrated.

For all three materials, we evidence particular structural and compositional transformations in the layers as a function of annealing temperature and time. All structures tend to reach an epitaxial relation with the SiC substrates. In contrast to Si layers which preserve Si composition, both Ti and W layers are transformed into new phases which were identified. The dewetting modeling and potential chemical and structural reactions during interface reconstructions will be discussed in relation to all of these findings.

ABSTRACT. Nitrogen (N)-doped 4H silicon carbide (4H-SiC) has shown great success in high-power electronics, although high density of dislocations still limit the performance and reliability of high-power devices based on 4H-SiC [1, 2]. In a vertical high-power device, the concentrations of N in 4H-SiC substrate and homoepitaxial layer are in the range of 1018-1019 cm-3 and 1014-1016 cm-3, respectively [3]. In this work, we establish the interaction mechanism between N and dislocations in 4H-SiC, and tailor the electronic and kinetic properties of dislocations by doping. We find that the interaction between N dopants and dislocations changes the electronic and kinetic behaviors of dislocations in 4H-SiC. Both Kelvin probe force microscopy (KPFM) measurements and first-principles calculations indicate that basal plane dislocations (BPDs) and threading edge dislocations (TEDs) create acceptor-like states in 4H-SiC. During N doping, N atoms spontaneously decorate the dislocation cores of BPDs and TEDs. The accumulation of positively charged N dopants at the cores of dislocations turns the defect states of BPDs and TEDs from to donor-like states. Since 4H-SiC based power devices compose differently N-doped layers, these understanding on the effect of N on the electronic properties of dislocations paves the way for the understanding on the electron transport in 4H-SiC based power devices. We then investigate the interaction between N and dislocations, and its effect on the kinetics of dislocations in 4H-SiC. By combining nanoindentation tests and transmission electron microscopy (TEM) observations, we illustrate that the shear stress dominates the stress field of nanoindentated 4H-SiC. The shear stress gives rise to the formation and slip of BPDs, as well as the polymorph transition from 4H-SiC to 3C- and amorphous SiC. N dopants could facilitate the slip of BPDs, and thus release the shear-stress field. This gives rise to the decreased mechanical properties, such as the hardness, elastic modulus, and fracture toughness, of N-doped 4H-SiC. The insight may help the design of the processing of undoped and N-doped 4H-SiC wafers. In conclusion, we have demonstrated that N dopants are prone to spontaneously accumulate at the cores of BPDs and TEDs during the N doping of 4H-SiC. The N decoration shifts the acceptor-like states of BPDs and TEDs to donor-like states, which results in the donor-like character of BPDs and TEDs in N-doped 4H-SiC. Kinetically, N decoration enhances the slip and piling up of BPDs, reducing the hardness, elastic modulus and fracture toughness of 4H-SiC. Our work not only sheds light on the processing of differently doped 4H-SiC wafers, but also paves the way for understanding the electron transport of 4H-SiC based power devices.

[1] T. Kimoto et al., Fundamentals of silicon carbide technology: growth, characterization, devices, and applications, John Wiley & Sons (2014). [2] H. Luo et al., ACS Appl. Electron. Mater. 4, 1678 (2022). [3] J. Li et al., Phys. Rev. Appl. 17, 054011 (2022). [4] J. Li et al., ACS Appl. Electron. Mater. 5, 2664 (2023). [5] X. Liu et al., J. Phys. D: Appl. Phys. 55, 334002 (2022). [6] X. Liu et al., Appl. Phys. Lett. 120, 052105 (2022).

ABSTRACT. In SiC substrate manufacturing, grinding, slicing and bevel polish steps add to the density of surface and subsurface defects, while lapping and final CMP steps result in far-from-ideal final surface finishes as both cause the formation of large numbers of lateral and vertical cracks within the plastic zone of the substrate and beyond. In this study, we aim to reduce the number of scratches as well as surface and subsurface defects by a novel method which we call CARE-TEC® or “CAtalyst-Referred Etching Technology”.

Our state-of-the-art load-lock system has four electrochemically assisted polishers, a robotic wafer handling arm, and an integrated substrate cleaning module. The system is uniquely designed to reduce surface smoothness to below 1 nm, while significantly reducing the number of surface and sub-surface defects. Such stringent specifications are crucial for producing epi-ready SiC (and also GaN) substrates.

Our technology employs a polymeric pad onto which a catalytic platinum or ruthenium film is sputtered. With just water as the slurry substitute, an electric potential is then applied to the SiC substrate and the pad. The principal mechanism of polishing SiC can be described by the reaction below where SiC is continuously etched away by catalytically converting the top layers of the SiC to monolayers of silicon dioxide which are then removed mechanically (via polishing) at moderate pressures:

SiC + 8H+ + 4H2O → SiO2 + CO2 + 8H+

A similar mechanism is also responsible for gallium nitride electropolishing:

GaN + 6H+ + 3H2O → Ga2O2 + N2 + 6H+

Results, using a Lasertec inspection system (Fig. 1), show the presence of 339 defects on a 150-mm “epi-ready” SiC substrate (left). After removing only 20 nm of SiC from the surface with CARE-TEC®, the total number of defects has dropped to 95 (center). This slight thickness removal seems to have caused the appearance of subsurface latent scratches that could not be seen before our electrochemical CMP step. With the removal of another 80 nm of SiC using CARE-TEC®, the total number of defects further drops to only 31 (right) where most of the scratches and micro-cracks are no longer detectable.

Electrical results by Denso measured on multiple Schottky Barrier Diodes (Fig. 2) show a dramatic improvement in gate leakage current when CARE-TEC® is used. Applying CARE and CMP after activation annealing achieved approximately a single-digit or more reduction in leakage current density with a reverse voltage in the SBDs. The leakage current variation at - 600 V for the case of CARE-TEC® was the smallest of three samples tested.

Results (by Denso) concerning time-dependent dielectric breakdown (TDDB) on MOS capacitors, again we see (Fig. 3) orders of magnitude improvement when CARE-TEC® is used. Applying CARE-TEC® and CMP, after deposition of a p-type epitaxial layer, achieved approximately single digit or more improvement in the lifetime.

ABSTRACT. Silicon carbide has become popular in the applications of power electronic devices since the emergence of electric vehicles. Despite the superior electrical properties, the quality of SiC materials is not good enough to make the cost comparable to the conventional silicon-based devices. Efforts to understand the defect behavior and improve the growth process should be continued. In PVT growth of 4H-SiC, a facet region forms at the very early stage and exists during the whole process [1, 2] due to the slower and stable growth rate along c direction. Inside this facet region, doping concentration and strain analysis has been conducted [3]. In this study, threading dislocation behavior around the facet region of off-axis 4H-SiC crystals grown by PVT method is characterized by X-ray topography [4] with Rigaku XRTMicron. Threading dislocation density maps are generated by XRT Toolbox, a data processing software suite. It is firstly observed that in the off-axis c-plane wafer, there is a reduction of threading screw dislocations (TSDs) or threading mixed dislocations (TMDs) at the facet region boundary (Figure 1). To explore the cause of decreased TSD/TMD density, an axial slice sample is prepared by cutting a boule along (11 ̅00) plane and across the facet region. 0004 transmission X-ray topograph is recorded so that contrast of TSD/TMD is dominant in the image, according to the g∙b criterion. It is discovered that there is a redirection of the threading dislocations at the facet boundary (Figure 2). It is observed that the propagation direction is strictly c direction inside the facet region, while as soon as the dislocation reaches the facet boundary, it bends towards the step flow direction. This dislocation bending mechanism will be analyzed. The relation between dislocation bending and the effective local reduction in TSD/TMD density will be discussed.

[1] T. Ailihumaer, H. Peng, Y. Liu, B. Raghothamachar, M. Dudley, Characterization of Dislocations in 4H-SiC Single Crystals at the Initial Growth Stage by Synchrotron X-ray Topography, ECS Transactions 98(6) (2020) 125. [2] S. Hu, Y. Liu, Q. Cheng, Z. Chen, X. Tong, B. Raghothamachar, M. Dudley, Investigation of defect formation at the early stage of PVT-grown 4H-SiC crystals, Journal of Crystal Growth 628 (2024) 127542. [3] T. Ailihumaer, Y. Yang, J. Guo, B. Raghothamachar, M. Dudley, Evaluation of Model for Determining Nitrogen Doping Concentration from Resultant Strain in Heavily Doped 4H-SiC Crystals, ECS Transactions 86(12) (2018) 53. [4] B. Raghothamachar, M. Dudley, X-Ray Topography, Materials Characterization, ASM International2019.

ABSTRACT. Silicon Carbide (SiC) is a wide bandgap semiconductor with great potential for power devices with properties such as a wide bandgap, high breakdown voltage, and thermal stability [1]. There's a growing demand for 4H-SiC high voltage devices capable of withstanding 1.7 to 6.5 kV, sought after in applications like hybrid systems, shipboard and power grid setups, and high-speed trains. Typically, these devices are manufactured on 4H-SiC wafers with thick epilayers to enhance breakdown voltages [2], yet uniformly doping such thick epilayers is challenging. One viable solution involves employing multi-step high energy ion implantation through the system developed at Brookhaven National Laboratory's Tandem Van de Graaff accelerator facility [3], which can implant ions at energies reaching up to 150 MeV. Utilizing this system, medium voltage charge balance devices, including 2 kV and 3.8 kV superjunction structure PIN diodes, have been successfully demonstrated [4]. However, high energy ion implantation introduces notable lattice strain by displacing host atoms in the epilayer and characterizing this strain is important to understand the damage caused by high energy implantation. Previously, synchrotron X-ray plane wave topography (SXPWT) and reciprocal space mapping (RSM) techniques have been utilized to assess the distribution of strain within a 12 µm epilayer of a 4H-SiC epiwafer subjected to multi-step, high-energy implantation with 4.4 x 1016 cm-3 Al ions at room temperature. The findings reveal that the implanted region exhibits a strain level approximately 2.5 x 10-4 higher than that of the non-implanted region [5]. To minimize the as-implanted damage, multi-step, implantation with 5 x 1016 cm-3 Al ions has been employed at RT, 300 °C and 600 °C, where the corresponding strain measured from RSM (Fig. 1(a) to 1(c)) are 4.1 x 10-4, 3.3 x 10-4, and 2.0 x 10-4, respectively[6]. A reduction in strain upon increase of implant temperature by the dynamic annealing effect is clearly observed. Recently, Steinbach and coworkers have reported that placing a jagged shape Energy-Filtered for Ion Implantation (EFII) manufactured by MI2-Factory can result in a box concentration profile by single implantation [7], which can possibly decrease the strain level in the implanted wafer. Implantation via EFII at RT with 5 x 1016 cm-3 Al ions has been conducted and triple axis \omega-2\theta scans have been employed for the implanted epi-wafer with EFII, where separations between the main peak and the satellite peak are 45” and strain level of 3.1 x 10-4 is measured from RSM. The extent of strain in wafer implanted with EFII at RT is comparable to wafer implanted at 300 °C as reported in [6]. SIMS analysis will be carried out to measure concentration profile to compare with wafer implanted at RT without EFII.

[1] A.A. Lebedev and V.E. Chelnokov, Semiconductors 33, 999–1001 (1999). [2] T. Liu, et. al, IEEE Access, 7 145118-145123. (2019) [3] P. Thieberger, et. al, Nucl. Instrum. Methods Phys. Res. B. 442 36-40. (2019) [4] R. Ghandi, et. al, 2022 International Electron Devices Meeting (IEDM), pp. 9.1.1-9.1.4 (San Francisco, CA, USA, 2022) [5] Z. Chen, et. al, Materials Science Forum 1062, 361-365 (2022) [6] Z. Chen, et. al, Proceedings of ICSCRM 2023, (accepted) [7] T. Steinbach , et. al, Microelectronic Engineering 222 (2020) 111203

ABSTRACT. Gallium nitride (GaN) is a wide bandgap semiconductor of growing importance in high power [1] and RF applications [2,3]. Magnetic resonance techniques have long been useful in investigating properties of many semiconductors. Although some studies of the electronic materials physics of GaN structures appear in the literature, a detailed understanding has yet to develop. One promising avenue of investigation has been optically detected magnetic (ODMR) [4]. While there are advantages in probing defects optically, ODMR results are not necessarily relevant to the electrical performance of the devices. Electrically detected magnetic resonance (EDMR) is an excellent tool to investigate electrically active defects. There is very limited literature dealing with EDMR and GaN [5,6]. A related technique, near zero field magnetoresistance (NZFMR), in which measurements are performed under a very low quasi-static magnetic field without the presence of microwaves can provide much of the same information available with EDMR [7,8]. To the best of our knowledge, there is no literature on NZFMR on GaN currently in print; however, this abstract dealing with GaN pn junctions and a second abstract dealing with GaN Schottky diodes represent the first contributions of these novel techniques to GaN electronic materials physics. In this work, we investigate defects present in GaN pn junction diodes, utilizing both NZFMR (Figure 1) and EDMR (Figure 2). The devices were prepared at Pennsylvania State University. The diodes are doped with Mg and Si, with concentrations of 1019 cm-3 and 5x1017 cm-3, respectively. The EDMR response is due to spin dependent recombination. Since spin dependent recombination involves a deep level defect, it is essentially certain that the response at least in part involves a deep level defect [9]. It should be noted that we observe a large difference in the width of the X-band EDMR response and the NZFMR response. The isotropic g of the EDMR response is approximately 2.0026, with a linewidth of approximately 5 Gauss. It is very unlikely that the EDMR response and the NZFMR response are due to the same defect. To the best of our knowledge, the only previously published room temperature EDMR results on GaN were reported by Brandt et al. [6] They attribute their response to three defects with overlapping signals. Brandt et al. observed an EDMR linewidth of approximately 150 Gauss. The g which we observed has also been reported in ODMR paper by Palczewska et al. [10], where they also investigate GaN. They reported a linewidth similar to ours of about 4 Gauss. Glaser et al. [11] also reported ODMR results taken at 1.6K on GaN with a g of about 2.003, which was a minimum of 150 Gauss wide. Our results demonstrate that quite simple room temperature EDMR and NZFMR measurements have great potential in developing a fundamental understanding of electronic materials physics issues in GaN based solid state devices.

[1] E. A. Jones, F. F. Wang, and D. Costinett, IEEE J. Emerg. Sel. Top. Power Electron. 4, 707–719 (2016). [2] F. Zeng, J. X. An, G. Zhou, W. Li, H. Wang, T. Duan, L. Jiang, and H. Yu, Electronics 7, 377 (2018). [3] H. Amano, Y. Baines, E. Beam, M. Borga, T. Bouchet, P. R. Chalker, M. Charles, K. J. Chen, N. Chowdhury, R. Chu et al., J. Phys. D: Appl. Phys. 51, 163001 (2018). [4] D. Carbonera, Photosynth Res 102, 403-414 (2009). [5] M. W. Bayerl, M. S. Brandt, M. Stutzmann, phys. Stat. Sol. (a) 159, R5 (1997). [6] M. S. Brandt, N. M. Reinacher, O. Ambacher, and M. Stutzmann, Mat. Res. Soc. Symp. Proc. (Materials Research Society) Vol. 395 (1996). [7] N. J. Harmon, S. R. Mcmillan, J. P. Ashton, P. M. Lenahan, M. E. Flatté, IEEE Transactions on Nuclear Science Vol. 67, 7 (2020). [8] E. B. Frantz, D. J. Michalak, N. J. Harmon, E. M. Henry, S. J. Moxim, M. E. Flatté, S. W. King, J. S. Clarke, P. M. Lenahan, J. Appl. Phys. 130, 065701 (2021). [9] C.J. Cochrane and P.M. Lenahan, J. Appl. Phys. 112, 123714 (2012). [10] M. Palczewska, B. Suchanek, R. Dwili~ski, K. Pakua, A. Wagner, M. Kami~ska, MRS Internet Journal of Nitride Semiconductor Research Vol. 3, 45 (1998). [11] E. R. Glaser, W. E. Carlos, G. C. B. Braga, J. A. Freitas, W. J. Moore, B. V. Shanabrook, R. L. Henry, A. E. Wickenden, D. D. Koleske, H. Obloh, P. Kozodoy, S. P. DenBaars, U. K. Mishra, Phys. Rev. B Vol. 65, 8 (2002)

ABSTRACT. Commercial junction barrier Schottky diodes were fabricated with two different post-Al-ion-implantation-annealing processes (A) and (B) 1. Process (A) involves a higher post-implantation annealing temperature of 1950 oC and then deposition of metal electrode. Process (B) involves a lower annealing temperature of 1700 oC, followed by the deposition of a sacrificial oxide at 1200 oC, removal of the oxide and then deposition of metal electrode. The two batches of samples were studied by deep level transient spectroscopy (DLTS). The corresponding spectra and parameters are respectively shown in Figure 1 and Table I. Three peaks are identified in Batch A samples, which are associated with Ti, carbon interstitial Ci and carbon vacancy V¬C. For Batch B samples, the VC signal is suppressed to below the detection limit and the Ci concentration is enhanced. The suppression of carbon vacancy is due to creation of excessive carbon at the oxide/SiC interface during the oxidation2 and the subsequent diffusion into the SiC; and the reduction of thermal equilibrium generation of VC3 at the very high temperature of 1950 oC. The excessive carbon creation is evidenced by the enhancement of the Ci DLTS signal. The two batches of samples have similar parameter of barrier height Φ (1.22 eV and 1.26 eV for A and B respectively), ideality factor n (1.12 and 1.07), Ron (8.06 cm2 and 8.43 cm2) and Von (0.80 eV and 0.92 eV). However, the reverse biased leakage current of the Batch B sample is significantly lower than that of Batch A, having values of 1.6 mAcm-2 and 0.05 mAcm-2 at the bias of -1200 V for A and B respectively1. The post-Al-implantation annealing of Batch B has the reverse biased current >30 times reduced comparing to the process A1. Figure 2 shows the Ln(J/E) against E1/2 of the leakage current J and the electric field E for the Batch A sample. The leakage current data is well described by Poole-Frenkel (PF) emission current associated with carrier emission from the defect trap in the band gap to the conduction band1 : J=KE exp⁡{-q(Φ_T-√(qE/πε_s ε_0 )/kT)} where K is a constant dependent on the carrier concentration and Φ_T is the ionization energy of the trap. Fitting the equation to the data yields the fitted value Φ_T=0.65 eV1, which is very close to that of the carbon vacancy obtained by DLTS (=0.66-0.70 eV). This implies that the leakage current of the Batch A sample is dominated by the PF emission from the carbon vacancy to the conduction band. The suppression in the leakage current of Batch B sample is associated with the removal of carbon vacancy, which is the dominant origin of the leakage current 1,4.

ABSTRACT. 4H-SiC shows great prospects in power devices due to its high electric breakdown strength, high bulk carrier mobility, high-temperature stability and high thermal conductivity. However, due to the technical challenges in the fabrication process, high cost of 4H-SiC power devices hinders their widespread application. Therefore, porosified 4H-SiC substrates are targeted for epitaxial growth for reducing the defect density in the epitaxy layer [1]. Even more, this technology promises the optimization of power device fabrication processes on cost-efficient, engineered substrates [2]. Besides the application in power electronics, porosified SiC has extensive applications in catalysis, sensors and MEMS [3, 4]. Photoelectrochemical etching (PECE) can effectively porosify 4H-SiC from both Si-face and C-face, and the degree of porosity into the bulk is well controllable for specific application, for instance rugate mirrors [4]. The PECE from the C-face of 4H-SiC wafers leads to columnar pores along the [0001] direction (Fig.1a). Pore diameters have been discovered to be related to the applied voltage, hydrofluoric acid (HF) concentration, etching depth and diffusion coefficients [5-6]. However, it is still not possible to precisely control the diameter profile along the columnar pores. From the crystalline structure of 4H-SiC, the columnar pores along [0001] direction should mostly expose {10-10} (Fig.1b) and {11-20} (Fig.1c) crystal planes, or some other high-index crystal planes which are composed of the {10-10} and {11-20} in a different ratio. To precisely adjust the pore diameter, the etching rates on the {10-10} and {11-20} crystal planes need to be tailored, which can be enabled by modifying the surface passivation of the specific crystal plane. Doing so, an in-depth understanding of the surface chemistry of the {10-10} and {11-20} crystal planes during PECE process in an HF electrolyte is necessary. Recently, density functional theory (DFT) calculations have successfully revealed the mechanism of platinum-assisted HF etching of SiC [7]. In our PECE of 4H-SiC from the C-face [4-6], the pore walls of the columnar pores are newly created during the etching process and they are immediately passivated in the HF electrolyte containing HF and H2O molecules as well as F− and HF2− ions. In this work, the adsorption and reaction of the molecules and ions on the 4H-SiC {10-10} and {11-20} surfaces will be simulated by DFT. Fig. 2 shows one single HF or H2O molecule adsorbed on the 4H-SiC {10-10} or {11-20} surface, whose adsorption energies (Eads) are listed in Table I. On both 4H-SiC {10-10} and {11-20}, HF can be dissociatively adsorbed with F bonding to Si and H to C with high Eads value of −4.08 and −3.55 eV, respectively. The presence of Si-F and C-H bonds have also been experimentally demonstrated by infrared spectroscopy of the porous 4H-SiC after PECE [5]. Water is molecularly adsorbed with Eads of −0.93 eV on {10-10} surface, while it also dissociates on {11-20} surface with Eads of −2.66 eV, forming Si-OH and C-H. Considering the high affinity of Si to F, the surfaces should be terminated by F at the Si sites and by H at the C sites, with a moderate probability of Si to be terminated with OH groups. These surface terminations stabilize the newly created pore walls. However, to describe the passivation in more detail, simulations of subsequent reaction paths of the terminated surfaces in the HF electrolyte must be performed, in which the effect of the applied voltage during PECE process on the pore walls needs to be included.

ABSTRACT. To date, we have achieved a reduction of the expansion of single Shockely staking faults (SSSFs) by proton implantation in 4H-SiC epitaxial layers, and this technology was named as a Stacking Fault Knockdown by High Energy Ion Implantation (SF-KHII) method. However, defect generation due to proton implantation is unavoidable in the epitaxial layers, and the generated defects may have side effects on device performance. Thus, in this study, we implanted protons into a 4H-SiC substrate and performed epitaxial growth. Subsequently, we fabricated PiN diodes and performed electrical stress tests to observe the suppressive effects of proton implantation into the substrate on the SSSF expansion.

ABSTRACT. Oxidation of 4H-SiC is an instrumental part in processing of SiC devices. Within this work, an extensive experimental study was conducted to help develop a comprehensive TCAD process simulation model for oxidation of 4H-SiC. This model captures three key aspects of thermal oxidation: the oxidation rate, the oxide shape, and the injection of carbon interstitials.

ABSTRACT. Various edge termination structures have been designed to suppress electric field crowding in high-voltage SiC power devices. Field limiting rings (FLR) and junction termination extension (JTE) are the most representative edge termination structures. FLR requires a precise patterning process to implement narrow ring spacing. The JTE structure has good termination efficiency and transfers potential through double-sided depletion over a wide area, the role of precise patterning process is less important. However, in the case of single-zone (SZ)-JTE, the breakdown voltage (BV) changes rapidly depending on the JTE doses, so a lot of structures including ring-assisted (RA)-JTE, multi-zone (MZ)-JTE are used for edge termination of high voltage SiC devices [1-2]. To design a JTE structure stable to process deviations, we designed 3.3 kV SiC PiN diodes with different JTE structures.Fig. 1 shows 3.3 kV SiC PiN diodes with (a) SZ-JTE, (b) RA-JTE, (c) step-JTE (S-JTE), and (d) SRA-JTE. WJTE is 100 µm for SZ-JTE and RA-JTE. WJTE1 and WJTE2 for S-JTE and SRA-JTE are 70 µm and 30 µm respectively. Based on the combination of P+, P-base, and deep P layers, each region of the SRA-JTE is labeled layer 1, layer 2, and layer 3. Layout and doping profile of SRA-JTE is shown in Fig. 2. Fig. 3 shows the BV simulation results for the four structures. As expected, SZ-JTE is the most sensitive to the Pbase dose. For RA-JTE, high concentration of P+ rings distribute the electric field therefore shows high BVs at the dose of P-base is low. In contrast, S-JTE exhibits a low BVs almost like SZ-JTE under the condition of P-base doses are low, but it shows high BVs at high P-base doses. This is because layer 3 does not include deep P, resulting in a layer with a lower effective dose compared to layer 1 and layer 2. We observed that SRA-JTE has a high BVs at both low and high P-base doses, and then we fabricated 3.3 kV SiC PiN diodes with SRA-JTE on 6-inch wafers, which showed the best performance.Design specifications of each wafer are shown in Table I. The fabricated diodes were measured for forward and reverse characteristics under on-wafer state using an auto probe equipment. Fig. 5 shows the forward characteristic for each wafer. The voltage value at an anode current density of 100 A/cm2 is defined as the forward voltage drop (VF). The VF of each wafer is 5.24, 3.97, 3.86, and 3.81 V. The lower concentration of P-base decreases the amount of holes injection from the anode to drift layer, which increases the VF. Fig. 6 is a reverse characteristic of each wafer. We defined the BV as the voltage when the reverse current is 10 µA. The BV of each wafer is 3.98, 4.01, 4.10, and 3.58 kV, which shows that it is possible to achieve a stable BV of more than 3.3 kV in a wide range of P-base doses. Most notably, we determine the optimal total P-base dose condition is 4.0 × 1012 cm−2 with relatively low forward voltage and high BV on wafer 3. In this paper, we designed 3.3 kV class SiC PiN diodes with SZ-JTE, RA-JTE, S-JTE, and SRA-JTE through simulation to design a JTE structure which is robust to process deviation. We extracted the BVs as a function of P-base layer dose for each structure and fabricated PiN diodes with SRA-JTE. As the dose of P-base increases, hole injection increases and the value of VF is decreased. The BV was then extracted through reverse measurement and found to be very similar to the simulated value. From the above measurements, it was found that the 3.3 kV SiC PiN diode with SRA-JTE has a VF value of 3.86 V and a BV of 4.1 kV under the condition of P-base dose is 4.0 × 1012 cm−2.

ABSTRACT. Silicon carbide (SiC), a critical semiconductor material for advanced power devices, requires efficient and damage-free dicing methods to maintain its high performance and reliability. Conventional dicing techniques, such as ultrasonic blade dicing and dry laser dicing, often induce mechanical or thermal stresses that lead to detrimental cracks and dislocations, such as basal plane dislocations (BPDs), which are serious defects in SiC power devices. The method we have developed, water-jet guided laser (WGL) processing, offers a promising alternative. Using a fine water jet as a waveguide for the pulsed laser, WGL processing ablates the SiC wafer while simultaneously cooling it, thereby preventing mechanical stress and reducing the incidence of cracks and BPDs near the dice edges. Previous studies have shown significant reductions in BPDs and chipping with WGL compared to traditional methods, despite the presence of asymmetric dark and light contrasts in X-ray topography (XRT). This study advances our understanding of WGL processing by investigating these XRT contrasts through bi-directional XRT and energy dispersive X-ray (EDX) analysis of processed grooves. The observed asymmetric contrasts along the groove were due to the direction of X-ray incidence. In addition, our results show that the light contrasts observed along the grooves are primarily due to oxidation that occurs during the laser ablation process. Overall, WGL processing demonstrates a capability for BPD-free dicing of SiC wafers, providing a method that minimizes damage while maintaining wafer integrity. Future work will focus on optimizing processing parameters to improve damage prevention and processing efficiency. This process holds great promise for improving the manufacture of high performance SiC-based devices.

ABSTRACT. Abstract: Heavily p-type doped (P+) implants are commonly used to achieve low specific contact resistance (SCR) for p-body diodes through a costly ion implantation process. Alternatively, our study proposes a single-step plasma treatment method using BCl3 plasma. This method incorporated a high concentration of self-activated p-type boron dopants in the SiC lattice with minimal damage. Experimental I-V data from Schottky Barrier Diodes (SBDs), combined with TCAD simulation, demonstrated that approximately 40% of boron atoms were activated in the SiC lattice (at a depth of 30-40 nm) without the need for high temperature ion implant activation. Our approach using plasma treatment realizes an SCR value (ρc) of ~ 5.6×10-5 Ω∙cm2, which is approximately 1 order of magnitude lower than that of untreated samples. Introduction: Variations caused by a rapid change in drain-source voltage (dVds/dt) can influence the electrical potential within the p-body region during transistor switching [1]. Several factors contribute to such influence: (i) Increased output capacitance charge due to higher doping concentrations in the drift layers, leading to a high displacement current during switching; (ii) Low hole mobility of SiC from the high sheet resistance of the p-body region [2]; and (iii) High SCR in the p-body ohmic contact [3-4]. P+ implantation plays a critical role in enhancing carrier injection and hole tunneling at the MS interface, despite its high cost and unwanted defects [6]. Plasma doping offers a promising method for incorporating dopants into the SiC lattice with minimal crystal damage at lower temperatures [5]. This study investigates the effectiveness of a single-step BCl3 plasma treatment for self-activated p-type boron dopant incorporation into SiC. This method to form ohmic contacts at the p-body could facilitate higher switching speeds and minimize switching losses in SiC MOSFETs. Results and Discussion: First, a 1 μm-thick p-type epitaxial (p-epi) SiC layer with an aluminum doping of 1017 cm-3 on an n-type SiC substrate was used. This substrate was chosen to emulate the p-body region of the SiC MOSFET. The samples were wet cleaned and treated with different BCl3 plasma conditions for further analysis. Boron concentration more than 1020 cm-3 was observed near the surface with enhanced concentration up to a depth of 30-40 nm over the untreated sample, as shown in the secondary ion mass spectrometry (SIMS) profile in Fig. 1 (a). In Fig. 1 (b), X-ray Photoelectric Spectroscopy (XPS) spectra revealed a notable presence of boron atoms on the surface of the treated samples, with the boron 1s peak detected at 180-189 eV. Previous studies have established that BCl3 plasma has the capability to etch SiC [8]. Therefore, we optimized our treatment process to minimize surface etching with a minimal etching depth less than 5 nm, as evidenced in transmission electron microscopy (TEM) images in Fig. 1 (c). We further conducted atomic force microscopy (AFM) to examine the surface roughness after plasma treatment, showing low roughness values Ra of < 3 nm, as depicted in Fig. 1 (d). It is noteworthy that prior research has addressed how minor surface etching and low Ra values are unlikely to substantially affect the quality of ohmic contact [5]. The self-activation of boron atoms after BCl3 plasma treatment was investigated using Schottky Barrier Diodes (SBDs). The diodes were fabricated on commercial n-epi wafers with a nitrogen doping of (1016 cm-3) as shown in Fig. 2 (a). Electrical measurements conducted on the SBDs revealed a substantial increase in the knee voltage (Vknee) by +1.5 V for treated samples, as depicted in Fig. 2 (b). This indicates self-activation of the boron atoms during the plasma treatment process. Simulations in Sentaurus TCAD estimated that approximately ~ 40% of the boron dopants were activated, consistent with experimental observation of the increased Vknee after plasma treatment, as demonstrated in Fig. 2 (c). Circular Transmission Line Method (CTLM) structures were fabricated with a Ti-based metal stack (Ti/Al/Ni) on the p-SiC as shown in Fig. 3 (a) for SCR extraction. Ohmic I-V behaviour was observed on CTLM structures from different gap spacings of 20-100 μm after post metal deposition annealing (PMDA) at 950 °C as shown in Fig. 3 (b-e). The SCR of treated samples exhibits 1 order of magnitude reduction from 10-4 Ω∙cm2 (untreated) to 5.6×10-5 Ω∙cm2 (treated). Note that SCR values were obtained from three sets of CTLM structures. This reported SCR value is relatively low for moderately doped p-SiC (1017 cm-3) as benchmarked with other studies on highly doped substrates (> 1019 cm-3) as illustrated in Fig. 4. TEM-EDX colour mappings in Fig. 5 (a-j), revealed intermetallic diffusion of Al into the SiC and the formation of Ti3SiC2 layers after PMDA. Boron atoms were observed in the SiC lattice and out diffusion to the surface after PMDA. Conclusion: We experimentally demonstrated a BCl3 plasma treatment method that incorporated activated boron dopant atoms (~ 40%) in a single step at low temperatures (< 200 °C). This high concentration of boron atoms facilitated high carrier injection at the MS interface which forms favourable ohmic contacts reducing the SCR by almost 1 order of magnitude to ρc 5.6×10-5 Ω∙cm2. The SCR value obtained was relatively low for mildly doped p-SiC when benchmarked with highly doped p-type substrates. This novel single step plasma treatment allows reduction of SCR at the source region in p-SiC. Acknowledgement: This work was supported by A*STAR (Agency for Science, Technology and Research Singapore), under Grant No. A20H9A0242.

ABSTRACT. When prospecting the performances of any emerging semiconductor, Schottky barrier diodes (SBDs) are the devices which lead the way in technical advancements, also being important from a commercial and scientific standpoint [1]. In the domain of UV detection, despite silicon carbide’s (SiC) indirect bandgap, relevant devices such as blue LEDs, UV photodiodes and high temperature rectifiers have become established [2]. SiC’s intrinsic carrier concentration is lower than silicon by a factor of 1018, which should result in a much lower dark current. However, because of the high concentration of defects in SiC substrate, anomalously high dark current values were reported [3]. In this study, we fabricated and tested the performances of SiC SBD structures as UV detectors, using Indium–tin-oxide (ITO) as gate electrode (Schottky contact). Prior to fabrication, the ITO film (200 nm) was deposited on a SiC substrate and annealed at different temperatures ranging between 200 - 1000°C. The resulting films were compared with a commercial one, in terms of crystalline structure, using X-ray diffraction techniques (Fig. 1). The XRD pattern of the commercial ITO presents a set of diffraction peaks at 2θ = 21.5°, 30.6°, 35.5°, 37.8°, 39.9°, 41.9°, 45.7°, 51.1°, 56.1°. In the case of the as-deposited sample (ITO/SiC), without any post-thermal treatment, no diffraction peaks were observed. Only a broad band was evinced, indicating the amorphous structure of the sample. After post-thermal treatments, the crystalline structure of the samples is evidenced by the presence of the characteristic ITO diffraction peaks. No other diffraction peaks were identified by XRD, either from impurities or secondary compounds, such as silicides. It can be observed that the position of the diffraction peaks is not affected by the annealing temperature, which clearly indicates that the lattice constant of ITO remains unchanged. The same experiments were performed on quartz substrates, aiming to obtain better performances in terms of transparency. The optical transmission of the resulted films was measured, at room temperature, in the 200 – 700 nm wavelength range, using an Agilent Cary 5000 spectrophotometer. The spectral resolution was 1 nm and the recorded spectra were corrected by subtracting the absorption of the substrate. The results are shown in Fig. 2. After annealing, the optical transparency of the films was significantly increased over the entire domain (200 – 700 nm). The transmission spectra show fringes due to optical interference, which also confirms the homogeneity of the deposited ITO layers. All films have a high optical transparency, above 70 % in the visible domain, but the optimal effectiveness range includes the UV region: 250 – 360 nm. At those wavelengths, thin films of ITO behave differently depending on thermal annealing temperatures. The responsivity of the SiC photodiode has a maximum at ~ 280 nm [4], where the associated transmission of the film reaches the value of 5 % for the sample annealed at 400°C (ITO400), 5 times higher compared to the one sintered at 600°C (ITO600). At 300 nm, the transmission of the ITO400 film increases up to 27% and is 2 times higher compared to ITO600. At 360 nm, the highest value of the transmission for the ITO film (~ 80%) is obtained at, also for ITO400. These results demonstrate the potential of the ITO400 film to be used as a transparent gate electrode in UV photodetectors based on SiC. This best performing annealing process was used to obtain SBDs. The devices were fabricated starting from an n-type SiC wafer with and epitaxial layer having a doping concentration around 1016 cm-3. The ohmic contact was obtained by a sputtering deposition of Ni (100 nm) followed by a high temperature annealing at 1050°C, for 3 min, in Ar atmosphere. The test structures were electrical characterized at two different wavelengths from UV domain: 368 and 396 nm (Fig. 3) using two different power densities. The photocurrent is increasing by almost three order of magnitude at 368 nm, for a power density of 10 mA/cm2 and it is inversely proportional with the wavelength. A slight increase with power density is also observable. Further details regarding the performances of the fabricated structures will be presented at the conference.

ABSTRACT. Silicon carbide (SiC) is a wide bandgap semiconductor, with superior physical and chemical properties allowing the fabrication of devices able to work at high voltage and high temperature [1]. To further improve devices, the fabrication of 4H-SiC vertical devices includes a grinding step of the substrate backside (C-face) reducing the device ON resistance. This implies a modification of the process flow and of the ohmic contact fabrication [2]. In this case, since the ohmic contact is performed at the end of the process flow, Rapid Thermal Annealing (RTA) cannot be used anymore without affecting the frontside materials. Then, to preserve the materials integrity, Laser Thermal Annealing (LTA) is currently used to achieve the backside ohmic contact. Several investigations were performed to study such contacts formed from titanium (Ti) or nickel (Ni) layers by LTA [3–5]. From the literature, nickel seems the most favorable metal to form highly performant ohmic contact by LTA, with specific contact resistances in the 10-5 Ω.cm2 range. Based on our previous results on titanium and nickel, these contacts reached the ohmicity since they turn into their liquid phase. Therefore, the wetting properties of 4H-SiC C-face may play a major role in the reaction between metal and SiC surface. Generally, researches focused on the ohmic contacts involve a cleaning step with acid mixtures, like the Radio Corporation of America (RCA) sequence. Nevertheless, due to the elaboration of the backside ohmic contact at the end of the device fabrication, those chemical solutions can affect materials deposited on the wafer frontside. As a consequence, either a sacrificial layer has to be deposited on the front face before the cleaning sequence or a new surface treatment, that do not affect wafer frontside, has to be performed before the metal deposition. In this study, we investigated the effect of the SiC wafer back-sputtering before the nickel deposition. To do so, after a simple solvent cleaning of the C-face with acetone, an in-situ argon (Ar) plasma was generated in the chamber of the sputtering equipment to treat the sample surface. The chamber pressure was 17 mTorr and the RF power was 100 W. This 4H-SiC surface treatment consumes some atomic layers. The removal rate was estimated around 26 nm.hr-1 by measuring a step with an Atomic Force Microscope (AFM). Consecutively to this Ar plasma treatment, a 100 nm-thick nickel layer was deposited on the SiC. Finally, samples were irradiated with a tripled frequency YAG laser (355 nm) at a fluence of 5 J.cm-2. The irradiations were performed at 30 kHz with a scanning speed of 800 mm.s-1. The Figure 1 shows AFM characterizations of the 4H-SiC surface after different Ar plasma treatments. For the shortest duration of 1 min, the scratches present at the surface due to the polishing stage are clearly visible. Those scratches seem to be softened after 10 min treatment. From 20 min to 60 min, the 4H SiC surface morphology presents grains. Despite of the morphology modifications, whatever was the treatment duration, the roughness was always found lower than 1 nm. The Figure 2 presents Scanning Electron Microscope (SEM) images of contacts annealed at 5 J.cm 2 for several surface treatments. The surface morphology evolves with the back-sputtering duration. Without any surface treatment, the contact surface seems homogeneous, fully covering the SiC surface. However, a lot of nanoparticles are fully covering the contact after the irradiation (not visible at the magnification presented here). For the shortest back-sputtering treatments, the nickel reacts with SiC by forming uncontinuous contact at the pulse center, surrounded by almost uncovered SiC, itself encircled by thick Ni-rich structures. For a 20 min treatment, the gap between the irradiations is partially filled, suggesting a higher wetting of the liquid nickel onto the SiC. After 60 min of Ar plasma treatment, the contact morphology is quite regular, especially at the pulse center and the nanoparticles density, covering the contact, is massively reduced compared to other conditions. In this case, the higher effective contact surface should be beneficial to reach better electrical performance and contact reliability. According to those observations, it seems that the wetting properties of the SiC evolves with the Ar plasma treatment, affecting the reaction of the liquid Ni during the laser irradiation. This modification could be more likely related to the SiC surface morphology evolution. Finally, electrical and structural characterizations will be compared to highlight the influence of the Ar plasma treatment on the contact electrical performance and its phase composition.

ABSTRACT. Replacing SiO2 by dielectrics with higher dielectric constant offers advantages for Silicon Carbide power devices. In this paper, MOS capacitors with dielectric stacks of 2-45 nm SiO2 and 30 nm atomic layer deposited ZrO2 or HfO2 were examined. This study demonstrates that the electrical failure of the SiO2 film initiates the breakdown in SiO2/high-k stacks. With thicker SiO2 the Fowler-Nordheim mechanism dominates the carrier conduction enabling low leakage current and high electric breakdown field, even at temperatures up to 200°C. Stacks with thinner SiO2, on the other hand, show a higher k-value. Ultimately, we show that 6 nm of interfacial SiO2 below 30 nm of crystalline ZrO2 reduces the hysteresis by 50% while maintaining a high dielectric constant of 13 and providing a high breakdown field (6.7 MV/cm) as well as low leakage current (6.6 x 10-9 A/cm2).

ABSTRACT. In the recent years, the possibility to use the internal body-diode of the 4H-SiC power MOSFET is rising the scientific community attention, due to the possibility to implement simplified topologies in the final application [1,2]. In this context, although 4H-SiC MOSFETs can satisfy the mission profile requirements even in the presence of crystalline defects (i.e. carrot-like or prismatic stacking fault), understanding how the device properties are impacted by these defects is mandatory to probe the robustness of the body-diode under operative conditions [3]. In fact, such crystalline defects have been investigated on epitaxial material and/or in p-i-n junctions [4]; to date there is not enough investigation on implanted materials or complex MOSFET structures. This point is a fundamental aspect deserving attention to comprehend the device behavior in the presence of carrot-like defects. In this paper, the intrinsic electronic structure of a carrot-like defect and its impact on the properties of 4H-SiC MOSFETs are investigated by means of temperature dependent electric measurements, photoluminescence spectra and Kelvin Probe Force Microscopy. In this experiment, 650 V class 4H-SiC Power MOSFETs were used. The devices were fabricated on n-type (0001) 4H-SiC substrates, 150 mm in diameter and 350 μm thick, having a resistivity in the range of 0.012-0.025 Ω cm. An epitaxial layer of 6 μm thick with a doping concentration of about 1 × 1016 cm-3 was used. Overlapping the wafer-level maps obtained by optical inspection with the final device mask set, two different families of MOSFETs were selected and investigated with and without a carrot-like defect. After the electrical characterization, the MOSFETs were completely de-layered to expose the 4H-SiC bare surface with no metal and no insulators on top [5,6]. Fig. 1 shows the electrical characterization performed on the body-diode of the 4H-SiC power MOSFET with (in red) and without (shades of blue) a carrot-like defect. In particular, Figs. 1a and 1b show the body diode forward characterization in two different current range, i.e., the 1 A and 50 A ranges, respectively. It can be noticed that the MOSFET with the carrot shows a lower turn-on voltage (Fig. 1a) and a larger series resistance (Fig. 1b) compared to the MOSFET without the carrot defect. On the other hand, Fig. 1c shows the temperature-dependent characterization of the reverse biased body-diode of the MOSFET with and without a carrot-like defect. It can be noticed that the avalanche breakdown of the diode occurs at about 900 V, independent of the presence of defect, thus indicating that the body-diode robustness is not affected by the presence of such kind of crystalline defects. However, at low VDS values the current level in the MOSFET with the carrot is larger than in the MOSFET without the carrot keeping the current below 10 µA at VDS = 600 V. Hence, keeping such low leakage current values, both devices can pass the screening process according to the limits of the accepted protocols (JEDEC). Interestingly, at VDS = 600 V the current values measured between 25 °C and 150 °C show a weak temperature dependence for the MOSFET with the carrot while the MOSFET without a carrot-like defect show a current variation of more than a factor ten. This behavior can be qualitatively explained by an altered diffusion and generation/recombination current between the two conditions. In fact, qualitatively the body-diode current is a function of the semiconductor intrinsic carrier concentration ni which is exponentially related to 1/EG and the lower is the semiconductor band gap, the larger is the ni with a weak temperature dependence. In order to elucidate this macroscopic behavior, nanoscale Kelvin Probe Force Microscopy (KPFM) was performed onto the de-layered surface of the MOSFET. Fig. 2a shows the surface morphology acquired across the JFET/body region and the carrot appears as a depression on the surface. Fig. 2b shows the surface potential measured by KPFM on the carrot-like defect. As can be noticed in Fig. 2c, a surface potential variation of 90 mV is measured with respect of the surrounding JFET region. This indicates that the distance between the vacuum level and the Fermi level in the carrot is 90 mV larger than in the n-type semiconductor of the JFET. Hence, in the crystalline defect the Fermi level lays 90 mV below the surrounding 4H-SiC ideal material. Finally, the physical nature of the carrot-like defect was investigated on the delayered MOSFET by photo-luminesce (PL) under a 355 nm laser-diode stimulation at room temperature. The PL spectra were collected in the reference region far from the crystalline defect (Fig. 3a) and focusing the laser onto the carrot defect (Fig.3b). As can be seen in Fig. 3c, the spectra were normalized to the SiC perfect PL signal at 3.18 eV. In the region between 2.2 and 2.8 eV a there is a wide band typically observed in 4H-SiC subjected at ion implantation (either for the body and source regions formation). The spectrum collected onto the carrot exhibits a reduction in this band also called donor-acceptor band edge [7] and the PL carrot signals raised with the appearance of a peak between 2.5 and 2.6 eV. This peak may correspond to a double Schockley Stacking Fault (2 SSF) or alternatively to an inclusion of 3C-SiC inside the 4H-SiC crystal. The whole characterization can be summarized looking at Fig.3d, where the carrot-like defect is described with a semiconductor with a shrunk band-gap tending to gather positive charges enhancing the carrier recombination with a (quasi) Fermi level (in red) positioned below the (quasi) Fermi level of the 4H-SiC. The results provide a better understanding of the impact of the carrot-like defect incorporated in the 4H-SiC and can be particularly useful for MOSFET technology, qualification screening and reliability. [1] M. Kang, et al; 2019 IEEE 7th WiPDA [2] A. Fayyaz, G. Romano, A. Castellazzi, Microelectronics Reliability, vol. 64, pp. 530-534, 2016. [3] B. Carbone et al; IEEE IRPS (2023) [4] S. Asada et al; IEEE Trans Electr Dev., 68, 3468 (2021) [5] P. Fiorenza, et al; Nanotechnology 31 (2020) 125203 [6] P. Fiorenza, et al; IEEE IRPS (2021) [7] I.G. Ivanov, et al PHYSICAL REVIEW B 67, 165211 (2003)

Fig. 1. ID-VDS with and without a carrot-like defect, in high (a) and low (b) current range. Temperature dependent reverse bias (c) and a current level comparison at VDS = 600 V (d). Fig.2. AFM (a) and KPFM (b) surface potential across the carrot. (c) Surface potential variation across the carrot.

Fig. 3. (a) Reference and (b) defect regions where the (c) PL spectra are collected. (d) Schematic representation of the band diagram across the defect.

ABSTRACT. Extensive experiments and simulations indicate that single-event effects (SEE) can trigger a second breakdown in 4H-SiC vertical power devices prior to reaching avalanche breakdown [1,2]. This second breakdown has been linked to ion-induced mesoplasma formation, proving catastrophic and inevitably resulting in thermal termination [2,3]. However, SEE effects in 4H-SiC lateral power devices have hardly been investigated. Due to differences in the electric field profiles between lateral and vertical power devices, SEEs in lateral devices may exhibit unique characteristics. In this study, we assess the robustness of 1.2kV 4H-SiC lateral RESURF power MOSFET and explore the SEEs originating from different heavy ion strike locations. The target 4H-SiC lateral power MOSFET, optimized for 1.2kV, incorporates RESURF layer and field plate designs [4], as shown in Fig.1. An N-type RESURF region, featuring a dose of 5e12 cm-2 and a thickness of 0.5µm, is implemented between the channel and the drain to support the blocking voltage. The RESURF dose is matched with the p-type epitaxial region, which has a doping concentration of 5e15 cm-3 and a thickness of 10µm. The pitch and width of the device are set to 31µm. SEEs from various strike locations, labeled in Fig. 1(a), are simulated electrothermally using a 3D TCAD device simulator (Sentaurus) with the best 4H-SiC material parameters and previously reported silver ion model in 4H-SiC (LET=46.1MeV-cm2/mg) [5,6]. To accurately capture the effects from heavy ion, a refined mesh along the ion path is generated (Fig. 1(b)). Electrode contacts are set to 300K as the thermal boundary condition Failure is identified when the peak local lattice temperature exceeds 3000K, the decomposition temperature of 4H-SiC. The simulated results of different strike cases are summarized in Table. I. Device survives vertical (+y) strikes at the source, gate channel, and middle portion of the drift (RESURF) region — areas typically susceptible to vertical heavy ion strikes in vertical device, at full blocking voltage with minimum heating. Notably, mesoplasma shifted away from the ion path to drain terminal (Fig. 2) in the cases of the vertical (+y) and lateral (+z) strikes at the drift region. This is likely because of the lateral electric field in the drift region. Furthermore, a lateral strike along +z direction at full blocking voltage is performed in the drain-side RESURF region. Similarly, there is no significant heating. Remarkably, substantial voltage drops across the heavy ion paths are absent in all previously mentioned strikes. Failure occurs in both vertical (+y) and lateral (-x) strikes at the drain, indicating that the drain of this device is vulnerable to heavy ion strikes. Interestingly, failure does not occur in the case of drain vertical (+y) at full blocking voltage if the p-body contact is floated (Fig. 3(a)). However, the floated body contact has minimal effect against lateral (-x) drain strike (Fig. 3(b)). It can be observed from these results that worst SEE takes place when most voltage drop is across the ion path. As shown in the electrostatic potential contours in Fig. 3(a), floating the body contact reduces effective voltage drop across the vertical ion path to about half the blocking voltage while having no effect on the lateral voltage drop along the lateral ion path. We evaluate and analyze the SEEs from various heavy ion strike directions and locations in 1.2kV lateral RESURF power MOSFET, yielding new insights into the failure mechanisms and SEB voltage optimization. [1] C. Martinella et al., Microelectronics Reliability, vol. 128, 2022. [2] J.A. McPherson et al., IEEE Trans. Nucl. Sci., vol. 68, no. 5, pp. 651-658, 2021. [3] J.A. McPherson et al., Mater. Sci. Forum, vol. 1004, pp. 889–896, 2020. [4] S. Banerjee et al., IEEE Elec. Device Letters, vol. 22, no. 5, pp. 209-211, 2001. [5] P.J. Kowal et al., Proc. ANS RPSD 2018, American Nucl. Society, 2018. [6] J.A. McPherson et al., IEEE Trans. Nucl. Sci., vol. 66, no. 1, pp. 474-481, 2019.

ABSTRACT. The 1.2 kV SiC MOSFETs have a large Miller plateau (Qgd) and Crss due to the wide overlap of gate and drain. To reduce the value of Qgd and Crss, SiC dummy Gate MOSFETs are suggested by controlling the depletion region on the JFET under the dummy gate to decrease Cdep, which is formed in series with Cox that affects Crss. In order to enhance the switching characteristics, we substitute the dummy gate with SBD. This allows the Crss to be reduced by creating a large depletion region in the JFET region, resulting in lower MOSFET turn-off losses. Also, the SBDs have a lower forward voltage drop than P-N diodes, the ultra fast reverse recovery characteristics of 1.2 kV SiC MOSFETs employing embedded SBDs adjacent surface of JFET regions can be achieved [3]. In this paper, the 1.2 kV MOSFETs using internal SBD integration on the JFET region are suggested to improve switching characteristics by reducing Crss. To reduce cell-pitch, we applied short N-source and ladder type structure. We used Ni as a Schottky metal which work function is 5.15 eV. And the static and dynamic characteristics were investigated by using TCAD simulation compared with 1.2 kV dummy gate structure. The half-cell of the structures used in the study are illustrated in Fig.1, and the specifications show in Table 1. The difference of depletion of region of structure (a) and (b) was investigated when VDS = 20 V and VGS = 18 V and the result shows in Fig.2. Through this, the structure (a) has much larger depletion region than structure (b). Because, a lot of charges in the Schottky metal affect the expansion of the depletion region when reverse bias is applied at the SBD. The static characteristics, such as Ron.sp, Vth and BV (breakdown voltage) are investigated and the results show in Table Ⅱ. It is confirmed that the structure (b) has large Ron.sp than structure (a) due to the reduced JFET region due to the wide depletion region. The diode characteristics about the structures shown in Fig.3. The structure (b) exhibits a lower forward voltage drop than structure (a) due to the operation of the integration SBDs at the reverse mode. Moreover, the WSchottky is wider, which results in a reduced forward voltage drop due to the expansion of Schottky region. To confirm the Qgd, we extracted the gate charge and the results are shown in Fig. 4. The structure (a) exhibits a wider Miller plateau than structure (b), which is attributed to the larger depletion capacitance. It was extracted that the Qgd of structure (a) is 0.27 nC, while structures (b) with WSchottky = 1.0 μm, 1.2 μm, and 1.4 μm have Qgd values of 0.173 nC, 0.162 nC, and 1.58 nC, respectively. We also conducted DPT about the structure (a) and (b) to investigate the turn-on characteristics and turn-off characteristics of the MOSFETs and the results show in Fig.5 and Fig.6. As illustrated in Fig. 5, the peak current of structure (b) is observed to be lower than that of structure (a), which can be attributed to the embedded SBD on the JFET region. It is demonstrated that the structure (a) has a large rising time of VDS than structure (b) due to the large Qgd. Through these results, it is confirmed that the SiC MOSFET using internal integration have superior switching characteristics, with a BV exceeding 1.2 kV.

ABSTRACT. SiC substrate is a key enabler for high voltage and high current technology. Most of the SiC commercial devices use a planar-gate design on multiples nodes. To continue the shrinkage and enabling better performances, the trench-gate architecture (typically used in Silicon IGBT technology) is becoming a preferred choice by semiconductor manufacturers. One of the main usages of SiC power technology is for Automotive purpose: In this paper we demonstrate 3DSEM capabilities to monitor the SiC trench etch process enabling exceptionally reliable devices. The electrical characteristics of SiC MOSFET fabricated on trench side wall, relay on the quality of the trench morphology. 3DSEM using a tilted electron beam, offers a high-resolution imaging of the trench sidewall. It is used to measure trench depth, sidewall angle, and bottom roughness. This capability is complementary to top view CDSEM, it is not destructive, and it offers larger statistical measurement sample across wafer in a relatively short time, compared with any other destructive method.

ABSTRACT. Thermal impedance is critical for the performance of SiC MOSFETs, yet standard methods such as the one-dimensional transient thermal impedance measurement (JESD51-14) face challenges with these devices. Commonly, the forward voltage drop across the intrinsic body diode is used as a temperature-sensitive parameter (TSP) for measurements. However, in SiC MOSFETs, issues like threshold voltage instability and MOS-channel leakage currents at zero gate-source voltage lead to inaccuracies. This study examines various SiC MOSFETs, investigating how gate-source voltage affects TSP and exploring the impact of threshold voltage variations and channel architecture on leakage and measurement reproducibility. Findings indicate that TSP stabilizes and measurement reproducibility improves at lower gate-source voltages, suggesting that minimizing channel leakage can significantly enhance the reliability of thermal impedance measurements. The research aims to refine thermal impedance measurement methods for better performance and reliability of SiC power semiconductors.

ABSTRACT. The cubic polytype of SiC has been presented since a long time as a good candidate for the fabrication of sensors operating in harsh environments. In the past century, pioneering works already argued on the benefit of its mechanical properties for membrane or other suspended structures fabrication [1-2], in part due to development of surface micromachining solutions derived from the silicon technology, and also due to sustained efforts for handling material fabrication. Nowadays, it is worth mentioning that despite a valuable continuous scientific feed on the topic (see [3-5] for instance), the maturation of the SiC use towards MEMS applications remains inconspicuous. Discussion on this statement is out of the scope of this presentation but two major reasons can be highlighted. As for every new technology, successing in requires to progress all fabrication steps, ideally, as a whole. In this regard, the previous decades have seen a huge amount of knowledge created concerning the material elaboration, giving a detailed landscape about the 3C-SiC growth methods, and growth- mechanical- or doping related issues [6,7]. Although, SiC processing have been addressed deeply but with developments oriented towards the hexagonal 4H-SiC polytype, letting efforts on 3C-SiC lagging behind. So, initiating new efforts gathering various laboratory skills for fitting material properties with device finality, is a must for taking advantage of the unique properties of SiC, especially for applications in harsh environments (high temperatures, high gas velocities or in radiative environments…). In this presentation, after reviewing why 3C-SiC remains of lively interest for some MEMS applications, we will present current progresses in our consortium, concerning the use of 3C-SiC for two harsh environments applications: hydrogen gas detection using sensor without sensitive layer and turbulent air flow measurements by thermal approach. At first, the material elaboration (CVD process - CRHEA – Valbonne) will be presented, along with the structural and electrical properties of the different forms of interest (monocrystalline 3C-SiC/Si, textured 3C-SiC/Si, amorphous SiC/Si) (Fig. 1). Subsequently, different suspended SiC test structures have been fabricated for assessing the mechanical properties (GREMAN Tours), with discussion about the interest of textured form and stress management (Fig.2). We will finally present and comment about some ongoing developments (i) on the fabrication of low detection limit and selective 3C-SiC based hydrogen sensor (IMS Bordeaux) (Fig. 3) and (ii) the assessment of double clamped micromachined SiC wire for thermal measurement of gas flow (IEMN Centrale Lille) highlighting thermal properties of SiC wires (Fig. 4). The French National Research Agency (ANR) within the scope of the RESISTE project (grant #ANR-22-PEEL-0002) financially supports the present work.

ABSTRACT. In this digest, the 3rd quadrant operation performance of both 3rd generation (Gen-3) and 4th generation (Gen-4) SiC power MOSFETs, namely the Gen-3 Planar MOSFET, Gen-3 Asymmetrical Trench MOSFET, Gen-4 Symmetrical Double-Trench MOSFET and Gen-4 Trench-Assisted Planar are tested and analyzed in terms of their 3rd quadrant performance.

ABSTRACT. Current hadron colliders use silicon strip and pixel array radiation detectors with high spatial but limited time resolution. These devices also require complex and bulky cooling systems to operate near -30 °C to control radiation damage effects. Next generation collider detectors, now in construction, will incorporate silicon low gain avalanche detectors (Si-LGADs) that offer improved timing resolution but with low spatial resolution. For future colliders, further improvements are required in timing performance, spatial resolution, mass, and radiation resistance. Thus, we are developing 4H-SiC LGADs that, due to material properties outlined in Table I, promise faster timing, lower mass (due to high temperature operation) and potential improved radiation resistance. This research focuses on Priority Research Directions of radiation detectors as marked in the 2019 DOE Basic Research Needs Study [1]. Here, we describe the fabrication and electrical behavior of first-generation 4H-SiC LGAD structures and compare these devices against reference 4H-SiC PiN diodes to observe the presence of gain. The epitaxial stack for the fabricated 4H-SiC LGAD structure is shown in Fig. 1. Minimum Ionizing Particles (MIPs) penetrate the detector, generating electron-hole pairs (EHPs) that are swept out due to the high electric field present in the drift region. Electrons travel towards the n++ substrate and holes towards the p++ contact. Unlike Si LGADs, 4H-SiC LGADs are designed with an n-type gain layer. As holes travel through the thin gain region, they generate further EHPs and induce avalanche. Device fabrication begins with selectively dry etching until the drift region for mesa isolation. The etched sidewall surfaces are passivated with SiO2 through thermal oxidation and PECVD. Low-resistivity ohmic contacts are formed by depositing and annealing a Ti/Ni and Ti/Al metal stack as the cathode and anode, respectively. Additional metal for probing is deposited on the annealed contacts. 4H-SiC PiN diodes with the same epitaxial stack as the LGAD structure, but without the gain layer, were fabricated to quantitatively compare the LGAD structure performance. Devices with a circular anode contact were tested without irradiation. The LGAD structures exhibited a breakdown voltage (BV) of 1160 V (Fig. 2a). Larger leakage currents are observed in the LGAD structures vs. the PiN diodes. This is also visualized as a current “gain” in Fig. 2b, which is calculated as the ratio of ILGAD/IPiN. This gain is expected due to the presence of the gain layer in the LGAD structure. It is important to note that neither device type uses an optimized edge termination strategy. Thus, BV can be increased in the future. C-V characteristics of the LGAD structure in Fig. 2c show full depletion of the gain layer at 77 V (prior to breakdown), which satisfies the requirement of a functioning LGAD. The difference from simulation results are due to deviations from the target doping levels and thicknesses. Gain layer doping of 4.58×1017 cm-3 is estimated. This represents a small deviation from the target level (ND,Gain = 2.84×10^17 cm^-3). Drift layer doping of 3.78×10^14 cm^-3 and 4.80×10^14 cm^-3 was estimated from both the LGAD and PiN diode respectively (Fig. 2d). Overall, these results suggest a high likelihood of 4H-SiC LGAD functionality. In the future, temperature-dependent I-V characteristics will be conducted to confirm avalanche behavior. Moreover, radiation testing will be conducted to assess gain and transient response.

Acknowledgement: DOE Grant #DE-SC0024252 (PM: Helmut Marsiske), NSF (ECCS-1542015)

[1] B. Fleming et al., “Basic Research Needs on High Energy Physics Detector Research & Development,” Dec. 2019. doi: 10.2172/1659761.

Table I. Potential advantages of 4H-SiC compared to silicon.

Fig. 1. Target epitaxial stack of the (a) 4H-SiC LGAD structure and (b) 4H-SiC PiN diode.

Fig. 2. (a) I-V characteristics of a 75 µm pad diameter 4H-SiC LGAD structure and PiN diode under reverse bias. Devices were measured in the dark. (b) Calculated gain (ILGAD/IPiN) of the 4H-SiC LGAD under reverse bias. (c) Experimental and simulated C-V characteristics of a 600 µm pad diameter 4H-SiC LGAD structure and PiN diode under reverse bias. (d) Experimental inverse C-V curves of a 600 µm pad diameter 4H-SiC LGAD structure and PiN diode under reverse bias. Linear fits are used to calculate the gain layer and drift layer net doping levels in the LGAD structure and PiN diode. The inset shows a close up on the the depletion voltage of the gain layer in the LGAD structure.

ABSTRACT. M. Melton1, C. L. Frewin2, Kaustubh Deshpande3, Arjun Ramakrishnan4, S E Saddow1,5 1. Department of Medical Engineering, USF Tampa, Florida USA 2. Crystal Cybernetics LLC., Monroe, Michigan USA 3. Eywa Neuro, Mumbai, India; 4. BSBE, IIT Kanpur, India 5. Department of Electrical Engineering, USF Tampa, Florida USA

E-mail: MMelton3@USF.edu

Background: Conventional implantable neural devices are typically fabricated with materials that are quickly identified by the body as a foreign substance, thus eliciting inflammatory responses [1]. These ongoing acute immunological processes extend into chronic inflammation, leading to glial encapsulation and neuronal loss around the implants and abiotic reactions substantially reducing in the performance of the device [1]. Most of the neural interface community is focused on neuroscience utilizing animal models, where short-term in-vivo functionality and neural tissue damage is not a significant issue. However, for human applications a long-term, reliable, implantable neural interface is extremely important, but remains an urgent challenge due to reported acute inflammatory responses and material failures [1].

Research Hypothesis: A neural implant that is homogeneously constructed from a single, robust material, such as silicon carbide (SiC), would likely improve long-term device performance, as metals and polymers, known to suffer abiotic degradation in-vivo, are not in contact with tissue when implanted. Therefore, only SiC materials, integrated together into a homogeneous system, will be in contact with the harsh environment of the human body, and thus many of the reliability challenges reported in the literature will be eliminated. Our research hypothesis is that a neural interface, constructed solely of SiC without the presence of metals or polymers contacting tissue, will withstand the harsh environment of the human body and allow for long-term, reliable, in-vivo device performance.

Methods: 3C-SiC Devices are fabricated on Si via the hetero-epitaxy of n- and p-type doped epilayers. The n-type layer is doped to around 1E19 cm-3 to form a quasi-metallic conducting mesa what is formed on a p- base layer (doping ~ 1E16 cm-3) thus forming a p-n junction which electrically isolates adjacent conductor traces. The electrode traces are formed using DRIE (deep-reactive ion etching). After forming the electrode traces an amorphous SiC (a-SiC) layer is deposited using PECVD, and subsequently etched using RIE to create openings in the insulator film. Ti/Au is then deposited in an e-beam evaporator to form the bonding pads required for electrical connection of the probes to the recording/stimulation electronics. It should be noted that these metal bond pads are not implanted into tissue, Finally, the Si wafer is removed via backside etching (DRIE) to release the 3C-SiC probes from the Si substrate.

Results: The design of the device packaging has been completed with two variants fabricated to date: A standard PCB board type package, as is the industry standard, and a flexible package that will allow for ease of use and to reduce tissue damage during surgical placement of the all-SiC probes into the brain. Once packaged, the devices will be tested in-vivo in a rodent model.

Supporting Figures: {Image 1} Background: Si MEA material defects (in-vivo): Corrosion of platinum electrode tips. Parylene insulation cracking and delamination led to substantial tissue encapsulation. [2].

{Image 2} Research Hypothesis: (left) Mouse CNS tissue response to Si and 3C-SiC implants [3]. Biocompatability (middle) and Dynamic hemocompatibility (right) histograms based on ISO10993 standard testing. 3C-SiC and a-SiC are highly compatible with cells/platelets thus motivating the development of an all-SiC interface based solely on these materials. [4].

{Image 3} Methods/Results: Optical image before probe definition etch and packaged 16 channel interface on PBC header [4].

[1] Chen, Hongxu, et al. "Bioinspired microcone-array-based living biointerfaces: enhancing the anti-inflammatory effect and neuronal network formation." Microsystems & Nanoengineering 6.1 (2020): 58. [2] Barrese, James C., Juan Aceros, and John P. Donoghue. "Scanning electron microscopy of chronically implanted intracortical microelectrode arrays in non-human primates." Journal of neural engineering 13.2 (2016): 026003. [3] Frewin, C. L., et al. "Silicon carbide neural implants: In vivo neural tissue reaction." 2013 6th International IEEE/EMBS Conference on Neural Engineering (NER). IEEE, 2013. [4] Saddow, S.E. Silicon Carbide Technology for Advanced Human Healthcare Applications. Micromachines 2022, 13, 346. https://doi.org/10.3390/mi13030346 [5] Chenyin Feng, “Development of Carbon and Silicon Carbide Based Microelectrode Implantable Neural Interfaces,” Ph.D., Electrical Engineering, University of South Florida, 2021.

ABSTRACT. Low on-state resistance of SiC power MOSFETs in a wide temperature range is a highly important aspect for the design of SiC power MOSFETs. Besides temperature T, gate-source voltage Vgs and load current IL are also application-related parameters that affect the on-state resistance RdsON of SiC power MOSFETs. The RdsON of SiC power MOSFETs can feature both negative and positive temperature coefficients, depending on Vgs. This can be attributed to a decreasing share of the channel resistance Rch and an increasing share of JFET/drift resistance Rdrift within the total RdsON with temperature. Using a parameterized TCAD model of planar-gate SiC power MOSFETs, which takes into account processing and structural device design parameters, this paper addresses the design of a planar-gate SiC power MOSFET with respect to the current and temperature RdsON dependence. The results point out that both current and temperature-dependence of RdsON must be considered for selecting and/or designing a SiC power MOSFET for given application requirements and that the optimization process is greatly enriched using the developed parametrized model. Furthermore, the importance of including not only the T- but also the IL-dependence of RdsON for a more accurate estimation of the virtual junction temperature during power cycling is addressed.

ABSTRACT. Silicon-Carbide (SiC) MOSFETs are highly desirable due to their lower on-resistance (RON), higher breakdown voltage, and stronger high-temperature performance compared to silicon devices at medium power applications. The faster switching with the higher power density native to these applications presents new challenges for designers of SiC MOSFET devices. Without complete simulation support, costly fabrication-based design cycles are needed. Therefore, an accurate model parameter set in a device simulator is indispensable to carry out reliable simulations. However, TCAD simulations for SiC often lead to the inaccurate results mainly due to the lack of information such as the interface properties, bulk/interface mobility degradation caused by different manufacturing batches, processes and application conditions. Since the previous studies have focused on calibration of the interface traps only, so it does not fit well over a wide voltage range, which is because the device performance also quite relies on other properties such as the bulk trap, mobility degradation, and Schottky barrier. In this work, we report an accurate calibration strategy of the TCAD model parameters for a 1200V vertical SiC MOSFET by considering the overall physical model parameters such as trap distribution along the SiO2/SiC interface, mobility degradation, and Schottky contact. The proposed method achieved the improved predictive performance for current-voltage (I-V) (Vds=0~5V, Vgs=0~20V), capacitance-voltage (C-V) characteristics (Vds=0~800V) and short-circuit (SC) performance (Vds=800V).

ABSTRACT. In this paper the stress field distribution in 3C-SiC (111) resonators has been studied by micro-Raman measurements and COMSOL simulations. The measurements show that the asymmetry of the anchor points configuration produce an asymmetry in the stress filed distribution. This behavior has been confirmed also by the simulations. Furthermore, from the simulations the importance of the reduction of the under etching of the anchor points of the resonators has also been observed. In fact the reduction of this under etch produces a decrease of the stress in the double clamped beams, a small reduction of the resonance frequency, and a large reduction of the Q-factor and then of the oscillation frequency stability of the resonators in closed-loop operation.

ABSTRACT. In this work, we propose and examine a split gate p-IGBT structure. The electrical characteristics are discussed by adjusting CSL implant energy, and dose. For the switching characteristic,the turn-off time of the GSG-IGBT can be improved by 6% in comparison with that of the C-IGBT.

ABSTRACT. In this study, the influence of the wet-POA process with different treatment time on the threshold voltage of p-channel 4H-SiC MOSFET is investigated. The wet-POA process is an effective method to reduce the threshold voltage of the p-channel 4H-SiC MOSFET. Though it has been reported that the interface trap density decreases by applying the wet-POA process, the dependence of annealing time on electrical characteristics of the MOS structures has not been detail indicated. In this work, the effects of the wet-POA process on the p-channel 4H-SiC MOSFETs were investigated, and Vth reduction was discussed.

ABSTRACT. The demand for power modules capable of enduring high temperatures and delivering high power has surged with the advancement of high-power electronic devices for automotive, aerospace, solar panel, wind generator, and power grid applications [1-3]. In principle, the performance of power modules hinges on the characteristics of the power semiconductor devices, the packaging materials, and the packaging technologies. Due to its superior properties over Silicon (Si) devices, the Silicon Carbide (SiC) based power module has attracted extended interests [4, 5]. This paper presents the development and demonstration of a half-bridge leg SiC power module with advanced features such as small form factor, high performance, high temperatures sustainability, and double-sided cooling capability. The proposed power module incorporates two SiC chips, a customized lead frame (LF), four specially designed copper clips, high-temperature resistant bonding and encapsulation materials. Initially, the conventional direct bonded copper (DBC) substrates for the power module are replaced with a dedicated lead frame, resulting in a thinner and lighter module structure. Furthermore, the proposed power module enables a double-sided liquid cooling scheme by utilizing the flat copper clips on the top side of SiC devices, enhancing its thermal performance. The utilization of high-temperature resistant materials such as epoxy molding compound (EMC), die attachment (DA), and lead-free solder ensures the module's sustainability at high temperatures. Additionally, an adhesive dielectric thermal interface material (TIM) with high thermal conductivity is recommended to bond the power module with the liquid-cooled heat sink, further improving its thermal performance (refer to Fig. 1).” The development process involves modeling and simulations to optimize the design, high-temperature resistant materials evaluation to choose the proper materials, and test samples fabrication/assembly for power module demonstration. Performance characterization, reliability assessment, and failure analysis of the developed power module are also conducted. Below are the key findings of the study: • The developed power module is with a thickness of less than 1mm (excluding the cooling plate) and a junction-to-case thermal resistance of 0.09 ℃/W. • High-temperature-resistant materials have been successfully applied to the developed power module. • The assembly process of the power module has been optimized. Fabricated power module is shown in Fig. 2. • Reliability assessment has been performed and the test results are summarized in Table I. Representative structure function curves of the sample undergone PCTs are presented in Fig.3 • Failed samples have undergone failure analysis, revealing delamination and cracks in the die attach layer of the power module as potential root causes for these failures. (refer to Fig. 4). Acknowledgement: This work was supported by the Science and Engineering. Research Council of A*STAR (Agency for Science, Technology and Research) Singapore, under Grant No. A20H9a0242 Reference: [1] I. H. Ji, et, al, Proceedings of 2023 IEEE International Reliability Physics Symposium (IRPS), [2] F. Sommer, et, al, Proceedings of the 2022 International Power Electronics, p. 1390. [3] K. Matocha, et, al, Proceedings of 2019 IEEE International Reliability Physics Symposium (IRPS). [4] N. Kaminski and O. Hilt, Proceedings of Components of Power Electronics and their Applications 2023; ETG Symposium, p. 71. [5] D. J. Lichtenwalner, et, al, Proceedings of 2020 IEEE International Integrated Reliability Workshop (IIRW).

ABSTRACT. Formation of highly doped and defect-free p-type junctions at reduced cost remains one of the important limitations for the manufacturing of high performances SiC devices. Today process of record presents some limitations in term of defectivity, maximal implanted doses (~1E15 at/cm²) and cost (request a carbon cap during furnace annealing to avoid SiC dissociation). Indeed, if the implanted dose becomes too important (>4E15 at/cm²), basal stacking faults (BSF) are formed during the furnace annealing step [2]. To overcome these limitations, an alternative solution based on high-temperatures (>500°C) implantation and microsecond ultraviolet laser annealing (later referred as UV-LA) is proposed. This solution presents the advantages to be able to implant and activate high doses of aluminum (1E16 at/cm²) while remaining defect-free. Moreover, the manufacturing costs with this solution are reduced since there is no need of a carbon cap during the laser annealing step.

ABSTRACT. Silicon carbide (SiC) is one of the promising materials for the next generation of power devices. However, the manufacturing for high performances SiC devices at reduced costs presents some process challenges like the process formation of the backside ohmic contact. In this context, UV nanosecond laser annealing (NLA) is investigating thanks to its spatially localized anneal due to its ultrashort timescale and its shallow light absorption. NLA emerges as promising solution to form an ohmic contact on the backside while preserving the thermal stability on the frontside [1,2]. SCREEN_LT3100 platform equipped with a XeCl excimer laser (λ = 308 nm and ̴ 160 ns full width at half maximum pulse duration) was used, allowing a specific and local melt process limited near the surface. Among its unique capabilities, LT3100 is leveraging best-in-class process uniformity for melting applications but also present a productivity in-line with high volume manufacturing requirements. In order to provide a complete overview of benefits of NLA in the formation of backside ohmic contact, single pulse and multi-pulse regimes over a wide range of laser energy density (ED) were investigated. A 80 nm thick Ni layer was deposited on Si face of standard nitrogen doped 4H-SiC substrate (Nd=6x1018 at/cm3). Blanket and patterned (c-TLM structures) wafers were irradiated using the LT3100 at room temperature (RT) or using a heating chuck (HC) at 400°C. Electrical properties and microstructural features have been derived from different types of characterizations: c-TLM to verify the ohmicity of the contact and determined the contact resistivity , sheet resistance (Rs) measurements, X ray diffraction (XRD) and transmission electron microscopy (TEM) observations. Otherwise, the thermal budget control during NLA was demonstrated. Fig. 1.a compares the temperature gradient across Ni/SiC stack obtained by NLA and RTP. The Temperature does not exceed 200°C even at 100 µm in depth from the surface, therefore the high temperature region is very localized near the surface, whereas the diffusion of heat during RTP annealing affects the front side device. The measured contact resistivity (ρc) reaches 210-5 Ω.cm2 with RTP [3] and 310-5 Ω.cm2 with NLA (Fig.1.b). Therefore, an equivalent level is obtained with NLA while keeping the frontside cold. Afterwards, ρc has been measured as a function of the pulse number in the (2.0-5.5 J/cm2 ) ED range. For different series tested with 1, 5, 10 and 20 pulses, perfectly linear I-V curves can be obtained with a minimum contact resistivity. The process window for ohmic contact remains within the domain for which Rs drop is detected for blanket samples. By increasing the pulses number, the ED necessary to form an ohmic contact decreases (Fig1.c). For the 1 and 10 pulses series processed at HC = 400°C (Fig 1.d), the ρc obtained (1x10-5 Ω.cm2) is lower than obtained by RTP reference [4]. To investigate the formed silicide phase as well as the film uniformity after NLA, TEM cross section observations and 2θ-XRD scans have been performed. Fig.2.a presents cross-section TEM images of the stack Ni/4H-SiC before and after NLA. The Ni rich layer has been replaced by a uniform NixSiy alloy layer. Additionally, the XRD measurements of the 10 pulses series at RT are shown in Fig.2. b. For high ED (> 4.0 J/cm2) NiSi2 phase is evidenced. The formation of this Si-rich phase is concomitant with the formation of ohmic contacts after NLA with minimal ρc [5]. In conclusion, in this work, different approaches have been explored: single and multipulse at RT and with HC at 400°C to evaluate the different advantages of NLA. It has been demonstrated that the LT-3100 from SCREEN is an ideal solution to form an ohmic contact on the backside of the SiC devices thanks to its short-time localized annealed and its excellent process uniformity.

[1] P. Badalà et al., Ni/4H-SiC interaction and silicide formation under excimer laser annealing for ohmic contact, Materialia. 9 (2020) 100528. [2] F. Mazzamuto et al., Low Thermal Budget Ohmic Contact Formation by Laser Anneal, Mater. Sci. Forum. 858 (2016) 565–568. [3] S. Liu et al., A method to improve the specific contact resistance of 4H-SiC Ohmic contact through increasing the ratio of sp2-carbon, Appl. Phys. Lett. 117, (2020) 023503. [4] F.La via et al., Schottky–ohmic transition in nickel silicide/SiC-4H system: is it really a solved problem?, Microelectronic Engineering, p. 519-523, 2003. [5] Z. Zhou et al., Characteristics of Ni-based ohmic contacts on n-type 4H-SiC using different annealing methods, Nanotechnol. Precis. Eng. 4 (2021) 013006.

ABSTRACT. The next missions in space require high-power (HP) systems, mostly HP motor drives in the order of several tens of kW for several applications. This work considers a three phase (3P) 56 kW electric motor drive. The analyzed topology is the 2 level (2L) 3P voltage source converter (VSC). It has a dedicated battery, which operates at 150 V when fully charged, but can go as low as 100 V in the end of discharge. At the lowest input voltage and maximum power, the 2L 3P VSC must operate at 300 ARSM, creating a challenging environment for current space graded Si technology. Using analytical loss calculation models this work shows the benefits of using HP half-bridge (HB) SiC modules for such applications, achieving reduced PCB area and improved efficiency.

ABSTRACT. Cubic silicon carbide (3C-SiC) is a promising photoelectrode material for photoelectrochemical (PEC) water splitting, due to its chemical stability, ideal energy band positions that straddle the water redox potentials with the adequate band gap. To make theoretical solar-to-hydrogen efficiency, it is important to enhance the carrier lifetime by improving crystalline quality. One proposed approach to improving the quality is to reduce the double positioning boundary (DPB). In this work, we fabricated single-domain 3C-SiC on an off-oriented 4H-SiC substrate. “Off-oriented” sample was cut from a 100-µm-thick Al-doped p-type 3C-SiC epitaxial wafer (NA<1×10 16 cm -3 ) grown on a high purity semi-insulating (HPSI) 4H-SiC substrate with 0.2° inclined towards the < 11 ̅ 00 >direction from the (0001) Si-face. A second sample, “On-oriented”, was same epitaxial grown layer on a HPSI 4H-SiC substrate with the (0001) Si face. The carrier lifetime of the samples was quantified by employing the microwave photoconductivity decay (µ-PCD) method in a 355 nm pulsed yttrium aluminum garnet laser with a photon density of 5.7×10 14 cm −2 per pulse. To evaluate the PEC properties, A three-electrode system was employed to observe photocurrent from the 3C-SiC. The Ti/Al/Ni ohmic contacts were fabricated on the epilayer side of the samples by deposition and subsequent annealing in Ar gas at 1000 °C for 5min. In PEC experiments, we employed the electrolyte contained 1mol/L H 2 SO 4 and a solar simulator as the light source with an irradiation power of 100 mW/cm 2 . Figure 1 shows white light confocal microscope images of samples for surface. For the Off-oriented sample (Fig. 1(a)), we observed uniformed yellowish color areas and black lines, which are domains and DPBs. For the On-oriented sample (Fig. 1(b)) domains seem to be randomly formed. Figure 2 presents electron backscattered diffraction (EBSD) maps of 3C-SiC surfaces for the Off-oriented and On-oriented samples. In Fig. 2 (a), we observed a single domain on the Off-oriented sample. In Fig. 2 (b), on the On-oriented sample, there are two domains. Figure 3 shows the excess carrier decay curves for the samples. The lifetimes of the fast decay in Off- and On-oriented samples are approximately 120 and 60 ns, respectively. The result indicates that the single domain epilayer has longer carrier lifetime because of the decreased density of DPBs. Figure 4 shows PEC properties for the 3C-SiC on On-and Off-oriented Samples. For the 3C-SiC surface of the Off-oriented sample, the onset potential was approximately 0.5 V vs Ag/AgCl, while the cathodic current was -0.38 mA/cm 2 at -1 V vs Ag/AgCl. Conversely, for the 3C-SiC surface of the On-oriented sample, the onset potential was approximately 0.3 V vs Ag/AgCl, while the cathodic current was -0.3 mA/cm 2 at -1 V vs Ag/AgCl. The superior PEC property for the Off-oriented sample indicates decrease in the water reduction overpotential due to the single domain structure, and thus single domain 3C-SiC epilayers on off-oriented 4H-SiC substrates is promising for water splitting applications.

ABSTRACT. Bipolar degradation may occur in a SiC MOSFET when the body diode is operated in the third quadrant. This phenomenon typically leads to an increase of both the forward voltage drop (VSD) and the on-resistance (RDSon). For current level within the nominal range, bipolar degradation is mainly driven by basal plane dislocations (BPDs) in the epi drift layer. For much higher current levels, the root cause for bipolar degradation is mainly BPDs from the substrate wafer surface which are converted into threading edge dislocations (TEDs) at the beginning of the epitaxial growth [1-3]. To assess the substrate quality and the conversion process from BPDs into TEDs during epitaxial growth evaluation of six different 150mm SiC wafer suppliers is done. 1.2 kV MOSFETs (IMW120R140M1H) are fabricated on each substrate using the productive epi process. From each wafer at least 30 chips are taken and stressed in DC mode with an increasing current level (15min at each stress level). To determine if bipolar degradation is present RDSon measurements are performed before and after each stress step. For the extreme stress conditions both current level and chip temperature are beyond allowed datasheet limits. XRT measurements are performed for some suppliers to determine the BPD density distribution across the wafer. Fig. 1 shows two examples, one with an average density of 1350 BPDs/cm² and other with 346 BPDs/cm². In both cases, the density at the wafer edge is significantly higher than in the wafer center. Therefore, chips are taken from the wafer edge for the stress experiment. Fig. 2a shows the average drift of at least 30 chips from supplier A to F, while Fig. 2b shows the drift of supplier A for some selected single chips. Two distinct regimes can be observed, one is that up to a certain current level, no drift occurs. This indicates good conversion of BPDs to TEDs during the epitaxial process, regardless of the wafer supplier. Above around 1000 A/cm², several chips exhibit significant bipolar degradation. Other studies report findings that are consistent with the onset of bipolar degradation at a critical current density [4-5]. SiC MOSFETs from different manufacturers are investigated for a more comprehensive analysis. An upper limit for stable operation between 400 and 900 A/cm², depending on device technology and epi design, is determined using the described stress procedure. With this method for every substrate quality and device technology a safe operating current density can be determined. In addition, the comparison of wafers from the same supplier is performed to estimate the variability of bipolar degradation at high current levels. Fig. 3 shows the average RDSon drift of 3 different wafers for supplier A. The legend provides the average BPD density for each wafer. The wafer with the minimum BPD density exhibits nearly no drift. The other two wafers with BPD densities above 1000/cm² show significant drift, but the absolute value of the drift is not proportional to the BPD density. To provide evidence that bipolar degradation is the reason behind the observed RDSon drifts an emission microscope (EMMI) image is taken for a device with 15% drift. In Fig. 4, bar shaped and triangular stacking faults can be seen as dark blue areas covering around 15% of the active area.

ABSTRACT. In this paper, a method for suppressing bipolar degradation through proton implantation was investigated. Previous work suggests implantation applied to the full thickness of the epi layer, which results in unwanted defects leading to a deterioration in performance. In this work, proton implantation to the buffer layer was successful in reducing the forward-voltage drift ΔVF of the fabricated SiC PiN diode by 81.5% at a current density of 100A/cm2, by applying room temperature proton irradiation at a dose of 1×1016 cm-2

ABSTRACT. This study explores the advanced trench etch processing techniques for fabricating SiC superjunction Schottky diodes. We employed Inductively Coupled Plasma-Reactive Ion Etching (ICP-RIE) on 4H-SiC substrates to create deep, narrow trenches necessary for superjunction structures. Our findings indicate a decrease in etch rates with reduced trench widths below 10 µm, necessitating optimized etching recipes. The study delineates the etching parameters' influence on trench dimensions and identifies optimal conditions that mitigate surface contamination and maximize etching efficiency. This research contributes to the enhanced fabrication of high-voltage SiC devices, promising significant advancements in power electronics.