ABSTRACT. Silicon carbide (4H-SiC) devices with blocking voltage rating up to 3.3kV have been successfully commercialized [1]. Two key factors for this are the availability of lower cost, high quality SiC substrates, and the availability of low defect epitaxial layers with a thickness of up to 30 m. SiC devices also have the potential to outperform Si devices for higher voltage applications beyond 6.5kV due to lower power dissipation and superior thermal conductivity [2]. For this, thicker epitaxial layers are required for higher blocking voltage. In-grown stacking faults (IGSF) can be generated during epitaxial growth of SiC and can have a more complex nature in thick epitaxial layers [3]. These IGSFs can cause device leakage and can also result in surface defects that may influence oxide reliability in SiC MOSFETs. Hence, it is essential to investigate their formation and microstructure. In this work, we perform an analysis of IGSFs that were formed at different stages of epitaxial growth, analyze their spectral emission and identify possible formation mechanisms using ultraviolet photoluminescence (UVPL) imaging with spectral content as well as multi-vector X-ray topography (XRT). SiC epitaxial layers with 180m thickness, low n-doping of 5x1014 cm-3 were grown on 150 mm diameter SiC substrates with a 20m thick 1x1018 cm-3 highly n-doped buffer layer using conventional chemical vapor deposition with chlorinated chemistry in a hot-wall epi-reactor. UVPL extended defect mapping was performed on a custom setup with 355nm laser excitation. Several spectral filters with ~10 nm bandpass from 400-700nm are being used to observe luminescence images of various IGSFs. Additionally, -PL mapping of selected defects areas were measured using a customized grating based spectrometer with 325nm laser excitation. XRT measurements were performed using a Rigaku XRTmicron system. Section topography was also performed on selected sample IGSF regions to investigate defect evolution and propagation with depth. IGSFs of various sizes were observed in the wafers as shown in Fig 1. This indicates that they did not form at the substrate / epitaxial interface but at a later stage during epitaxial growth. They also appeared to have a different microstructure. Many of them were a Frank-type IGSF, but there were others that also had Shockley-type regions. XRT imaging of the same defect regions, as shown in Fig. 2, shows contrast that indicates the presence of multiple components of fault vectors for different stacking faults. Spectral UVPL images also correspond with these results and show some regions of the faults having emission in the ~415-420nm range, which corresponds to Shockley stacking faults [4]. Other regions show emission ~430nm, indicating an extrinsic Frank-type fault [5]. Complete details from spectral UVPL imaging and -PL mapping from the IGSFs will be presented to determine the various fault types in more detail. Additionally, depth resolved section XRT will be shown to analyze the origins of the IGSFs during the epitaxial growth process.

[1] D. Xing et al., pp 1-6, 2020 WiPDA Asia, doi.org/10.1109/WiPDAAsia49671.2020.9360270. [2] J. Wang, et. al., IEEE Industrial Electronics Magazine, 3, 16-23, (2009). [3] N. A. Mahadik, et. Al., Scripta Materialia 235, 115598, (2023). [4] Sridhara et. al. Appl. Phys. Lett. 79, 3944 (2001) [5] Tsuchida et. al., J. Crys. Growth 310, 757 (2008)

ABSTRACT. 4H-SiC power devices have proven value in applications like EVs, but future demands require further refinements. While much focus is on moderate power devices, 4H-SiC holds potential for ultra-high-power applications. Key challenges include growing extremely thick, high-quality epitaxial layers with controlled doping and improved minority carrier lifetimes (MCLs) – ideally without post-growth enhancement. For widespread adoption, substrate availability, processing adaptability, and cost must also be addressed. Thick epitaxial layers are crucial for high-voltage power devices, enabling lower doping and reduced conduction losses. Challenges include achieving fast growth rates, maintaining crystal quality over increasing thicknesses, and growth on standard 4°-off substrates. Chloride-based chemistry offers promise for fast growth rates, and together with careful in-situ surface preparation basal plane dislocations (BPDs) replication into epilayer can be minimized. The complexity of controlling defects and surface roughness increases in thicker layers, hence the growth of extremely thick 4H-SiC layers on 4°-off substrates includes distinct challenges compared to prior works on 8°-off substrates [1]. Here we demonstrate the growth of high-quality, 280 µm thick 4H-SiC layers, suitable for 30 kV blocking voltage, on 4°-off 4-inch diameter substrate suitable for advanced ultra-high-power applications. Although our extended presentation will detail how growth parameters impact layer properties, here we mention them briefly together with some of the characterization results for the final 280 μm thick epitaxial layer structure. The epitaxial layers were grown using a chloride-based process with SiHCl3 (TCS) as the silicon source to enable high growth rates. Growth parameters were then optimized to achieve improved quality of epilayers according to the growth rate. Low doping concentrations can be achieved at high growth rates together with increased C/Si ratio following the site competition model [2]. However, above certain growth rates the surface of epitaxial layers gets significantly rough, making the polytype replication challenging. In addition, we have previously shown that the surface roughness is also influenced by choice of different hydrocarbons, both during surface preparation and epitaxial growth [3]. Furthermore, we have found that there is also an upper limit for the C/Si ratio for high growth rates above which the epitaxial layer misses the polytype replicability and turns into polycrystalline SiC. Interestingly, this limit differs significantly for the different hydrocarbons, where even introducing additional chlorine would not change the results. Accordingly, the maximum possible C/Si ratio was then investigated for the different hydrocarbons (here methane and propane) at different growth rates to define the possible window for these parameters. Furthermore, it was also observed that the incorporation of N for a similar N/C ratio will be different for the different hydrocarbons. Next, for the improvement of MCL, growth parameters had to be adjusted in a way that the concentration of the two most important lifetime limiting defects; boron and carbon vacancy related ones, are minimized. Interestingly, the most suitable condition for minimized Z1/2 (low growth temperature and high C/Si ratio) increases the incorporation of boron related defects and vice versa [4]. Thus, the optimum value was found to have the lowest possible of each defect and accordingly improved MCL in as-grown epilayers. Hence, 2.7μs of MCL was achieved for 25μm thick epitaxial layer [4]. Following the fine adjustment of the growth parameters, six full-wafer growth runs with different thicknesses above 125 μm and similar layer structure were grown with slightly varied growth temperature, growth rate and C/Si ratio to investigate the characteristics of each. A summary of the different series of growth runs is presented in Table I. We performed a series of experiments to optimize the growth parameters such as substrate surface preparation, growth temperature and C/Si ratio, under different conditions using CH4 and C3H8 to obtain suitable epilayer properties at different growth rates for thick epilayers. After defining the most suitable growth parameters, epitaxial growth of a low doped 280 μm thick layers was performed. Fig.1a shows the schematic of the layers structure of the thick epitaxial wafer, whereas the cross-section optical image is given in Fig.1b. A highly doped buffer layer was also grown before the growth of 280 µm thick drift layer. Epilayer characterization included DIC optical microscopy, TRPL mapping, Raman spectroscopy, X-ray topography, PL imaging, and CV measurement. Optical microscopy revealed a relatively rough surface with a few triangular defects and short step bunching. TRPL mapping (Fig. 1c) showed an average MCL of ~3μs in as-grown epilayer with no stacking faults except those associated with triangular defects. Comparing the measured lifetime on the thick layer with the one measured on 25μm thick layer, suggests a saturation limit for lifetime in as-grown epitaxial layers grown in our CVD reactor, a more detailed analysis will be presented. Raman spectroscopy verified the epitaxial layer was 4H-polytype throughout the thickness (Fig. 1d). Further analysis of doping and thickness uniformity, X-ray topography and PL imaging will be presented later in detail and different types of defects and their distribution will be discussed. Comparing optical and TRPL maps, with the assumption that nearly all BPDs were converted to TEDs, the calculated yield for (2x2), (4x4) and (10x10) mm2 dies sizes are about 93%, 76% and 50%, respectively.

ABSTRACT. Semiconductor devices based on polytype heterojunctions are an attractive application of SiC. To obtain a single-domain 3C-SiC epilayer on 4H-SiC, we developed the simultaneous lateral epitaxy (SLE) method. The heterojunction obtained by SLE consists of a coherent interface between 4H-SiC(0001) Si-face and 3C-SiC(-1-1-1) C-face, which is known to generate a two-dimensional hole gas (2DHG). To generate a two-dimensional electron gas (2DEG), on the other hand, the interface must consist of the 4H-SiC(000-1) C-face and 3C-SiC(111) Si-face. To obtain either 2DEG or 2DHG at will, the SLE method has been extended to form epitaxial layers of alternating stacks of 4H-SiC and 3C-SiC. To form single-domain 3C-SiC on 4H-SiC, 3C-SiC mononuclear (ηc) must be generated spontaneously on the basal plane of 4H-SiC, which is a necessary condition for eliminating the double-positioning boundary (DPB). On the other hand, the generation of 4H-SiC nuclear on the surface of 3C-SiC layer is practically difficult even if the surface is atomically flat. This is because, the stacking sequence of 4H-SiC is not uniquely determined. In this study, the 3C-SiC surface is arranged so that the stacking sequence originally contained in the 4H-SiC substrate propagates laterally on it. To achieve this, ηc must be placed at specific locations. It should be noted that each ηc is shifted to a relative [0001] direction. Then the 3C-SiC layer originating from ηc and surrounding the 4H-SiC layer expand in the [11-20] direction by SLE. Finally, a 4H-SiC layer can be inserted between each 3C-SiC layer. Even if each ηc generated is in a twinning relationship, they are isolated by the intermediate 4H-SiC layer and thus are spared from DPB generation. 4H-SiC with a surface tilted 4 degrees in the [11-20] direction relative to the (0001) plane is used as a substrate for SLE. Before the epitaxial growth, grooves of 8 μm-width and 0.8 μm-depth are formed on the substrate surface by photolithography and dry etching techniques. All grooves are deflected away from the [1-100] direction forming vertices (τ) in the [11-20] direction. Then, the single-nucleation of 3C-SiC is promoted near τ, which is located relatively upstream in the area in between adjacent grooves. The spacing of adjacent τ in the [11-100] direction (P), the width of τ with respect to the [-1-120] direction (Z), and the spacing of adjacent grooves (W) are varied. After the groove formation, a specific cubic close-packed structure is exposed on the topmost surface of the substrate by Step-Alignment(R) treatment, and then a 5.5 μm-thick SiC layer is epitaxially grown. A single 3C-SiC layer is epitaxially grown at Area-1 (Z=20 μm, P=40 μm, W=150 μm) on 4H-SiC layer, while multiple 3C-SiC layers extend in the [11-20] direction at Area-2 (Z=20 μm, P=200 μm, W=20 μm). A linear 3C-SiC surface parallel to the [1-100] direction is observed among 4H-SiC surface at Area-3 (Z=10 μm, P=40 μm, W=150 μm). Cross-sectional TEM image at Area-3 clearly shows that all the hetero-interfaces are coherent and parallel to the basal plane. As described above, it is possible to obtain 4H-SiC(0001) Si-face / 3C-SiC(-1-1-1) C-face and 4H-SiC(000-1) C-face / 3C-SiC(111) Si-face interfaces simultaneously. This makes it possible to place 2DEG and 2DHG regions at the desired locations, giving more flexibility in device design.

ABSTRACT. Transfer of high-quality graphene from its growth substrate to substrates of technological interest can be necessary to enable its use in certain applications, however it remains challenging to achieve large-area transfer of graphene that is clean and intact. This work utilizes a dry transfer technique in which an adhesive metal stressor film is used to exfoliate epitaxial graphene from SiC(0001) [1]. In this method, the strain energy in the metal film must be high enough to allow for uniform exfoliation, but low enough such that self-exfoliation of graphene does not occur. We investigate the dry transfer of monolayer epitaxial graphene (MEG) and hydrogen-intercalated, quasi-freestanding bilayer graphene (QFBEG) grown by sublimation of Si from nominally on-axis 6H-SiC(0001) in a CVD reactor in Ar ambient. A magnetron sputtered Ni stressor layer is used to exfoliate epitaxial graphene and transfer to GaAs, glass, and SiO2/Si substrates. The Ar pressure during sputtering is found to impact the stress, film density, and roughness of the Ni film, as determined from wafer curvature and X-ray reflectivity (XRR) measurements. By using appropriate sputtering conditions, the Ni/graphene film exfoliates from the entire area of the SiC substrate with use of thermal release tape. Atomic force microscopy (AFM), scanning electron microscopy (SEM), Raman spectroscopy, x-ray photoelectron spectroscopy (XPS), and Nomarski microscopy are used to characterize the graphene. The Ni 2p peak was not detected in XPS of the transferred graphene after removal of the Ni film by etching in acid. Additionally, XPS revealed minimal oxide present at the graphene-GaAs interface, consistent with previous reports for this dry transfer method [2]. Raman spectroscopy mapping showed that predominately monolayer graphene is transferred from MEG, while predominately bilayer graphene is transferred from QFBEG. Raman spectroscopy of the SiC substrate after MEG exfoliation shows the 6√3 buffer layer that forms during growth on SiC(0001) remains on the SiC substrate. Consequently, if there are regions of exposed 6√3 buffer layer in the as-grown MEG on SiC, AFM shows that there are corresponding gaps in the transferred graphene film where the areas of exposed buffer layer do not transfer. The 6√3 buffer layer is not present in QFBEG due to the hydrogen-intercalation process. It is found that the same Ni sputtering conditions that led to uniform exfoliation and transfer of MEG result in micron-scale tears in the Ni/QFBEG film. By lowering the strain energy in the sputtered Ni film, these tears can be reduced or eliminated.

[1] Kim, J., et al., Science, 342, 833 (2013). [2] Kim, H., et al., ACS Nano, 15, 10587 (2021).

ABSTRACT. Two-dimensional silicon carbide (2D SiC) has received significant attention recently, with various theoretical studies delving into the structure and fundamental properties of both 2D SiC and its nonstoichiometric counterparts. This rapidly increasing interest comes from the immense potential and promises that such materials hold for several applications including power electronics, optoelectronic and photonic applications, among many others. Owing to its reduced thickness, 2D SiC possesses a unique combination of physical and chemical properties (e.g., direct band gap, enhanced photoluminescence, and variouse non-linear optical properties) that are absent in bulk SiC. Further, one of the most significant advantages of 2D SiC over any other 2D material is its expected high-temperature capabilities, as silicon carbide can tolerate high temperatures and extreme environments. These characteristics are critical for many applications and make SiC nanosheets a potential game-changer for future semiconductors.[1–4] In addition to SiC nanosheets, other low-dimensional silicon carbide structures such as one dimensional SiC nanowires, and nonstoichiometric SixCy[3] nanosheets offer several unique structural and physical properties and provide superior materials control and device flexibility and scalability compared to bulk SiC. They enable ultimate scaling. Because of their reduced thickness and quantum confinement effects, low dimensional silicon carbide materials enable the fabrication of smaller, thinner, denser, and more flexible SiC electronic and optoelectronics devices, as well as novel device concepts. Or in the case of quantum applications, these emerging nano materials are expected to enable deterministic placement of color centers at the level of nanometers or angstroms. Low dimensional SiC semiconductors are also useful for sensing applications and as well as extreme environments, where many components, including silicon, fail at high temperatures or harsh environment. This presentation, thus, focuses on our ongoing experimental work on low dimensional silicon carbide, aiming to inspire more experimental and theoretical works into these emerging nano semiconductors. We will present our recent data from 1D and 2D SiC materials and devices. Both liquid exfoliation and chemical vapor deposition methods have been used for materials preparations. Fig. 1. shows schematics of chemical structures of 2D SiC and the calculated phonon band energy. Fig. 2 presents results from transmission electron microscopy (TEM) and other structural characterizations, and figures 3 and 4 show our recent electrical measurements from both SiC nanowire and SiC nanosheet. In summary, we fabricated and tested novel low diemnsional silicon carbide. Our experimental findings validated the existing theoretical studies and demonstrated the feasibility of developing and testing SiC nanosheets optical and electrical devices and shows that the 2D/1D-nature of these nanosheets/nanosheets opens several possibilities for future silicon carbide technologies. These results will benefit further optimization of SiC technologies through integrating low dimensional materials.

ABSTRACT. Recently gallium nitride (GaN)-based solid-state devices have demonstrated extraordinary effectiveness for high-power, high-frequency, and high-temperature technology. The basic properties of the AlGaN/GaN material combination make it an excellent choice for microwave devices. Silicon is the most cost-effective adopted substrate for large-scale fabrication of GaN devices [1]. However, interfacial stress, dislocation density and meltback etching caused by Silicon outdiffusion remain significant disadvantages. GaN on SiC offers superior thermal performance and fewer defects due to better lattice and thermal matching but comes at a higher cost and with manufacturing difficulties. A further challenge is represented by the common use of SiC off-axis substrates. In the off-axis orientation the two orthogonal directions in the vicinal c-plane, along [1120] and [1100] (with and without periodic surface steps, respectively) can stimulate anisotropic epitaxy and amplify the effects of the different thermal expansion rates during the cooling process post-growth, potentially causing additional strain and cracking in the GaN layer [2]. In this work Trimethylgallium (TMGa), Trimethylaluminum (TMAl) and ammonia (NH3) were used as the precursors for Gallium (Ga), Aluminium (Al) and Nitrogen (N) sources respectively. HEMT layer was carried out on 3 processes where the deposition of a 2 m GaN buffer layer at 1020 °C was followed by the growth of 16 nm thick AlGaN layer. The epitaxial growth of GaN was conducted employing three distinct methodologies: the Standard Process (SP) method adhered to the established protocol for GaN epitaxy on Si substrates. Subsequently, a specialized procedure was formulated for SiC substrates, which was further bifurcated into two stages, designated as P1 and P2. Each stage differing on AlN growth parameters. Within the specialized SiC procedure, one of the stages was subjected to trials on SiC substrates measuring 500 µm, both on-axis and 4° off-axis, as well as on a 350 µm SiC substrate. Additionally, a control epitaxial growth on a Silicon substrate was performed to serve as a reference point. Upon wafer flatness evaluation, distinct behaviors were observed. Adopting the conventional SP process, wafer exhibited a curvature with a bow range of 187.2 µm, whereas the Silicon wafer demonstrated a bow range of 46.2 µm. As depicted in Figure 1a, in the case of on axis SiC substrates, the process variations resulted in flatness values susceptible to thinner SiC substrate thicknesses due to augmented thermal stress during cooling rate, ranging from 78.3 µm to 178.2 µm when transitioning from a 500 µm to a 350 µm SiC substrate in P1 and from 37.22 µm to 136.1 µm in P2. Among all processes, it is worth noting that off-axis oriented GaN on SiC growths resulted in the lowest bow range as high as 29.65 µm in the P1 and 19.75 µm in the revised process P2. Full Automated Optical microscopy inspection of the wafers revealed a high percentage of Total Usable Area (TUA). Particularly in Figure 1b, the inspections indicated that the highest 1mm2 TUA was 99.57% in P2 with 0.46 cm-2 defects density. It is noted that the surface remains smooth in the case of GaN on SiC (Figure1c), while, in the case of GaN on Silicon, onset of microcracking is disclosed due to stress (Figure1d). Full wafer Photoluminescence (PL) analysis, performed with a =266 nm excitation laser, revealed that the off-axis GaN on SiC underwent P2 growth exhibited a standard deviation in the GaN signal intensity of 9.9% in band edge spectral region. As depicted in Figure 1e, the spatial map of the emission wavelength indicates a localized emission peak at (364.1±0.1) nm. As attested for GaN grown under P2, the emission intensities exhibit variations that rely on crystallographic orientation. Peak intensities are demonstrably higher for the on-axis GaN on SiC sample compared to the off-axis sample, suggesting that the misorientation in the off-axis sample may intensify lattice mismatch and consequently increase the concentration of dislocations. As a result, the off-axis sample manifested a reduced PL intensity. Conversely it was attested the rising in PL signal in the intrabandgap region in Figure 1e. The emission map delineates a specific area indicative of intrabandgap recombination from 500 to 650 nm. This spectral region corresponds to the commonly observed yellow luminescence (YL) band associated with defects in GaN. Potential origins of the YL band in GaN include dislocations as well as various point defects such as Ga vacancies (VGa) or VGa complexes, such as VGaON or VGaSiN and C related point defects [3]. The uniformity of this signal across the wafer is quantified by a standard deviation of 6.5%, with a marginal intensification noted towards the periphery of the wafer. Concurrently, the presence of Fabry-Perot oscillations indicates that uniformity in the arrangement of the grown layers is preserved. This is further corroborated by Vertical Scanning Interferometry (VSI) profilometry measurements, which reveal that the Root Mean Square roughness (Sq) on a 250×100 mm2 area is (3.98±0.16 nm) nm for the off-axis sample in P2 as displayed in Figure (1g). This result is notably comparable to the Sq of (3.35±0.09) nm observed for the GaN on Si grown underwent SP. Comparative evaluations of the data suggest that Sq is elevated for the on-axis samples processed through P2, exhibiting a range from (8.96±0.96) nm to (7.36±0.66) nm. In contrast, for P1, the Sq values are recorded between (7.04±1.78) nm and (5.02±0.40) nm. The compositional analysis depicted in Figure 1h illustrates that the off-axis sample from process P2 contains an Al fraction of (30.4± 0.71)%. This data suggests that the P2 facilitates a higher Al incorporation rate, and exhibit an upward trend in the Al fraction from process P1 to process P2. In light of the results, the research presented herein provides valuable insights into the optimization of 150 mm GaN on SiC MOCVD growth, establishing the 4° off-axis SiC substrate as a promising contender for the improvement of GaN on SiC High Electron Mobility Transistors (HEMTs).

[1] Feng, Sirui, et al. Advanced Materials 34.23, 2201169,(2022). [2] Yao, Lei, et al. Intern. Jour. of Electronics and Communication Engineering 6.9, 931-934,(2012). [3] Reshchikov, Michael A., and Hadis Morkoç. Journal of applied physics 97.6, 5-19 (2005) [4] Su, Chung-Wang, et al. Solid-State Electronics 179,107980, (2021).

ABSTRACT. Currently, SiC is widely recognized as one of the most prominent wide bandgap semiconductors, with expanding applications in harsh environments, such as high temperature and radiation exposure. We developed a planar structure 4H-SiC GAA JFET, where the channel region is formed through ion implantation at varying doses, and its transfer characteristics were evaluated. Moreover, we constructed a common-source amplifier and assessed the maximum voltage gain. We were able to modify the threshold voltage and produce both normally-on and normally-off JFETs by changing the amounts of channel dose. The maximum voltage gain of SiC GAA JFET source-common amplifier is estimated to be −17.1 (24.6 dB), −112.6 (41.0 dB), and −226.7 (47.1 dB) at VDD=10, 20, and 30 V, respectively.

ABSTRACT. Bipolar degradation poses a critical challenge in SiC devices, driven by the expansion of single Shockley stacking faults (1SSFs) from basal plane dislocations (BPDs). This study investigates the effects of helium implantation on the suppression of 1SSFs expansion. Experimental results demonstrate that the expansion of stacking faults was suppressed by helium implantation. We consider that the BPDs were immobilized by presence of point defects introduced by implantation.

ABSTRACT. Experimental depth profiles measured by Secondary Ion Mass Spectrometry (SIMS) confirmed successful channeling implantations and were compared to Monte Carlo Binary Collision Approximation (MC-BCA) simulations performed in Synopsis Sentaurus TCAD. A significant discrepancy was observed in the depth profiles for energies above 10 MeV between the SIMS results and those predicted by TCAD simulations. This indicates that the commonly used physical models for describing the ion track need to be revised and calibrated for this high-energy range. By utilizing SIMS measurements alongside simulation algorithms such as TCAD Sentaurus (Synopsis) and SIIMPL, critical model parameters essential for high-energy implantation simulations can be identified. The goal is to understand their effect in the high-energy range and gain insight into the underlying physical phenomena governing ion interaction with the semiconductor crystal at such kinetic energies.

ABSTRACT. The strain induced by thermal oxidation and ion implantation on a series of samples is studied via a Raman spectroscopy analysis. The results show that both thermal oxidation and ion implantation induce a tensile stress on the SiC crystal. New Raman modes were also observed after ion implantation and thermal oxidation.

ABSTRACT. A P-iso structure for monolithic integration of planar CMOS and 1.7 kV VDMOSFET on 4H-SiC formed by high energy ion implantation is studied. Design parameters are evaluated by TCAD simulation. The better process condition is then verified by actual test structures. A 2 kV blocking capability is achieved. It is believed that the high energy ion implantation method has the potential to be used in isolation above 3.3 kV.

ABSTRACT. SiC CMOS has received increasing attention for integrated circuits operating at high temperatures. To develop SiC CMOS circuits, reduction of threshold voltage (VTH) in SiC p-channel MOSFETs is essential because the VTH is unusually high at the present stage. Although “counter-doping” is a promising technique to reduce VTH, studies on counter-doping (buried channel) in SiC p-channel MOSFETs are very limited. In this study, counter-doped SiC p-channel MOSFETs were fabricated with various Al doses to investigate the effect on VTH reduction. Furthermore, high-temperature operation of SiC CMOS inverters with a logic threshold (VTH,logic) of nearly half of a low supply voltage (5 V) are demonstrated using the counter-doped p-channel MOSFETs.

ABSTRACT. Reliability under blocking has become a hot topic these days for MOS based SiC power devices. Although while running only a single point high temperature reverse bias (HTRB) qualification test at or near maximum rated drain bias and at maximum rated junction temperature can fulfill the qualification requirements for blocking reliability, it does not provide sufficient information to determine device lifetime of SiC-MOS devices during high voltage off-state stress. Like gate bias mediated time-dependent dielectric breakdown (TDDB), to enable blocking lifetime extrapolation at operating condition, the gate oxide (GOX) lifetime modeling using accelerated reverse bias (ARB) stressing which typically employs multiple VDS stress values beyond the rated drain bias but below the avalanche voltage, has become a popular method in the SiC community [1-2]. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified modeling approach where a single stress voltage ARB/HTRB test for a reasonable stress duration can be run to project GOX lifetimes under blocking.

Figure 1 shows the median time to fail (MTTF) plot derived from an ARB test where three sets of Wolfspeed 1200 V rated packaged parts were stressed with drain voltage VDS values of 1310V, 1380V and 1450V at 175°C for nearly one year to gather failure statistics. From the failure distribution which follows Weibull statistics, lifetime projection at a reduced operating voltage was then performed by extracting fitting parameters via maximum likelihood estimation and employing a “linear E-model” [3]. Although this method is ideal, it is extremely time-consuming and also challenging for certain devices as depicted above.

Figure 2 portrays an alternative approach for off-state lifetime modeling utilizing the “linear E-model” and a single stress voltage failure data obtained from a qualification type HTRB or ARB test running for a certain duration (preferably 1000 hours or more). According to “linear E-model” a blocking lifetime curve can be drawn for any drain bias using TTF = C + gamma * VDS. However, such an estimation will still need the knowledge of either voltage acceleration gamma or intercept C. Estimation of gamma is non-trivial and equally challenging as constructing lifetime curves from multiple drain biases. Conversely, the intercept C represents the lifetime of a device when VDS is extrapolated to 0. At zero gate or drain bias the GOX lifetime is likely determined by the physics of diffusion and subsequent degradation mechanism. Hence the conjecture that Cblocking~CTDDB at VDS,V_GS=0 for a given device technology (identical oxide thickness, drift thickness, cell design etc.) and temperature likely should hold at least for a first order approximation. From the year-long ARB test (Fig. 1) extracted Cblocking~1e13 hours closely match with the CTDDB value obtained from TDDB test done on similar devices at 175°C, further corroborates this assumption. Thus, the knowledge of C value from a TDDB test, along with a known Weibull slope (beta) likely can be utilized to construct a blocking lifetime curve for any failure percentile from a single drain bias stress test data.

Figure 3 presents hypothetical scenarios (0 failures after 1000 hours of stressing) of projecting MTTF from a 1200 V rated product for different VDS and C values. In Fig. 3(a), C values are varied from 1e11 to 1e14 hours, while Fig. 3(b) predicts MTTF for various VDS values ranging from 1200 V to 1400 V. Similar projections can be made for other scenarios with various sample sizes and beta values and will be shared in the extended version. Figure 4 discusses some possible shortcomings of this technique. Consideration has been given to scenarios where blocking lifetime estimated from TDDB extracted C value predicts favorable TTF numbers, but lifetime extracted from multiple VDS stress voltages is influenced by an alternative failure mechanism, as shown in Fig. 4(a). In such cases, relying on a single stress voltage may yield an overly optimistic off-state lifetime estimate. However, in such cases the dominant blocking failure mechanism likely will be unrelated to intrinsic GOX breakdown and should be tackled in a manner beyond the scope of this study. Conversely, if the TDDB lifetime is adversely affected by a mechanism other than intrinsic GOX failures, then by virtue of lower C value, the blocking lifetime estimation might get impacted and will project a rather pessimistic value. So, it is imperative to make sure that the C value estimated from TDDB, represents true intrinsic GOX failure mechanism.

In conclusion, we present a novel alternative modeling technique to project MOSFET intrinsic GOX lifetime under blocking from a single drain bias stress dataset with the aid of TDDB results done on a similar group of devices at the same temperature which is otherwise extremely time consuming or even impossible to model.

The authors would like to acknowledge the valuable discussion with J.W. McPherson in this regard.

ABSTRACT. In order to qualify and characterize the lifetime of semiconductor power packages, the ECPE Guideline AQG 324 [1] defines and describes the corresponding required tests. One of these tests is active power cycle testing (PCT), which necessitates the precise transient measurement of the virtual junction temperature Tvj. For SiC MOSFETs, the voltage drop of the body diode VSD(T) is employed as a temperature-sensitive electrical parameter (TSEP). Recent studies on advanced SiC MOSFETs from various manufacturers demonstrated that the commonly used static temperature calibration method may result in a significant error in the estimation of Tvj [2, 3]. This is due to a novel observed transient behavior of VSD after a gate bias switch with a constant measurement current Imeas and temperature, which leads to a calculation error of Tvj in the range of 10 K. This study continues and deepens the investigation of the effect, examining the influence of those factors that can be adjusted in PCT. The objective is to establish correlations between these parameters and the currently unknown underlying semiconductor physics. Furthermore, methods for minimizing the effect without the additional effort of the proposed advanced dynamic calibration method needs to be identified [2]. The electrical circuit used for this investigation is depicted in Fig. 1. Fig. 2 illustrates the time curve of Tvj, the Drain-Source current IDS, and the Gate-Source voltage VGS are shown for both the conventional PCT load and cooling cycle (right) as well as for the new pattern with no load current to investigate the effect. Using the second scenario, 5 out of 10 devices from different manufactures shows a significant transient shift of VSD after switching VGS from the maximum positive to negative values according to the data sheet. This deviation is designated as ΔVSD, representing the disparity between VSD right after the gate bias switch including device and circuit charging effects, and the end of the cooling cycle toff. This transition of the gate is necessary in power cycling to close the MOSFET channel after the heating phase. Furthermore, the significance and influence of the values of Imeas (10..90 mA), negative VGS (-4..-12 V) and the temperature (20..150 °C) were analyzed in a measurement series. The results, shown in Fig. 4, are divided into blocks for better visualization. The results indicate that a higher negative UGS,off reduces ΔVSD, but is not able to fully eliminate the effect even at -12 V, which is beyond the data sheet limit value for VGS. There is also a clear dependency of the temperature, whereas ΔVSD decreases with higher temperature at low Imeas and increases with high Imeas respectively. A review of the results from 12 individual devices of the same type, as shown in Fig. 5, reveals a high degree of variability among the devices under test (DUT). This underscores the necessity for the recording of individual calibration curves for each DUT prior to the PCT.

[1] ECPE Guideline AQG 324: Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles, 03.1/2021, ECPE European Center for Power Electronics e.V. ( 2021). [2] J. Breuer, F. Dresel, A. Schletz, J. Klier, J. Leib, M. März, and B. Eckardt, Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling – a Dynamic Approach, in CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems (Düsseldorf 2024) pp. 239–245. [3] M. Noah, C. Fuentes, and F. Filsecker, Dynamic calibration: How to properly estimate junction temperature in SiC MOSFETs subject to body diode voltage shift, in CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems (Düsseldorf 2024) pp. 725–730.

ABSTRACT. Silicon carbide (SiC) power products may experience voltage degradation which stem from the stacking faults (SFs) growth, commonly known as bipolar degradation (BD). To properly evaluate the BD impact on electric performance of devices it is important to distinguish it from other stress-related degradation e.g., power metal or interconnection. This aspect has not yet been addressed, although the bipolar degradation mechanism is well-understood [1–2]. This work outlines a methodology by modifying the power cycling test (PCsec) to PCmsec to systematically investigate the effect of bipolar degradation while controlling the impact of thermal degradation. This approach enables a thorough evaluation of the distinct influences of both degradation contributors. In this study, we prepared 4H-SiC Merged-PiN-Schottky (MPS) bare dies (650V/10A) with known basal plane dislocations (BPDs) and SFs to evaluate their impact on performance under PCmsec stress. The samples, soldered and Al-bonded on Cu-Si3N4-Cu substrates, were subjected to fast switching in a millisecond to achieve high current density (J) while maintaining low chip junction temperatures (Tvj). The PCmsec stress condition involved a heating time ton = 1 ms and a cooling time toff = 100 ms, as shown in Fig. 1(a). During the PCmsec stress, VF is continuously measured during the heating and cooling phases with high-speed measurement cards in the testbench, applying a 30 mA measurement current (Imeas). Shortly after the heating phase, VF data from 25 – 200 μs was used to extrapolate Tvj, max, using the DUT as a temperature sensor via the Vj (T) method [2]. Before the next heating phase at 100 ms, when the chip reaches ambient temperature (Ta), VF data is used to extrapolate the Tvj, min. As shown in Fig. 1(b), under this condition a high J = 2550 A/cm² was achieved well triggering the device into bipolar operation while thermal degradation is controlled with a Tvj, max = 130 °C well below the chip's solder liquidus point ( 240 °C) and the device Tj max = 175 °C. In contrast, when subjected to 10 ms square pulses almost similar to the condition in [3], the chip's temperature rose to > 520 °C at the same current density, approaching the melting point of aluminum (Al), as shown in Fig. 2(a). This resulted in the chip's destruction and major degradation of the solder interconnects within a few seconds of testing. The transition from the heating phase to the cooling phase introduces switching transients up to the first 25 μs, causing inaccurate Tvj, max measurement. To validate the Tvj, max extrapolation, FEM simulation was performed. The temperature averaged on the chip surface was evaluated as the numerical estimated Tvj, max. At the end of the heating phase, a deviation of 46 °C is shown between the testbench extrapolation and simulation at cycle 9321, as seen in Fig. 2(b). However, using an oscilloscope with a higher sampling rate of 1 μs, the temperature difference aligns closer to the simulated value (~10 °C), ensuring it remains within the acceptable limit. To assess degradation contributions, the diodes went through three post-stress static electrical characterizations: (i) via bond wires, (ii) using a needle probe and not the bond wires and, (iii) again via bond wires to confirm consistency, as shown in Fig. 3. Results indicated deviations between measurements with and without bond wires, underlining the influence of thermal degradation. Photoluminescence (PL) results confirmed bipolar degradation occurring at J > 3.5 times the J nominal value. Overall, a VF shift of below 10% at high current (45A) was observed after subjecting the devices to 100k cycles (~100 seconds) at 2295 A/cm2. In such assembly, the main part of this shift was attributed to bond wire degradation, while the remaining part was linked to top-side Al–power metal reconstruction and recombination-induced stacking faults (SF) causing bipolar degradation. No difference was observed for device rated current of 10 A. Further details will be provided in the full paper.

ABSTRACT. In overcurrent turn-off events, the SiC MOSFET can be subjected to excessive current levels beyond its rated specification. In this work, the overcurrent turn-off robustness limit of SiC MOSFETs from three manufacturers (M1, M2 and M3) was studied up to very high turn-off currents to find the destruction and failure type. All the devices were able to withstand higher overcurrent turn-off and a positive gate-source voltage in the range of 42V to 53V. The main failure for all the devices was the gate damage, indicated by increased gate leakage current. Further, the impact of the negative gate-source voltage on the overcurrent turn-off ruggedness strongly varies for different manufacturers. The SiC MOSFETs can withstand very high positive gate-source voltages under overcurrent turn-off without any degradation in their electrical parameters up to their critical limit.

ABSTRACT. In this work, it is revealed that the well-known S1 defect level, assigned to the Si vacancy (VSi) in 4H-SiC [1], consists of up to three contributions, two of which are related to carbon antisite-vacancy (CAV) pair structures. The defects were identified by consistent defect characteristics, namely the trap level EC − ET with respect to the conduction band bottom (EC being the energy of the conduction band edge), the capture cross-section σ , determined by admittance spectroscopy (AS), and hybrid density functional theory (DFT) calculations. High-resolution AS was used to analyze intrinsic electrically active defects in various 4H-SiC samples. For comparison of characteristics and identification of the underlying defects, deep-level transient spectroscopy (DLTS) and, complementary, DFT calculations were performed. Differently grown, non-commercial 4H-SiC samples of type A, B, and C with Schottky contacts based on specific growth parameters were selected (see Ref. [2] for growth parameters and Fig. 1 (b) for doping concentrations ND). While the epi(taxial)-layers of type A and B were (0001) oriented and grown 4° off-cut towards the [11 ̄20] direction, sample type C was grown on-axis along the [11 ̄20] direction. Additionally, commercial 1.2 kV Schottky diodes purchased from CREE / Wolfspeed were analyzed (sample type D). Fig. 1 (a) shows an example of a conductance spectrum for sample type B. The maxima of the conductance at the different temperatures follow Arrhenius behavior, allowing to calculate the trap level EC − ET, the capture cross-section σ , and the defect density Nt of the trap. The defect characteristics measured by AS and DLTS are summarized and compared in Fig. 1 (b). Clearly, the σ and EC − ET of Z1/2 is quite well comparable between the two measurement techniques. However, significant differences between the results from AS and DLTS, especially in the capture cross section, are found for the level assigned to S1. The S1 defect was also detected in sample type D. In order to further investigate its details, one sample was exposed to a 1.8 MeV proton beam of 1 × 1012 cm−2 fluence at an angle of 8◦ with respect to the surface normal to avoid channeling. In Fig. 2, two frequency and temperature dependent conductance peaks (cf. Peak I and III) are clearly visible at −1 V DC bias for the (a) non-irradiated and (b) irradiated sample. A shoulder between both peaks of the non-irradiated sample (cf. Peak II), which becomes distinct after the irradiation, indicates a third contribution. Using the conductance maxima, the defect characteristics of all three contributions are found to be in the range of the literature values for S1. [3] The relatively small capture cross-section of Peak III indicates a low probability of capturing another electron (the majority charge carrier in n-type SiC) into this defect configuration. Therefore, an assignation to the triple-negatively charged silicon vacancy is reasonable. For Peak I and II, the σ has been determined to be about 3 orders of magnitude larger than for Peak III. Here, the probability of capturing or releasing another electron is higher. Peaks I and II are, therefore, considered to be contributions from CAV-type of defects, as their transitions are anticipated to involve the neutral state [4]. From hybrid DFT studies we found that CAV and VSi defect configurations are separated by high energy barriers (> 3 eV), which could explain the formation of both structures under growth (non-equilibrium) conditions [4]. Besides calculating formation energies and charge transition levels of CAV and VSi, the carrier capture kinetics was investigated from first-principles. Here, we calculated the coefficients and cross-sections for the capture of free-electrons at CAV and VSi traps [5]. Table 1 collects the defect characteristics for both, AS measurements and hybrid DFT calculations. While the results support the hypotheses provided above, a deeper analysis is presented in the final paper.

ABSTRACT. The silicon vacancy (VSi) in 4H silicon carbide (4H-SiC) is a well-known single photon emitter and spin center, and a strong contender for applications in a variety of quantum technologies, including quantum computation, communication networks, and quantum sensing [1, 2]. Schottky barrier diodes (SBDs) based on SiC have been studied with photoluminescence (PL), and the results show an increase in the emission intensity of the VSi in the space charge region (SCR), suggesting the possibility to manipulate the charge state occupation by controlling the band-bending [3]. Furthermore, transitions between the bright and so-called dark states (q = 0, −2, −3) are suspected to occur when an electrical bias is applied, however, the dark states cannot be observed with PL. Here, low-energy muon-spin spectroscopy (LE-μSR) measurements were performed on an SiC-SBD, to directly probe the SCR with nanometer depth-resolution. In the LE-μSR experiment, a beam of positive muons (μ+) is implanted in the sample to obtain information about the magnetic and electronic environment of the material. The final muonium state depends on the defects present and the doping type and concentration in the material [4,5]. In the case of the VSi, the complex formed with the μ+ serves as a probe of the charge occupation of the defect [6]. The SBD sample was prepared on an n-type SiC epilayer purchased from CREE/Wolfspeed with 10 μm thickness and doping concentration ND =1 × 1017 cm−3, which was irradiated with protons to a fluence of 1× 1014 cm−2. After irradiation, a 20 nm Al layer was deposited on SiC. The sample was annealed at 425 ◦C for 30 minutes, to obtain a detectable concentration of VSi (∼3.0 × 1015 cm−3) but reduce the VC concentration (∼3.7 × 1015 cm−3) below the sensitivity level of LE-μSR for this defect [6,7]. The concentration of the defects was obtained using deep-level transient spectroscopy (DLTS). As shown in Fig. 1 a), by using μ+ implantation energies E in the range of 2–20 keV, it is possible to probe the Al layer and the SiC epilayer up to a depth of ∼130 nm. Fig. 1 b) shows a full energy scan, where at 2 keV to 5 keV the Al layer is probed, and the diamagnetic fraction FD is high due to Mu+ final state in the metal. Between E = 6 and 20 keV, the SiC epilayer is probed where Mu− is expected to form for such a doping concentration. In addition to the conventional LE-μSR setup, an external electric bias was applied to manipulate the band-bending and width of the SCR. The measurements with applied electric field were performed at 10 K, in freeze out regime of carriers, and 100 K at which ionization of the donors in SiC is about 50%. At 100 K (Fig. 2 a)) the applied reverse bias (−0.6 V) causes a drop in FD in the probed region, suggesting an increase in the SCR width, as expected. Similarly, a forward bias (0.4 V) increases FD, due to Mu−formation as free electrons are pulled towards the interface and the SCR becomes narrower. At this temperature, the changes in the VSi charge state are not directly observed due to the presence of free electrons, but these results highlight that band bending in the SBD can be induced by biasing. The measurements at 10 K (Fig. 2 b)) show an effect only when an applied forward bias is applied, with a reduction of FD, at the expense of neutral Mu0 formation. At a bias of 0 V and −0.6 V, the VSi charge state could. therefore, be q = −1 or q = −2, but no clear distinction is possible from the muon signal. Interestingly, at a bias of 0.4 V, indeed a charge transition to q = −3 seems to be possible, and only the filling of this state allows for an electron pick-up to form the Mu0 state.

ABSTRACT. Irradiation of semiconductor substrates by medium to high energy protons is a well-established technique useful for localized control of doping concentration and charge carrier lifetime. While in the past decades it has been extensively used in silicon-based electronics engineering, it still represents matter of discussion in relation to the new generation wide band-gap materials, such as 4H-SiC (silicon carbide). Proton irradiation of 4H-SiC leads to formation of electrically active defects, where those associated with the carbon vacancy (VC) have been identified as the main electron lifetime killers [1, 2]. Intentional creation/annihilation of charge carrier traps, a practice known as defect engineering, is becoming an integral part of 4H-SiC based power device manufacturing process as it enables precise control of electrical properties in ultimate devices. An aspect that has not yet been explored in detail is the control of implantation profile shape in channeling proton implants. The 4H-SiC has been found highly suitable for channeling implantation of conventional dopants (like B, N, Al, P) [3], giving access to box-shaped doping profiles with lower amount of irradiation induced damage. While analogous results are expected for protons, and there is a quite significant interest in developing this technology for defect engineering purposes, to date there are no consistent data in the literature concerning with channeling implantation of protons in 4H-SiC substrates. In this study, the effects of ion channeling on the depth distribution of medium energy proton implants in epitaxial 4H-SiC were investigated. N-type 4H-SiC epilayer, grown on the (0001) plane, with a nominal off-cut angle of 4° toward the [1120] direction, was implanted with 350 keV protons, with beam alignment ranging from [0001] channeling direction to random conditions. Samples were aligned and implanted in an RBS chamber, using low to medium doses of protons. Hydrogen depth profiles of medium dose implants (5e14 cm-2) were successfully measured by Dynamic SIMS, by applying the pre-sputtering method described in [4, 5, 6]. Defect depth profiles of Z1/2 (VC) and S1 (VSi) electron traps of low dose implants (5e9 cm-2) were measured by Deep Level Transient Spectroscopy (DLTS). Electrical and elemental depth profiles were then combined to obtain information about the effect of ion channeling on the generation of defects in the implanted volume. The obtained results show that channeling implantation of protons in high quality 4H-SiC epilayers produces a very low degree of damage, minimizing the occurrence of the random peak and leaving the channeled region relatively free of defects. Such features make the technique suitable for discrete profile shape adjustments and peak depth control by only playing on the beam alignment conditions, thus representing a valuable means for high precision localized in-depth control of defects.

ABSTRACT. Semiconductor devices based on gallium nitride (GaN) have attracted significant attention for a variety of high power and high frequency applications [1]. Among the wide range of devices based on GaN, Schottky diodes have been researched extensively for the past two decades [2-3]. They show excellent performance due to their high critical breakdown field strength and high-temperature resistance. Recently, analytical techniques such as electrically detected magnetic resonance (EDMR) and near-zero field magnetoresistance (NZFMR) have been successfully utilized to identify the roles point defects play in semiconductor device physics [4]. We report on EDMR and NZFMR studies on GaN Schottky diodes. To the best of our knowledge, these results are the first EDMR and NZFMR results ever reported on GaN Schottky diodes. In this work, n-type GaN Schottky diodes from [5] were utilized with Rhenium contacts deposited by electron-beam evaporation and sputtering. An intense isotropic single line with g = 2.0025(±0.0003) has been observed at low (85 MHz, and 500 MHz, see Fig. 1-2.) and high frequency (9.237 GHz, see Fig. 3.) at moderate forward bias (0.6 V). The measurements were carried out at room temperature. The intensity of the EDMR signal increases monotonically by about an order of magnitude with forward bias from 0.6 to 1.4 V. No signal was detectable with reversed bias. The line-width of the EDMR single line at all measured frequencies, that is 85 MHz, 500 MHz and 9.2 GHz, is about 12 G. This indicates that the line- width is likely due to hyperfine interaction with nearby magnetic nuclei. The EDMR and NZFMR signals were present only in diodes with Re-sputtered contacts and no signal was found in diodes with Re contacts deposited by E-beam evaporation in devices with the nearly identical ideality factors (1.03 and 1.02 respectively). Using electron paramagnetic resonance (EPR), a narrow single line with a similar g-factor (g = 2.0026) was previously observed in AMMONO GaN crystals and Mg-doped GaN epitaxial layers by [6], and was tentatively ascribed to a deep acceptor. These results indicate that NZFMR and EDMR measurements will provide fundamental understanding of electronic transport in GaN-based Schottky diodes. This work was funded by the Office of Naval Research under Grant N00014-22-1-2462 and supported by the Air Force Office of Scientific Research under Award No. FA9550-22-1-0308. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Office of Naval Research or the United States Air Force. Approved, DCN# 0543-1813-24. [1] S. J. Pearton et al., J. Appl. Phys. 86, 1–78 (1999) [2] Yu Shao et al., J. Phys. D: Appl. Phys. 57 093001 (2024) [3] Noorah A Al-Ahmadi., Mater. Res. Express 7 032001 (2020) [4] C. J. Cochrane and P. M. Lenahan, J. Appl. Phys. 112, 123714 (2012) [5] A. Molina and S. E. Mohney, Mater. Sci. Semicond. Process. 148, 106799 (2022). [6] M. Palczewska et al., MRS Internet Journal of Nitride Semiconductor Research Vol. 3, 45 (1998)

ABSTRACT. The impact ionization coefficient of carriers is an important physical property for predicting and designing the breakdown voltage of power devices. This study theoretically investigates the behaviors of the impact ionization coefficients in 4H-SiC, including their anisotropy and temperature dependence, by full-band Monte Carlo simulations. The mechanisms behind these properties are discussed focusing on the band structures and the carrier distribution functions.

ABSTRACT. Carrier transport properties such as mobility and drift velocity are the basic information of materials to predict the device performance and to understand the physical phenomena. Although the mobility in SiC has been intensively studied including its anisotropy, the previous research on the high-field drift velocity is limited to the in-plane direction of the c-face, and there are few reports on that along the c-axis. In this study, the authors determined the electron drift velocities parallel and perpendicular to the c-axis over a wide electric field range (1 – 200 kV/cm) by a conductance technique using SiC(11-20) samples and discussed its anisotropy.

ABSTRACT. The availability of ultra-thick (>100 μm) 4H-silicon carbide (SiC) epitaxial layers has already enabled high voltage (> 10 kV) devices, such as diodes [1], insulated-gate bipolar transistors (IGBTs) [2] and thyristors[3] for applications such as HVDC grid level power transfer. A requirement for good performance in these high voltage devices is a high carrier lifetime τeff (>1 µs) throughout the epitaxial thickness. This material system is typically grown with a τeff around 1 µs, which has been shown to be limited by the Z1/2 defect level. τeff enhancement is typically performed by thermal oxidation or carbon implantation. However, the enhancement throughout the drift thickness is diffusion limited due to the low diffusion coefficients of carbon and oxygen in SiC. Common carrier lifetime measurement techniques such as microwave-detected photoconductance decay (µPCD) only probe the near-surface region of the epilayer. Hence they provide only limited information on thick layers especially after enhancement. Here, we present a technique to assess the bulk quality of thick layers directly. Photoexcited muon spin spectroscopy (photo-µSR) has been suggested as a method to study the quality of crystalline silicon by assessing charge carrier lifetime [4]. It is based on the implantation of (anti)muons into the sample and analysis of the positrons emitted upon their decay. Muons can be implanted fully spin polarized and when deposited into semiconductors they interact with the electron gas to form the hydrogen isotope muonium. Upon interaction with the (random) electron spin, the initial muon spin is either maintained or lost, whenever muonium is formed or the electron is exchanged. This impacts the direction of positron emission, and our analysed quantity is the rate of depolarization after a muon implantation pulse. This depolarization rate scales with electron concentration, which can be influenced by illumination. Variation of illumination intensity or the delay between pump (laser) and probe (muons) allows analysis of carrier dynamics and inference of carrier lifetime. In this work we applied both approaches to the investigation of 100 µm thick epitaxial 4H-SiC layers after various thermal pretreatments. Epitaxial layers were grown at Warwick on 100 mm-diameter, 4° off-axis, SiC wafers using an LPE ACiS M8 chemical vapour deposition reactor. Low doped (< 2e1014cm-3) 4H-SiC homoepitaxial layers were grown at 1550 °C at a nominal thickness of 100 µm and using Trichlorosilane (HCl3Si, TCS) and Ethylene (C2H4) with a C/Si ratio of 0.796.We examined four distinct samples with photo-µSR: one in its untreated state (labelled as-grown), and three samples (labelled Ox-S1, Ox-S7, and Pass-S4) subjected to post deposition treatments. After RCA cleaning, thermal oxidation was conducted on all three samples at 1400 °C in a 1:4 O2:Ar atmosphere for 4 h in a high-temperature furnace, followed by a 10% HF SiO2 etching treatment for 5 min. The Ox-S7 sample underwent this process again followed by annealing at typical post-implantation activation temperatures (1750 °C for 4 h in Ar ambient). Sample Pass-S4 underwent phosphorus pentoxide (P2O5) deposition at 1,000°C after a dilute nitrous oxide (N2O) thermal growth [5]. Both samples underwent a 10 % HF etching treatment remove the SiO2 layers. τeff,PCD was assessed prior to and after muon exposure via µPCD in a custom Freiberg Instruments spotMDP setup. We condense the photo-µSR measurements performed on the samples to the total muon spin asymmetry decay difference between dark and illuminated measurements, as illustrated in Fig.1(b). This quantity encompasses the impact of carrier density Δn on the muon spin asymmetry. We compare this quantity to numerical simulation of the experiment to extract τeff,µSR. Even with simple assumptions (e.g. negligible interface recombination) we achieve good agreement between experimental data and simulation, as shown in Fig.2. We compare our results to µPCD measurements before and after muon exposure and get an overall good agreement as seen in Fig.3. Due to the surface-near signal detection, τeff,PCD is not very representative of deeper regions of the epitaxial layer. The photo-µSR method on the other hand is sensitive to what region or depth the muons are implanted in, which can be influenced through the use of degrader foils, as discussed e.g. by Murphy et al. [6]. This allows to assess τeff of epilayers with more practically relevant weighing compared to µPCD.

ABSTRACT. While ion implantation is commonly carried out for p-type doping of 4H-SiC, high dose Al implantation leads to the formation of point defects that can harm the mobility of carriers in the channel of 4H-SiC MOSFETs [1,2]. For this reason, it is important to investigate species other than Al, for p-type doping of SiC. In this study, we present an ab-initio study of the electronic properties of acceptor impurities, with valency two or three, in both 4H-SiC bulk and in SiO2/4H-SiC interfaces. Ab initio calculations were performed on a 128-atom 4H-SiC supercell and a 100 atom SiO2/4H-SiC slab. For the latter, a 20 Å vacuum was set along the c-direction and dangling bonds were passivated by H. We used Troullier-Martins pseudopotentials and the Perdew-Burke-Ernzerhof (PBE) form of the generalized gradient approximation (GGA) for the exchange-correlation potential. A double- plus polarization was used as atomic orbital basis set. Both systems were relaxed until the forces on the atoms were <0.02 eV/Å. Formation energies (Eform) were estimated using the methodology described in Ref. [3]. In fig.1, we show the Eform of the Mg, Zn and Sc substitutional impurities sitting at Si(k) sites and bonded to either single (N), double (O) or triple (Cl) donor impurities. For Mg (fig.1(a)), the isolated substitutional impurity gives rise to two acceptor levels, at 0.6 eV and 1.14 eV above the valence band edge (EV). When a complex with N is formed (MgSiNC), a single donor level arises (EV+0.2 eV). The same occurs for MgSiOC, while for MgSiClC the (3-/2-) level arises close to the edge of the conduction band (EC). A similar effect can be seen when ZnSi bonds to N, O or Cl (fig.1(b)), with the difference that, unlike MgSi, ZnSi shows the presence of a donor level (EV+0.3 eV). On the other hand, ScSi (fig.1(c)) shows an amphoteric behavior, with a donor (EV+0.50 eV) and an acceptor (EV+0.77 eV) level in the bandgap. Its complexes with donors give rise to shallow double donor levels close to EV and also shallow acceptor levels close to EC. Estimation of the binding energy of the studied complexes is in progress. Since we observed that both Mg and Zn have a similar electronic behavior, we focused on the electronic properties of Mg and Sc in an abrupt SiO2/4H-SiC interface. First, we observe that the main contributions to the density of states (DOS) on the valence and conduction bands are due to the 2p orbital of C atoms and 3p of Si atoms. Although not shown in here, when MgSi is present in the oxide, no states can be seen in the bandgap (Egap) while ScSi gives rise to a state at midgap. On the other hand, if MgSi or ScSi are at the interface, new states arise in the proximity of EV, due to the formation of C dangling bonds. When analyzing the MgSi-CO complex (fig.2(a)), we observe three states at EV+0.1 eV, EV+0.8 eV and EV+2,0 eV due to the dangling bonds of the Mg first neighbors (C atoms). When MgSi is in the oxide (fig.2(b)), the MgSi-CO complex gives rise to a level at EV+1.8 eV. Regarding the ScSi-CO complex, when ScSi is at the interface (fig.3(a)) or in the SiO2 (fig.3(b)), one state at EV+1.2 eV arises, together with shallow states close to EV. To conclude, we analyzed the electronic properties of substitutional Mg, Zn and Sc atoms in bulk 4H-SiC and at the SiO2/4H-SiC interface, by first-principles calculations. We found that while Mg behaves as a deep acceptor, Zn and Sc show an amphoteric behavior. Such a behavior is also found when the impurities bind to single, double and triple donors. When Mg or Sc are incorporated at the interface or in the oxide, this results in the formation of C dangling bonds which lead to the rise of shallow states close to the valence band. This suggests that the presence of impurities such as Mg, Sc or Zn during 4H-SiC MOSFET processing can be detrimental for the mobility of charge carriers in the device channel.

[1] T. Kobayashi et al., APL 108, ,152108 (2013). [2] T. Kobayashi et al., JAP 121, 145703 (2017). [3] C. Freysoldt et al., PRB 93, 165206 (2016) and references therein.

ABSTRACT. Accurate performance prediction of SiC MOSFETs using TCAD necessitates models for both impact ionization coefficients and mobility at SiC MOS interfaces; the former has been previously reported by us. However, a standardized mobility model for SiC MOS interfaces has not yet been established due to the complex physics inherent to SiC MOS interfaces. To address this gap, we have developed a physically grounded and reliable mobility model for SiC MOSFETs in TCAD, which is applicable under a wide range of experimental conditions. This model is derived from our comprehensive investigations into the physics that govern mobility at SiC MOS interfaces, including the energy distribution of interface traps near the conduction band and the elucidation of the dominant scattering mechanisms affecting mobility.

ABSTRACT. Channel mobility is one of the most critical parameters in 4H-SiC based Power MOSFETs and contributes a significant fraction of device on-state resistance (RON). 4H-SiC has a hexagonal crystal structure and the bulk mobility is anisotropic, larger in the (0001) direction (parallel to the a-face or m-face), and lower perpendicular to that (along Si-face directions). Such an anisotropic nature is also observed in channel mobilities when channels are formed along these crystallographic orientations. Experimentally, it has been shown that the a-face channel mobility is much higher compared to the Si-face, making a-face a very attractive option for a wide range of applications in the power electronics market. However, to the best of our knowledge, Technology Computer Aided Design (TCAD) modelling of the a-face channel mobility is missing in the literature. In this paper, we present a well calibrated a-face channel mobility model that shows an excellent match with the available experimental data and further provides critical insights into the anisotropic nature of channel mobility in 4H-SiC MOSFET structures.

ABSTRACT. The design of multi-chip power modules is challenging due to circuit asymmetries that can lead to unequal switching losses of parallel-connected devices and hence, uneven temperature distribution. Furthermore, it can potentially cause oscillation of control signals, which, in turn, leads to ringing within the current switching waveforms. Circuit asymmetries come from circuit layout parasitics defined by module design and a parameter spread of SiC power MOSFET dies due to tolerances in the device manufacturing process. Depending on the device design and gate circuit, ringing can violate stability causing a destructive failure of the power devices. Accordingly, dynamic performance of multi-chip SiC power MOSFET modules should not only be characterized by switching losses but also in terms of ringing. This paper aims to evaluate how the parameter spread of SiC power MOSFETs affects the switching stability for a given layout design. The developed simulation framework involves Technology Computer Aided Design (TCAD) process and device modeling, time domain switching circuit simulations of SiC power MOSFETs connected in parallel taking into account a virtual prototype of an in-house-designed Double Pulse Test (DPT) setup with two parallel-connected MOSFETs, and the corresponding frequency domain simulations performed to evaluate quantitatively stability. The proposed modeling procedure will lead to the guidelines for pairing devices based on their electrical performance and circuit layout design, with the aim to ensure reliable and long-lasting operation of multi-chip power modules.

ABSTRACT. Silicon Carbide (SiC), a wide bandgap semiconductor material, has attracted worldwide attention in power MOSFETs with distinct properties, such as low leakage current, high operating temperatures, and a high critical electric field. A precise compact model for a SiC power MOSFET is crucial to validating those benefits in power electronics applications using circuit simulations. Here we introduce a SPICE model for a SiC power MOSFET, designed with physics-based sub-circuit components. A planar SiC vertical power MOSFET structure is decomposed into sub-circuit components such as n-channel MOSFET (nMOS), junction-FET (JFET), and drift resistor (RDrift) as shown in Fig. 1. The components provide current-voltage simulations, which are used to define physics-based SPICE model parameters of the sub-circuit model components (Fig. 2). As shown in Fig. 3, the nMOS is represented by a BSIM3 component, where the modeling of the transconductance is important to determine static and dynamic simulations. The JFET is expressed as a two-terminal resistor (RJFET) based on the TCAD-based physical parameters of doping concentration, channel area (JFET area), and electron mobility. The RDrift is calculated based on TCAD calibration, which is independent of the junction capacitance. A Compact Model Coalition (CMC) model represents the body diode in the SPICE model. Cgs, Cgd, and Cds are analytically interpreted to capture gate and drain-bias dependence. In the SPICE model, p-well resistors are incorporated at the connection between the nMOS and the body diode, influencing the nMOS threshold voltage due to MOSFET body effect [5]. Based on TCAD analysis and physics-based understanding of the power MOSFET structure, the physics-based SPICE sub-circuit components are developed to represent device behaviors for junction temperature ranging from 25℃ to 175℃. In the switching simulations (shown in Fig. 4), the turn-on, miller plateau, and turn-off transient behaviors are analyzed with each component model characteristic, enabling the regulation of the power switching performance via physics-based parameters such as channel mobility, SiC doping concentration, and junction capacitances. In summary, we analyzed the planar SiC power MOSFET structure using TCAD and translated into the physics-based SPICE model. In the full paper, the TCAD-based sub-circuit components used for the development of the SPICE components will be discussed in detail. The switching transient simulations provide the relationship between temperature and the time derivative of the drain-source voltage (dV/dt). The proposed SPICE model enables computationally-efficient and physically meaningful electrical characteristics, providing the potential to explore further applications of SiC power MOSFETs.