EPEPS 2026: 35TH IEEE CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS
PROGRAM

Days: Sunday, October 18th Monday, October 19th Tuesday, October 20th Wednesday, October 21st

Sunday, October 18th

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Monday, October 19th

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10:10-11:10 Session 10: Modeling and Simulation
10:10
Constraining Poles of Parameterized Macromodels (abstract)
10:30
An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications (abstract)
10:50
Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems (abstract)
14:00-15:20 Session 13: Packaging Research from APAC Region
14:00
Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption (abstract)
14:20
Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context (abstract)
14:40
Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression (abstract)
15:00
Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards (abstract)
15:40-17:00 Session 14: Machine Learning for Interconnect Modeling
15:40
Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer (abstract)
16:00
Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels (abstract)
16:20
Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics (abstract)
16:40
Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage (abstract)
17:00-18:30 Session 15: Poster Session
Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping (abstract)
Active Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines (abstract)
AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling (abstract)
Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet (abstract)
SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios (abstract)
Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity (abstract)
Package-level thermal optimization for high-power-density AI accelerators (abstract)
Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate (abstract)
8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology (abstract)
Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs (abstract)
Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM (abstract)
Tuesday, October 20th

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10:00-11:00 Session 17: AI for Electronic Design Automation
10:00
Efficient Agentic Touchstone Analysis via DSL (abstract)
10:20
PDGChat: A Fine-Tuning Dataset For LLMs (abstract)
10:40
Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference (abstract)
11:20-12:20 Session 18: Heterogeneous Integration and HBM
11:20
Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects (abstract)
11:40
Signal Integrity Design and Optimization of High-Bandwidth Memory Test System (abstract)
12:00
Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces (abstract)
13:50-15:10 Session 21: Signal Integrity 1
13:50
Mitigating the Impact of Glass Weave on Bidirectional High-Speed Signaling (abstract)
14:10
A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure (abstract)
14:30
A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions (abstract)
14:50
Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links (abstract)
15:30-16:50 Session 22: Signal Integrity 2
15:30
Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers (abstract)
15:50
Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM) (abstract)
16:10
Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver (abstract)
16:30
Simulation-driven Adaptive Estimation of Worst-case Power Noise (abstract)
16:50-18:10 Session 23: Power Integrity
16:50
Design of Integrated Voltage Regulators using a Generative Waveform Surrogate (abstract)
17:10
Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects (abstract)
17:30
Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery (abstract)
17:50
Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery (abstract)
Wednesday, October 21st

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09:00-10:00 Session 24: Electromagnetics
09:00
Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework (abstract)
09:20
Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects (abstract)
09:40
Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme (abstract)
10:00-11:00 Session 25: Thermal-Mechanical Analysis
10:00
Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design (abstract)
10:20
Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems (abstract)
10:40
Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment (abstract)
11:30-12:50 Session 26: RF and Quantum Interconnects
11:30
Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter (abstract)
11:50
Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction (abstract)
12:10
Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K) (abstract)
12:30
Harvesting Waste Heat for Autonomous Reconfigurability in VO2-Based spSIW Interconnect (abstract)