Advanced Packaging for High-Speed Chiplet Interconnects: Technologies, Methodologies, and Standards (abstract)

From Co-Packaged Optics to Co-Packaged Photonic Systems (abstract)

Signal and Power Integrity Analysis for Next-Generation 2.5D/3D Advanced Packaging (abstract)

Opportunities in NeuroAI: A Hardware-Software Co-Design Perspective (abstract)

Gaussian Processes for Data-Efficient Uncertainty Quantification, Optimization and Active Learning (abstract)

Electromagnetic Modeling of 3D Integrated Circuits with Integral Equation Methods (abstract)

AI Meets Chips and Packaging: From Prediction to Generation (abstract)

Constraining Poles of Parameterized Macromodels (abstract)

An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications (abstract)

Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems (abstract)

Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption (abstract)

Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context (abstract)

Physics-Guided Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression (abstract)

Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer (abstract)

Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels (abstract)

Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics (abstract)

Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage (abstract)

Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping (abstract)

Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines (abstract)

AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling (abstract)

Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet (abstract)

SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios (abstract)

Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity (abstract)

Package-level thermal optimization for high-power-density AI accelerators (abstract)

Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate (abstract)

8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology (abstract)

Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs (abstract)

Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM (abstract)

Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards (abstract)

Circuits and Packaging for Next Generation AI Datacenters (abstract)

Efficient Agentic Touchstone Analysis via DSL (abstract)

PDGChat: A Fine-Tuning Dataset For LLMs (abstract)

Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference (abstract)

Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects (abstract)

Signal Integrity Design and Optimization of High-Bandwidth Memory Test System (abstract)

Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces (abstract)

Mitigating the Impact of Glass Weave on Bidirectional High-Speed Signaling (abstract)

A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure (abstract)

A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions (abstract)

Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links (abstract)

Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers (abstract)

Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM) (abstract)

Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver (abstract)

Simulation-driven Adaptive Estimation of Worst-case Power Noise (abstract)

Design of Integrated Voltage Regulators using a Generative Waveform Surrogate (abstract)

Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects (abstract)

Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery (abstract)

Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery (abstract)

Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework (abstract)

Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects (abstract)

Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme (abstract)

Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design (abstract)

Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems (abstract)

Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment (abstract)

Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter (abstract)

Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction (abstract)

Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K) (abstract)

Harvesting Waste Heat for Autonomous Reconfigurability in VO2-Based spSIW Interconnect (abstract)