EPEPS 2026: 35TH IEEE CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS

A
Abdelzaher, Salma	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery
Achar, Ramachandra	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
Achar, Ramachandra	Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems
Ahmed, Mohammed Farhan	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Altaher, Mohammad Sanad	Active Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines
An, Hyunjun	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Aoki, Masaaki	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
Arora, Geetansh	8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology
Ashida, Kishio	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling
Aygün, Kemal	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
B
Bae, Jaegeun	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM) Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Bakir, Muhannad	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
Bradde, Tommaso	Constraining Poles of Parameterized Macromodels
C
Carlucci, Antonio	Constraining Poles of Parameterized Macromodels Simulation-driven Adaptive Estimation of Worst-case Power Noise
Chada, Arun	Efficient Agentic Touchstone Analysis via DSL
Chang, Shih-Chieh	Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context
Chatterjee, Soumyadeep	PDGChat: A Fine-Tuning Dataset For LLMs
Chen, Dekang	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
Chen, Xu	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
Chen, Xuan	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer
Cheng, Chen	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
Cho, Hyungho	Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Chu, Yunhui	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Covolo, Davide	Simulation-driven Adaptive Estimation of Worst-case Power Noise
Cusano, Michele	Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer
D
Darweesh, Raheeq	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
De Araujo, Stefan	Efficient Agentic Touchstone Analysis via DSL
Doyle, Matt	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
F
Franzon, Paul D.	Package-level thermal optimization for high-power-density AI accelerators PDGChat: A Fine-Tuning Dataset For LLMs
Fu, Peng	Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping
G
Gharib, Mohamed	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery
Go, Dong-Jae	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
Goralka, Nick	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Grace, Dylan	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
Grivet-Talocia, Stefano	Constraining Poles of Parameterized Macromodels Simulation-driven Adaptive Estimation of Worst-case Power Noise
Gu, Yalong	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
Guo, Madeleine	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
Guo, Yuandong	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
H
Hamaguchi, Takashi	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression
Harubeppu, Yu	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling
Hejase, Jose	Mitigating the Impact of Glass Weave on Bidirectional High-Speed Signaling A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions
Hessling, Jan	Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
Hsu, Jimmy	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
Hu, Xinyi	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
Hwang, Chulsoon	Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects
I
Ikeguchi, Takashi	Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression
Iwabuchi, Akio	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
J
Javaid, Ahsan	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems
Joy, Soumitra	Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K) Harvesting Waste Heat for Autonomous Reconfigurability in VO2-Based spSIW Interconnect
Ju, Huafang	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
Jung, Changhyun	Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM
K
Karim, Ataul	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Kashyap, Priyank	PDGChat: A Fine-Tuning Dataset For LLMs
Kim, Byeongmok	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Kim, Joungho	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM) Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Kim, Kang-Wook	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
Kim, Keunwoo	Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Kim, Mun-Ju	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
Klarqvist, Karsten	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Kotikalapudi, Nikhil	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
Krishna, Ram	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
Kumar, Anuj	Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver
Kumar, Rahul	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
Kunieda, Toshiki	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
L
Lee, Gwantaek	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM) Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Lee, Hyuni	Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity
Lee, Junghyun	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption
Lee, Junghyun	Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Lee, Seungjae	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM) Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Lee, Yen Chun	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Li, Jiazhen	Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping
Li, Yongzhong	Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme
Lin, Han-Ting	Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter
Liu, Cheng-Wei	Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context
Luk, Clement	Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
M
Mahesh Rao, Karthik	Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
Mahmud, Md Sultan	Design of Integrated Voltage Regulators using a Generative Waveform Surrogate
Majnaric, Jeffrey	8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology
Manfredi, Paolo	Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer
Manna, Bibhas	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
Mathur, Anuj	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems
Meng, Fanhua	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
Mia, Md Zesun Ahmed	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
Min, Byung-Cheol	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
Miyamoto, Akiyasu	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression
Mochizuki, Akihiro	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
Molter, Michael	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
Murata, Chanz	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Mutnury, Bhyrav	Efficient Agentic Touchstone Analysis via DSL Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
N
Naghibi, Zohreh	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
Nakano, Nobuhiko	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
Nguyen, Chris	Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects
Noman, Md. Omar	Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K)
O
Ogawa, Sean	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate
Ogawa, Sean	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
Okhmatovski, Vladimir	Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects
Oladeinde, Adewale	A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions
Omar, Abdelrahman	Harvesting Waste Heat for Autonomous Reconfigurability in VO2-Based spSIW Interconnect
P
Palermo, Samuel	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
Panda, Sushil	Package-level thermal optimization for high-power-density AI accelerators
Park, Junho	Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Park, Sehoon	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure
Partin-Vaisband, Inna	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery
Paulik, George	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
Q
Qi, Shutong	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
R
Rahimzadeh Khorasani, Ramin	Design of Integrated Voltage Regulators using a Generative Waveform Surrogate
Rao, Vinay	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
Rosenbaum, Elyse	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
Rouf, Nirjhor	PDGChat: A Fine-Tuning Dataset For LLMs
S
Sadeghi, Ayoub	Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
Saha, Arnob	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
Satagopan, Venkat	Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
Schuster, Christian	Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
Sengupta, Abhronil	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
Sheikh Sofla, Sohrab	Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
Shengjuan, Zhou	Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet
Shimomura, Soshi	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression
Shivappa, Manjunath	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
Song, Chiho	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
Song, Wil Choon	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
Suh, Haeseok	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Suh, Haeseok	Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Swaminathan, Madhavan	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference Design of Integrated Voltage Regulators using a Generative Waveform Surrogate Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
T
Tan, Aik Hong	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
Tannir, Dani	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
Tesfai, Abel	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
Tobaben, Mathis	Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
Torreele, Maxim	Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework
Torun, Hakki	Mitigating the Impact of Glass Weave on Bidirectional High-Speed Signaling
Tripathi, Jai Narayan	Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver
Triverio, Piero	Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer
U
Uematsu, Yutaka	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression
V
Vande Ginste, Dries	Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework
Vanderstraeten, Emile	Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework
Victor, Ashita	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
W
Wander, Abhijit	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
Weisshaar, Andreas	Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter
Weller, Thomas	Active Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines
Wen, Yuejiang	PDGChat: A Fine-Tuning Dataset For LLMs
Wenzel, Robert	8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology
Y
Yang, Chaemin	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM) Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Yang, Pin-Yuan	Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context
Yang, Zhiping	Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects
Ye, Duye	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
Yeh, Yuting	A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions
Yoo, Kyung-Bin	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure
Yoon, Jiwon	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Yoon, Youngsu	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Yoshioka, Kentaro	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
Z
Zan, Mengen	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
Zhang, Hanyu	Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects
Zhang, Zhichao	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
Zheng, Ronnie	Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping
Zhou, Tingdong	8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology

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