EPEPS 2026: 35TH IEEE CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS

This page contains an index consisting of author-provided keywords.

2
2.5D/3D integration	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems
224G/448G SerDes	Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
224Gb/s	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
3
3D IC packaging	Package-level thermal optimization for high-power-density AI accelerators
A
Active learning	Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping
ADC-based receiver	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
Advanced package	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios
advanced packaging	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
Advanced packaging 3D integration	Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Ag sintered layer	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
Ag sintering chip attachment	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate
Agents	Efficient Agentic Touchstone Analysis via DSL
AI Data Centers	Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery
AlGaNGaN	Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
AMB sub strate	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate
AMEn solver	Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects
Automation	Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
B
balanced line	Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure
Bandwidth	A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions
bidirectional	Mitigating the Impact of Glass Weave on Bidirectional High-Speed Signaling
boundary element method	Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme
bridged-T coil (BTC)	Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter
Bump map	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios
C
channel allocation	Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
Chiplet	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet
chiplets	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
circuit ports	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
Co-optimization	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling
Co-packaged Optics	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
common-mode modulation	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
Compute-In-Memory system design	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
correlation	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
crosstalk	Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
Crosstalk Suppression	Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K)
Cryogenic	Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K)
Cu surface roughness	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate
current mode driver	Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver
custom base die	Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
D
D-stability	Constraining Poles of Parameterized Macromodels
D2D link	Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity
Data-driven macromodeling	Constraining Poles of Parameterized Macromodels
dataset	PDGChat: A Fine-Tuning Dataset For LLMs
DDR5 RDIMM	Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM
decoupling capacitor	Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Deep equilibrium model	Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems
Design space exploration	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling
Design Space Exploration (DSE)	Design of Integrated Voltage Regulators using a Generative Waveform Surrogate
die-to-die interconnects	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
differential tab structures	A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions
direct-attach copper cable	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
DNN inference	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
DSL	Efficient Agentic Touchstone Analysis via DSL
DTC	Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet
Dual side cooling	Package-level thermal optimization for high-power-density AI accelerators
E
electromagnetic modeling	Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects
Enhanced SNR	Balanced Line-based Ultra-wideband Channel with Enhanced SNR for 224G/448G SerDes Links
Eye diagram	Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios
F
fast Fourier transform	Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme
fatigue analysis	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
fiber-weave	Mitigating the Impact of Glass Weave on Bidirectional High-Speed Signaling
Filtering	Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K)
finite element analysis	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate
finite-volume modeling	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems
G
Gaussian process regression	Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
Gaussian processes	Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer
Generative AI	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling
Graphics processing unit	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption
Ground bounce	Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver
H
Harmonic Balance	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
HBF	Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity
HBM	Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity
HBM test system	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Heat Harvesting	Harvesting Waste Heat for Autonomous Reconfigurability in VO2-Based spSIW Interconnect
heterogeneous integration	Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context
high bandwidth flash	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption
high bandwidth memory	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
high current	Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects
High Density Interconnect (HDI)	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
high performance computing	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
High speed signaling	Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression
high-bandwidth memory	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
High-performance computing	Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery
high-speed channel	Mitigating the Impact of Glass Weave on Bidirectional High-Speed Signaling
high-speed interconnect	Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet
high-speed signalling	Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver
High-Step VR	Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery
I
impedance	A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions
Insertion Loss(IL)	Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards
Interconnects	Active Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines
interposer	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems
interposer channel	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption
J
jitter	Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
L
large language model inference	Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity
large language models	PDGChat: A Fine-Tuning Dataset For LLMs
Liquid Cooling	Package-level thermal optimization for high-power-density AI accelerators Active Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines
low-voltage differential signalling	Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver
LPDDR	Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
LPDDR5X	8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology
M
Machine Learning	Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
Machine Learning (ML)	Design of Integrated Voltage Regulators using a Generative Waveform Surrogate
Macromodeling	Simulation-driven Adaptive Estimation of Worst-case Power Noise
Measurement techniques	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
mechanical	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
memory interfaces	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
Method of Moments	Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects
millimeter wave circuits	Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter
minimum power loss	Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects
ML and AI-based approaches	Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context
ML and AI-based approaches to interconnect and packaging problems	Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
Model Order Reduction	Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design
Modeling	Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
Modeling and simulation	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
Moment-matching method	Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design
Multi-objective Bayesian optimization	Bayesian Optimization of Crossbar-Based Compute-In-Memory System Design for Efficient DNN Inference
Multi-physics	AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling
Multiconductor transmission lines	Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems
multifin devices	Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
multiphysics modeling	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
multiphysics simulation	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems
N
nanowire	Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework
Neural Networks	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
NMC	Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity
Noisy data	Constraining Poles of Parameterized Macromodels
Nonlinear circuits	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
O
on-chip passives	Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter
Optical I/O	Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics
optimal condition	Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects
P
P/N skew calibration	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
package	8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology
PAM-4 wireline transceiver	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
Parameterized macromodeling	Constraining Poles of Parameterized Macromodels
PDGs	PDGChat: A Fine-Tuning Dataset For LLMs
PDN	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
phase shifter	Systematic Synthesis of Ultra-Compact On-Chip E-Band 360° Phase Shifter
phase-locked loop	Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
Physics Based	Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
power consumption	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption
power delivery network	Equal Source Voltages for Minimum DC Conduction Loss in High-Current Power-Delivery Interconnects
power distribution network	Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
power gating	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems
Power Integrity	Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery Simulation-driven Adaptive Estimation of Worst-case Power Noise Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
projection	Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme
PSIJ	Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet
Q
Quantum systems: interconnection and packaging	Improved Signal Integrity Modeling for Quantum Flex Circuits via Low-Temperature Dk/Df Extraction
R
receiver equalization	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
Reconfigurable Interconnect	Harvesting Waste Heat for Autonomous Reconfigurability in VO2-Based spSIW Interconnect
Recurrent neural network	Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems
reinforcement learning	Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM
retimer-dependence reduction	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure
return path	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
S
SerDes	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
SiC power devices	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate
Signal and power integrity	Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context
Signal and power integrity issues	Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer Channels
signal integrity	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption Signal Integrity Design and Optimization of High-Bandwidth Memory Test System Fast Electromagnetic Analysis of Multiscale Structures Using MultiAIM with an Improved Projection Scheme Efficient Agentic Touchstone Analysis via DSL Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity 8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM
signal integrity recovery structure	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure
silicon interposer	Signal Integrity Design and Optimization of High-Bandwidth Memory Test System
Simulation	Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer PCBs
Simultaneous switching noise (SSN)	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios
SIPI	Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet
Spoof Surface Plasmon Polaritons	Rooftop SSPP Interconnect with Filtering and Crosstalk Suppression at Cryogenic State (77 K)
statistical eye simulation	Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
Steady state analysis	An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications
Surrogate model	Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression
surrogate modeling	Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage
T
TDP	Package-level thermal optimization for high-power-density AI accelerators
tensor train	Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects
Test Fixture	Active Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines
Thermal	Analysis on creep strain and fatigue resistance of Ag sintered bonding layers in SiC chip systems using Ag sintering chip-attachment
thermal distribution	Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power Consumption
thermal integrity	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems
Thermal Management	Active Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines
Thermal resistance	Package-level thermal optimization for high-power-density AI accelerators
thermal stress	Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB substrate
thermal sweep	Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping
Thermal-mechanical simulation	Component-Based Model Order Reduction of Thermal-Mechanical Analysis for Chiplet Design
time-dependent density functional theory	Investigation of Nanowire Crosstalk through an Ab-Initio EM/QM Simulation Framework
Time-Domain Vector Fitting	Simulation-driven Adaptive Estimation of Worst-case Power Noise
time-interleaved ADC	Common-Mode Sign-Based P/N Skew Calibration for 212.5-Gbps PAM-4 Wireline Receivers
Transformer neural network	Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems
Transient electrothermal co-simulation	Fast Transient Electrothermal Co-Simulation for Thermal-Integrity Analysis of Power-Gated 2.5D/3D Systems
transmission lines	Impact of Ground Bounce on Logic-HIGH in Differential Signalling: Case Study of a Current-Mode Driver
trigate transistors	Non-Uniform Channel Allocation in Multi-Fin GaN Tri-Gate Transistors for Package-Integrated Power Delivery
TX FIR tuning	Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping
U
UCIe	Physics-Informed Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process Regression Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects
Universal Chiplet Interconnect Express-Advanced (UCIe-A)	SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios
USB4	A Low-Power, Low-Cost USB4 Cable Using an Ultra-Wideband Signal Integrity Recovery Structure
V
Vanadium Dioxide	Harvesting Waste Heat for Autonomous Reconfigurability in VO2-Based spSIW Interconnect
Vertical Power Delivery	Model-Driven Design Exploration of Hybrid Voltage Regulators for Vertical Power Delivery
Vertical Power Delivery (VPD)	Design of Integrated Voltage Regulators using a Generative Waveform Surrogate
via interconnects	A Differential Tab Structure Design for Optimizing 200G+ PCB Via Transitions
Voltage supply noise	Voltage Supply Noise Analysis of Phase-Locked Loop (PLL) Structure in Custom Base Die of High Bandwidth Memory (HBM)
volume integral equation	Tensor-Train Accelerated Solution of Three-Dimensional Volume Integral Equations in Modeling of Optical Interconnects
W
wave ports	Dual-Referenced Circuit Ports for Hybrid Modeling and Correlation of HPC Memory Interfaces
Worst-Case Droop	Simulation-driven Adaptive Estimation of Worst-case Power Noise
Y
yield-aware design	Cost-Aware Design Space Exploration of Yield-Compliant UCIe Interconnects

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