Program for Monday, October 19th: Talk View

PROGRAM FOR MONDAY, OCTOBER 19TH: TALK VIEW

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View: with abstracts session overview

9:00

9:30

10:00

10:30

11:00

11:30

12:00

12:30

13:00

13:30

14:00

14:30

15:00

15:30

16:00

16:30

17:00

17:30

18:00

18:30

09:00-09:10 Welcome Remarks

09:10-10:10

AI Meets Chips and Packaging: From Prediction to Generation

David Z. Pan

10:10-10:30

Constraining Poles of Parameterized Macromodels

Antonio Carlucci, Tommaso Bradde, Stefano Grivet-Talocia

10:30-10:50

An Efficient NN Architecture for Harmonic Balance-based Analysis for SI Applications

A. Mathur, A. Javaid, V. Rao, D. Tannir, Z. Naghibi, R. Achar

10:50-11:10

Deep Equilibrium Recurrent–Transformer (DERT) Model for Large Coupled Interconnect Systems

Ahsan Javaid, Anuj Mathur, Ramachandra Achar

11:30-12:30 APAC Special Panel Session

12:30-14:00 TPC Meeting

14:00-14:20

Thermal-Aware Signal Integrity Analysis of GPU-HBM-HBF Interposer Channels Considering HBF Power

Lee, Lee, Yoon, Yoon, Kim, Park, Bae, An, Suh, Yang, Lee, Kim

14:20-14:40

Transformer-Based S-Parameter Prediction for Chiplet Interconnects with Sparse Global Context

Pin-Yuan Yang, Cheng-Wei Liu, Shih-Chieh Chang

14:40-15:00

Physics-Guided Wideband S-Parameter Prediction for UCIe Interconnect using Resonance-Aware Gaussian Process

S. Shimomura, A. Miyamoto, T. Hamaguchi, T. Ikeguchi, Y. Uematsu

15:00-15:10 Keysight Demonstration Presentation

15:40-16:00

Data-Efficient Training of Machine Learning Surrogates with Application to a Memory Interposer

Michele Cusano, Paolo Manfredi, Xuan Chen, Piero Triverio

16:00-16:20

Pattern- and Channel-Aware Physics-Assisted Deep Learning for Per-DQ Eye-Metric Estimation in RDL Interposer

H. Cho, J. Lee, H. Suh, J. Kim, J. Bae, C. Yang, G. Lee, S. Lee

16:20-16:40

Machine-Learning-Based Multi-Channel Optical I/O Analysis for Co-Packaged Optics

Dekang Chen, Yalong Gu, Duye Ye, Zhichao Zhang, Kemal Aygün

16:40-17:00

Physics-Derived Machine Learning Surrogate Modeling for Rapid LPDDR Signal Integrity Triage

Venkat Satagopan, Ram Krishna, Clement Luk, Karthik Mahesh Rao

17:00-18:30 Welcome Reception

17:00-18:30

Active-Learning-Based TX FIR Tuning for High-Speed Links Under Dynamic Thermal Ramping

Jiazhen Li, Ronnie Zheng, Peng Fu

Immersion Cooling Fixture for High Power Testing of Planar Microwave Transmission Lines

Mohammad Sanad Altaher, Thomas Weller

AI-Assisted Chiplet Design Space Exploration with Physics-Aware Reduced-Order Modeling

Y. Uematsu, T. Hamaguchi, S. Shimomura, Y. Harubeppu, K. Ashida, A. Miyamoto

Signal and Power Integrity Analysis of 32 Gbps Die-to-Die Interconnects for Chiplet

Zhou Shengjuan, Qian Wang, Jian Cai

SI/PI Trade-off Analysis of UCIe-A Interfaces Considering Power/Ground-to-Signal Bump Ratios

S. Lee, J. Lee, H. An, B. Kim, H. Suh, Y. Yoon, J. Yoon, C. Yang, G. Lee, J. Kim

Design and Analysis of HBM-HBF-NMC Architecture for LLM Inference Considering Signal Integrity

Yang, Yoon, Suh, Lee, An, Park, Kim, Yoon, Lee, Lee, Lee, Kim

Package-level thermal optimization for high-power-density AI accelerators

Sushil Panda, Paul D. Franzon

Influence of interface roughness between Ag sintered bonding layer and Cu on thermal stress in SiC power chip system with AMB

Sean Ogawa, Masaaki Aoki, Akio Iwabuchi, Toshiki Kunieda, Nobuhiko Nakano

8533 MT/s LPDDR5X Package Design with Memory-on-Board Topology

Jeffrey Majnaric, Tingdong Zhou, Robert Wenzel, Geetansh Arora

Extension of a 2D CIM-Based Approach for Efficient and Automated Computation of Resistances for DC-Analysis of Multilayer

Mathis Tobaben, Jan Hessling, Christian Schuster

Physics-Aware Reinforcement Learning for Timing-Margin Optimization of High-Speed DDR5 RDIMM

Changhyun Jung, Joungho Kim, Haeseok Suh

Design Optimization for 224Gbs Channel in High Density Interconnect Printed Circuit Boards

Mengen Zan, Chen Cheng, Fanhua Meng, Xinyi Hu, Huafang Ju, Jimmy Hsu

11:10-11:30 Coffee Break

12:30-14:00 Lunch Break

15:10-15:40 Coffee Break