PROGRAM
Days: Wednesday, July 17th Thursday, July 18th Friday, July 19th
Wednesday, July 17th
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14:15-15:15 Session 2: Keynote Address by Sharon Hu
"Exploiting Ferroelectric FETs: From In-Memory Computing to Machine Learning and Beyond"
Chair:
15:15-16:15 Session 3: Emerging Topics
Chair:
| 15:15 | Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders (abstract) |
| 15:35 | Graphene Nanoribbon-based Synapses with Versatile Plasticity (abstract) |
| 15:55 | Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies (abstract) |
16:45-18:25 Session 4: RRAM and Memristor
Chair:
| 16:45 | Novel 3D architecture of the 1S1R devices (abstract) |
| 17:05 | ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing (abstract) |
| 17:25 | ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation (abstract) |
| 17:45 | Experimental Investigation of Memristance Enhancement (abstract) |
Thursday, July 18th
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09:00-10:40 Session 5: Emerging Device-circuit-system Co-design for Interaction
Chair:
| 09:00 | A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement (abstract) |
| 09:20 | A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency (abstract) |
| 09:40 | Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes (abstract) |
| 10:00 | Spintronic Memories: From Memory to Computing-in-Memory (abstract) |
| 10:20 | REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing (abstract) |
11:00-12:40 Session 6: Neural Network Architectures
Chair:
| 11:00 | Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience (abstract) |
| 11:20 | Detecting and Bypassing Trivial Computations in Convolutional Neural Networks (abstract) |
| 11:40 | An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks (abstract) |
| 12:00 | Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction (abstract) |
| 12:20 | An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing (abstract) |
14:00-15:40 Session 7: Novel Concepts
Chair:
| 14:00 | Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions (abstract) |
| 14:20 | ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning (abstract) |
| 14:40 | A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs (abstract) |
| 15:00 | Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon (abstract) |
| 15:20 | Plasma Modified Silicon Nitride Resistive Switching Memories (abstract) |
16:00-17:40 Session 8: Magnetic Memories
Chair:
| 16:00 | High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM (abstract) |
| 16:20 | A compact model of stochastic switching in STT magnetic RAM for memory and computing (abstract) |
| 16:40 | Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM (abstract) |
| 17:00 | Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque (abstract) |
| 17:20 | Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction (abstract) |
Friday, July 19th
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09:00-10:00 Session 9: Keynote Address by Kaushik Roy
"Stochastic & Neuromorphic Computing with Magnetic Tunnel Junctions: Prospects and Perspectives"
Chair:
10:30-11:50 Session 10: Emerging memory enabled computing
Chairs:
| 10:30 | Enabling New Computing Paradigms with Emerging Symmetric-Access Memories (abstract) |
| 10:50 | Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach (abstract) |
| 11:10 | Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors (abstract) |
| 11:30 | Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads (abstract) |