NANOARCH 2019: 15TH IEEE / ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES

A
Abu Lebdeh, Muath	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation
Ali, Rashid	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
Angizi, Shaahin	Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach
Attarimashalkoubeh, Behnoush	Novel 3D architecture of the 1S1R devices
B
Bocquet, Marc	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
C
Cai, Hao	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Cai, Hao	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement
Cai, Hao	REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing
Carboni, Roberto	A compact model of stochastic switching in STT magnetic RAM for memory and computing
Cotofana, Sorin	Graphene Nanoribbon-based Synapses with Versatile Plasticity
Cucu Laurenciu, Nicoleta	Graphene Nanoribbon-based Synapses with Versatile Plasticity
D
Dimitrakis, Panagiotis	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon Plasma Modified Silicon Nitride Resistive Switching Memories
Drechsler, Rolf	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Du Nguyen, Hoang Anh	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation
F
Fan, Deliang	Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach
Frerix, Steffen	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Fröhlich, Saman	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
G
Gu, Mingyang	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Gupta, Sumeet	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
H
Hamdioui, Said	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation
Han, Jie	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
Han, Menglin	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Harms, Jon	A compact model of stochastic switching in STT magnetic RAM for memory and computing
He, Weifeng	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
Hirtzlin, Tifenn	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
Hou, Zhengyi	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
Huang, Zhe	Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
I
Ielmini, Daniele	A compact model of stochastic switching in STT magnetic RAM for memory and computing
Iqbal, Md Arif	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
J
Jao, Nicholas	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
Jiang, Yande	Graphene Nanoribbon-based Synapses with Versatile Plasticity
Jiao, Xun	Detecting and Bypassing Trivial Computations in Convolutional Neural Networks
K
Kang, Wang	Spintronic Memories: From Memory to Computing-in-Memory
Karafyllidis, Ioannis	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon Plasma Modified Silicon Nitride Resistive Switching Memories
Karakolis, Panagiotis	Plasma Modified Silicon Nitride Resistive Switching Memories
Kim, Minhwan	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
Klein, Jacques-Olivier	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
Krishna Ramanathan, Akshay	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
L
Leblebici, Yusuf	Novel 3D architecture of the 1S1R devices
Li, Xueqing	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Li, Zhengang	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
Lian, Chenyu	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
Lin, Sheng	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
Liu, Bo	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement
Liu, Leibo	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
Liu, Mingyue	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Liu, Weiqiang	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
Locatelli, Nicolas	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
Lombardi, Fabrizio	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
Lu, Yongjie	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
Lyle, Andy	A compact model of stochastic switching in STT magnetic RAM for memory and computing
M
Ma, Dongning	Detecting and Bypassing Trivial Computations in Convolutional Neural Networks
Ma, Haoyuan	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
Ma, Xiaolong	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
Macha, Naveen Kumar	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Mao, Zhigang	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
N
Nafría, Montserrat	Experimental Investigation of Memristance Enhancement
Nan, Jiang	Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions
Narayanan, Vijaykrishnan	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
Narayanan, Vijaykrishnan	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
Naviner, Lirida	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Normand, Pascal	Plasma Modified Silicon Nitride Resistive Switching Memories
Ntinas, Vasileios	Experimental Investigation of Memristance Enhancement
P
Paler, Alexandru	Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
Penkovskyi, Bogdan	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
Portal, Jean-Michel	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
Q
Qiao, Fei	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Querlioz, Damien	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
R
Raghunathan, Vijay	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
Raha, Arnab	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
Rahman, Mostafizur	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Rallis, Konstantinos	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon
Repalle, Bhavana Tejaswini	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Robert Basmadjian,	Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
Rodríguez, Rosana	Experimental Investigation of Memristance Enhancement
Rubio, Antonio	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon Experimental Investigation of Memristance Enhancement
S
Sampson, John	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
Sandhu, Gurtej	A compact model of stochastic switching in STT magnetic RAM for memory and computing
Shan, Weiwei	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
Shirinzadeh, Saeideh	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Siddik, Manzar	A compact model of stochastic switching in STT magnetic RAM for memory and computing
Sirakoulis, Georgios Ch.	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon Plasma Modified Silicon Nitride Resistive Switching Memories Experimental Investigation of Memristance Enhancement
Srivinasa, Srivatsa	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
Sun, Hao	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
Sun, Yanan	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
T
Tao, Yunsong	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Taouil, Mottaqiallah	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation
Thirumala, Sandeep Krishna	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
V
Vernocchi, Elena	A compact model of stochastic switching in STT magnetic RAM for memory and computing
Vincent, Adrien F.	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
W
Wang, Chengzhi	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
Wang, Guanda	Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Wang, He	Graphene Nanoribbon-based Synapses with Versatile Plasticity
Wang, Jinkai	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Wang, Tao	An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
Wang, Yanzhi	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
Wang, You	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
Wei, Shaojun	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
Wu, Chengjun	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
Wu, Juejian	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Wu, Xiulong	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
X
Xie, Lei	REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing
Xie, Lei	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Xu, Jiaming	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
Y
Yang, Huazhong	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Yang, Jianxun	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
Yang, Jun	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Yin, Shouyi	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
Yu, Jintao	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation
Yuan, Geng	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
Z
Zeng, Lang	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
Zhang, Deming	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
Zhang, He	Spintronic Memories: From Memory to Computing-in-Memory
Zhang, Jin	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
Zhang, Kaili	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
Zhang, Kun	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Zhang, Tingting	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
Zhang, Xueying	Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions
Zhang, Youguang	Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Zhang, Youguang	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
Zhang, Youguang	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
Zhang, Yue	Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Zhang, Zhizhong	Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Zhao, Weisheng	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes Spintronic Memories: From Memory to Computing-in-Memory Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
Zhao, Weisheng	Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Zhong, Hongtao	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Zhou, Yongliang	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement

Disclaimer | Powered by EasyChair Smart Program