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14:15-15:15 Session 2: Keynote Address by Sharon Hu

"Exploiting Ferroelectric FETs: From In-Memory Computing to Machine Learning and Beyond"

15:15-16:15 Session 3: Emerging Topics
Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders

ABSTRACT. Approximate computing at the nanoscale provides a new approach for low power design for error-tolerant applications. Many emerging nanotechnologies are based on majority logic (ML) and therefore the 3-input majority gate has been used as the basic building block in digital circuit design. In this paper, we consider the design of approximate radix-4 Booth multipliers based on ML. In particular, an approximate partial product encoder and an approximate correction term encoder are proposed. A new metric referred to as the influence factor is defined and used to assess the approximate radix-4 Booth algorithm for different sizes of multipliers. The proposed designs are evaluated using hardware metrics as well as error metrics. It is shown that they offer superior performance. Image processing as a case study of error-tolerant applications are also presented to show the validity of the proposed designs.

Graphene Nanoribbon-based Synapses with Versatile Plasticity

ABSTRACT. Designing and implementing artificial systems that can be interfaced with the human brain or that can provide computational ability akin to brain's processing information efficient style is crucial for understanding human brain fundamental operating principles and to unleashing the full potential of brain-inspired computing. As basic neural network components, responsible for information transfer between neurons, artificial synapses able to emulate analog biological synaptic behaviour are of particular interest. State of the art CMOS and memristor-based synapses suffer from scalability drawbacks (large energy consumption and area footprint), variability-induced instability, and are not bio-compatible. In this paper, we propose a generic Graphene Nanoribbon (GNR) based synapse structure and demonstrate that by changing GNR geometry and external bias voltages it can emulate different synaptic plasticity behaviours, i.e., Spike Timing Dependent Plasticity and Long-Term Depression and Potentiation, and that both excitatory and inhibitory synaptic behavior can be obtained with the same GNR geometry. To demonstrate biologically plausible operation, we make use of low voltage bias (0.1V, 0.2V) and consider inputs consistent with measured brain synapses data, i.e., -50mV to 50mV pre- and post-synaptic spikes voltage range, and -60ms to 60ms time range. The simulations indicate that by changing the GNR shape we can enrich the plasticity behaviour (potentially beyond the considered cases) and the plasticity change of 100% provided by natural synapses can be achieved. Our investigation clearly suggests that the proposed GNR synapse structure is a promising candidate for large-scale neuromorphic systems integration, which might potentially bring novel insight on brain neurophysiology, as it requires a small footprint, is energy effective, biocompatible, and versatile from the synaptic behaviour point of view.

Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies

ABSTRACT. Clifford gates play a role in the optimisation of Clifford+T circuits. Reducing the count and the depth of Clifford gates, as well as the optimal scheduling of T gates, influence the hardware and the time costs of executing quantum circuits. This work focuses on circuits protected by the surface quantum error-correcting code. The result of compiling a quantum circuit for the surface code is called a topological assembly. We use queuing theory to model a part of the compiled assemblies, evaluate the models, and make the empiric observation that at least for certain Clifford+T circuits (e.g. adders), the assembly's execution time does not increase when the available hardware is restricted. This is an interesting property, because it shows that T gate scheduling and Clifford gate optimisation have the potential to save both hardware and execution time.

16:45-18:25 Session 4: RRAM and Memristor
Novel 3D architecture of the 1S1R devices

ABSTRACT. In this work, we present a novel 3D architecture of one-selector-one-resistor (1S1R). This design eliminates the needs of physical wiring and provides valuable information for isolated selector/resistor elements together with their 1S1R integrated configuration. This architecture could be implemented for a broad selection of materials and structures.

ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing

ABSTRACT. In-memory computing is a promising solution for the issue of memory bottleneck in current computing systems. ReRAM is a non-volatile memory technology which natively im- plements basic logic operations and therefore enables to perform computational tasks. This allows to realize post von Neumann computer architectures with merged memory and processor. In this paper, we propose a fully automated compiler using and- inverter graphs (AIGs) for a conventional in-memory computer architecture which supports parallel computation within regular ReRAM crossbar arrays. The proposed synthesis scheme opti- mizes crossbar mapping to increase parallelism and lower the number of memory reads and allocated ReRAM devices which results in considerable reductions in latency and area of in- memory implementations. Experimental results reveal minimum speed-ups of factor 2 compared to recent works while consuming a fraction of the ReRAM devices.

ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation

ABSTRACT. Memristors have the potential to solve the memory access bottleneck in conventional computer architectures. However, they also suffer from problems such as low endurance and large resistance variation. To address these problems, we present a robust logic scheme named ESL that performs Boolean operations in the peripheral circuit of the crossbar memory. It does not change the states of memristors, which is beneficial to maintaining a long lifetime. ESL senses the resistance of input memristors via two different paths when performing AND and OR operations. Therefore, it can guarantee the operation correctness even under large resistance variations. We verified ESL using SPICE simulations and Monte Carlo analysis. Simulation results show that ESL is more robust compared with state-of-the-art logic schemes.

Experimental Investigation of Memristance Enhancement

ABSTRACT. Memristor devices are two-terminal nanoscale circuit elements that exhibit nonvolatile information storing and can be manufactured in ultra-dense arrays with low-power operation. Although, theoretically, memristors are strong candidates for novel memory and computing applications, the fabricated devices show high variability, both device-to-device and cycle-to-cycle, such as varying switching behaviour and maximum (Rmax) and minimum (Rmin) resistance values. Those limitations in the device's Rmax/Rmin ratio suppress the wide use of memristors in memory or logic applications, thus, this work presents the enhancement of this ratio on actual memristor devices, namely Knowm memristors, due to the introduction of external noise as a beneficial disturbance, following the nonlinear system phenomenon known as Stochastic Resonance.