TALK KEYWORD INDEX

This page contains an index consisting of author-provided keywords.

1 | |

1S1R architecture | |

3 | |

3D integration | |

A | |

analog computing | |

approximate computing | |

approximate memory | |

area efficiency | |

Arithmetic | |

Artificial Synapse | |

B | |

binarized neural networks | |

binary neural network(BNN) | |

BL Tracking | |

Booth encoder | |

C | |

Capacitive Coupling | |

Check-pointing | |

Circuit design | |

CMOS | |

compact modeling | |

compiler | |

ComPRIMe | |

Computation Workload | |

computing in memory | |

Computing-In-Memory | |

configurable adder | |

content addressable memory | |

convolutional neural network | |

Convolutional Neural Networks | |

cross-point array | |

Crosstalk Computing | |

Crosstalk Logic | |

Cu electrode | |

customized accelerator design | |

D | |

dynamic adaptation of approximate bit-width | |

E | |

Emerging Non-Volatile Memory | |

error resilience | |

error tolerance | |

F | |

FeFET | |

ferroelectric transistors | |

field-free | |

G | |

GNR | |

Graphene | |

H | |

Hardware Acceleration | |

I | |

impedance spectroscopy | |

In-memory computing | |

in-memory logic implementation | |

inference architecture | |

influence factor | |

L | |

Lattice defects | |

layout-friendly | |

linear correcting code | |

Logic | |

Logic Synthesis | |

M | |

Machine Learning | |

MAGIC | |

Magnetic Non-volatile SRAM (MNV-SRAM) | |

Magnetic Random Access Memory | |

magnetic skyrmion | |

Magnetic tunnel junction | |

magnetic tunnel junction (MTJ) | |

magnetic tunneling junction (MTJ) | |

majority logic | |

Majority Network | |

mapping | |

matrix operation | |

Memory | |

memory-augmented neural networks | |

memristance enhancement | |

Memristor | |

memristor crossbar | |

memristor devices | |

Model Compression | |

Monolithic 3D Integration | |

MRAM | |

N | |

NEGFs | |

Neural network acceleration | |

Neuromorphic Computing | |

nitride | |

Non volatile master flip flop | |

Non-volatile | |

O | |

operator scheduling | |

Optimization | |

P | |

parallelism | |

Perpendicular shape anisotropy | |

process variation | |

Pulse shape | |

Q | |

quantum computing | |

R | |

racetrack memory | |

RC memory | |

read access time | |

Reconfigurability | |

Reliability | |

ReRAM | |

resistance switching | |

Resistive Random Access Memory (ReRAM) | |

resistive-switching memory (RRAM) | |

reuse | |

Reverse voltage | |

ring shaped | |

RRAM | |

S | |

selector device | |

Self-Timing SA | |

sensing margin | |

Sensing Yield Improvement | |

sneak path | |

Spin obit torque | |

spin transfer torque magnetic tunnel junction | |

spin-orbit torque (SOT) | |

spin-transfer torque RAM (STT-MRAM) | |

Spintronic memory | |

SRAM | |

ST-MRAM | |

STDP | |

stochastic computing primitive | |

stochastic resonance | |

stochastic spiking neuron | |

stochastic switching | |

STT-MRAM | |

surface code | |

Switching variability modeling | |

Symmetric memory | |

symmetric memory access | |

T | |

time domain | |

Timing Window for Sensing | |

topological assembly | |

Trivial Computations | |

True random number generator | |

V | |

VCMA | |

Vector Matrix Multiplication | |

Volatile | |

voltage controlled magnetic anisotropy (VCMA) | |

voltage sense amplifier | |

W | |

writing failure |