NANOARCH 2019: 15TH IEEE / ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES

This page contains an index consisting of author-provided keywords.

1
1S1R architecture	Novel 3D architecture of the 1S1R devices
3
3D integration	Novel 3D architecture of the 1S1R devices
A
analog computing	An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
approximate computing	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
approximate memory	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
area efficiency	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
Arithmetic	REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing
Artificial Synapse	Graphene Nanoribbon-based Synapses with Versatile Plasticity
B
binarized neural networks	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
binary neural network(BNN)	An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
BL Tracking	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement
Booth encoder	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
C
Capacitive Coupling	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Check-pointing	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
Circuit design	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation
CMOS	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
compact modeling	A compact model of stochastic switching in STT magnetic RAM for memory and computing
compiler	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
ComPRIMe	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Computation Workload	Detecting and Bypassing Trivial Computations in Convolutional Neural Networks
computing in memory	Spintronic Memories: From Memory to Computing-in-Memory
Computing-In-Memory	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
configurable adder	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
content addressable memory	Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions
convolutional neural network	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
Convolutional Neural Networks	Detecting and Bypassing Trivial Computations in Convolutional Neural Networks
cross-point array	Novel 3D architecture of the 1S1R devices
Crosstalk Computing	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Crosstalk Logic	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Cu electrode	Plasma Modified Silicon Nitride Resistive Switching Memories
customized accelerator design	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
D
dynamic adaptation of approximate bit-width	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
E
Emerging Non-Volatile Memory	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
error resilience	Dynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience
error tolerance	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
F
FeFET	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
ferroelectric transistors	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
field-free	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
G
GNR	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon Graphene Nanoribbon-based Synapses with Versatile Plasticity
Graphene	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon Graphene Nanoribbon-based Synapses with Versatile Plasticity
H
Hardware Acceleration	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning Detecting and Bypassing Trivial Computations in Convolutional Neural Networks
I
impedance spectroscopy	Plasma Modified Silicon Nitride Resistive Switching Memories
In-memory computing	Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
in-memory logic implementation	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
inference architecture	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
influence factor	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
L
Lattice defects	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon
layout-friendly	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
linear correcting code	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
Logic	REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing
Logic Synthesis	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
M
Machine Learning	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
MAGIC	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
Magnetic Non-volatile SRAM (MNV-SRAM)	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
Magnetic Random Access Memory	Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach
magnetic skyrmion	Spintronic Memories: From Memory to Computing-in-Memory
Magnetic tunnel junction	Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
magnetic tunnel junction (MTJ)	A compact model of stochastic switching in STT magnetic RAM for memory and computing
magnetic tunneling junction (MTJ)	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
majority logic	Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders
Majority Network	A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
mapping	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
matrix operation	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
Memory	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
memory-augmented neural networks	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
memristance enhancement	Experimental Investigation of Memristance Enhancement
Memristor	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing
memristor crossbar	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
memristor devices	Experimental Investigation of Memristance Enhancement
Model Compression	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
Monolithic 3D Integration	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
MRAM	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement
N
NEGFs	Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon
Neural network acceleration	Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach
Neuromorphic Computing	Graphene Nanoribbon-based Synapses with Versatile Plasticity
nitride	Plasma Modified Silicon Nitride Resistive Switching Memories
Non volatile master flip flop	Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
Non-volatile	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
O
operator scheduling	An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks
Optimization	ResNet Can Be Pruned 60x: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning
P
parallelism	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Perpendicular shape anisotropy	Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
process variation	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
Pulse shape	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Q
quantum computing	Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
R
racetrack memory	Spintronic Memories: From Memory to Computing-in-Memory Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions
RC memory	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
read access time	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
Reconfigurability	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
Reliability	ESL: A Robust Memristor-based Logic Design Resilient to Resistance Variation Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
ReRAM	ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
resistance switching	Plasma Modified Silicon Nitride Resistive Switching Memories
Resistive Random Access Memory (ReRAM)	Novel 3D architecture of the 1S1R devices
resistive-switching memory (RRAM)	Plasma Modified Silicon Nitride Resistive Switching Memories
reuse	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
Reverse voltage	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
ring shaped	Ring-Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions
RRAM	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
S
selector device	Novel 3D architecture of the 1S1R devices
Self-Timing SA	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement
sensing margin	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
Sensing Yield Improvement	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement
sneak path	Novel 3D architecture of the 1S1R devices
Spin obit torque	Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction
spin transfer torque magnetic tunnel junction	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
spin-orbit torque (SOT)	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
spin-transfer torque RAM (STT-MRAM)	A compact model of stochastic switching in STT magnetic RAM for memory and computing
Spintronic memory	Spintronic Memories: From Memory to Computing-in-Memory
SRAM	An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
ST-MRAM	Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction
STDP	Graphene Nanoribbon-based Synapses with Versatile Plasticity
stochastic computing primitive	A compact model of stochastic switching in STT magnetic RAM for memory and computing
stochastic resonance	Experimental Investigation of Memristance Enhancement
stochastic spiking neuron	A compact model of stochastic switching in STT magnetic RAM for memory and computing
stochastic switching	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes A compact model of stochastic switching in STT magnetic RAM for memory and computing
STT-MRAM	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
surface code	Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
Switching variability modeling	A compact model of stochastic switching in STT magnetic RAM for memory and computing
Symmetric memory	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
symmetric memory access	Enabling New Computing Paradigms with Emerging Symmetric-Access Memories
T
time domain	An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing
Timing Window for Sensing	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement
topological assembly	Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies
Trivial Computations	Detecting and Bypassing Trivial Computations in Convolutional Neural Networks
True random number generator	Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes
V
VCMA	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM
Vector Matrix Multiplication	Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads
Volatile	Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors
voltage controlled magnetic anisotropy (VCMA)	Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque
voltage sense amplifier	High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM
W
writing failure	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM

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