ABSTRACT. This paper first presents a review of the circuit topologies of recently emerged symmetric memories that support 2-dimensional row-wise and column-wise accesses of read and write operations. Supporting technologies include CMOS, ferroelectric FET (FeFET) and two-terminal resistive memory devices. This paper will reveal how the emerging memory feature of access flexibility could enable new computing paradigms by providing fundamental savings of memory access times with column-wise memory access support. This benefit exists in both conventional applications and emerging computing, such as in-memory database and neural networks. In addition, this paper also proposes 2T1R, a new symmetric memory circuit design based on two-terminal resistive devices, such as RRAM and MTJ. This new design exhibits improved leakage power and scaling capability, as compared with the existing RRAM-based crossbar symmetric memory design.

ABSTRACT. Latest algorithmic progression has brought competitive classification accuracy for neural networks despite constraining the network parameters to ternary or binary representations. These findings show significant optimization opportunities to replace computationally-intensive convolution operations (based on multiplication) with more efficient and less complex operations such as addition. In hardware implementation domain, processing-in-memory architecture is becoming a promising solution to reduce massive power-hungry data traffic between computing and memory units, leading to significant improvement of entire system performance and energy efficiency while running such large networks. In this paper, we review several of our recent works regarding Processing-in-Memory (PIM) accelerator based on Magnetic Random Access Memory (MRAM) computational sub-arrays to efficiently accelerate the inference process of quantized neural networks within digital non-volatile memory rather than using analog crossbar operation. In this way, we investigate the performance of two distinct in-memory addition schemes compared to other digital methods based on processing-in-DRAM/GPU/ASIC design to tackle DNN power and memory wall bottleneck.

ABSTRACT. This paper presents a reconfigurable ferroelectric FET (R-FEFET), which has a unique capability to tune its operation between volatile (logic) and non-volatile (memory) modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks interacting with a common transistor channel. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Utilizing the unique attributes of R-FEFETs, we present a 3T non-volatile memory which achieves significant power savings over FEFET based memories by virtue of the control terminal. Our analysis shows that R-FEFET based memory exhibits 55% lower write power, 37-72% lower read power (at iso-access time) and 33% lower area compared to a standard FEFET based memory. We also present two variants of non-volatile flip-flops (NVFFs) based on R-FEFETs. The first design features true embedding of non-volatile element (via R-FEFET) enabling a fully automatic backup operation. In the second design, we introduce need-based backup, which lowers energy during normal operation at the cost of area with respect to the first design. Compared to a previously proposed FEFET based NVFF, the first design achieves 47% lower check-pointing energy, with a penalty of 6% in operation energy while the second design shows 30% lower check-pointing energy with similar operation energy. Under system evaluation, the R-FEFET based NVFFs achieve 25-33% register-level energy savings, in a state-of-the-art intermittently-powered platform.

ABSTRACT. Recent advances in emerging technologies such as monolithic 3D Integration (M3D-IC) and emerging non-volatile memory (eNVM) have enabled to embed logic operations in memory. This alleviates the “memory wall” challenges stemming from the time and power expended on migrating data in conventional Von Neumann computing paradigms. We propose a M3D SRAM dot-product engine for compute in-SRAM support used in applications such as matrix multiplication and artificial neural networks. In addition, we propose a novel computing in RRAM-based memory architecture to efficiently solve the computation intensity of sparse dot products. Specifically, the index assessment of sparse matrix-vector multiplication used in support vector machines (SVM). At maximum throughput, our proposed RRAM architecture achieves 11.3× speedup when compared against a near-memory accelerator.