ITC 2023: INTERNATIONAL TEST CONFERENCE 2023

This page contains an index consisting of author-provided keywords.

2
2.5D	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
3
3DIC	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
A
Adaptive Test in Practice	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
ADC nonlinearity	New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs
ADC Testing	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
AI	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
AI/Machine Learning in Test	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Alternate test	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
AMS Circuits	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Analytics	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
Angle of Arrival estimation	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
AR	Delivering the Metaverse Vision with AI, AR/VR and Silicon Design Innovations
ATE	Method for adjusting termination resistor value using PMU of ATE
ATPG	GPU-based Concurrent Static Learning
ATPG test patterns	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Automotive	Four Wheels and A Billion Lines of Code – Enabling the Future of Automotive
B
Biochips	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
BIST	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
Built-in Self Repair	Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation
built-in self-test	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
C
chain diagnosis	Predicting the resolution of scan diagnosis
chain diagnosis resolution	Predicting the resolution of scan diagnosis
Channel damage	Method for diagnosing channel damage using FPGA transceiver
ChatGPT	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
Chip performance prediction	Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data
Chiplet	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation On-Package Chiplet Innovations with Universal Chiplet Interconnect Express (UCIe): Challenges and Opportunities
Circuit Probing	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
clock tree diagnosis	Global control signal defect diagnosis in volume production environment
CMOS image sensor	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
Code	Four Wheels and A Billion Lines of Code – Enabling the Future of Automotive
Coherent sampling	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
contrastive learning	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation
control signal diagnosis	Global control signal defect diagnosis in volume production environment
Convolutional neural network	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
D
Data converter test	New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs
DC Test	Method for adjusting termination resistor value using PMU of ATE
Deep neural network	Towards Robust Deep Neural Networks against Design-time and Run-time Failures
Defect oriented test	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
defect-oriented tests	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
design for diagnosis	Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
Design for Test	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Design-for-Testability	Enabling In-field Parametric Testing for RISC-V Cores Device-Aware Test for Ion Depletion Defects in RRAMs
device-aware defect model	Device-Aware Test for Ion Depletion Defects in RRAMs
DFT	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation Transitioning eMRAM from Pilot Project to Volume Production Power Domain Aware DFT Implementation
diagnosis	Low cost production scan test for compression based designs Method for diagnosing channel damage using FPGA transceiver
diagnosis accuracy	Predicting the resolution of scan diagnosis
diagnosis and debug	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
diagnosis resolution estimation	Predicting the resolution of scan diagnosis
Digital Predistortion	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Direct Digital Synthesizer	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Dynamic Characteristic	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
E
ECC	Transitioning eMRAM from Pilot Project to Volume Production
ECC tuning	Transitioning eMRAM from Pilot Project to Volume Production
ECC-aware test	Transitioning eMRAM from Pilot Project to Volume Production
Electrical characterization	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Elliptical Envelope outlier detection	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
embedded-test	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
eMRAM	Transitioning eMRAM from Pilot Project to Volume Production
Explainable AI	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
F
Fault Characterization	Analysis and Characterization of Defects in FeFETs
fault injection attack	Towards Robust Deep Neural Networks against Design-time and Run-time Failures
fault modeling	Device-Aware Test for Ion Depletion Defects in RRAMs Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Feature Selection	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
FeFETs	Analysis and Characterization of Defects in FeFETs
FFT	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Finite State Machine	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
Flexible Parallel Port	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
FMCW radars	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
FPGA	Enabling In-field Parametric Testing for RISC-V Cores Method for diagnosing channel damage using FPGA transceiver
FPP	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
functional broadside (launch-on-capture) tests	Compaction of Functional Broadside Tests for Path Delay Faults using Clusters of Propagation Lines
Functional Safety	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
G
Gate-Level Netlist Analysis	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
Good die in bad neighborhood	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
GPGPU	GPU-based Concurrent Static Learning
GPUs	Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
H
Hardware Security	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
Harmonics	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
HIES	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
HPC	Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
I
IE	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
IEEE 1500	Power Domain Aware DFT Implementation
IEEE 1801	Power Domain Aware DFT Implementation
IEEE 1838	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
in-field testing	Enabling In-field Parametric Testing for RISC-V Cores
interpolation	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
L
Laser Fault Injection	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
Latent defects	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
linear resistors	Device-Aware Test for Ion Depletion Defects in RRAMs
logic diagnosis	Predicting the resolution of scan diagnosis
logic diagnosis resolution	Predicting the resolution of scan diagnosis
Low Power	Power Domain Aware DFT Implementation
LSF	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
M
machine learning	Analysis and Characterization of Defects in FeFETs High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing A Full-Stack Approach for Side-Channel Secure ML Hardware Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
magnetic coupling	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Manufacturing Defects	Analysis and Characterization of Defects in FeFETs
Manufacturing Self Test	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
masking	A Full-Stack Approach for Side-Channel Secure ML Hardware
MBIST	Transitioning eMRAM from Pilot Project to Volume Production Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation
memory aging	Transitioning eMRAM from Pilot Project to Volume Production
memory fault injection	Transitioning eMRAM from Pilot Project to Volume Production
Memory Integrity	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
Memory Repair	Transitioning eMRAM from Pilot Project to Volume Production Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation
memory test	Transitioning eMRAM from Pilot Project to Volume Production
memory yield	Transitioning eMRAM from Pilot Project to Volume Production
Metaverse	Delivering the Metaverse Vision with AI, AR/VR and Silicon Design Innovations
Methodology	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Microfluidic	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Microvalve	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
MIMO radars	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
Mitigation scheme	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
ML	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
Monolithic 3D	Scan Cell Segmentation based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs
Monotonicity	Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data
MRAM	Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM
Multi-die design	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
N
N-detect Pattern Generation	Robust Pattern Generation for Small Delay Faults under Process Variations
neutron-induced errors	Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
non-redundant VIA	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
O
On-chip monitor	Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data
optical test	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
Outlier Detection	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Oversampling	Method for diagnosing channel damage using FPGA transceiver
P
parallel acceleration	GPU-based Concurrent Static Learning
parametric testing	Enabling In-field Parametric Testing for RISC-V Cores
path delay faults	Compaction of Functional Broadside Tests for Path Delay Faults using Clusters of Propagation Lines
PDMS	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
PG-TVD Logic	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
Physically Unclonable Functions	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Plenary Keynote	On-Package Chiplet Innovations with Universal Chiplet Interconnect Express (UCIe): Challenges and Opportunities
PMU	Method for adjusting termination resistor value using PMU of ATE
post silicon	Low cost production scan test for compression based designs
Power Domain	Power Domain Aware DFT Implementation
power prediction	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Principal component analysis	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
Proactive Infant Defect Prediction	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Probe Life Cycle	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Q
Quality Improvement	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Quantum computing	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Quantum dot	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
R
radiation hardening	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Read resistance trim	Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM
Reduced code testing	New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs
Reinforcement learning	Scan Cell Segmentation based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs
reliability	Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
RISC V	A Full-Stack Approach for Side-Channel Secure ML Hardware
robustness	Towards Robust Deep Neural Networks against Design-time and Run-time Failures
Room temperature	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Rowhammer	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
RRAM test	Device-Aware Test for Ion Depletion Defects in RRAMs
RTL design	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
S
Scalable Security	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
Scan	Power Domain Aware DFT Implementation
scan atpg	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
scan chain diagnosis	Global control signal defect diagnosis in volume production environment
scan defect	Low cost production scan test for compression based designs
scan diagnosis	Predicting the resolution of scan diagnosis
scan diagnosis resolution	Predicting the resolution of scan diagnosis
scan-based testing	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Screening	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Security	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Security Rules	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
Security Validation	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
semi-supervised learning	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation
semiconductor manufacturing	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation
Sensor Data	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Shared Bus	Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation
side channels	A Full-Stack Approach for Side-Channel Secure ML Hardware
Signal Selection	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Silent Data Corruption	Robust Pattern Generation for Small Delay Faults under Process Variations
silicon defect diagnosis	Predicting the resolution of scan diagnosis
Silicon Lifecycle Management	Enabling In-field Parametric Testing for RISC-V Cores
Single Electron Transistor	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
single-event double-node upset	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
single-event upset	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Small Delay Faults	Robust Pattern Generation for Small Delay Faults under Process Variations
soft error	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Software	Four Wheels and A Billion Lines of Code – Enabling the Future of Automotive
Solid State Drives (SSD)	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Spin qubit	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
static learning	GPU-based Concurrent Static Learning
stray field	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Stress test	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
STT-MRAM	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Successive approximation ADC	New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs
systematic defect	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
Systemic Error Characterization	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
T
TAT	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
Termination resistor	Method for adjusting termination resistor value using PMU of ATE
test application time	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
test compaction	Compaction of Functional Broadside Tests for Path Delay Faults using Clusters of Propagation Lines
test coverage	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
test development	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
test generation	Compaction of Functional Broadside Tests for Path Delay Faults using Clusters of Propagation Lines
Test points	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Test power reduction	Scan Cell Segmentation based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs
Test time reduction	Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM
test vehicles	Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
testing	Towards Robust Deep Neural Networks against Design-time and Run-time Failures
thermal prediction	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Timing closure	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Timing-aware ATPG	Robust Pattern Generation for Small Delay Faults under Process Variations
Transistor metrics	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
transition delay fault	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
trimming	Transitioning eMRAM from Pilot Project to Volume Production
Tuning Analog/Mixed-signal circuits	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
U
UCIe	On-Package Chiplet Innovations with Universal Chiplet Interconnect Express (UCIe): Challenges and Opportunities
udfm	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Unclonability	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
UPF	Power Domain Aware DFT Implementation
V
VLSI	Low cost production scan test for compression based designs Global control signal defect diagnosis in volume production environment
VR	Delivering the Metaverse Vision with AI, AR/VR and Silicon Design Innovations
Vulnerability Assessment work Flow	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
W
Wafer level	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
wafer map pattern recognition	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation
Wafer Testing	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Wafer-level defect pattern	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Y
Yield	Low cost production scan test for compression based designs Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation
yield learning	Global control signal defect diagnosis in volume production environment Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
Z
zero defects	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes

Disclaimer | Powered by EasyChair Smart Program