ITC 2023: INTERNATIONAL TEST CONFERENCE 2023

A
Amarnath, Chandramouli	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
Amrouch, Hussam	Analysis and Characterization of Defects in FeFETs
Amrouch, Hussam	Robust Pattern Generation for Small Delay Faults under Process Variations
Archer, Brian	Low cost production scan test for compression based designs
Arora, Manish	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Arunachalam, Ayush	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Ataman, Ferhat Can	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
Aysu, Aydin	A Full-Stack Approach for Side-Channel Secure ML Hardware
Aziza, Hassen	Device-Aware Test for Ion Depletion Defects in RRAMs
B
Baban, Navajit Singh	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Bandejia, Ankit	Power Domain Aware DFT Implementation
Banerjee, Sanmitra	Scan Cell Segmentation based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs
Banerjee, Savita	Delivering the Metaverse Vision with AI, AR/VR and Silicon Design Innovations
Banerjee, Suvadeep	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Basu, Kanad	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Bhargava, Gaurav	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
Bhattacharjee, Sukanta	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Bletsch, Tyler	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
Bodhe, Shraddha	Global control signal defect diagnosis in volume production environment
Bose, Sankalp	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
C
Cai, Haoran	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Carro, Luigi	Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
Chakrabarty, Krishnendu	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation Scan Cell Segmentation based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs Analysis and Characterization of Defects in FeFETs
Chakravadhanula, Krishna	Power Domain Aware DFT Implementation
Chandra, Anshuman	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Chang, Daehyun	Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM
Chang, Norman	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Chao, Mango	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Chatterjee, Abhijit	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
Chatterjee, Urbi	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Chaudhuri, Arjun	Scan Cell Segmentation based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs Analysis and Characterization of Defects in FeFETs
Chen, Rebecca	Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data
Chen, Zixiao	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Chern, Mason	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
Chillarige, Sameer	Low cost production scan test for compression based designs
Chiueh, Herming	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Choi, Jaemoo	Method for diagnosing channel damage using FPGA transceiver Method for adjusting termination resistor value using PMU of ATE
Colon-Bonet, Glenn	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Couet, Sebastien	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
D
D'Souza, Jayant	Predicting the resolution of scan diagnosis
Das, Sanjay	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Das Sharma, Debendra	On-Package Chiplet Innovations with Universal Chiplet Interconnect Express (UCIe): Challenges and Opportunities
De Greve, Kristiaan	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Debaud, Philippe	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
Devendhiran, Manoj	Predicting the resolution of scan diagnosis
Dray, Cyrille	Transitioning eMRAM from Pilot Project to Volume Production
Dubey, Anuj	A Full-Stack Approach for Side-Channel Secure ML Hardware
Dupree, Matthew	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
E
Eiki, Makoto	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Elsayed, Asser	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
F
Fahy, Michael	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Farahmandi, Farimah	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
Farheen, Tasnuva	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
Fieback, Moritz	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs Device-Aware Test for Ion Depletion Defects in RRAMs
Forte, Domenic	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
G
Gandla, Mohan	Power Domain Aware DFT Implementation
Gelda, Khushal	Transitioning eMRAM from Pilot Project to Volume Production
Ghasemi, Seyedehmaryam	Enabling In-field Parametric Testing for RISC-V Cores
Gielen, Georges	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Girard, Patrick	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
Glowatz, Andreas	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Gnad, Dennis	Enabling In-field Parametric Testing for RISC-V Cores
Godfrin, Clement	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Goel, Sandeep Kumar	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Grill, Alexander	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Gu, Yunfei	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Guo, Minyi	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Guo, Xinfei	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Gupta, Anuj	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
H
Hamdioui, Said	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs Device-Aware Test for Ion Depletion Defects in RRAMs
Hatayama, Kazumi	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
He, Chen	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data
Hellebrand, Sybille	Robust Pattern Generation for Small Delay Faults under Process Variations
Ho, Matt	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Holzhausen, Ryan	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
Hsiao, Ming-Hsien	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Hsieh, Bing-Han	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
Hu, Hanbin	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation
Huang, Junlin	Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
Huang, Yu	GPU-based Concurrent Static Learning
Hun, Shin	Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM
Hung, Shao-Chun	Scan Cell Segmentation based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs
I
Ichikawa, Tamotsu	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Iimori, Daisuke	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Inoue, Michiko	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Ishida, Takashi	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Iwata, Hiroyuki	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
J
Jafarzadeh, Hanieh	Robust Pattern Generation for Small Delay Faults under Process Variations
Jain, Sahil	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
Janicki, Jakub	Predicting the resolution of scan diagnosis
Jin, Xiankun	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Joardar, Biresh	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
K
Kajiyama, Masuo	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Kalyan, Rahul	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Kang, Minho	Method for diagnosing channel damage using FPGA transceiver Method for adjusting termination resistor value using PMU of ATE
Kar, Gouri Sankar	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Karkare, Nikhil	Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation
Karri, Ramesh	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Katayama, Shogo	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Katoh, Kentaroh	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Keim, Martin	Transitioning eMRAM from Pilot Project to Volume Production
Khan, Moiz	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Khanna, Naveen	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Kibria, Rasheed	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
Kim, Youngdae	Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM
Klemme, Florian	Robust Pattern Generation for Small Delay Faults under Process Variations
Kobayashi, Haruo	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Kodali, Harshitha	Transitioning eMRAM from Pilot Project to Volume Production
Komarraju, Suhasini	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
Kongala, Sudhakar	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
Krautter, Jonas	Enabling In-field Parametric Testing for RISC-V Cores
Kubicek, Stefan	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Kumar, Akhilesh	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Kumar Y.B., Chethan	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
Kuwana, Anna	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
L
Lai, Liyang	GPU-based Concurrent Static Learning
Laouamri, Oussama	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Lee, Seongkwan	Method for diagnosing channel damage using FPGA transceiver Method for adjusting termination resistor value using PMU of ATE
Lee, Shu-Wen	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Lefevre, Julia	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
Li, James Chien-Mo	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Li, Jie	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Li, Katherine Shu-Min	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Li, Peng	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data
Li, Pengju	Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
Li, Ruoyu	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Li, Ying-Shiun	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Li, Yu	Towards Robust Deep Neural Networks against Design-time and Run-time Failures
Liang, Chia-Wei	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Liang, Huaxiao	GPU-based Concurrent Static Learning
Liang, Zhe-Jia	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Lin, Xiaoze	GPU-based Concurrent Static Learning
Liu, Ching-Min	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Liu, Yun-Sheng	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
Lorenzelli, Francesco	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Lyu, Yinxuan	Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
M
Maeda, Yoichi	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Maghari, Nima	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
Mao, Haijing	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Marinissen, Erik Jan	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Matsushima, Jun	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Mayer, Jeff	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Meehl, Dale	Power Domain Aware DFT Implementation
Meschkov, Sergej	Enabling In-field Parametric Testing for RISC-V Cores
Mukherjee, Nilanjan	A New Framework for RTL Test Points Insertion Facilitating a “Shift-Left DFT” Strategy
Mukherjee, Subhasish	Power Domain Aware DFT Implementation
N
Nadeau-Dostie, Benoit	Transitioning eMRAM from Pilot Project to Volume Production
Najafi Haghi, Zahra Paria	Robust Pattern Generation for Small Delay Faults under Process Variations
Nakamura, Tomoki	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Nakatani, Takayuki	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Nandakumar, Bharath	Low cost production scan test for compression based designs
Natarajan, Suriyaprakash	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Nguyen, Vuong	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Nigh, Chris	Diagnosis of Systematic Delay Failures through Subset Relationship Analysis
O
Okamoto, Toshiyuki	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Orozaliev, Ajymurat	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Ortega, Eduardo	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
Ozev, Sule	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
P
Paik, Woohyun	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
Pant, Pankaj	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Papameletis, Christos	Power Domain Aware DFT Implementation
Park, Cheolmin	Method for diagnosing channel damage using FPGA transceiver Method for adjusting termination resistor value using PMU of ATE
Patidar, Ankita	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Pomeranz, Irith	Compaction of Functional Broadside Tests for Path Delay Faults using Clusters of Propagation Lines
Pradeep, Wilson	Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation
R
R, Aswin	New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs
Raha, Arnab	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Rajan, Monikka	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
Ramesh, Saidapet	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Rao, Sandeep	Improving Angle Of Arrival Estimation Accuracy for mm-Wave Radars
Rao, Siddharth	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Rech, Paolo	Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
Reimer, Jan Dennis	Robust Pattern Generation for Small Delay Faults under Process Variations
Romain, Luc	Transitioning eMRAM from Pilot Project to Volume Production
Ryynaenen, Maija	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
S
Santos, Fernando	Understanding and Improving GPUs’ Reliability Combining Beam Experiments with Fault Simulation
Sato, Keno	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Sato, Takashi	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Schramm, Lori	Transitioning eMRAM from Pilot Project to Volume Production
Schulze, John	Global control signal defect diagnosis in volume production environment
Schwarz, Sergej	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Shankaranarayanan, Bharath	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Sharma, Manish	Predicting the resolution of scan diagnosis Global control signal defect diagnosis in volume production environment
Shintani, Michihiro	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Shukla, Akhilesh	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Singhal, Sarthak	Power Domain Aware DFT Implementation
Sinha, Arani	Maximizing stress coverage by novel DFT techniques and relaxed timing closure
Sinhabahu, Nadun	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Song, Yong-Ak	Biochip-PUF: Physically Unclonable Functions for Microfluidic Biochips
Stucchi, Michele	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Styblinski, Adam	Global control signal defect diagnosis in volume production environment
Su, Fei	Enhanced ML-based Approach for Functional Safety Improvement in Automotive AMS Circuits
T
Tahoori, Mehdi	Enabling In-field Parametric Testing for RISC-V Cores
Takagi, Misaki	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Takashima, Fumiaki	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
Talukdar, Jonti	Simply-Track-And-Refresh: Efficient and Scalable Rowhammer Mitigation
Tammana, Akhil	OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
Taouil, Mottaqiallah	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs Device-Aware Test for Ion Depletion Defects in RRAMs
Tehranipoor, Mark	ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
Thapar, Dhruv	Analysis and Characterization of Defects in FeFETs
Thomann, Simon	Analysis and Characterization of Defects in FeFETs
Thomas, Morgan	Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
Tsai, Han-Ya	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Tyagi, Vistrita	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
U
Urban, Szczepan	Predicting the resolution of scan diagnosis Global control signal defect diagnosis in volume production environment
V
Vachani, Dipti	Four Wheels and A Billion Lines of Code – Enabling the Future of Automotive
Virazel, Arnaud	Predictor BIST: An “All-in-One” Optical Test Solution for CMOS Image Sensors
Vyas, Archana	Power Domain Aware DFT Implementation
W
Walia, Yash	Novel Methodology to Optimize TAT and Resource utilization for ATPG Simulations for Large SoCs
Wan, Danny	Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Wang, Jyi Ren	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Wang, Li-C.	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
Wang, Lowry P.-T.	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Wang, Naixing	GPU-based Concurrent Static Learning
Wang, Sying-Jyan	Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
Wang, Xingyu	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Wang, Zihu	Recognizing Wafer Map Patterns using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation
Wen, Charles H.-P.	Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
Won, Jun Yeon	Method for diagnosing channel damage using FPGA transceiver Method for adjusting termination resistor value using PMU of ATE
Wu, Chentao	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Wu, Kai-Chiang	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Wu, Song	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Wu, Yu-Tsung	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Wunderlich, Hans-Joachim	Robust Pattern Generation for Small Delay Faults under Process Variations
X
Xu, Qiang	Towards Robust Deep Neural Networks against Design-time and Run-time Failures
Xun, Hanzhi	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs Device-Aware Test for Ion Depletion Defects in RRAMs
Y
Yamamoto, Shuhei	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Yanez, Jesse	Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Yang, Fei	GPU-based Concurrent Static Learning
Yang, Min Jian	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
Yang, Yun-Feng	High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
Yang, Yuxin	GPU-based Concurrent Static Learning
Yassine, Abdullah	Global control signal defect diagnosis in volume production environment
Yen, Chia-Heng	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
Yin, Yuxuan	Domain-Specific Machine Learning based Minimum Operating Voltage Prediction using On-Chip Monitor Data
Yu, Liangliang	Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
Yuan, Rong	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Yuan, Sicong	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs Device-Aware Test for Ion Depletion Defects in RRAMs
Yun, Jongsin	Transitioning eMRAM from Pilot Project to Volume Production
Z
Zeng, Yueling	IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
Zhang, Taile	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Zhang, Yawen	Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-based Proactive Defect Prediction
Zhang, Ziwei	Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Zhao, Yujie	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
Zimnowlodzki, Piotr	Global control signal defect diagnosis in volume production environment
Zou, Wei	Transitioning eMRAM from Pilot Project to Volume Production

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