ABSTRACT. The extensive adoption of safety-critical applications in high-assurance environments has laid emphasis on safeguarding the Functional Safety (FuSa) of such systems. To this end, we formulated a novel unsupervised learning-based FuSa violation detection solution for automotive Analog and Mixed Signal (AMS) circuits (ITC’22). However, existing approaches are limited by pre-specified feature inputs, and lack rationale for identifying observation signals. To address these issues and further augment our original solution, we propose a novel anomaly detection strategy involving: (1) a genetic algorithm-based feature selection approach, (2) a novel signal selection algorithm to identify the best intermediate circuit signal, both for enhanced detection performance and reduced latency, and (3) an explainable AI-based framework to enhance user interpretability and transparency of our existing solution. The proposed approach, evaluated on two representative automotive AMS circuits, furnishes up to 100% detection accuracy and 2.3X reduction in detection time, thereby exhibiting the efficacy of our solution.

ABSTRACT. Single-event-induced soft errors (SEDU) are serious issues in advanced nano-scale technology, causing malfunctions in systems. Previous studies have attempted to prevent SEDU by incorporating protection mechanisms in cell designs or modifying the physical layout. This paper proposes a LESER framework to reconstruct the latch design, achieving 100% SEDU tolerance with minimum performance penalties. Experiments show that the reconstructed design can achieve a 100% soft error protection rate with the costs of an increment of 6.4% in area, 1% in timing and power penalty.

ABSTRACT. Achieving ZERO defects has historically relied on port-level test-coverage (TC) from traditional scan Stuck-At and Transition-Delay tests. Defect-Oriented tests from Siemens showed a new way to measure test coverage using layout-based Total-Critical area. With the ever-shrinking process nodes, the BEOL layers are closer together and the redundancy factor of VIA’s, especially the lower VIA layers has been dropping down significantly. Internal studies from quality and reliability failures confirmed non-redundant (NR) VIA defects that escaped all traditional detailed test coverage analysis. This motivated us to collaborate closely with our EDA tool vendor to develop a new industry first per-layer NR VIA fault model extraction flow using which we were able to successfully quantify NR VIA TC for set of scan atpg tests running in production test program. Details of a case-study using new fault extraction and fault simulation flow to quantify per-layer NR VIA TC will be discussed in this paper.

ABSTRACT. Delay faults have become increasingly important in modern designs due to decreasing technology node size and increasing operation frequency. However, diagnosis of delay faults can be challenging since there are typically few of failing bits in the test failures. In this work, a two-phase flow is presented to identify systematic delay failures and improve their corresponding diagnosis resolution. First, the subset relationships among test failures are analyzed to identify systematic defects. Then, representative test failures in the subset relationships are selected for diagnosis of the defect behavior. Experiments on two cores of an industrial design with three cases show over 33x, 69x, and 8x improvement on delay fault diagnosis resolution. Furthermore, the proposed technique can be easily integrated with commercial tools.

ABSTRACT. Scan diagnosis is relied upon to provide localized defect suspects for failing die using failing test cycle information for that die and design data. These suspects from scan diagnosis have been used to drive failure analysis (FA) to find the root cause of manufacturing yield loss. The fewer suspects that scan diagnosis produces (higher diagnosis resolution), the quicker and more efficient the FA cycle time - mainly due to the reduced need for fault isolation for these highly resolved diagnosis reports. Identifying design or test pattern-related bottlenecks to diagnosis resolution earlier in the design cycle can be useful to anticipate the impact of a particular design on yield learning. In the technique described in this paper, we show how diagnosis resolution can be estimated from design data for both chain and logic defects. Detailed comparison of diagnostic metrics and resolution statistics from silicon results presented show a strong correlation.

ABSTRACT. This paper presents an all-in-one test solution for CMOS image sensors allowing to fully replace the optical test done today with an ATE by a low cost embedded (BIST) test solution that reduces test time.

ABSTRACT. Modern system-on-chip (SoC) designs are becoming prone to numerous security threats due to the evergrowing complexity and size of the designs. Therefore, the early stage of the VLSI design flow requires a comprehensive security verification framework. The control flow of an SoC, generally implemented using finite state machines (FSMs), is not an exception to this requirement. The control FSMs may be prone to fault-injection and denial-of-service (DoS) attacks or have inherent information leakage and access control issues at the gate-level netlist abstraction. Therefore, defining a set of security rules (guidelines) for obtaining FSM implementations free from particular security-critical bugs after performing logic synthesis is crucial. Moreover, a framework is required to validate that these security rules are followed. In this paper, we propose a set of such security rules for control FSM design and a verification framework called ARC-FSM-G to check for those security rule violations.

ABSTRACT. A physical attack on a secure device can leak sensitive data, which can have severe consequences for an individual, company, or government. Research today focuses on identifying hardware vulnerabilities and designing countermeasures to increase security. One such countermeasure is the implementation of the camouflaging gate called PG-TVD, which ensures protection against reverse engineering and side-channel attacks. However, proper investigation is needed to determine if the countermeasure opens the door to other powerful attacks, such as laser fault injection attacks. Identifying the vulnerability against this attack requires a proper assessment. As the first attempt to understand laser sensitivity in PG-TVD, we develop a workflow for assessing a circuit layout's sensitivity to LFI. We use this workflow to analyze the PG-TVD, giving the laser-sensitive areas. Depending on the information obtained by our workflow, we propose, design, and simulate a mitigation scheme that mitigates the laser sensitivity in PG-TVD logic cells by 83%.

ABSTRACT. Rowhammer is a memory vulnerability that can compromise system-level security. Rowhammer occurs when a DRAM row is accessed repeatedly, potentially causing bit-flips for neighboring rows. The threshold for Rowhammer has decreased from 139K accesses in 2014 to 3.2K in 2022. This threshold is projected to decrease further. Many existing solutions are not scalable, incur high overhead, or fail to offer protection in realistic scenarios. We propose Simply-Track-And-Refresh (STAR) as an effective and scalable Rowhammer mitigation. We compare STAR’s performance overhead to recent solutions, HYDRA and AQUA. At ultra-low thresholds (500), STAR introduces 9.5x/31.7x lower average execution time overhead than HYDRA/AQUA. In addition, STAR introduces up to 4.3x lower area overhead and up to 3.3x lower power consumption compared to HYDRA and AQUA. We present proof of correctness, area and power consumption results derived using CACTI, and evaluation results from the PARSEC, SPLASH-2, SPEC2006, SPEC2017, and PAMPAR benchmark suites.

ABSTRACT. In silicon bring-up and yield analysis of complex ICs, such as those used in artificial intelligence (AI) and automotive applications, debug and diagnosis are crucial components. Reducing turn-around time for testing each IC increases profitability. This paper discusses a production scan pattern generation approach for designs with test compression that reduces scan channel load and unload times, among other savings, thereby reducing costs of testing. Results show upto 500X reduction in cycle count on industrial designs.

ABSTRACT. In semiconductor manufacturing processes, there are several causes of typical defects in silicon wafers, such as operational flaws or equipment malfunctions, which may lead to circuit failure and defective products. Therefore, testing is instrumental in improving overall yield and reliability. GDBN (good die in bad neighborhood) is an widely-used technique of rejecting potentially defective wafers in advance based on the concept that defects tend to cluster together. However, previous studies related to GDBN are limited to a local observation by using a narrow-sighted window and thus ignore the defects patterns of the wafers. In this paper, by leveraging information of wafer defect patterns and extending the observation range to the entire wafer, we strengthen the GDBN method to recognize the potentially defective dice more effectively based on the feature of the different defect patterns. The method proposed in this paper is realized by convolutional neural network technology, and it is also the first method to consider defect patterns of wafers as features to solve the problem of GDBN. Several experiments are conducted on a real-world WM-811K dataset, and the results show that our proposed method not only reduce the cost of return merchandise authorization (RMA) but the DPPM (Defective Parts Per Million) more significantly over other existing methods.

ABSTRACT. Recently, RISC-V processors have been proposed in domains with high demand on functional safety, such as autonomous driving or medical devices. Therefore, enabling in-field test and measurement methods to ensure correct functionality over the entire chip lifecycle has become a necessity. We propose an ISA extension for RISC-V cores to enable on-chip telemetry for software-controlled in-field parametric testing. Moreover, we introduce a so-called Path Transient Monitor (PTM), which is connected to the critical path of the core. Through custom instructions, the PTM is able to measure output transients with a timing resolution 1000 times (~11.5 ps) higher than the rated clock period (few ns) of the RISC-V core, allowing thorough assessment of the device health state. As a case study, we implement our proposed setup as an FPGA-based hardware prototype and investigate the impact of process and design variation, temperature, and input data, to evaluate the collected sensor data.

ABSTRACT. Power awareness has become an important dimension for recent advances in VLSI. Multiple functional power domains (PD) are forcing Design-for-Test (DFT) designers to adjust DFT insertion and implementation to comply with IEEE 1801 correctness. Several challenges emerge for DFT tools and engineers, including but not restricted to a) additional low power cells inserted & crossings created due to DFT connections, b) power aware scan chain connection with optimal scan wirelength, and c) ensuring Unified Power Format (UPF) correctness post DFT insertion. This paper describes power domain aware DFT techniques for core wrapping, heterogenous fanouts and PD fencing aware scan chain stitching. A correct by construction approach results in fewer low power cells, improved scan wirelength & fewer IEEE 1801 rule violations. The EDA automation demonstrated in this paper reduces the manual overhead for chip designers to ensure power correctness of the design after DFT implementation

ABSTRACT. To achieve best-in class power performance & area (PPA), today's complex processor cores with shared bus architecture typically use single physical memory (PM) across multiple logical memories (LM) to improve overall design efficiency. However, such an implementation imposes several limitations on enabling redundancy and repair support using on-chip memory test, resulting in a degraded repair coverage thereby impacting yield. In this paper, we propose a few novel strategies to seamlessly enable redundancy sharing across LMs shared by a single PM to mitigate the limitation with conventional approaches. Additional schemes are proposed to resolve potential conflict conditions that could arise as a result of this redundancy sharing. The experimental results by using the proposed solutions on two sample clusters on a large-scale design using shared bus architecture bridged a gap of 5-6% drop in repair coverage due to the shared physical memory implementation.