ABSTRACT. ITC Vice Program Chair Savita Banerjee (whose day job is as a Senior Manager in DFX at Meta) will lead an interactive discussion with her Meta colleagues Caitlin Kalinowski (Head, AR Hardware), Manohar Palluri (Sr. Director, Generative AI), and Edith Beigne (Director, Reality Labs Research). The dialog will focus on how the Metaverse is expected to transform social connection and touch on the challenges fueling a new wave of innovation and disruptive technology to revolutionize how we experience it. These use cases amplify the need for a vertically optimized stack from software to silicon and opens the door for unique problems to solve in test and manufacturability.

ABSTRACT. This paper presents key ideas behind IEA-Plot, a software framework designed to conduct test data analytics through chat. We use wafer-based analytics as an example application to discuss the ideas. IEA-plot interacts with a user through a dialog and produces plots according to user instructions. At the core of IEA-Plot is a knowledge graph connecting a frontend natural language parser to a backend API. This knowledge graph captures our analytics knowledge in the specific domain. Usage examples are presented based on test data collected from a recent production line.

Note: The IEA (Intelligent Engineering Assistant) was proposed in ITC 2018. IEA-Plot is a re-designed of the original IEA, using the latest language technologies such as GPT3.5 and S-Bert. The backend API includes the Minions analytic approach (published in ITC 2021) to support feedforward and feedback wafer pattern based analytics (published in ITC 2022). The use of knowledge graph is essential in the current design. IEA-Plot is not just a tool, but a framework showing how an IEA can be built to leverage the power of the latest language models and at the same time, incorporate domain-specific knowledge (in our case, the knowledge about the specific test data analytics) into an AI agent.

ABSTRACT. Although automotive semiconductors must comply with the standard dynamic part average testing (DPAT) defined by the Automotive Electronics Council, it remains challenging to detect outliers that deviate from the spatial trend within a wafer. Outlier detection using Gaussian process (GP) regression has recently been proposed and outperformed DPAT. However, the detection performance degrades when faulty large-scale integrations are densely included in the regression. Furthermore, the applicable test items are limited because of the long computation time for regression. We propose an outlier detection method by applying ensemble learning to GP regression for simultaneously improving the detection performance and shortening the learning time. Experimental results on industrial production test data demonstrate that the proposed method improves the robustness against latent faulty chip detection by 15.6% while reducing the computation time by 98.6% compared with the conventional GP- based method.

ABSTRACT. Wafer map analysis is essential for yield improvement in semiconductor manufacturing. However, manually annotating wafer map data is expensive and time-consuming, which drives up the demand for exploring label-efficient methods for wafer analysis. This paper proposes a novel semi-supervised contrastive learning framework for wafer map pattern feature extraction and classification. Our framework uses supervised contrastive learning on small amount of labeled data to learn a better latent space representation. Furthermore, a dual-encoder latent-space model is incorporated to best optimize the simultaneous use of labeled, unlabeled data, and varying types of data augmentations for representation learning. Finally, we enrich the semantics of the learned latent representation space by introducing new "inter-wafer data augmentation". Our experiments show that our method leads by a large performance gap compared to existing wafer pattern recognition techniques, and suggests that superior accuracy may be achieved simply by semi-supervised learning without resorting to labeling-intensive supervised learning.

ABSTRACT. Silicon spin qubits are one of the most promising platforms for large-scale quantum computing. In this platform, a qubit, i.e., the basic unit of quantum information, is associated with the spin of a single electron confined in a region in silicon called a quantum dot. Silicon spin qubit devices must be operated at 40mK in a 3He/4He dilution refrigerator. This requirement results in long cool-down times and increased costs, which slow down the technology development. Our research aims at developing a high-volume, room-temperature screening technique to assess quantum dot variability and select suitable candidates for mK measurements. In this paper, we present transistor measurement results of quantum dots across a 300mm wafer at temperatures ranging from 225K to 300K. We analyze the statistical distribution of transistor metrics to detect outliers across temperatures, to prevent wasting measurement time and resources at mK on known bad devices.

ABSTRACT. Static learning is a learning algorithm for retrieving implicit logical relationships between nodes in a netlist. The learning results play an important role in improving automatic test pattern generation (ATPG), such as increasing fault coverage and reducing pattern count. In this work, we study accelerating static learning on graphics processing units (GPUs). By tailoring to the architectural features of GPUs, an algorithm of concurrent static learning is proposed. Multiple learning jobs are carried out simultaneously or concurrently in the same netlist. Moreover, the forward and backward implications of these concurrent jobs are processed as a whole, which leads to better utilization of the computing resources on GPUs. Experiments show that the algorithm can achieve up to 253x speedup against a single-threaded commercial tool and is about 1.8 times better than existing GPU-based solutions.

ABSTRACT. Flow-based microfluidic biochips (FMBs) have microvalves as key components. The physical characteristics of the microvalves vary instance-to-instance due to the inherent variability of numerous fabrication parameters. In this work, we leverage this unclonable, unpredictable instance-specific system behavior and propose physically unclonable functions (PUFs) for FMBs, namely Biochip-PUFs (Bio-PUFs in short). We utilize variability in the microvalve membrane deflection response associated with the actuation pressure challenge to be our Bio-PUF parameter. Based on the distributions of the parameters measured on actual FMBs, we complement our Bio-PUF measurements via simulations of the FMB’s microvalves in Comsol Multiphysics. Furthermore, we present a scheme based on the transient response of the microvalve actuation to augment the Bio-PUF authentication. The major advantage of this scheme is that we do not need any additional hardware to generate/implement the PUF module. The biochip itself can act as PUF instances while continuing to operate in normal functioning mode.

ABSTRACT. Graphics Processing Units (GPUs) are essential in High-Performance Computing (HPC) and safety-critical applications. This market shift led to significant improvements in the programming frameworks and tools and concerns about their reliability. However, GPUs’ high complexity poses challenges in evaluating their reliability. We conducted the first cross-layer GPU reliability evaluation to unveil (and mitigate) GPU vulnerabilities. The proposed evaluation is achieved by comparing and combining extensive neutron beam experiments, fault simulation, and application profiling. Based on this detailed analysis, a novel methodology to estimate GPUs application FIT rate is proposed. The cross-layer evaluation enables two novel hardening solutions: (1) Reduced Precision Duplication With Comparison (RP-DWC) executes a redundant copy in reduced precision. RP-DWC delivers excellent fault coverage, up to 86%, with minimal execution time and energy consumption overheads (13% and 24%, respectively). (2) Dedicated software solutions for hardening Convolutional Neural Networks (CNNs) can correct up to 98% of the errors.

ABSTRACT. Machine learning (ML) has recently emerged as an application with confidentiality requirements due to the high model development costs. The limited research on securing ML hardware makes them a lucrative target for side-channel attacks. Recent works have already shown the possibility of reverse engineering the model internals by exploiting the timing, and power side channels. Solving this problem requires analyzing the vulnerabilities in the current ML applications and developing full-stack countermeasures from the ground up —formal security proofs, design and implementation of ML-specific security primitives, practical security validations, and integration of the solution in the context of current ML frameworks. We achieve three objectives: 1) analyze the side-channel vulnerabilities in the blocks of an ML accelerator, 2) design, implement, and validate countermeasures to mitigate those vulnerabilities, and 3) add usability and flexibility to the solution–support multiple ML architectures via secure software APIs, and also tape out the final ASIC.

ABSTRACT. Deep Neural Networks (DNNs) have gained widespread adoption, but they also exhibit post-deployment failures that pose risks to property and life. Consequently, enhancing DNN robustness in safety-critical areas is crucial. This paper improves the robustness of DNN models against failures that may arise during either design time or run time. For design failures, we introduce TestRank, an efficient method for identifying DNN design issues. Constrained by test resources, TestRank selects high-quality test cases leveraging intrinsic and contextual attributes of test samples. HybridRepair then offers effective failure repair by selectively annotating failure regions and utilizing semi-supervised learning techniques. To counteract run-time fault injection attacks, we propose D2NN and DeepDyve, which introduce the dual modular redundancy concept to models for protection at the neuron and system levels, respectively. This delicate redundancy achieves lightweight protection for DNN-based systems. Evaluation performed on various image classification datasets demonstrates the effectiveness of our approaches.

ABSTRACT. The automotive industry is undergoing one of the most significant technology revolutions in human history, unleashed by the power of software. Vehicles of the future hold the potential to save millions of lives, help save the planet, and deliver enriching experiences that improve our quality of life. As future generations of vehicles adopt modern technologies and a rapid rise in electronics, we must work together as an industry to enable this critical transformation.

In her keynote, Dipti will discuss the holistic approach required to deliver these vehicles of the future and the investments required in hardware, software, and industry collaborations to make this vision a reality.

-------------- Senior Vice President & General Manager, Automotive Business, Arm

Dipti leads the organization responsible for delivering Arm-based solutions in the transformational opportunities of automotive.

Previously, Dipti served as Vice President and General Manager of the Product Management and Customer Enablement division in the IoT Group at Intel. Before that, Dipti held several leadership positions at Texas Instruments and led the creation of the company’s Sitara brand of Arm MPUs.

Dipti is on the Women’s Leadership Council for the Global Semiconductor Association. She holds a BS in Computer Engineering from Texas A&M, an Executive MBA degree from the University of Texas, and is a graduate of the Executive Education programs at Stanford, Harvard, and Cambridge business schools.

ABSTRACT. High test power causes thermal damage to chips under test. We need power and thermal analyses to ensure thermal safety of ATPG patterns. This requires long runtime and large disk storage because there are many cycles in ATPG patterns. In this paper, we propose power and thermal predictions for test applications. To save runtime, we use multiple ML models and decay surface models for power and thermal predictions, respectively. To save storage, we build features from flip-flop values, so we don’t need internal logic values from gate-level simulation. Our mean absolute percentage error (MAPE) for power prediction is less than 8%. Our mean absolute error (MAE) for thermal prediction is less than 1.2℃. We enable transient thermal analysis of long ATPG patterns, with 75X runtime speedup and 118X storage reduction. Our predictions are scalable with test speed, so they can be used to optimize test time while ensuring thermal safety.

ABSTRACT. As Moore’s Law approaches its physical limits, monolithic 3D (M3D) integration offers continued power, performance, and density improvements. However, M3D integration can lead to large power supply noise (PSN) in the power distribution network due to high current demand and long conduction paths, leading to PSN-induced voltage droop problems. The PSNinduced voltage droop is more severe for at-speed delay testing than for the functional mode. Power-safe testing is therefore essential to prevent good chips from failing on the tester (i.e., yield loss). We propose a scan cell segmentation framework to reduce power consumption during scan capture. We use reinforcement learning to insert scan cell segments that can minimize switching activity without any adverse impact on test coverage. Simulation results for benchmark M3D designs highlight the effectiveness of the proposed framework.

ABSTRACT. In the recent storage market, Flash-based Solid State Drives (SSDs) have become high-performance alternatives to Hard Disk Drives (HDDs), dramatically increasing SSD shipments. To guarantee product reliability and quality to remain competitive, SSD manufacturers pay significant efforts in technology qualification and reliability design, especially in Manufacturing Self-Test (MST) processes. However, the cost of the MST process becomes more prominent as the memory density of SSD increases. In this paper, we study the MST data in over 20,000 SSDs and propose a novel and economical approach to dynamically reduce the MST overhead by proactive infant defect prediction based on Generative Adversarial Network-Attention based Spatial-Temporal Sequence-to-Sequence network (GAN-ASTSeq). It reduces the temporal cost by 80.2% (i.e., improves the efficiency by 4x) while maintaining an outstanding detection rate of defects.

ABSTRACT. The development of Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) mass production requires high-quality test solutions. Accurate and appropriate fault modeling is crucial for the realization of such solutions. This paper targets the fault modeling and test generation for all interconnect and contact defects in STT-MRAMs and shows that using the defect injection (as linear resistors) and circuit simulation for fault modeling without incorporating the impact of magnetic coupling will result in an incomplete set of fault models; hence, not accurate enough. Magnetic coupling is an inherent property of STT-MRAM (by stray field) and may foster the occurrence of additional memory faults. Not considering magnetic coupling clearly will give rise to additional escape. The paper introduces a compact model for STT–MRAM that incorporates the intra- and inter-cell stray field, uses this model to derive the whole set of fault models for interconnect and contact defects, and finally proposes an efficient test solution.

ABSTRACT. The mass production of Resistive Random Access Memory (RRAM) devices is impacted by the emergence of unique defects and faults. Hence, there is a pressing need for a comprehensive understanding of manufacturing defects and the development of high-quality RRAM tests. This paper introduces and characterizes a new defect called Ion Depletion (ID); this defect leads to a reduction in the high resistance state and not the low resistance state, while its non-linear electrical characteristics cannot be effectively described through traditional fault modeling and test approaches. To address this challenge, a Device-Aware (DA) defect model is developed, incorporated into a Verilog-A RRAM model, and calibrated using measurements to accurately describe the physical behavior. Afterward, fault analysis is performed based on the DA defect model, with simulation results demonstrating that the ID defect may sensitize undefined state faults. Finally, dedicated test and diagnosis solutions for the ID defect are proposed.

ABSTRACT. Emerging devices are susceptible to manufacturing defects due to immature fabrication processes. Ferroelectric field-effect transistors, referred to as FeFETs, are promising emerging devices, but the impact of manufacturing imperfections on these devices has yet to be studied. Thus, we combine a technology CAD (TCAD) model with a fault-injection technique to represent fabrication defects in a FeFET. The TCAD model is calibrated against a fabricated metal-ferroelectric-metal capacitor and uses a multi-domain ferroelectric-layer structure. We address two classes of defects in the ferroelectric layer and map them to stuck-at-fault models referred to as neutral faults (SAP0) and stuck-at-plus and stuck-at-minus (SAP+ and SAP−) faults. We also develop a machine-learning framework to characterize these fault-injected FeFET devices. Our study of defects in ferroelectric FET (FeFET), which is done for the first time, and the insights gained thereof can provide valuable feedback for the fabrication and yield learning of FeFET-based circuits.