The ITC’23 Program Committee is taking some inspiration from the Physics community for our opening panel on Monday afternoon: every decade, the US National Research Council publishes a short list of the “grand challenges” in the discipline which then drives planning, research, and funding.  This approach has spread to other organizations, including the National Academy of Engineering, which has a list of 14 such challenges.

We’ll get in on the action with an interactive town hall session that aims to articulate the “grand challenges of test” that our community can use to help guide the direction of innovation in our world.  Dr. Anne Gattiker from IBM Research will facilitate the discussion with some prompting from a few experts to elicit input from the entire audience.  Here’s your chance to make your voice heard and be part of an incredibly exciting time in our industry.

Panelists:

Phil Nigh, Broadcom

John Carulli, Global Foundries

Jeff Rearick, AMD

2 more panelists TBD

ITC 2023 is happening at a time of significant activity in the foundational IEEE standards used by our community: IEEE 1149.1 and IEEE 1687 are both in the process of being refreshed as they approach their 10-year anniversaries, IEEE P2427 is deep into the ballot resolution phase, other family members IEEE P1687.1 and P1687.2 are well underway, IEEE P2654 is tackling the very challenging problem of system test access and management, and IEEE P2929 is making the first substantial foray into standardization of hardware debugging techniques.  This session will give the audience an update on the progress being made by these working groups and will emphasize the interactions between these various standards in pursuit of a coherent set of solutions.

Speakers:

• 1149.1 : Heiko Ehrenberg (GoepelUSA)
• 1687 : Martin Keim (Siemens)
• P2427 : Anthony Coyette (On Semi)
• P1687.2 : Steve Sunter (Siemens)
• P1687.1 and P2654 : Jeff Rearick (AMD)
• P2929 : Sankaran Menon (Intel)

The presenters are going to talk about the latest developments in advanced memory technologies and reveal application trends in the age of automotive and artificial intelligence.

Talk 1: “Test Challenges for GAA in the Race Between Nanometers and Angstroms”, Karen Amirkhanyan (Synopsys, Armenia), Hayk Danoyan (Synopsys, Armenia), Artur Ghukasyan (Synopsys, Armenia), Gurgen Harutyunyan (Synopsys, Armenia), Knarik Kyuregyan (Synopsys, Armenia), Grigor Tshagharyan (Synopsys, Armenia)

Talk 2: “NN-ECC: Embedding Error Correction Codes in Neural Networks using Multi-task Learning”, Soyed Tuhin Ahmed (Karlsruhe Institute of Technology, Germany), Surendra Hemaram (Karlsruhe Institute of Technology, Germany), Mehdi B Tahoori (Karlsruhe Institute of Technology, Germany)

Talk 3: “DFT, Test Challenges and Solution to Enable the Large Scale SoC with HBM”, Shinichiro Ikeda (Socionext, Japan), Hitoaki Nishiwaki (Socionext, Japan), Arun Kumar (Synopsys, USA)

Presentations from four Platinum Sponsors: Synopsys, Advantest, Galaxy and Teradyne. Each presentation will be 30-minute long.

The Heterogenous Integration Roadmap is an industry-wide collaboration guiding the chiplet-based ecosystem that has become the driver of the “More-than-Moore” era.  One key element of that roadmap is taking shape as the Universal Chiplet Interconnect express standard, the first version of which has been published and is quickly being followed up with extensions dealing with, among other things, test features.  This session will outline the key points of the HIR and then dive deeply into several aspects of UCIe.

Presenters:

Michael Braun, Advantest

Debendra Das Sharma, Intel

Sandeep Goel, TSMC

Yervant Zorian, Synopsys

Abstract: The session will discuss hardware, communication and societal challenges to enable an immersive and inclusive Metaverse

Talk 1: “Addressing Metaverse Hardware Reliability challenges with Silicon Lifecycle Management”, Jyotika Athavale (Synopsys, USA), Yervant Zorian (Synopsys, USA)

Talk 2: “Bridging Technology and Humanity to Cultivate an Inclusive Metaverse”, Jeewika Ranaweera (IEEE Future Directions)

Talk 3: "Successes and challenges of making the Metaverse accessible everywhere and for everyone", Nikolai Leung (Qualcomm, USA), Dr. Bojan Vrcelj (Qualcomm, USA), Dr. Imed Bouazizi (Qualcomm, USA), Dr. Peerapol Tinnakornsrisuphap (Qualcomm, USA), Dr. Prashanth Hande (Qualcomm, USA), Dr. Thomas Stockhammer (Qualcomm, Germany)

The test community is a diverse one, yet many of us may not be familiar with either the subtleties or the complexities of how best to work in such an environment.  In this moderated panel session, we’ll hear several of our test colleagues tell their stories and give us practical suggestions on how we can be better allies, help members of under-represented groups get a better foothold, and create more welcoming and inclusive workplaces.  In contrast to (often counterproductive) DEI compliance training, this session focuses on the narratives from people you know in our community and steps you can take to become a more aware coworker.

1- Speaker: Haralampos-G. Stratigopoulos (Sorbonne Université, CNRS, LIP6)Title: Functional Safety of Spiking Neural Network VLSI Implementations

2- Speaker: Stefano De Carlo (Politecnico di Torino)

Title: Safety of AI and AI for safety: from CMOS to emerging technologies in neural networks

3- Speaker: Yervant Zorian (Synopsys)

The explosion of Artificial Intelligence applications has already touched the design and test communities and may be poised to fundamentally change the way that we test engineers approach our jobs.  The panelists in this session will catalog some of the existing tasks where AI has made an impact, then speculate on others that may be next on the list.  The underlying question that the discussion with the audience will seek to answer is “Will AI take my job away -or- make me better at doing my job?”

AI for the front-end (DFT, ATPG, Fault simulation) (3 x 15-minute talks)

        Krishna Chakravadhanula (Cadence Design Systems)

        Rahul Singhal (Synopsys)

        Ron Press (Siemens)

    AI for the back-end (diagnosis, debug, yield enhancement) (3 x 15-minute talks)

        Narender Hanchate (Cadence Design Systems)

        Guy Cortez (Synopsys)

        Jayant D’Souza (Siemens)

$52 billion from the US Chips Act and €43 billion ($47 B) from the EU Chips Act is a lot of money flowing into the semiconductor business.  How will it be spent?  Besides the foundries, will there be a portion available to the design and test sectors?  What is the status of these programs and how can we learn more about them?  The experts on our panel will share their knowledge and experience.

Panelists:

Antonio De La Serna (Siemens)

Jonathan Hoganson (AMD)

John Carulli (Global Foundries)

Subramanian Iyer (Director of the CHIPS R&D National Advanced Packaging Manufacturing Program)

"Fleet Health and Silent Data Corruptions in Meta Infrastructure", Harish Dattatraya Dixit, Meta

“Could Standardizing RAS Requirements Impact Silent Data Corruption?”, Yervant Zorian, Jyotika Athavale, Synopsys

“Harnessing the Power of Microarchitectural Modeling for Fast Prediction of SDC rates throughout Silicon Lifetime”, Dimitris Gizopoulos, University of Athens

Silent Data Errors (aka Silent Data Corruption) has garnered significant attention in the last couple of years emerging from relative obscurity over the previous two decades. At ITC 2022, there was near unanimous agreement in the Test community that the topic of Silent Data Errors (SDE) is one of the biggest test challenges now and in the foreseeable future. Most of the focus of the Test Community in the past has been on achieving extremely high test quality at time t=0, relying on extensive DFT methodologies and design rule checks to achieve high test coverage coupled with advanced ATPG techniques to minimize test escapes and field returns.

With wide-spread deployment of leading-edge semiconductor products in high-dependability and mission critical applications that also have a long field life any latent defects, test escapes, design marginalities, and aging related degradation may result in SDEs. The panel will address and discuss the following questions related to SDEs.

• What are the primary contributors of SDE – test escapes, design marginalities, design bugs, software bugs, or aging related degradation? What are we learning from the RMA parts?
• Is the quality of test (time t=0 testing) good enough today? What is missing? How can test quality be improved?
• If one wants to use a wide variety of advanced defect models to improve test quality, the number of test patterns is going to explode. How to deal with ever-increasing number of test patterns without affecting the test cost?
• Does SDE present an opportunity to the Test community to look at issues well beyond time t=0, and bring in new innovations and technologies into the mainstream and give a new lease of life to Semiconductor Test?

This panel of experts from diverse field will bring in fresh insights to this emerging topic and engage with the audience in a lively discussion of the challenges and opportunities that SDE presents to the Test community.

Moderator: Anne Meixner (Semiconductor Engineering)

Panelists:

1. 1. Sandeep Bhatia (Google)
   2. Sankar Gurumurthy (AMD)
   3. David P. Lerner (Intel)
   4. Jennifer Dworak (SMU)
   5. Janusz Rajski (Siemens DISW)
   6. Noam Brousard (proteanTecs)