ABSTRACT. High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure such as co-packaged optics to meet the demands of the supercomputing landscape. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape.

Universal Chiplet Interconnect Express (UCIe), is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; like the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express® and Compute Express Link (CXL)®. In this talk, we will discuss the usages and key metrics associated with different technology choices in UCIe and how it will evolve going forward. We will also delve into the challenges and opportunities for chiplets connected through UCIe, including test and debug.

------------

Dr. Debendra Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies in the Data Platforms and Artificial Intelligence Group at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture.

Dr. Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Board Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.

Dr. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst.​ He holds 175 US patents and 450+ patents world-wide. He is a frequent keynote speaker, plenary speaker, distinguished lecturer, invited speaker, and panelist at the IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, various Universities (CMU, Texas A&M, Georgia Tech, UIUC, UC Irvine), and Intel Developer Forum. He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the IEEE Region 6 Outstanding Engineer Award in 2021, the first PCI-SIG Lifetime Contribution Award in 2022, and the IEEE Circuits and Systems Industrial Pioneer Award in 2022.

ABSTRACT. This paper proposes a new framework for inserting test points (TPs) at RTL enabling better Power-Performance-Area-Testability optimization during synthesis yielding quick turn-around time and faster Time-to-Market. It introduces the concept of editable nodes in RTL designs and avoids locations that are difficult to modify. Early identification of editable nodes in the RTL to guide and drive the TP analysis engine helps in improving the quality of TPs inserted into the design. In addition, the proposed methodology involves optimization of the RTL, a quick synthesis of the design, and TP analysis at the netlist-level by avoiding locations that are pre-marked as ‘dont-touch’. Once the TP locations are identified in an internal unmapped gate representation, they are back-annotated and inserted in the RTL. Experimental results show that the effectiveness of TPs inserted at RTL closely match the gate-level with added benefits of better area, timing, test coverage, and pattern-count optimization.

ABSTRACT. Chip-let based multi-die 3DIC design methodology is the paradigm shift in semiconductor manufacturing that enables scalable design integration for SysMoore era. Stacking multiple heterogeneous dies in a single stack opens chip design to a world of unexplored challenges. One such challenge is testing of the individual dies and the integrated complex stack to improve DPM. The IEEE 1838 standard defines 3DIC DFT architectures for individual dies and stack level test. In this paper we present a case study on an industrial design to leverage EDA tools and flows to implement IEEE 1838 compliant DFT architectures for full die and integrated stack.

ABSTRACT. Accurate static linearity measurement of high-resolution analog-to-digital converters (ADCs) requires multiple hits per code (HPC), leading to high test time and test cost. State of the art techniques for linearity testing require analog stimuli that hit all the ADC codes, thus generating large volume of data. This paper introduces a new algorithm for linearity testing of successive approximation register (SAR) ADCs with significantly less data and time. The proposed algorithm uses a linear combination of a set of parameters along with curve fitting techniques to estimate the ADC nonlinearity, by hitting a small subset of the ADC codes. Simulation and measurement results demonstrate that the integral nonlinearity (INL) a 16-bit ADC obtained using the proposed method with only 0.03 HPC, closely matches that from a 256-HPC histogram test with 0.4 LSB accuracy. Additionally, the ADC test data acquisition time has been substantially reduced to 3% of existing 1-HPC test methods.

ABSTRACT. Millimeter-wave radars are used to estimate the position of an object relative to the radar position in terms of the range, azimuth angle, and elevation angle. Typical radar operation includes transmitting a chirp signal, receiving the signal reflected by the objects in the environment, and mixing these signals at the receiver chain. For multiple antenna systems, the range can be calculated for each transmit and receive antenna, yielding multiple measurements. To increase the accuracy, these results are averaged. Angle estimation makes use of the phase differences between different antenna paths. Since there is only one calculation across all antenna elements, this calculation does not benefit from averaging. In addition to these random errors, systemic errors occur in the process of angle calculation. In this paper, we analyze the root cause of the systemic error and propose solutions to correct for this error to increase angle estimation accuracy.

ABSTRACT. Prevalent specification-based AMS testing techniques require the use of complex test circuits or regressors that are difficult to implement on-chip. Complementary defect based testing requires simulating large defect sets under assumed failure mechanisms. Our proposed OATT approach overcomes these limitations. OATT maximizes the number and magnitude of the statistical principal components (PCA) of the time-domain DUT test responses across manufacturing process corners. This allows construction of multi-dimensional Gaussian probability density model that characterizes the distribution of responses in the principal components domain. Outliers of this model are classified as defective devices using calibrated confidence ellipses, implicitly detecting devices with parametric as well as hard defects. Enabled by the PCA approach, the DUT response is acquired using coherent undersampling and does not require explicit signal reconstruction. Post-manufacture tuning is performed to minimize statistical distance from the nominal Gaussian model using reinforcement learning. Simulation results demonstrate the viability of the proposed approach.

ABSTRACT. This paper describes two harmonics cancellation techniques using digital predistortion for low-distortion sinusoidal signal generation with direct digital synthesizer; it is targeted for the dynamic characteristic testing of 14-bit and 16-bit 1MS/s ADCs and their testing sinusoidal wave frequencies are around 100kHz. (i)The first one is an analog method for the 16-bit ADC testing. The HD2 and HD3 of the raw sinusoidal signal are measured and their 180-degree phase-shifted signals are generated with an auxiliary DAC and added to the original signal to cancel the HD2 and HD3. Our experiments show that -120dBc of HD2 and HD3 can be achieved. (ii)The second is a digital method for the 14-bit ADC. The digital data of the 180-degree phase-shifted signals of the measured HD2 and HD3 are added to the raw digital data of the direct digital synthesizer. Our experiments show that -92dBc of HD2 can be achieved.

ABSTRACT. Stress test requires voltage elevation for screening latent defects. Timing closure at elevated voltages increases area, power, and timing convergence effort. Use of toggle monitor and timing closure on select DFT logic addresses these issues.

ABSTRACT. One of the bottleneck’s being observed for multi-billion gate SoC’s is the overall time taken to verify various modes of operation in simulation. Analysis done with large number of Testbenches, we can identify few steps like compile and elaboration of the DUT, simulation of power-on and initialization sequences, etc., being repetitive in nature. Longer it takes to compete these repetitive steps, lower the efficiency of the overall cycle and longer the resource will be utilized. This paper proposes a methodology for improving the Turn-around-Time (TAT) and resource utilization for verification of Design-For-Test patterns.

ABSTRACT. Manufacturing of very high scale semiconductor chips can potentially result in defects in global control and clock circuitry. Such a defect can lead to multiple simultaneous scan chain failures and was previously omitted in volume yield learning efforts. In this paper, we will present a novel methodology that provides diagnosis of defects in the control and clock networks. We present evaluation results using advanced node production chips silicon data and failure analysis.

ABSTRACT. If a transmission line carrying a high-speed signal is damaged, for example by poor contact, the transmitted signal will have a slight increase in jitter. Normally, an oscilloscope or a Vector network analyzer (VNA) is required to measure this jitter increase. In this study, we will show that it is possible to diagnose small losses in transmission lines using only an FPGA without instruments by transmitting a pulse signal through the CH to be diagnosed and then oversampling it in an FPGA to statistically accurately measure the width of the transmitted pulse and detect the small pulse width reduction that occurs when a loss occurs.

ABSTRACT. Sometimes an ATE will measure the output characteristics of a specific pin on an IC you want to test. Typically, an output pin is set to output a value of 0 or 1, and the ATE measures the voltage across that output with a load resistor connected. In this case, the load resistor is either a discrete resistor or a termination resistor inside the tester's signal receiving IC, but sometimes the resistance value of this resistor is incorrect or you want to change it to test with a different resistance condition. This may require additional resistors or switches. This paper presents a method to change the load resistance without additional components by using the current output function of the PMU built into the tester equipment.

ABSTRACT. Embedded non-volatile RAM technology, and in particular Magneto-resistive RAM (MRAM), continues making great progress in read/write speed and cycling endurance, now rivaling traditional memory technologies. This advancement together with their low-energy consumption and non-volatility opens huge application markets. While stand-alone MRAM products are already being deployed, the first pilot applications for embedded MRAM are just starting to emerge. The availability of Design-for-Test (DFT) tools is key in the transition from low-volume technology exploration and pilot projects to high-volume production. In this paper we explore a new aspect of a Memory Built-In Self-Test (MBIST) tool for eMRAM, namely Error Correcting Code (ECC)-aware test and repair technology. This new MBIST capability provides the ability to make in-system, user-programmable trade-offs concerning the eMRAM repair resources. Having extra control over the repair resources in turn increases both manufacturing yield as well as the longevity of the product in its application.

ABSTRACT. For successful read operation in MRAM, resistive memory requires a reference resistance which has middle resistance values of data 0 and 1. Generally, the read method used in MRAM is to use a reference cell having the intermediate resistance. This conventional method has weakness on read disturb rate and temperature change. To avoid these weaknesses, new read scheme has been developed that sets reference resistances with controllable resistances instead of reference cells. This paper presents the algorithmic trim method of finding the reference resistance by adjusting the controllable resistor. The number of failed bits for each read resistance was checked. In addition, a sampling method and a binary search method were introduced to improve test efficiency. Using algorithmic read resistance trim, yield was improved by 23.7% and test time was reduced by 80%. Also, test time of trim module was reduced by 95% compared to the beginning (<0.4 second).

ABSTRACT. In the wafer testing process, the needle tips for circuit probing (CP) should always be contamination-free. However, continuous testing will affect measurement quality since probe tips are exposed to contaminating substances. Thus, proper prober needle cleaning mechanism plays an important role. Three circuit probing cleaning challenges may result in yield loss. First, prober needle cleaning are currently defined by prior experience and the occurrence of die failure. Second, the process is inefficient since there is no prediction mechanism for embedded and bonded debrisprior to a test. Third, over cleaning reduces the needle's life. To address these issues, we propose a framework based on real-time die contact resistance analysis. The framework employs supervised machine learning to develop a recognition mechanism for detecting sudden foreign material buildups and monitoring needle degradation based on the sensor data so as to enhance yield of wafer probing and increase the expected probe life cycle.

ABSTRACT. Determining the minimum operating voltage ($V_{min}$) of chip designs is critical for low power dissipation and assurance of functional safety during manufacturing test and in-field monitoring. We demonstrate how on-chip monitor data can be leveraged to provide accurate minimum operating voltage prediction using a domain-specific machine learning approach. Given limited measured chip data, the key challenge in developing a machine learning approach is to provide an accurate prediction while addressing overfitting and selecting a subset of optimal features. To this end, we propose to utilize a novel monotonic lattice neural network architecture that is geared towards accurate prediction by imposing domain-specific monotonic relationships between the input sensor data and $V_{min}$. Furthermore, we perform effective feature selection by considering both the correlation between each feature and $V_{min}$ as well as the co-linearity between the features. Experiments demonstrate superior performance in comparison with linear regression and conventional neural networks.

ABSTRACT. Functional broadside tests can be used for detecting delay faults without overtesting. A large pool of functional broadside tests is obtained when the tests are extracted from available functional sequences. In this case, tests that are extracted later may be effective for test compaction even if they do not detect new faults. This article addresses the problem of test compaction for path delay faults in this scenario. The main contribution of the article is the use of clusters of lines satisfying propagation conditions for path delay faults to identify tests that are potentially important for test compaction. Experimental results for benchmark circuits demonstrate the importance of considering tests that do not detect new path delay faults, and the effectiveness of clusters.

ABSTRACT. Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate the effectivity of such patterns, different circuit instances may show a different fault coverage. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings. The method overcomes the complexity limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations. A statistical learning scheme maximises the coverage of SDFs in an entire circuit population following the variation parameters of a calibrated industrial FinFET transistor model. The method combines efficient ATPG for Transition Faults with fast timing-aware fault simulation on GPUs. Experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detect while the fault coverage even increases compared to both N-detect and timing-aware ATPG.

ABSTRACT. Test vehicles are important circuits for process yield learning at early stage. In-house customized standard cell libraries should also be evaluated from the yield perspective. In this paper, we propose novel logic test vehicles to offer high resolution diagnosis capability of in-house designed standard cell libraries. Both stuck-at and cell-aware faults are injected to evaluate the diagnosability of the test vehicles. Nearly ideal cell-level diagnosis results can be obtained to reflect the FEOL/MEOL yield detractors of the process technology under development. All standard cells in libraries are embedded in the test vehicles with even distributions. The designed test vehicles are compatible with commercial physical design flow and have statistically significant area when limited volume of chips are considered.