ITC 2018: INTERNATIONAL TEST CONFERENCE

This page contains an index consisting of author-provided keywords.

3
3D IC	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
3D-stacked ICs	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
A
ABFT	*Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
access-time minimization	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
Accuracy	Improving Diagnosis Resolution and Performance at High Compression Ratios
Adaptive testing	Fine-Grained Adaptive Testing Based on Quality Prediction
Alternate test	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
analog and mixed-signal validation	Production Tests Coverage Analysis in the Simulation Environment
Analog circuits	Improving Analog Functional Safety Using Data-Driven Anomaly Detection
Anomaly Detection	Improving Analog Functional Safety Using Data-Driven Anomaly Detection
Asynchronous circuits	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
ATPG	Detection of low power Trojans in standard cell designs using built-in current sensors. DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies Improving Power, Performance and Area with Test: A Case Study
Automatic test pattern generation	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
Automotive IC	Improving Analog Functional Safety Using Data-Driven Anomaly Detection
automotive reliability	XLBIST: X-Tolerant Logic BIST
B
Bayesian Networks	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
bit error rate	Polynomial Chaos modeling for Jitter estimation in high-speed links
broadcast	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
Built-In Self-Diagnostic	*Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips
Built-in self-test	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test
C
Compression	Improving Diagnosis Resolution and Performance at High Compression Ratios
Concolic testing	Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
Consulting	Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
Control checkout	Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
Core router system	Self-Learning Health-Status Analysis for a Core Router System
Counterfeit Detection	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
coupling	Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
coverage analysis	Production Tests Coverage Analysis in the Simulation Environment
Cpk	Fine-Grained Adaptive Testing Based on Quality Prediction
critical area	Total Critical Area Based Testing
D
Data Analytics	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
Data-Driven	Improving Analog Functional Safety Using Data-Driven Anomaly Detection
debug methodology	An effective methodology for automated diagnosis of functional pattern failures to support silicon debug
defect based test	Total Critical Area Based Testing
defect classification	Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
Defect localization	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Defect Oriented Test	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Defect simulation	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Defects	Electrical Modeling of STT-MRAM Defects
Design for testability	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
DFT	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
Diagnosis	Improving Diagnosis Efficiency via Machine Learning Improving Diagnosis Resolution and Performance at High Compression Ratios
dicing tape	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
dictionary based diagnosis	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
digital-to-analog-converters	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
DPPM Reduction	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
E
Electromagnetic Measurements	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
Emerging Non Volatile Memory	Test for Supply Noise and Endurance for Emerging Non-Volatile Memories
Endurance Test	Test for Supply Noise and Endurance for Emerging Non-Volatile Memories
extrapolated reconstruction	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
F
Fail log	Improving Diagnosis Efficiency via Machine Learning
Failure analysis	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
fault coverage	Total Critical Area Based Testing
fault model	Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
fault tolerance	*Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
Fault-Tolerant	*Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips
faults	Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
feature engineering	Self-Learning Health-Status Analysis for a Core Router System
FinFET Technologies	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
frequency	Improving Power, Performance and Area with Test: A Case Study
functional broadside tests	On Close-to-Functional Test Sequences
functional diagnosis	An effective methodology for automated diagnosis of functional pattern failures to support silicon debug
Functional Safety	Improving Analog Functional Safety Using Data-Driven Anomaly Detection
functional test sequences	On Close-to-Functional Test Sequences
G
Generative Model	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
H
Hardware Security	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Hardware Trojan	Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
Hardware Trojan Detection	Detection of low power Trojans in standard cell designs using built-in current sensors.
hardware trojans	Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Health monitoring	Self-Learning Health-Status Analysis for a Core Router System
high speed channels	Polynomial Chaos modeling for Jitter estimation in high-speed links
high-speed signal interface test	A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
HVM diagnosis	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
I
IDDT	Detection of low power Trojans in standard cell designs using built-in current sensors.
IEEE 1687	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
IJTAG	IJTAG Integrity Checking with Chained Hashing Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
in-system automotive test	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test
Instruction set characterization	Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
integrity checking	IJTAG Integrity Checking with Chained Hashing
Intra-cell diagnosis	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
IP Trust Verification	Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify
IR-Drop	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
Isometric compression	Hypercompression of Test Patterns
J
jitter	Polynomial Chaos modeling for Jitter estimation in high-speed links
jitter injection	A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
JTAG security	Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
L
Logic BIST	XLBIST: X-Tolerant Logic BIST
Low power test	Hypercompression of Test Patterns
M
Machine Learning	Polynomial Chaos modeling for Jitter estimation in high-speed links EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs Improving Diagnosis Efficiency via Machine Learning Fine-Grained Adaptive Testing Based on Quality Prediction Improving Analog Functional Safety Using Data-Driven Anomaly Detection
Machine learning based test	Artificial Neural Network Based Test Escape Screening Using Generative Model
Manufacturing yield	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
MEDA Biochips	*Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips
memristor	Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
micro-bumps	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
microprocessor debug	An effective methodology for automated diagnosis of functional pattern failures to support silicon debug
modeling	Polynomial Chaos modeling for Jitter estimation in high-speed links
Modular Test	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
N
near-threshold technology	Improving Power, Performance and Area with Test: A Case Study
Netlist Transformation and Simplification	TimingSAT: Decamouflaging Timing-based Logic Obfuscation
Neural network	Artificial Neural Network Based Test Escape Screening Using Generative Model
Neural Networks	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
No-Touch Test	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
O
Objective Analysis	Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
online scan diagnosis	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
Outlier screening	Artificial Neural Network Based Test Escape Screening Using Generative Model
overtesting	On Close-to-Functional Test Sequences
P
parallel IJTAG design	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
partial scan	Improving Power, Performance and Area with Test: A Case Study
polynomial chaos theory	Polynomial Chaos modeling for Jitter estimation in high-speed links
PPA	Improving Power, Performance and Area with Test: A Case Study
Pre-bond TSV test	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
Pre-silicon verification	Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
Precharge half-buffer	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
Principal Component Analysis	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
process variation	Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
production testing	Production Tests Coverage Analysis in the Simulation Environment
PVT variation	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
Q
QA/QC	Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
QoR	Improving Diagnosis Resolution and Performance at High Compression Ratios
quality prediction	Fine-Grained Adaptive Testing Based on Quality Prediction
Query-based Attack	TimingSAT: Decamouflaging Timing-based Logic Obfuscation
R
Read Failure	Test for Supply Noise and Endurance for Emerging Non-Volatile Memories
Resilience	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
Resolution	Improving Diagnosis Resolution and Performance at High Compression Ratios
RRAM	*Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
RRAM-based computing system	*Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
S
scan diagnosis	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
Scan-based test	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test Hypercompression of Test Patterns
secure hash	IJTAG Integrity Checking with Chained Hashing
segmented model	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Self-adaptation	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
Self-calibration	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
Self-learning	Self-Learning Health-Status Analysis for a Core Router System
SIC	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
Simulation	Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
sinusoidal interference injection	A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
SoC	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
SRAM diagnosis	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
static linearity testing	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
stressed eye testing	A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
STT-MRAM	Electrical Modeling of STT-MRAM Defects
stuck-at faults	Improving Power, Performance and Area with Test: A Case Study
Supply Chain Security	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
switching activity	On Close-to-Functional Test Sequences
Symbolic execution	Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
System Level Test	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Systems Engineering	Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
T
tape frame	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Test	IJTAG Integrity Checking with Chained Hashing Electrical Modeling of STT-MRAM Defects
test access	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Test data compression	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test Hypercompression of Test Patterns
Test generation	On Close-to-Functional Test Sequences Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
test quality	Total Critical Area Based Testing
test scheduling	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
test time reduction	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Testing	Test for Supply Noise and Endurance for Emerging Non-Volatile Memories
thinned wafer	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Time-series analysis	Self-Learning Health-Status Analysis for a Core Router System
Timing Aware CAT	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Timing-based IC Camouflaging	TimingSAT: Decamouflaging Timing-based Logic Obfuscation
TNS	Improving Power, Performance and Area with Test: A Case Study
Toggle Generator	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
transition delay faults	Improving Power, Performance and Area with Test: A Case Study
transition faults	On Close-to-Functional Test Sequences
trojan prevention method	Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
trust	IJTAG Integrity Checking with Chained Hashing
U
uSMILE	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
V
Variational autoencoder	Artificial Neural Network Based Test Escape Screening Using Generative Model
Verification of test and debug circuitry	Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
volume diagnosis	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
W
wafer probing	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
wireless cryptographic IC security	Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Write Failure	Test for Supply Noise and Endurance for Emerging Non-Volatile Memories
X
X-tolerance	XLBIST: X-Tolerant Logic BIST

Disclaimer | Powered by EasyChair Smart Program