Panelists:

• Dr. David Lam, CEO, MultiBeam
• Dr. Christian Boit, TU Berlin
• Dr. Ed Principe, President, Synchotron Research, Inc.
• Dr. Yousef Iskander, Technical Leader, Cisco
• Dr. Yier Jin, University of Florida

Panel Moderator: Dr. Mark Tehranipoor

Keynote Speaker:

Title: Working with safe, deterministic and secure intelligence from cloud to edge

Kenneth P. Caviasca
Vice President, Internet of Things Group
General Manager, Architecture, Silicon and Platform Engineering

The Internet of Things (IoT) will be the largest revolution in the data economy. At Intel, we understand the exponential power of data, and we’re making it practical and economical to put it to work from the edge to the cloud. Intel® technologies purpose-built for IoT deliver optimized performance at every point, practical ways to use artificial intelligence, broad connectivity support, and a built-in foundation of security to help protect your data and systems. Proven solutions from our partner ecosystem can reduce the time, cost, and risk of IoT deployments. By harnessing the massive flood of data generated by connected things—and using it to gain actionable insights—we’ll accelerate business transformation to a degree never seen before.

Kenneth P. Caviasca is vice president in the Internet of Things Group and general manager of architecture, silicon and platform engineering at Intel Corporation. He has overall responsibility for computing platforms targeted to the Internet of Things (IoT) market segment, including planning, architecture, user experience priorities, silicon definition, operating system porting, hardware, firmware, validation and manufacturing test. The IoT platforms developed by his team encompass product offerings based on Intel® Atom™, Intel® Core™ and Intel® Xeon® processors. Since joining Intel in 1984 as a silicon engineer in automotive controllers, Caviasca has held various technical and management positions in flash microcontrollers, embedded devices, video signal processors, security devices, chipsets, network processors, server processors and manufacturing operation startup. Before assuming his current position, he managed platform development for the Intelligent Systems Group, overseeing hardware, validation and software integration development. Earlier in his Intel career, he managed silicon development for the Communication Infrastructure Group and led a team responsible for delivering system-on-chip, server-class and chipset products for the embedded and communications market segment. Between 2008 and 2010, Caviasca’s development team won several premier supplier awards from industry-leading communications equipment suppliers. He and his team also won an Intel Achievement Award in 2004 for excellence in network processor development. Caviasca earned his bachelor’s degree in computer and electrical engineering from the University of Bridgeport in Connecticut and his MBA degree from the W. P. Carey School of Business at Arizona State University. He holds seven patents in circuits, CPU and video systems architecture.

This session comprises 10 presentations to highlight 10 posters in this year ITC poster program.

PO2: A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks. M. Portolan, R. Cantoro, E. Sanchez, M. Reorda, Politecnico di Torino

PO6: Dynamic Cloud-based Data Collection System. George Lawton III, Lawton Software

PO7: Layout-aware Wrapper for IP cores. Darshal Patel (AMD) and Khushboo Agarwal (AMD).

PO8: IEEE P1687.1: Extending 1687 to Non-TAP Interfaces. J. Rearick, AMD, A. Crouch, Amida, M. Keim, Mentor, M. Laisne, Dialog Semi, G. Colon-Benet, Intel

PO9: Visually-enhanced Dynamic Part Average Testing. A. Coyette, R. Vanhooren, W. Dobbelaere, ON Semiconductor, B. Esen, N. Xama, J. Caicedo, G. Gielen, Katholieke Universiteit Leuven

PO13: Concurrent IJTAG. Rene Krenz-Baath,HSHL

PO15: IEEE P1687.2: Extending 1687 to Analog Circuits. J. Rearick, AMD, S. Sunter, Mentor, V. Zivkovic, Cadence

PO22: Optimal SCAN Vector Count. T. Kogan, A. Rabenu, Intel

PO23:  What’s up with Analog Test Coverage?: IEEE P2427 IEEE - Working Group Progress. A, Meixner, The Engineers' Daughter, S, Abdennadher, Intel), S, Sunter, Mentor a Siemens Company. P. Sarson, Dialog Semiconductor

PO28: Method to Measure and Improve Toggle Coverage During High - Volume Quick-Kill Stress. J. Cooper, Intel

This welcome reception will be a joint event between ITC and ISTFA

Embedded Tutorial - Analog Fault Simulation: Practical Applications, Case Studies and Challenges

by Rubin Parekhji, Devanathan Varadarajan, Lakshmanan Balasubramanian, and Ken Butler of Texas Instruments

Analog fault simulation is gaining significant importance now given the compelling needs for robustness and high quality for analog IPs. EDA offerings have emerged, and standards are emerging as well. In this embedded tutorial, the presenters, (who have been working in this area for the past few years), will provide an overview of fault simulation for analog circuits, and share their experiences and highlight challenges required to be addressed to make its adoption main-stream. Case studies on actual analog IPs demonstrating several applications in design and manufacturing (coverage, defect based test, diagnosis, test optimisations, sensitivity analysis, etc.) will be presented.

Panelists:

• Navin Bishnoi, GLOBAL FOUNDARIES
• Christophe Eychenne, Bosch
• Nir Maor, Qualcomm
• Riccardo Mariani, Intel
• Rajagopalan Srinivasan, Nvidia
• Yervant Zorian, Synopsys

Panel Moderator: Paolo Bernardi, Polito Torino

Title: Trick or Treat: Is your supply safe? 

Abstract: Much like candy that ends up on the kitchen table at the end of a successful Halloween night, the microelectronics supply chain is a diverse bag of goodies that needs to be checked before it can be consumed.  This talk will explore challenges and opportunities in trusting and assuring an increasingly complex electronics global supply chain.

Bio: Dr. Matthew Casto is Chief of the Air Force Research Laboratory, Sensor's Directorate, Trusted Electronics Branch and is the Air Force's Hardware Assurance technical lead for the Department of Defense (DoD) Joint Federated Assurance Center. Dr. Casto is a Senior Electronics Engineer with a BSEE and MSEE degree from Wright State University, and a PhD from The Ohio State University Electro-science Laboratory. In his current role, Dr. Casto leads the Science and Technology portfolio for the DoD's Trusted and Assured Microelectronics Initiative, developing a new trust approach to ensure enduring availability and assured access to state-of-the-art microelectronics.

Instead of a regular keynote, this plenary session comprises several elevator talks to provide different perspectives on AI in Test. A follow-up panel will be held in the afternoon for further discussion.

The speakers include:

Ken Butler, Founder, Engineering Tools and Analytics Team, Texas Instruments, Dallas, Texas - A Semiconductor Test Perspective

       As we all know, semiconductor manufacturing is a complex process with many interacting components, any one of which can negatively impact quality and cost.  AI techniques have already shown great promise as a means to detect, diagnose, and correct for these issues quickly in volume production.  We will examine what is in use today and aspects that are being investigated for future deployment.

Anne E Gattiker, Principal Research Staff Member, IBM - Deep Learning perspective

      Recently Deep Learning, e.g. employing many-layered neural networks, has revolutionized fields such as Computer Vision and Natural Language Processing. What factors have lead to such remarkable advances in these fields and could the test field achieve similar gains?

Ira Leventhal, Vice President, New Concept Product Initiative, Advantest America, Inc. - ATE perspective

       I will discuss how Machine Learning, while showing great promise to solve challenging test-related problems, is not a one-size-fits-all solution. Separating the reality from the hype on how this technology can be successfully applied requires a solid understanding of the strengths/weaknesses of machine learning algorithms, and which applications are the best fit to the strengths. I’ll present real-world successes with applying AI-based semiconductor data analytics and show how these algorithms can outperform other approaches, when applied to the right class of problems.

Xinli Gu, Huawei - AI from a system builder perspective

      AI/ML (Machine Learning) is a tool that promotes formal data collection and value discovery. In a large telecom company with thousands of products, end-to-end data collection and analysis using ML technology is proven to be huge values and gradually becomes a “MUST” in the company process. This talk will use an example to demonstrate the framework in one of the applications.

Cheng-Wen Wu, Tsing Hua Distinguished Chair Professor with the EE Dept., NTHU, Hsinchu, Taiwan. - AI on Taiwan Semiconductor Industry

      The financial tsunami a decade ago had somewhat slowed down the global semiconductor business, until late 2016 when AI suddenly gave everybody new hope. In the same period, however, the semiconductor business in Taiwan continued its growing trend, though on a slightly different track as the industry had expected. Like a chameleon, sort of, the industry has to quickly adjust itself to survive in the global market trend of cloud, IOT, and AI. In my speech, I will give my perspective on the strengths and surviving skills of the semiconductor industry in Taiwan, and give the outlook of the industry in the AI age.

Remember the 1968 film "2001: A Space Odyssey?" Did you know ITC was born in 1969? As the film industry is celebrating the 50-year-old birthday of "2001: A Space Odyssey," ITC will be entering its 50th year in 2019. What has changed in the last 50 years in ITC and in our industry? Moving forward, what shall we expect? How ITC and the test community as a whole will change in the next 25 years?

Do you remember the fun in the past ITC? Will the machine HAL become the general chair for ITC 75?

Check out the MP4 promotion video for AI program this year: http://www.itctestweek.org/AI/

Let's bring back our fun memories and use a little bit imagination in this panel. 

The 2019 ITC-50 committee will be there to hear from you!

Following the AI mini-keynotes in the morning, this afternoon panel provides a forum to have more in-depth discussion.

AI has become an inevitable force to affect many industries. How do we see AI might transforms our industry? The most extreme question perhaps is: Will AI eventually eliminate test engineering? If not 100%, to what extent and when?

There are many questions surrounding AI and most importantly, do we really understand what AI is?

After hearing different perspectives in the morning, come and share your thoughts in this panel.