ABSTRACT. We propose a fine-grained adaptive testing method for digital ATE to reduce test cost. We train a quality-prediction model, partition chips into two groups based on predicted quality, and perform test selection in each group.

ABSTRACT. In order to reduce the access-time, we present a test-scheduling method that exploits broadcast and hardware parallelism and we can select the most efficient solution that minimizes the equivalent access-time.

ABSTRACT. The paper presents a new isometric test compression which ensures high test coverage and low switching due to programmable selection of full toggle scan chains based on circular test templates.

ABSTRACT. This paper presents new methods and experimental production test results from completely moving away from traditional fault methods towards using critical area based methods instead.

ABSTRACT. We propose a novel method to analyze test coverage for ATE tests of analog and mixed signal circuits in the simulation environment.

ABSTRACT. This paper defines the new concept of a close-to-functional test sequence from which close-to-functional broadside tests can be extracted to avoid overtesting of delay faults.

ABSTRACT. Partial scan should be considered as a way to help achieve the stricter requirements for low power devices that are needed for near-threshold technology and applications such as IOT.

ABSTRACT. An objective analysis method was developed and utilized to improve efficiency for simulation and testing for control systems and results show a 40% improvement in simulation cost efficiency.

ABSTRACT. Emerging non-volatile memories (NVMs) bring new test challenges. In this work, we are going to address the impact of supply noise (generated due to high write current) on parallel write/read operation in NVMs.

ABSTRACT. We propose a generic STT-MRAM defect modeling methodology which captures the non-linear behavior of defects appropriately. This methodology is subsequently illustrated by two examples namely the pinhole and sidewall redeposition defects.

ABSTRACT. This paper describes a new and automated intra-cell diagnosis flow for SRAMs to precisely determine the root cause of observed failures during test.

ABSTRACT. We propose an efficient fault-tolerant method for RRAM-based computing systems by utilizing row checksums and test-input vectors to extract signatures. This method recovers the classification accuracy of neuromorphic computing.

ABSTRACT. Logic locking is a promising countermeasure against intellectual property (IP) piracy, counterfeiting, hardware Trojans, reverse engineering, and overbuilding attacks. Yet, various attacks that use a working chip as an oracle have been launched on logic locking, undermining the defense of all existing locking techniques. This paper advances the state-of-the-art in logic locking by developing new countermeasures as well as attacks. We present two logic locking techniques, SARLock and SFLL, that provide quantitative security guarantees against the SAT, removal, and approximate attacks. We validate the effectiveness of proposed techniques by taping-out two silicon chips. We also study the interplay between logic locking and VLSI test, highlighting the security vulnerabilities associated with the test of locked chips. We develop three removal attacks to evaluate the security of existing logic locking techniques.

ABSTRACT. The paper presents the extended summary of the PhD thesis on new test point insertion techniques. The thesis provides a comprehensive study of innovative DFT schemes going far beyond traditional logic BIST-based applications of test points. The proposed methods visibly decrease pattern counts, reduce test generation and test application times, and increase test coverage by means of algorithms capable of identifying and resolving conflicts between circuit’s internal signals. In particular, it is shown that new test points provide, on the average, 2x-3x increase in test compression for stuck-at, transition and cell-aware patterns. Furthermore, it is demonstrated that test-point-centric DFT logic can be successfully used to lock a circuit or hide its functionality. As a result, this approach improves the overall hardware security against reverse engineering, IC cloning, and IP theft.

ABSTRACT. As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltage, and temperature conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors. Many of them correspond to high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this work, direct and surrogate-based optimization methods, including space mapping, are proposed based on suitable objective functions to efficiently tune the transmitter and receiver equalizers. The proposed methodologies are evaluated by lab measurements on realistic industrial post-silicon validation platforms, confirming dramatic speed up in PHY tuning and substantial performance improvement.

ABSTRACT. A hardware Trojan (HT) denotes the malicious addition or modification of circuit elements. The purpose of this work is to improve the HT detection sensitivity in ICs using power side-channel analysis. This paper presents three detection techniques in power based side-channel analysis by increasing Trojan-to-circuit power consumption and reducing the variation effect in the detection threshold. Incorporating the three proposed methods has demonstrated that a realistic fine-grain circuit partitioning and an improved pattern set to increase HT activation chances can magnify Trojan detectability.

ABSTRACT. This talk introduces the AI Theme in ITC 2018 program and provides an overview of the AI sessions.

ABSTRACT. This talk presents provably safe reinforcement learning that provides the best of both worlds: the exploration and optimization capabilities of learning along with the safety guarantees of formal verification.

ABSTRACT. This talk will examine sources and consequences of a range of biases, how they influence data, how outcomes based on flawed protocols and hence biased data can be invalid, and how the hazards posed by such invalidities can be mitigated.

ABSTRACT. A novel test pattern generation method is presented which can generate highly compact test patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool.

ABSTRACT. Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC’16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies.

ABSTRACT.  

ABSTRACT. Globalization of the supply chain as brought about new challenges in terms of the security and reliability of the hardware components. Recycled and re-used or counterfeit products are among the important problems, requiring an effective form of supply chain tracking. While many techniques have been proposed for digital circuits, supply-chain tracking has not been explored for RF circuits. In this paper, we propose to utilize the multitude of performance measurements for assigning and tracking identification numbers to RF devices. We show through simulations and hardware experiments that assigned IDs can be robustly determined via typical measurement equipment that is used during standard testing procedures and the IDs become invalid after several months of use, which enables the detection of used and recycled parts.

ABSTRACT. Analog hardware security is a largely unexplored topic and solutions are seriously lagging behind those for the digital counterpart. In this talk, we propose a hardware security methodology for mixed-signal integrated circuits (ICs), which represent a large subclass of analog ICs. The methodology can be used as a countermeasure

for IC piracy. It consists of locking the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. Metrics are proposed to quantify the security in the analog domain.

ABSTRACT. Despite common belief, face detection is not a solved problem especially in tough environments that include crowds and occlusion. Face detection using non-deep learning approaches that meet these challenges will be presented.

ABSTRACT. Influence-directed explanations shed light on the inner workings of black-box machine learning systems by identifying components that causally influence system behavior and by providing human-understandable interpretation to the concepts represented by these components. This talk describes instances of this paradigm that are model-agnostic and instances that are specific to deep neural networks.