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09:00-10:30 Session Plenary: Plenary and Keynote

Keynote Speaker:

Title: Working with safe, deterministic and secure intelligence from cloud to edge

Kenneth P. Caviasca
Vice President, Internet of Things Group
General Manager, Architecture, Silicon and Platform Engineering

The Internet of Things (IoT) will be the largest revolution in the data economy. At Intel, we understand the exponential power of data, and we’re making it practical and economical to put it to work from the edge to the cloud. Intel® technologies purpose-built for IoT deliver optimized performance at every point, practical ways to use artificial intelligence, broad connectivity support, and a built-in foundation of security to help protect your data and systems. Proven solutions from our partner ecosystem can reduce the time, cost, and risk of IoT deployments. By harnessing the massive flood of data generated by connected thingsand using it to gain actionable insightswe’ll accelerate business transformation to a degree never seen before.

Kenneth P. Caviasca is vice president in the Internet of Things Group and general manager of architecture, silicon and platform engineering at Intel Corporation. He has overall responsibility for computing platforms targeted to the Internet of Things (IoT) market segment, including planning, architecture, user experience priorities, silicon definition, operating system porting, hardware, firmware, validation and manufacturing test. The IoT platforms developed by his team encompass product offerings based on Intel® Atom™, Intel® Core™ and Intel® Xeon® processors. Since joining Intel in 1984 as a silicon engineer in automotive controllers, Caviasca has held various technical and management positions in flash microcontrollers, embedded devices, video signal processors, security devices, chipsets, network processors, server processors and manufacturing operation startup. Before assuming his current position, he managed platform development for the Intelligent Systems Group, overseeing hardware, validation and software integration development. Earlier in his Intel career, he managed silicon development for the Communication Infrastructure Group and led a team responsible for delivering system-on-chip, server-class and chipset products for the embedded and communications market segment. Between 2008 and 2010, Caviasca’s development team won several premier supplier awards from industry-leading communications equipment suppliers. He and his team also won an Intel Achievement Award in 2004 for excellence in network processor development. Caviasca earned his bachelor’s degree in computer and electrical engineering from the University of Bridgeport in Connecticut and his MBA degree from the W. P. Carey School of Business at Arizona State University. He holds seven patents in circuits, CPU and video systems architecture.


Li-C Wang (University of California Santa Barbara, United States)
Location: Ball Room
13:30-15:30 Session Room1: Paper 1: Test Cost Reduction
Vivek Chickermane (Cadence Design Systems, United States)
Location: Room 1
Mengyun Liu (Duke University, United States)
Renjian Pan (Duke University, United States)
Fangming Ye (HUAWEI, R&D, USA, United States)
Xin Li (Duke University, United States)
Krishnendu Chakrabarty (Duke University, United States)
Xinli Gu (HUAWEI, R&D, USA, United States)
Fine-Grained Adaptive Testing Based on Quality Prediction
SPEAKER: Mengyun Liu

ABSTRACT. We propose a fine-grained adaptive testing method for digital ATE to reduce test cost. We train a quality-prediction model, partition chips into two groups based on predicted quality, and perform test selection in each group.

Zhanwei Zhong (Duke University, United States)
Guoliang Li (AMD Inc. Beijing, China, China)
Qinfu Yang (AMD Inc. Beijing, China, China)
Krishnendu Chakrabarty (Duke University, China)
Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
SPEAKER: Zhanwei Zhong

ABSTRACT. In order to reduce the access-time, we present a test-scheduling method that exploits broadcast and hardware parallelism and we can select the most efficient solution that minimizes the equivalent access-time.

Jerzy Tyszer (Poznan University of Technology, Poland)
Yu Huang (Mentor, A Siemens Business, United States)
Sylwester Milewski (Poznan University of Technology, Poland)
Janusz Rajski (Mentor, A Siemens Business, United States)
Chen Wang (Mentor, A Siemens Business, United States)
Hypercompression of Test Patterns
SPEAKER: Janusz Rajski

ABSTRACT. The paper presents a new isometric test compression which ensures high test coverage and low switching due to programmable selection of full toggle scan chains based on circular test templates.

Friedrich Hapke (Mentor, A Siemens Business, Germany)
Peter Maxwell (ON Semiconductor, United States)
Total Critical Area Based Testing

ABSTRACT. This paper presents new methods and experimental production test results from completely moving away from traditional fault methods towards using critical area based methods instead.

13:30-15:30 Session Room2: Paper 2: Optimization & Simulation
Peter Wohl (Synopsys, United States)
Location: Room 2
Niveditha Manjunath (Austrian Institute of Technology, Austria)
Dieter Haerle (KAI, Austria)
Stephen Sabanal (Infineon Technologies AG, Austria)
Herbert Eichinger (Infineon Technologies AG, Austria)
Hermann Tauber (Infineon Technologies AG, Austria)
Andreas Machne (Infineon Technologies AG, Austria)
Christian Manthey (Infineon Technologies AG, Austria)
Mikko Väänänen (Infineon Technologies AG, Austria)
Radu Grosu (Vienna University of Technology, Austria)
Dejan Nickovic (Austrian Institute of Technology, Austria)
Production Tests Coverage Analysis in the Simulation Environment

ABSTRACT. We propose a novel method to analyze test coverage for ATE tests of analog and mixed signal circuits in the simulation environment.

Irith Pomeranz (Purdue University, United States)
On Close-to-Functional Test Sequences

ABSTRACT. This paper defines the new concept of a close-to-functional test sequence from which close-to-functional broadside tests can be extracted to avoid overtesting of delay faults.

Teresa McLaurin (Arm, United States)
Ignatius P. Lawrence (Texas A&M University, United States)
Improving Power, Performance and Area with Test: A Case Study

ABSTRACT. Partial scan should be considered as a way to help achieve the stricter requirements for low power devices that are needed for near-threshold technology and applications such as IOT.

Trevor Ault (Chevron, United States)
Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis

ABSTRACT. An objective analysis method was developed and utilized to improve efficiency for simulation and testing for control systems and results show a 40% improvement in simulation cost efficiency.

13:30-15:30 Session Room3: Paper 3: New Advancements Related To Memories
Masahiro Ishida (ADVANTEST Corporation, Japan)
Location: Room 3
Mohammad Nasim Imtiaz Khan (The Pennsylvania State University, United States)
Swaroop Ghosh (Intel, United States)
Test for Supply Noise and Endurance for Emerging Non-Volatile Memories

ABSTRACT. Emerging non-volatile memories (NVMs) bring new test challenges. In this work, we are going to address the impact of supply noise (generated due to high write current) on parallel write/read operation in NVMs.

Lizhou Wu (Delft University of Technology, Netherlands)
Mottaqiallah Taouil (Delft University of Technology, Netherlands)
Siddharth Rao (IMEC, Belgium)
Erik Jan Marinissen (IMEC, Belgium)
Said Hamdioui (Delft University of Technology, Netherlands)
Electrical Modeling of STT-MRAM Defects
SPEAKER: Lizhou Wu

ABSTRACT. We propose a generic STT-MRAM defect modeling methodology which captures the non-linear behavior of defects appropriately. This methodology is subsequently illustrated by two examples namely the pinhole and sidewall redeposition defects.

Tien-Phu Ho (STMicroelectronics/LIRMM-University of Montpellier,CNRS, France)
Eric Faehn (STMicroelectronics, France)
Arnaud Virazel (LIRMM-University of Montpellier,CNRS, France)
Alberto Bosio (LIRMM-University of Montpellier,CNRS, France)
Patrick Girard (LIRMM-University of Montpellier,CNRS, France)
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
SPEAKER: Eric Faehn

ABSTRACT. This paper describes a new and automated intra-cell diagnosis flow for SRAMs to precisely determine the root cause of observed failures during test.

Mengyun Liu (Duke University, United States)
Lixue Xia (Tsinghua University, China)
Yu Wang (Tsinghua University, China)
Krishnendu Chakrabarty (Duke University, United States)
*Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
SPEAKER: Mengyun Liu

ABSTRACT. We propose an efficient fault-tolerant method for RRAM-based computing systems by utilizing row checksums and test-input vectors to extract signatures. This method recovers the classification accuracy of neuromorphic computing.

13:30-15:30 Session Room4: TTTC PhD: TTTC PhD Competition - Final Round
Kuen-Jong Lee (National Cheng Kung University, Taiwan)
Location: Room 4
Muhammad Yasin (New York University, United States)
Ozgur Sinanoglu (New York University, UAE)
Towards Provably Secure Logic Locking for Hardening Hardware Security

ABSTRACT. Logic locking is a promising countermeasure against intellectual property (IP) piracy, counterfeiting, hardware Trojans, reverse engineering, and overbuilding attacks. Yet, various attacks that use a working chip as an oracle have been launched on logic locking, undermining the defense of all existing locking techniques. This paper advances the state-of-the-art in logic locking by developing new countermeasures as well as attacks. We present two logic locking techniques, SARLock and SFLL, that provide quantitative security guarantees against the SAT, removal, and approximate attacks. We validate the effectiveness of proposed techniques by taping-out two silicon chips. We also study the interplay between logic locking and VLSI test, highlighting the security vulnerabilities associated with the test of locked chips. We develop three removal attacks to evaluate the security of existing logic locking techniques.

Justyna Zawada (Poznan University of Technology/Mentor, a Siemens Business, United States)
Janusz Rajski (Mentor, a Siemens Business, United States)
Jerzy Tyszer (Poznan University of Technology, Poland)
On new class of test points and their applications

ABSTRACT. The paper presents the extended summary of the PhD thesis on new test point insertion techniques. The thesis provides a comprehensive study of innovative DFT schemes going far beyond traditional logic BIST-based applications of test points. The proposed methods visibly decrease pattern counts, reduce test generation and test application times, and increase test coverage by means of algorithms capable of identifying and resolving conflicts between circuit’s internal signals. In particular, it is shown that new test points provide, on the average, 2x-3x increase in test compression for stuck-at, transition and cell-aware patterns. Furthermore, it is demonstrated that test-point-centric DFT logic can be successfully used to lock a circuit or hide its functionality. As a result, this approach improves the overall hardware security against reverse engineering, IC cloning, and IP theft.

Francisco Elias Rangel-Patiño (Department of Electronics, Systems, and Informatics, ITESO – The Jesuit University of Guadalajara & Intel Corporation, Mexico)
José Ernesto Rayas-Sánchez (Department of Electronics, Systems, and Informatics, ITESO – The Jesuit University of Guadalajara, Mexico)
Nagib Hakim (Intel, United States)
Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

ABSTRACT. As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltage, and temperature conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors. Many of them correspond to high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this work, direct and surrogate-based optimization methods, including space mapping, are proposed based on suitable objective functions to efficiently tune the transmitter and receiver equalizers. The proposed methodologies are evaluated by lab measurements on realistic industrial post-silicon validation platforms, confirming dramatic speed up in PHY tuning and substantial performance improvement.

Fakir Sharif Hossain (Nara Institute of Science and Technology, (NAIST), Japan)
Michihiro Shintani (Nara Institute of Science and Technology, (NAIST), Japan)
Michiko Inoue (Nara Institute of Science and Technology, (NAIST), Japan)
Alex Orailoglu (University of California San Diego, United States)
Variation-Aware Hardware Trojan Detection through Power Side-channel

ABSTRACT. A hardware Trojan (HT) denotes the malicious addition or modification of circuit elements. The purpose of this work is to improve the HT detection sensitivity in ICs using power side-channel analysis. This paper presents three detection techniques in power based side-channel analysis by increasing Trojan-to-circuit power consumption and reducing the variation effect in the detection threshold. Incorporating the three proposed methods has demonstrated that a realistic fine-grain circuit partitioning and an improved pattern set to increase HT activation chances can magnify Trojan detectability.

13:30-15:30 Session Room5: AI 1: Safe and Unbiased AI

This session covers the promises and challenges of AI and that learning can sometime lead to false conclusions and unsafe situations.

Shawn Blanton (CMU, United States)
Location: Room 5
Shawn Blanton (CMU, United States)
Introduction To AI Theme in ITC 2018

ABSTRACT. This talk introduces the AI Theme in ITC 2018 program and provides an overview of the AI sessions.

Andre Platzer (CMU, United States)
Safe AI in CPS

ABSTRACT. This talk presents provably safe reinforcement learning that provides the best of both worlds: the exploration and optimization capabilities of learning along with the safety guarantees of formal verification.

Roy Maxion (CMU, United States)
The Mismeasure of AI

ABSTRACT. This talk will examine sources and consequences of a range of biases, how they influence data, how outcomes based on flawed protocols and hence biased data can be invalid, and how the hazards posed by such invalidities can be mitigated.

16:00-17:30 Session Room1: ITC Asia: Top 3 Papers From ITC Asia 2018

This session includes the top 3 papers from ITC Asia 2018, as recommended by ITC Asia program committee. One of them will be selected as the best paper for ITC Asia 2018. For ITC Asia program, see

Huawei Li (Chinese Academy of Sciences, China)
Location: Room 1
Yi-Cheng Kung (National Cheng Kung University, Taiwan)
Kuen-Jong Lee (National Cheng Kung University, Taiwan)
Sudhakar Reddy (University of Iowa, United States)
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
SPEAKER: Yi-Cheng Kung

ABSTRACT. A novel test pattern generation method is presented which can generate highly compact test patterns for both DC and AC faults in one ATPG run with no need to modify the ATPG tool.

Ying Wang (SKL of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China)
Wen Li (Institute of Computing Technology, Chinese Academy of Sciences, China)
Huawei Li (SKL of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China)
Xiaowei Li (SKL of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, China)
Lightweight Timing Channel Protection for Shared DRAM Controller
SPEAKER: Ying Wang
Riccardo Cantoro (Politecnico di Torino, Italy)
Aleksa Damljanovic (Politecnico di Torino, Italy)
Matteo Sonza Reorda (Politecnico di Torino, Italy)
Giovanni Squillero (Politecnico di Torino, Italy)
A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

ABSTRACT. Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC’16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies.

16:00-17:30 Session Room2: Special 1: New IEEE Standardization Efforts

The Test Technology Standards Committee (TTSC) oversees the development and introduction of new IEEE Test Standards into the electronics industry. In recent months, the TTSC has sponsored several new activities which push the bounds of current standards and paradigms. P2427 seeks to standardize fault modeling and defect coverage in the analog domain. 1687 is being extended both in the analog domains with P1687.2, and into other chip-level TAMs (other than 1149.1) by P1687.1. Pxxxx (STAM/SJTAG) seeks to solve some of the convoluted topological and protocol problems encountered when chips are loaded on boards put in backplanes in boxes in systems.

Adam Cron (Synopsys, United States)
Location: Room 2
Mayukh Bhattacharya (Synopsys, United States)
Towards an Analog Fault Standard
Stephen Sunter (Mentor, a Siemens Business, Canada)
Martin Keim (Mentor, a Siemens Business, United States)
Extending 1687 to Low Pin-Count and Mixed-Signal ICs
Joel Irby (Arm, United States)
STAM: The Final Frontiers of System Test Access Management



16:00-17:30 Session Room3: Security 1: Security Track Special Session: Analog Circuit Security
Yiorgos Makris (The University of Texas at Dallas, United States)
Location: Room 3
Rick Welker (Arizona State University, United States)
Fatih Karabacak (Arizona State University, United States)
Jennifer Kitchen (Arizona State University, United States)
Sule Ozev (Arizona State University, United States)
Using RF Front-End Characteristics for Supply Chain Tracking and Counterfeit Detection
SPEAKER: Sule Ozev

ABSTRACT. Globalization of the supply chain as brought about new challenges in terms of the security and reliability of the hardware components. Recycled and re-used or counterfeit products are among the important problems, requiring an effective form of supply chain tracking. While many techniques have been proposed for digital circuits, supply-chain tracking has not been explored for RF circuits. In this paper, we propose to utilize the multitude of performance measurements for assigning and tracking identification numbers to RF devices. We show through simulations and hardware experiments that assigned IDs can be robustly determined via typical measurement equipment that is used during standard testing procedures and the IDs become invalid after several months of use, which enables the detection of used and recycled parts.

Haralampos Stratigopoulos (Sorbonne Universite, CNRS, LIP6, France)
Securing Mixed-Signal ICs via Logic Locking

ABSTRACT. Analog hardware security is a largely unexplored topic and solutions are seriously lagging behind those for the digital counterpart. In this talk, we propose a hardware security methodology for mixed-signal integrated circuits (ICs), which represent a large subclass of analog ICs. The methodology can be used as a countermeasure

for IC piracy. It consists of locking the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. Metrics are proposed to quantify the security in the analog domain.

Waleed Khalil (The Ohio State University, United States)
Process Specific Functions for Assurance of Analog-Mixed-Signal Integrated Circuits
16:00-17:30 Session Room4: Poster 1: Highlights of 2018 Posters

This session comprises 10 presentations to highlight 10 posters in this year ITC poster program.

PO2: A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks. M. Portolan, R. Cantoro, E. Sanchez, M. Reorda, Politecnico di Torino

PO6: Dynamic Cloud-based Data Collection System. George Lawton III, Lawton Software

PO7: Layout-aware Wrapper for IP cores. Darshal Patel (AMD) and Khushboo Agarwal (AMD).

PO8: IEEE P1687.1: Extending 1687 to Non-TAP Interfaces. J. Rearick, AMD, A. Crouch, Amida, M. Keim, Mentor, M. Laisne, Dialog Semi, G. Colon-Benet, Intel

PO9: Visually-enhanced Dynamic Part Average Testing. A. Coyette, R. Vanhooren, W. Dobbelaere, ON Semiconductor, B. Esen, N. Xama, J. Caicedo, G. Gielen, Katholieke Universiteit Leuven

PO13: Concurrent IJTAG. Rene Krenz-Baath,HSHL

PO15: IEEE P1687.2: Extending 1687 to Analog Circuits. J. Rearick, AMD, S. Sunter, Mentor, V. Zivkovic, Cadence

PO22: Optimal SCAN Vector Count. T. Kogan, A. Rabenu, Intel

PO23:  What’s up with Analog Test Coverage?: IEEE P2427 IEEE - Working Group Progress. A, Meixner, The Engineers' Daughter, S, Abdennadher, Intel), S, Sunter, Mentor a Siemens Company. P. Sarson, Dialog Semiconductor

PO28: Method to Measure and Improve Toggle Coverage During High - Volume Quick-Kill Stress. J. Cooper, Intel

William Eklow (ITC, United States)
Location: Room 4
16:00-17:30 Session Room5: AI 2: Robust and Accountable AI
Shawn Blanton (CMU, United States)
Location: Room 5
Marios Savvides (CMU, United States)
Seeing faces through the eyes of Artificial Intelligence

ABSTRACT. Despite common belief, face detection is not a solved problem especially in tough environments that include crowds and occlusion. Face detection using non-deep learning approaches that meet these challenges will be presented.

Anupam Datta (CMU, United States)
Influence-directed explanations for machine learning systems

ABSTRACT. Influence-directed explanations shed light on the inner workings of black-box machine learning systems by identifying components that causally influence system behavior and by providing human-understandable interpretation to the concepts represented by these components. This talk describes instances of this paradigm that are model-agnostic and instances that are specific to deep neural networks.

17:30-19:15 Welcome Reception

This welcome reception will be a joint event between ITC and ISTFA