Talk Author Index

TALK AUTHOR INDEX

Shortcuts: A B C D E F G H I J K L M N O P R S T V W X Y Z

A
Abotbol, Yehonatan	Advanced Uniformed Test Approach for Automotive SoCs
Abraham, Jais	Test Challenges for Low Power SoCs
Agarwal, Nitin	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Ahadi Dolatsara, Majid	Polynomial Chaos modeling for Jitter estimation in high-speed links
Ahmed, Alif	Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
Andraud, Martin	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
Ankapong, Frank	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Antonopoulos, Angelos	Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Argyrides, Costas	ECC-Based FIT Rate Mitigation Technique for Automotive SoCs
Armstrong, Dave	Moving Adaptive Test to “AI Test”
Ault, Trevor	Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
B
Becker, Wiren Dale	Polynomial Chaos modeling for Jitter estimation in high-speed links
Bellay, Jeremy	Barricade methodology for detecting counterfeits
Bhattacharya, Mayukh	Towards an Analog Fault Standard
Bhunia, Swarup	Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify
Bishnoi, Rajendra	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM
Blanton, Shawn	Improving Diagnosis Efficiency via Machine Learning Introduction To AI Theme in ITC 2018
Boschi, Gabriele	Advanced Uniformed Test Approach for Automotive SoCs
Bosio, Alberto	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Botero, Ulbert	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
Brazil, Edward	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
C
Cantoro, Riccardo	A New Technique to Generate Test Sequences for Reconfigurable Scan Networks
Casarsa, Marco	Case Study and Advanced Functional Safety Solution for Automotive SoCs
Chaganti, Shravan K	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Chakrabarty, Krishnendu	Self-Learning Health-Status Analysis for a Core Router System
Chakrabarty, Krishnendu	*Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
Chakrabarty, Krishnendu	Fine-Grained Adaptive Testing Based on Quality Prediction *Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
Chakraborty, Prabuddha	Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify
Chakravadhanula, Krishna	Improving Diagnosis Resolution and Performance at High Compression Ratios
Chakravarty, Sreejit	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
Chaudhuri, Arjun	Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
Chen, Degang	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Chen, Harry	What would it take to achieve cost-effective system-level test?
Chen, Tsai-Chieh	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
Cheng, Eddy	Is it possible to impact quality of test with machine learning?
Cheng, Kwang-Ting	Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
Chhabra, Atul	Improving Diagnosis Resolution and Performance at High Compression Ratios
Chhabra, Atul	High Accuracy, Robust Multiple Defect Diagnosis Scheme
Chillarige, Sameer	Improving Diagnosis Resolution and Performance at High Compression Ratios
Chillarige, Sameer	High Accuracy, Robust Multiple Defect Diagnosis Scheme
Colburn, Jon	XLBIST: X-Tolerant Logic BIST
Cruz, Jonathan	Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify
D
Damljanovic, Aleksa	A New Technique to Generate Test Sequences for Reconfigurable Scan Networks
Daou, Fadi	Challenges of At-Speed testing of 112Gbps devices
Das, Sourav	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
Datta, Anupam	Influence-directed explanations for machine learning systems
Datta, Rudrajit	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Dubey, Sumit	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Dworak, Jennifer	IJTAG Integrity Checking with Chained Hashing
E
Eichinger, Herbert	Production Tests Coverage Analysis in the Simulation Environment
F
Faehn, Eric	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Fang, Chenlei	Improving Diagnosis Efficiency via Machine Learning
Farahmandi, Farimah	Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
Fast, Anja	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Fern, Nicole	Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
Fieback, Moritz	Testing Resistive Memories: Where we are standing and what is still missing?
Fodor, Ferenc	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Forte, Domenic	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
G
G, Swathi	Test Application and Evaluation Methods to Meet Run-time Self-test Requirements for Functional Safety
Galindez, Laura	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
Gallagher, Patrick	Enhancing Automotive Self-Test with Embedded Distributed Programming
Gangaram, Vijay	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
Gebregiorgis, Anteneh	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications
Ghosh, Swaroop	Test for Supply Noise and Endurance for Emerging Non-Volatile Memories
Girard, Patrick	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Glowatz, Andreas	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Golanbari, Saber	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications
Goteti, Prashant	Improving Analog Functional Safety Using Data-Driven Anomaly Detection
Grigoryan, Hayk	Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM ECC-Based FIT Rate Mitigation Technique for Automotive SoCs
Grosu, Radu	Production Tests Coverage Analysis in the Simulation Environment
Gu, Xinli	Self-Learning Health-Status Analysis for a Core Router System Fine-Grained Adaptive Testing Based on Quality Prediction
Gupta, Pallav	An effective methodology for automated diagnosis of functional pattern failures to support silicon debug Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
H
Haerle, Dieter	Production Tests Coverage Analysis in the Simulation Environment
Hakim, Nagib	Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
Hamdioui, Said	Electrical Modeling of STT-MRAM Defects Testing Resistive Memories: Where we are standing and what is still missing?
Hapke, Friedrich	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies Total Critical Area Based Testing
Harris, Ken	Practical Applications of Big Data Analytics in Semiconductor Manufacturing, Assembly and Test
Harutyunyan, Gurgen	Advanced Uniformed Test Approach for Automotive SoCs Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM ECC-Based FIT Rate Mitigation Technique for Automotive SoCs
Hatzopoulos, Alkis	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
Hejase, Jose	Polynomial Chaos modeling for Jitter estimation in high-speed links
Ho, Tien-Phu	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Hoque, Tamzidul	Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify
Hossain, Fakir Sharif	Variation-Aware Hardware Trojan Detection through Power Side-channel
Howell, Will	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Huang, Chao	Design Automation for Intelligent Automotive Systems
Huang, I-De	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
Huang, Qicheng	Improving Diagnosis Efficiency via Machine Learning
Huang, Yu	Hypercompression of Test Patterns
Hutner, Marc	Is it possible to impact quality of test with machine learning?
I
Ichiyama, Kiyotaka	A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
Inoue, Michiko	Artificial Neural Network Based Test Escape Screening Using Generative Model Variation-Aware Hardware Trojan Detection through Power Side-channel
Irby, Joel	STAM: The Final Frontiers of System Test Access Management
Ishida, Masahiro	A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
Iskander, Yousef	Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
J
Jian, Yu-Rong	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Jiao, Hailong	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
Jin, Shi	Self-Learning Health-Status Analysis for a Core Router System
Jin, Yier	TimingSAT: Decamouflaging Timing-based Logic Obfuscation
K
Kan, Senwen	IJTAG Integrity Checking with Chained Hashing
Kapatsori, Christiana	Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Karabacak, Fatih	Using RF Front-End Characteristics for Supply Chain Tracking and Counterfeit Detection
Katselas, Leonidas	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
Keim, Martin	Extending 1687 to Low Pin-Count and Mixed-Signal ICs
Khalil, Waleed	Process Specific Functions for Assurance of Analog-Mixed-Signal Integrated Circuits
Khan, Mohammad Nasim Imtiaz	Test for Supply Noise and Endurance for Emerging Non-Volatile Memories
Kitchen, Jennifer	Using RF Front-End Characteristics for Supply Chain Tracking and Counterfeit Detection
Kogan, Tal	Advanced Uniformed Test Approach for Automotive SoCs
Kumar, Anshul	High Accuracy, Robust Multiple Defect Diagnosis Scheme
Kung, Yi-Cheng	Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
Kusaka, Takashi	A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
L
Lan, Shuyue	Design Automation for Intelligent Automotive Systems
Lawrence, Ignatius P.	Improving Power, Performance and Area with Test: A Case Study
Lee, Kuen-Jong	Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
Leventhal, Ira	AI Engineering Assistants for ATE
Li, Guoliang	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
Li, Huawei	Lightweight Timing Channel Protection for Shared DRAM Controller
Li, James Chien-Mo	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
Li, Meng	TimingSAT: Decamouflaging Timing-based Logic Obfuscation
Li, Wen	Lightweight Timing Channel Protection for Shared DRAM Controller
Li, Xiaowei	Lightweight Timing Channel Protection for Shared DRAM Controller
Li, Xin	Fine-Grained Adaptive Testing Based on Quality Prediction
Li, Zipeng	*Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips
Liang, Hengyi	Design Automation for Intelligent Automotive Systems
Lingappan, Loganathan	Online Scan Diagnosis - A Novel Approach to Volume Diagnosis
Liu, Mengyun	Fine-Grained Adaptive Testing Based on Quality Prediction *Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
Liu, Yingdi	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test
Liu, Yu	Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Lu, Yichuan	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
M
Machne, Andreas	Production Tests Coverage Analysis in the Simulation Environment
Makris, Yiorgos	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Malik, Anil	Improving Diagnosis Resolution and Performance at High Compression Ratios
Malik, Anil	High Accuracy, Robust Multiple Defect Diagnosis Scheme
Manjunath, Niveditha	Production Tests Coverage Analysis in the Simulation Environment
Manthey, Christian	Production Tests Coverage Analysis in the Simulation Environment
Marinissen, Erik Jan	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs Electrical Modeling of STT-MRAM Defects
Martirosyan, Narine	Advanced Uniformed Test Approach for Automotive SoCs
Maston, Greg	XLBIST: X-Tolerant Logic BIST
Maxion, Roy	The Mismeasure of AI
Maxwell, Peter	Total Critical Area Based Testing
McLaurin, Teresa	Improving Power, Performance and Area with Test: A Case Study
Melchert, Gustavo	Is it possible to impact quality of test with machine learning?
Milewski, Sylwester	Hypercompression of Test Patterns
Mishra, Prabhat	Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
Mittal, Soumya	Improving Diagnosis Efficiency via Machine Learning
Mukherjee, Nilanjan	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test
N
Nair, Sarath M.	Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM
Nakamura, Yoshiyuki	Artificial Neural Network Based Test Escape Screening Using Generative Model
Nandakumar, Bharath	Improving Diagnosis Resolution and Performance at High Compression Ratios
Nandakumar, Bharath	High Accuracy, Robust Multiple Defect Diagnosis Scheme
Narayanan, Prakash	Test Application and Evaluation Methods to Meet Run-time Self-test Requirements for Functional Safety Improved RAM Sequential Tests for SoCs with Complex Memory Architectures
Nero, Matt	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
Nickovic, Dejan	Production Tests Coverage Analysis in the Simulation Environment
O
Orailoglu, Alex	Variation-Aware Hardware Trojan Detection through Power Side-channel
Ozev, Sule	Using RF Front-End Characteristics for Supply Chain Tracking and Counterfeit Detection
P
Pai, Chia-Cheng	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
Pan, David	Machine Learning for Yield Learning and Optimization TimingSAT: Decamouflaging Timing-based Logic Obfuscation
Pan, Renjian	Fine-Grained Adaptive Testing Based on Quality Prediction
Pan, Samuel	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
Papameletis, Christos	Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs
Parekhji, Rubin	Test Application and Evaluation Methods to Meet Run-time Self-test Requirements for Functional Safety
Platzer, Andre	Safe AI in CPS
Podpod, Arnita	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Pomeranz, Irith	On Close-to-Functional Test Sequences
Pradeep, Wilson	Improved RAM Sequential Tests for SoCs with Complex Memory Architectures
R
Rajski, Janusz	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies On new class of test points and their applications
Rajski, Janusz	Hypercompression of Test Patterns
Rajski, Janusz	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test
Rangel-Patiño, Francisco Elias	Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
Rao, Siddharth	Electrical Modeling of STT-MRAM Defects
Rayas-Sánchez, José Ernesto	Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
Reddy, Sudhakar	Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
Reddy, Sudhakar	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test
Redemund, Wilfried	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Reynick, Joe	DFT Considerations and Flow for a Large 2.5D/3D Device
S
Sabanal, Stephen	Production Tests Coverage Analysis in the Simulation Environment
Savvides, Marios	Seeing faces through the eyes of Artificial Intelligence
Schaub, Keith	AI Engineering Assistants for ATE
Schmerberg, Juergen	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Shakya, Bicky	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
Shamsi, Kaveh	TimingSAT: Decamouflaging Timing-based Logic Obfuscation
Shan, Chuanhe	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
Shanyour, Basim	Detection of low power Trojans in standard cell designs using built-in current sensors.
Sheikh, Abalhassan	*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models
Shen, Haoting	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
Shen, Ting-Yu	Test methodology for PCHB/PCFB based asynchronous pipeline circuits
Shintani, Michihiro	Artificial Neural Network Based Test Escape Screening Using Generative Model Variation-Aware Hardware Trojan Detection through Power Side-channel
Shoukourian, Samvel	ECC-Based FIT Rate Mitigation Technique for Automotive SoCs
Sinanoglu, Ozgur	Towards Provably Secure Logic Locking for Hardening Hardware Security
Sonza Reorda, Matteo	A New Technique to Generate Test Sequences for Reconfigurable Scan Networks
Squillero, Giovanni	A New Technique to Generate Test Sequences for Reconfigurable Scan Networks
Stern, Andrew	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
Stratigopoulos, Haralampos	Securing Mixed-Signal ICs via Logic Locking
Stucchi, Michele	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Su, Fei	A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing Improving Analog Functional Safety Using Data-Driven Anomaly Detection
Su, Wenhao	Design Automation for Intelligent Automotive Systems
Sumikawa, Nikolas	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
Sunter, Stephen	Extending 1687 to Low Pin-Count and Mixed-Signal ICs
Swaminathan, Madhavan	Polynomial Chaos modeling for Jitter estimation in high-speed links
Swenton, Joe	High Accuracy, Robust Multiple Defect Diagnosis Scheme
Swenton, Joseph	Improving Diagnosis Resolution and Performance at High Compression Ratios
T
Tahoori, Mehdi	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM
Taouil, Mottaqiallah	Electrical Modeling of STT-MRAM Defects
Taouil, Mottaqiallah	Testing Resistive Memories: Where we are standing and what is still missing?
Tauber, Hermann	Production Tests Coverage Analysis in the Simulation Environment
Tehranipoor, Mark	EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
Tragoudas, Spyros	Detection of low power Trojans in standard cell designs using built-in current sensors.
Tshagharyan, Grigor	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM
Tyszer, Jerzy	*Distinguished Paper: Deterministic Stellar BIST for In-System Automotive Test On new class of test points and their applications Hypercompression of Test Patterns
V
Venkataraman, Srikanth	DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Verhelst, Marian	On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
Virazel, Arnaud	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Väänänen, Mikko	Production Tests Coverage Analysis in the Simulation Environment
W
Waicukauski, John	XLBIST: X-Tolerant Logic BIST
Wang, Chen	Hypercompression of Test Patterns
Wang, Li-C	*Distinguished Paper: Concept Recognition in Production Yield Data Analytics An Autonomous System View To Apply Machine Learning
Wang, Ying	Lightweight Timing Channel Protection for Shared DRAM Controller
Wang, Yu	*Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
Wang, Zhilu	Design Automation for Intelligent Automotive Systems
Welker, Rick	Using RF Front-End Characteristics for Supply Chain Tracking and Counterfeit Detection
Wisnesky, Carl	Enhancing Automotive Self-Test with Embedded Distributed Programming
Wohl, Peter	XLBIST: X-Tolerant Logic BIST
Wu, Cheng-Wen	*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
Wu, Lizhou	Electrical Modeling of STT-MRAM Defects
X
Xia, Lixue	*Distinguished Paper: Fault Tolerance for RRAM-Based Matrix Operations
Y
Yang, Qinfu	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
Yasin, Muhammad	Towards Provably Secure Logic Locking for Hardening Hardware Security
Ye, Fangming	Fine-Grained Adaptive Testing Based on Quality Prediction
Yi, John	Evolution of System-Level Test at AMD
Yu, Huan	Polynomial Chaos modeling for Jitter estimation in high-speed links
Z
Zawada, Justyna	On new class of test points and their applications
Zhang, Ling	*Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips
Zhang, Zhaobo	Self-Learning Health-Status Analysis for a Core Router System
Zhong, Zhanwei	Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
Zhu, Qi	Design Automation for Intelligent Automotive Systems