ABSTRACT. This paper explores opportunities of using Bayesian Networks for resource-efficient one-shot on-chip statistical calibration of analog/RF circuits. The proposed approach is demonstrated for a low-noise amplifier implemented in 130nm CMOS.

ABSTRACT. This paper proposes a new, small-area test methodology for PCHB/PCFB without breaking any internal feedback loop. We also analyze the faults which were not studied seriously by previous research.

ABSTRACT. Novel linearity testing methods that significantly reduce test time are introduced for DACs with various architectures. New methods based on an interpolated segmented model are developed for interpolated DACs.

ABSTRACT. Probing challenges/solutions for multi-die stacked ICs: thin wafers on tape, large-array micro-bumps, analyzing PTPA, misalignment auto-correction. Contains case study, in which most of the discussed challenges and solutions are combined.

ABSTRACT. In this work we propose a method to provide realistic test conditions during modular test of digital 2D-SoCs and 3D-SICs, using programmable on-chip toggle generators.

ABSTRACT. We propose a no-touch TSV test methodology that is resilient against PVT variations, or test environment parameters, thus suitable for industry practical uses.

ABSTRACT. We propose an automated and scalable test generation method for activation of hardware Trojans in RTL designs. This method uses concolic testing to activate Trojans in large and complex benchmarks.

ABSTRACT. Ultra-low power dissipating Trojans can be detected by analyzing IDDT waveforms at each gate. A small number of current sensors are inserted using ATPG, regression analysis and appropriate standard-cell placement.

ABSTRACT. Introduction of a hardware dithering methodology for neutralizing Trojans in ICs. This prevention mechanism aims to occupy, or render unusable, the process variation margins, wherein Trojans operate while remaining concealed.

ABSTRACT. This talk surveys recent results of using various machine learning/deep learning techniques for performance modeling under uncertainty, lithography modeling with transfer/active learning, lithography hotspot detection, and IC mask optimizations. State-of-the-art methods are explained and challenges/opportunities are discussed.
 

ABSTRACT. Traditional data gathering and visualization techniques are becoming less and less useful in today’s manufacturing environment.  In this talk, we review the reasons why, along with practical examples illustrating the importance of integrated, automated analysis and triggered actions in the product ramps of today’s advanced products and manufacturing technologies.

ABSTRACT. Traditional IC DFT Engineers must expand their horizons to include the details of packaging, physical design, test hardware, and even board-level test techniques when working with large 2.5D/3D System-in-Package (SIP) devices. The planning, implementation, and production test for such a SIP is discussed in this presentation. Our discussion will also include challenges/solutions, and potential areas for new opportunities in supporting 2.5D/3D technologies in the future.

ABSTRACT. Low power SoCs impose unique challenges for DFT and for silicon testing. Tests have to be created so as not to exceed the power budget of the design, while, at the same time not imposing excessive costs for testing under these constraints. DFT techniques are also needed to detect manufacturing defects on the power management structures introduced in the design. This presentation will cover some of these challenges and the solutions to address these.

ABSTRACT. we propose the first daisy-chain design that can perform self-diagnosis and repair the detected faults. It works in a timely manner and can work in both on-line and off-line mode.

ABSTRACT. We present a physics-based classification of memristor fault origins and investigate design-induced coupling in dense memristor crossbars. The resulting conclusions provide valuable feedback to the fabrication and design of memristor-based circuits and facilitate test generation. 

ABSTRACT. This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies, including correlation to System-Level-Test fails.

ABSTRACT. We propose TimingSAT to evaluate the security of timing-based camouflaging strategies. TimingSAT consists of transformation and simplification procedures to enable efficient query-based attacks. The correctness of TimingSAT is formally proved.

ABSTRACT. This paper proposes to integrity check an IJTAG based design under test (DUT) as well as the DUT-accessing system, such as the DUT tester, to establish trust.

ABSTRACT. Undocumented scan and debug instructions can be exploited by hackers to undermine system security. Our technique detects anomalous out-of-spec JTAG instruction opcodes using commercial equivalence checking tools before tape-out.

ABSTRACT. Based on features extracted from fail logs, machine learning methods are used to predict diagnostic information without running time-consuming diagnosis. Experiments on various fail logs demonstrate the efficacy of the concept.

ABSTRACT. We propose a test escape detection method based on variational autoencoder that is widely used in neural network. Experiments demonstrates the proposed method detects test escapes more than 8.5 times compared to a conventional method.

ABSTRACT. This paper presents a concept-based workflow approach for yield data analytics. Neural network models are built to recognize plot-based concepts used in an analytic workflow.

ABSTRACT. We propose a supervised learning framework for hardware IP trust verification that utilizes a tool-generated robust training set and combines three machine learning models using a voting ensemble.

ABSTRACT. Today's globalized electronics supply chain is prone to counterfeit chip proliferation. We propose a novel method of counterfeit integrated circuit detection which utilizes design-specific electromagnetic fingerprints generated by clock distribution networks.

ABSTRACT. Battelle has developed a technology to nondestructively classify electronic components as authentic or counterfeit. The technology uses a method that creates feature vectors for each class of devices using a reconfigurable side channel power analysis test fixture. This test fixture monitors the power fluctuations of the device either via connection to a power or a ground pin while test signals are sent to the device. Power waveforms are processed, undergo dimensionality reduction techniques, and the resultant data is plotted in Principal Component Analysis (PCA) space to reveal information related to the authenticity of the device under test. To scale this technology to the full catalog of parts available to a production test house, unique tools have been created that provide automated test generation and scoring of feature vectors.

ABSTRACT. This talk draws an analogy to the autonomous system view of self-driving car for applying machine learning in a test application. Through such a system view it is more intuitive to see where a particular machine learning approach might be applied and what type of learning problem is to be solved. To give a concrete example, a short demo will be included to illustrate how such an autonomous system can be used for production yield data analytics.

ABSTRACT. This talk will discuss the challenges in designing the next-generation autonomous and connected vehicles, and present promising design automation techniques that tackle these challenges.