View: session overviewtalk overview
08:30 | On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs SPEAKER: Martin Andraud ABSTRACT. This paper explores opportunities of using Bayesian Networks for resource-efficient one-shot on-chip statistical calibration of analog/RF circuits. The proposed approach is demonstrated for a low-noise amplifier implemented in 130nm CMOS. |
09:00 | Test methodology for PCHB/PCFB based asynchronous pipeline circuits SPEAKER: Tsai-Chieh Chen ABSTRACT. This paper proposes a new, small-area test methodology for PCHB/PCFB without breaking any internal feedback loop. We also analyze the faults which were not studied seriously by previous research. |
09:30 | *Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models SPEAKER: Shravan K Chaganti ABSTRACT. Novel linearity testing methods that significantly reduce test time are introduced for DACs with various architectures. New methods based on an interpolated segmented model are developed for interpolated DACs. |
08:30 | *Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits SPEAKER: Erik Jan Marinissen ABSTRACT. Probing challenges/solutions for multi-die stacked ICs: thin wafers on tape, large-array micro-bumps, analyzing PTPA, misalignment auto-correction. Contains case study, in which most of the discussed challenges and solutions are combined. |
09:00 | Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs SPEAKER: Leonidas Katselas ABSTRACT. In this work we propose a method to provide realistic test conditions during modular test of digital 2D-SoCs and 3D-SICs, using programmable on-chip toggle generators. |
09:30 | A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing SPEAKER: Sourav Das ABSTRACT. We propose a no-touch TSV test methodology that is resilient against PVT variations, or test environment parameters, thus suitable for industry practical uses. |
08:30 | Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution SPEAKER: Prabhat Mishra ABSTRACT. We propose an automated and scalable test generation method for activation of hardware Trojans in RTL designs. This method uses concolic testing to activate Trojans in large and complex benchmarks. |
09:00 | Detection of low power Trojans in standard cell designs using built-in current sensors. SPEAKER: Basim Shanyour ABSTRACT. Ultra-low power dissipating Trojans can be detected by analyzing IDDT waveforms at each gate. A small number of current sensors are inserted using ATPG, regression analysis and appropriate standard-cell placement. |
09:30 | Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs SPEAKER: Christiana Kapatsori ABSTRACT. Introduction of a hardware dithering methodology for neutralizing Trojans in ICs. This prevention mechanism aims to occupy, or render unusable, the process variation margins, wherein Trojans operate while remaining concealed. |
Embedded Tutorial - Analog Fault Simulation: Practical Applications, Case Studies and Challenges
by Rubin Parekhji, Devanathan Varadarajan, Lakshmanan Balasubramanian, and Ken Butler of Texas Instruments
Analog fault simulation is gaining significant importance now given the compelling needs for robustness and high quality for analog IPs. EDA offerings have emerged, and standards are emerging as well. In this embedded tutorial, the presenters, (who have been working in this area for the past few years), will provide an overview of fault simulation for analog circuits, and share their experiences and highlight challenges required to be addressed to make its adoption main-stream. Case studies on actual analog IPs demonstrating several applications in design and manufacturing (coverage, defect based test, diagnosis, test optimisations, sensitivity analysis, etc.) will be presented.
10:30 | *Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips SPEAKER: Krishnendu Chakrabarty ABSTRACT. we propose the first daisy-chain design that can perform self-diagnosis and repair the detected faults. It works in a timely manner and can work in both on-line and off-line mode. |
11:00 | Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors SPEAKER: Arjun Chaudhuri ABSTRACT. We present a physics-based classification of memristor fault origins and investigate design-induced coupling in dense memristor crossbars. The resulting conclusions provide valuable feedback to the fabrication and design of memristor-based circuits and facilitate test generation. |
11:30 | DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies SPEAKER: Will Howell ABSTRACT. This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies, including correlation to System-Level-Test fails. |
10:30 | TimingSAT: Decamouflaging Timing-based Logic Obfuscation SPEAKER: David Pan ABSTRACT. We propose TimingSAT to evaluate the security of timing-based camouflaging strategies. TimingSAT consists of transformation and simplification procedures to enable efficient query-based attacks. The correctness of TimingSAT is formally proved. |
11:00 | IJTAG Integrity Checking with Chained Hashing SPEAKER: Senwen Kan ABSTRACT. This paper proposes to integrity check an IJTAG based design under test (DUT) as well as the DUT-accessing system, such as the DUT tester, to establish trust. |
11:30 | Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security SPEAKER: Nicole Fern ABSTRACT. Undocumented scan and debug instructions can be exploited by hackers to undermine system security. Our technique detects anomalous out-of-spec JTAG instruction opcodes using commercial equivalence checking tools before tape-out. |
10:30 | Test Application and Evaluation Methods to Meet Run-time Self-test Requirements for Functional Safety SPEAKER: Swathi G |
11:00 | Advanced Uniformed Test Approach for Automotive SoCs SPEAKER: Tal Kogan |
11:30 | Case Study and Advanced Functional Safety Solution for Automotive SoCs |
10:30 | Improving Diagnosis Efficiency via Machine Learning SPEAKER: Qicheng Huang ABSTRACT. Based on features extracted from fail logs, machine learning methods are used to predict diagnostic information without running time-consuming diagnosis. Experiments on various fail logs demonstrate the efficacy of the concept. |
11:00 | Artificial Neural Network Based Test Escape Screening Using Generative Model SPEAKER: Michihiro Shintani ABSTRACT. We propose a test escape detection method based on variational autoencoder that is widely used in neural network. Experiments demonstrates the proposed method detects test escapes more than 8.5 times compared to a conventional method. |
11:30 | *Distinguished Paper: Concept Recognition in Production Yield Data Analytics SPEAKER: Chuanhe Shan ABSTRACT. This paper presents a concept-based workflow approach for yield data analytics. Neural network models are built to recognize plot-based concepts used in an analytic workflow. |
14:00 | Improved RAM Sequential Tests for SoCs with Complex Memory Architectures SPEAKER: Wilson Pradeep |
14:30 | High Accuracy, Robust Multiple Defect Diagnosis Scheme SPEAKER: Bharath Nandakumar |
15:00 | Enhancing Automotive Self-Test with Embedded Distributed Programming SPEAKER: Carl Wisnesky |
14:00 | Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify SPEAKER: Tamzidul Hoque ABSTRACT. We propose a supervised learning framework for hardware IP trust verification that utilizes a tool-generated robust training set and combines three machine learning models using a voting ensemble. |
14:30 | EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs SPEAKER: Andrew Stern ABSTRACT. Today's globalized electronics supply chain is prone to counterfeit chip proliferation. We propose a novel method of counterfeit integrated circuit detection which utilizes design-specific electromagnetic fingerprints generated by clock distribution networks. |
15:00 | Barricade methodology for detecting counterfeits ABSTRACT. Battelle has developed a technology to nondestructively classify electronic components as authentic or counterfeit. The technology uses a method that creates feature vectors for each class of devices using a reconfigurable side channel power analysis test fixture. This test fixture monitors the power fluctuations of the device either via connection to a power or a ground pin while test signals are sent to the device. Power waveforms are processed, undergo dimensionality reduction techniques, and the resultant data is plotted in Principal Component Analysis (PCA) space to reveal information related to the authenticity of the device under test. To scale this technology to the full catalog of parts available to a production test house, unique tools have been created that provide automated test generation and scoring of feature vectors. |
Panelists:
- Navin Bishnoi, GLOBAL FOUNDARIES
- Christophe Eychenne, Bosch
- Nir Maor, Qualcomm
- Riccardo Mariani, Intel
- Rajagopalan Srinivasan, Nvidia
- Yervant Zorian, Synopsys
Panel Moderator: Paolo Bernardi, Polito Torino
14:00 | An Autonomous System View To Apply Machine Learning ABSTRACT. This talk draws an analogy to the autonomous system view of self-driving car for applying machine learning in a test application. Through such a system view it is more intuitive to see where a particular machine learning approach might be applied and what type of learning problem is to be solved. To give a concrete example, a short demo will be included to illustrate how such an autonomous system can be used for production yield data analytics. |
14:45 | Design Automation for Intelligent Automotive Systems SPEAKER: Qi Zhu ABSTRACT. This talk will discuss the challenges in designing the next-generation autonomous and connected vehicles, and present promising design automation techniques that tackle these challenges. |
Title: Trick or Treat: Is your supply safe?
Abstract: Much like candy that ends up on the kitchen table at the end of a successful Halloween night, the microelectronics supply chain is a diverse bag of goodies that needs to be checked before it can be consumed. This talk will explore challenges and opportunities in trusting and assuring an increasingly complex electronics global supply chain.
Bio: Dr. Matthew Casto is Chief of the Air Force Research Laboratory, Sensor's Directorate, Trusted Electronics Branch and is the Air Force's Hardware Assurance technical lead for the Department of Defense (DoD) Joint Federated Assurance Center. Dr. Casto is a Senior Electronics Engineer with a BSEE and MSEE degree from Wright State University, and a PhD from The Ohio State University Electro-science Laboratory. In his current role, Dr. Casto leads the Science and Technology portfolio for the DoD's Trusted and Assured Microelectronics Initiative, developing a new trust approach to ensure enduring availability and assured access to state-of-the-art microelectronics.