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08:30-10:00 Session Room1: Paper 4: Analog & Asynchronous
Haralampos-G. Stratigopoulos (Sorbonne Universités, UPMC Univ. Paris 6, CNRS, LIP6, France)
Location: Room 1
Martin Andraud (Katholieke Universiteit Leuven, Belgium)
Laura Galindez (Katholieke Universiteit Leuven, Belgium)
Yichuan Lu (UT Dallas, United States)
Yiorgos Makris (UT Dallas, United States)
Marian Verhelst (Katholieke Universiteit Leuven, Belgium)
On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs

ABSTRACT. This paper explores opportunities of using Bayesian Networks for resource-efficient one-shot on-chip statistical calibration of analog/RF circuits. The proposed approach is demonstrated for a low-noise amplifier implemented in 130nm CMOS.

Ting-Yu Shen (National Taiwan University, Taiwan)
Chia-Cheng Pai (National Taiwan University, Taiwan)
Tsai-Chieh Chen (National Taiwan University, Taiwan)
Samuel Pan (National Taiwan University, Taiwan)
James Chien-Mo Li (National Taiwan University, Taiwan)
Test methodology for PCHB/PCFB based asynchronous pipeline circuits

ABSTRACT. This paper proposes a new, small-area test methodology for PCHB/PCFB without breaking any internal feedback loop. We also analyze the faults which were not studied seriously by previous research.

Shravan K Chaganti (Iowa State University, United States)
Abalhassan Sheikh (Texas Instruments Inc., United States)
Sumit Dubey (Texas Instruments Inc., India)
Frank Ankapong (Texas Instruments Inc., United States)
Nitin Agarwal (Texas Instruments Inc., India)
Degang Chen (Iowa State University, United States)
*Distinguished Paper: Fast and accurate linearity test for DACs with various architectures using segmented models

ABSTRACT. Novel linearity testing methods that significantly reduce test time are introduced for DACs with various architectures. New methods based on an interpolated segmented model are developed for interpolated DACs.

08:30-10:00 Session Room2: Paper 5: 3D Test
Tm Mak (self, United States)
Location: Room 2
Erik Jan Marinissen (imec, Belgium)
Ferenc Fodor (imec, Belgium)
Arnita Podpod (imec, Belgium)
Michele Stucchi (imec, Belgium)
Yu-Rong Jian (National Tsing-Hua University, Taiwan)
Cheng-Wen Wu (National Tsing-Hua University, Taiwan)
*Distinguished Paper: Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits

ABSTRACT. Probing challenges/solutions for multi-die stacked ICs: thin wafers on tape, large-array micro-bumps, analyzing PTPA, misalignment auto-correction. Contains case study, in which most of the discussed challenges and solutions are combined.

Leonidas Katselas (Aristotle University of Thessaloniki, Greece)
Alkis Hatzopoulos (Aristotle University of Thessaloniki, Greece)
Hailong Jiao (Peking University, China)
Christos Papameletis (Cadence Design Systems, United States)
Erik Jan Marinissen (IMEC, Belgium)
Embedded Toggle Generator to Provide Realistic Test Conditions during Test of Digital 2D-SoCs and 3D-SICs

ABSTRACT. In this work we propose a method to provide realistic test conditions during modular test of digital 2D-SoCs and 3D-SICs, using programmable on-chip toggle generators.

Sourav Das (Intel, United States)
Fei Su (Intel, United States)
Sreejit Chakravarty (Intel, United States)
A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
SPEAKER: Sourav Das

ABSTRACT. We propose a no-touch TSV test methodology that is resilient against PVT variations, or test environment parameters, thus suitable for industry practical uses.

08:30-10:00 Session Room3: Paper 6: Security Track Paper Session: Hardware Trojans
Ujjwal Guin (Auburn University, United States)
Location: Room 3
Alif Ahmed (University of Florida, United States)
Farimah Farahmandi (University of Florida, United States)
Yousef Iskander (Cisco, United States)
Prabhat Mishra (University of Florida, United States)
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution

ABSTRACT. We propose an automated and scalable test generation method for activation of hardware Trojans in RTL designs. This method uses concolic testing to activate Trojans in large and complex benchmarks.

Basim Shanyour (Southern Illinois University- Carbondale, United States)
Spyros Tragoudas (Southern Illinois University- Carbondale, United States)
Detection of low power Trojans in standard cell designs using built-in current sensors.

ABSTRACT. Ultra-low power dissipating Trojans can be detected by analyzing IDDT waveforms at each gate. A small number of current sensors are inserted using ATPG, regression analysis and appropriate standard-cell placement.

Christiana Kapatsori (The University of Texas at Dallas, United States)
Yu Liu (The University of Texas at Dallas, United States)
Angelos Antonopoulos (The University of Texas at Dallas, United States)
Yiorgos Makris (The University of Texas at Dallas, United States)
Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs

ABSTRACT. Introduction of a hardware dithering methodology for neutralizing Trojans in ICs. This prevention mechanism aims to occupy, or render unusable, the process variation margins, wherein Trojans operate while remaining concealed.

08:30-10:00 Session Room4: Special 2: Embedded Tutorial: Analog Fault Simulation

Embedded Tutorial - Analog Fault Simulation: Practical Applications, Case Studies and Challenges

by Rubin Parekhji, Devanathan Varadarajan, Lakshmanan Balasubramanian, and Ken Butler of Texas Instruments

Analog fault simulation is gaining significant importance now given the compelling needs for robustness and high quality for analog IPs. EDA offerings have emerged, and standards are emerging as well. In this embedded tutorial, the presenters, (who have been working in this area for the past few years), will provide an overview of fault simulation for analog circuits, and share their experiences and highlight challenges required to be addressed to make its adoption main-stream. Case studies on actual analog IPs demonstrating several applications in design and manufacturing (coverage, defect based test, diagnosis, test optimisations, sensitivity analysis, etc.) will be presented.

Sule Ozev (Arizona State University, United States)
Location: Room 4
08:30-10:00 Session Room5: AI 3: Machine Learning in Yield Learning
Janusz Rajski (Mentor, A Siemens Business, United States)
Location: Room 5
David Pan (The University of Texas at Austin, United States)
Machine Learning for Yield Learning and Optimization

ABSTRACT. This talk surveys recent results of using various machine learning/deep learning techniques for performance modeling under uncertainty, lithography modeling with transfer/active learning, lithography hotspot detection, and IC mask optimizations. State-of-the-art methods are explained and challenges/opportunities are discussed.

Ken Harris (PDF Solutions, United States)
Practical Applications of Big Data Analytics in Semiconductor Manufacturing, Assembly and Test

ABSTRACT. Traditional data gathering and visualization techniques are becoming less and less useful in today’s manufacturing environment.  In this talk, we review the reasons why, along with practical examples illustrating the importance of integrated, automated analysis and triggered actions in the product ramps of today’s advanced products and manufacturing technologies.

10:30-12:00 Session Room1: Special: Testing of GigaScale Designs
Nilanjan Mukherjee (Mentor, United States)
Location: Room 1
Joe Reynick (eSilicon, United States)
DFT Considerations and Flow for a Large 2.5D/3D Device

ABSTRACT. Traditional IC DFT Engineers must expand their horizons to include the details of packaging, physical design, test hardware, and even board-level test techniques when working with large 2.5D/3D System-in-Package (SIP) devices. The planning, implementation, and production test for such a SIP is discussed in this presentation. Our discussion will also include challenges/solutions, and potential areas for new opportunities in supporting 2.5D/3D technologies in the future.

Jais Abraham (Qualcomm BDC, India)
Test Challenges for Low Power SoCs

ABSTRACT. Low power SoCs impose unique challenges for DFT and for silicon testing. Tests have to be created so as not to exceed the power budget of the design, while, at the same time not imposing excessive costs for testing under these constraints. DFT techniques are also needed to detect manufacturing defects on the power management structures introduced in the design. This presentation will cover some of these challenges and the solutions to address these.

10:30-12:00 Session Room2: Paper 7: Advanced & Emerging Devices
Fei Su (Intel, United States)
Location: Room 2
Ling Zhang (Hubei Polytechnic University, China)
Zipeng Li (Intel Inc., Santa Clara, United States)
Krishnendu Chakrabarty (Duke University, United States)
*Distinguished Paper: Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips

ABSTRACT. we propose the first daisy-chain design that can perform self-diagnosis and repair the detected faults. It works in a timely manner and can work in both on-line and off-line mode.

Arjun Chaudhuri (Duke University, United States)
Krishnendu Chakrabarty (Duke University, United States)
Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors

ABSTRACT. We present a physics-based classification of memristor fault origins and investigate design-induced coupling in dense memristor crossbars. The resulting conclusions provide valuable feedback to the fabrication and design of memristor-based circuits and facilitate test generation. 

Will Howell (Intel, United States)
Friedrich Hapke (Mentor, A Siemens Business, Germany)
Edward Brazil (Intel Corporation, Ireland)
Srikanth Venkataraman (Intel, United States)
Rudrajit Datta (Intel, United States)
Andreas Glowatz (Mentor, A Siemens Business, Germany)
Wilfried Redemund (Mentor, A Siemens Business, Germany)
Juergen Schmerberg (Mentor, A Siemens Business, Germany)
Anja Fast (Mentor, A Siemens Business, Germany)
Janusz Rajski (Mentor, A Siemens Business, United States)
DPPM Reduction Methods and new Defect Oriented Test Methods Applied to Advanced FinFET Technologies
SPEAKER: Will Howell

ABSTRACT. This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies, including correlation to System-Level-Test fails.

10:30-12:00 Session Room3: Paper 8: Security Track Paper Session: Securing HW & DFT
Saman Adham (TSMC, Canada)
Location: Room 3
Meng Li (The University of Texas at Austin, United States)
Kaveh Shamsi (University of Florida, United States)
Yier Jin (University of Florida, United States)
David Pan (The University of Texas at Austin, United States)
TimingSAT: Decamouflaging Timing-based Logic Obfuscation
SPEAKER: David Pan

ABSTRACT. We propose TimingSAT to evaluate the security of timing-based camouflaging strategies. TimingSAT consists of transformation and simplification procedures to enable efficient query-based attacks. The correctness of TimingSAT is formally proved.

Senwen Kan (Cypress Semiconductor, United States)
Jennifer Dworak (Southern Methodist University, United States)
IJTAG Integrity Checking with Chained Hashing
SPEAKER: Senwen Kan

ABSTRACT. This paper proposes to integrity check an IJTAG based design under test (DUT) as well as the DUT-accessing system, such as the DUT tester, to establish trust.

Nicole Fern (UC Santa Barbara, United States)
Kwang-Ting Cheng (The Hong Kong University of Science and Technology, Hong Kong)
Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
SPEAKER: Nicole Fern

ABSTRACT. Undocumented scan and debug instructions can be exploited by hackers to undermine system security. Our technique detects anomalous out-of-spec JTAG instruction opcodes using commercial equivalence checking tools before tape-out.

10:30-12:00 Session Room4: Automotive 1: Functional Safety and Case Studies
Peilin Song (IBM, United States)
Location: Room 4
Swathi G (Texas Instruments, India)
Prakash Narayanan (Texas Instruments, India)
Rubin Parekhji (Texas Instruments, India)
Test Application and Evaluation Methods to Meet Run-time Self-test Requirements for Functional Safety
Tal Kogan (Intel, Israel)
Gabriele Boschi (Intel, Italy)
Yehonatan Abotbol (Inomize, Israel)
Narine Martirosyan (Synopsys, Armenia)
Gurgen Harutyunyan (Synopsys, Armenia)
Advanced Uniformed Test Approach for Automotive SoCs
SPEAKER: Tal Kogan
Marco Casarsa (STMicroelectronics, Italy)
Case Study and Advanced Functional Safety Solution for Automotive SoCs
10:30-12:00 Session Room5: Paper 9: Machine Learning In Test and Diagnosis
Peter Maxwell (ON Semiconductor, United States)
Location: Room 5
Qicheng Huang (Carnegie Mellon University, United States)
Chenlei Fang (Carnegie Mellon University, United States)
Soumya Mittal (Carnegie Mellon University, United States)
Shawn Blanton (Carnegie Mellon University, United States)
Improving Diagnosis Efficiency via Machine Learning
SPEAKER: Qicheng Huang

ABSTRACT. Based on features extracted from fail logs, machine learning methods are used to predict diagnostic information without running time-consuming diagnosis. Experiments on various fail logs demonstrate the efficacy of the concept.

Michihiro Shintani (NAIST, Japan)
Yoshiyuki Nakamura (Renesas Electronics, Japan)
Michiko Inoue (NAIST, Japan)
Artificial Neural Network Based Test Escape Screening Using Generative Model

ABSTRACT. We propose a test escape detection method based on variational autoencoder that is widely used in neural network. Experiments demonstrates the proposed method detects test escapes more than 8.5 times compared to a conventional method.

Matt Nero (UCSB, United States)
Chuanhe Shan (UCSB, United States)
Li-C Wang (University of California Santa Barbara, United States)
Nikolas Sumikawa (NXP Semiconductors, United States)
*Distinguished Paper: Concept Recognition in Production Yield Data Analytics
SPEAKER: Chuanhe Shan

ABSTRACT. This paper presents a concept-based workflow approach for yield data analytics. Neural network models are built to recognize plot-based concepts used in an analytic workflow.

12:00-14:00Posters & Lunch
14:00-15:30 Session Room1: ITC India: Papers from ITC India
Jedrzej Solecki (Mentor, United States)
Location: Room 1
Wilson Pradeep (Texas Instruments, India)
Prakash Narayanan (Texas Instruments, India)
Improved RAM Sequential Tests for SoCs with Complex Memory Architectures
Bharath Nandakumar (Cadence Design Systems, India)
Anil Malik (Cadence Design Systems, India)
Sameer Chillarige (Cadence Design Systems, India)
Anshul Kumar (Cadence Design Systems, India)
Joe Swenton (Cadence Design Systems, India)
Atul Chhabra (Cadence Design Systems, India)
High Accuracy, Robust Multiple Defect Diagnosis Scheme
Carl Wisnesky (Cadence Design Systems, United States)
Patrick Gallagher (Cadence Design Systems, United States)
Enhancing Automotive Self-Test with Embedded Distributed Programming
SPEAKER: Carl Wisnesky
14:00-15:30 Session Room3: Paper 10: Security Track Paper Session: Trust but Verify
Naghmeh Karimi (University of Maryland, Baltimore County (UMBC), United States)
Location: Room 3
Tamzidul Hoque (University of Florida, United States)
Jonathan Cruz (University of Florida, United States)
Prabuddha Chakraborty (University of Florida, United States)
Swarup Bhunia (University of Florida, United States)
Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify

ABSTRACT. We propose a supervised learning framework for hardware IP trust verification that utilizes a tool-generated robust training set and combines three machine learning models using a voting ensemble.

Andrew Stern (University of Florida, United States)
Ulbert Botero (University of Florida, United States)
Bicky Shakya (University of Florida, United States)
Haoting Shen (University of Florida, United States)
Domenic Forte (University of Florida, United States)
Mark Tehranipoor (University of Florida, United States)
EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
SPEAKER: Andrew Stern

ABSTRACT. Today's globalized electronics supply chain is prone to counterfeit chip proliferation. We propose a novel method of counterfeit integrated circuit detection which utilizes design-specific electromagnetic fingerprints generated by clock distribution networks.

Jeremy Bellay (Battelle, United States)
Barricade methodology for detecting counterfeits

ABSTRACT. Battelle has developed a technology to nondestructively classify electronic components as authentic or counterfeit. The technology uses a method that creates feature vectors for each class of devices using a reconfigurable side channel power analysis test fixture. This test fixture monitors the power fluctuations of the device either via connection to a power or a ground pin while test signals are sent to the device. Power waveforms are processed, undergo dimensionality reduction techniques, and the resultant data is plotted in Principal Component Analysis (PCA) space to reveal information related to the authenticity of the device under test. To scale this technology to the full catalog of parts available to a production test house, unique tools have been created that provide automated test generation and scoring of feature vectors.

14:00-15:30 Session Room4: Automotive 2: Panel on Automotive Functional Safety


  • Navin Bishnoi, GLOBAL FOUNDARIES
  • Christophe Eychenne, Bosch
  • Nir Maor, Qualcomm
  • Riccardo Mariani, Intel
  • Rajagopalan Srinivasan, Nvidia
  • Yervant Zorian, Synopsys

Panel Moderator: Paolo Bernardi, Polito Torino

Paolo Bernardi (Polito Torino, Italy)
Location: Room 4
14:00-15:30 Session Room5: AI 4: AI and Autonomous Machines
Kenneth Butler (Texas Instruments, United States)
Location: Room 5
Li-C. Wang (UCSB, United States)
An Autonomous System View To Apply Machine Learning

ABSTRACT. This talk draws an analogy to the autonomous system view of self-driving car for applying machine learning in a test application. Through such a system view it is more intuitive to see where a particular machine learning approach might be applied and what type of learning problem is to be solved. To give a concrete example, a short demo will be included to illustrate how such an autonomous system can be used for production yield data analytics.

Shuyue Lan (Northwestern University, United States)
Chao Huang (Northwestern University, United States)
Zhilu Wang (Northwestern University, United States)
Hengyi Liang (Northwestern University, United States)
Wenhao Su (University of Michigan, United States)
Qi Zhu (Northwestern University, United States)
Design Automation for Intelligent Automotive Systems

ABSTRACT. This talk will discuss the challenges in designing the next-generation autonomous and connected vehicles, and present promising design automation techniques that tackle these challenges.

16:00-17:00 Session Keynote 2: Dr. Matthew Casto, Chief, Trusted Electronics, Air Force Research Laboratory

Title: Trick or Treat: Is your supply safe? 

Abstract: Much like candy that ends up on the kitchen table at the end of a successful Halloween night, the microelectronics supply chain is a diverse bag of goodies that needs to be checked before it can be consumed.  This talk will explore challenges and opportunities in trusting and assuring an increasingly complex electronics global supply chain.

Bio: Dr. Matthew Casto is Chief of the Air Force Research Laboratory, Sensor's Directorate, Trusted Electronics Branch and is the Air Force's Hardware Assurance technical lead for the Department of Defense (DoD) Joint Federated Assurance Center. Dr. Casto is a Senior Electronics Engineer with a BSEE and MSEE degree from Wright State University, and a PhD from The Ohio State University Electro-science Laboratory. In his current role, Dr. Casto leads the Science and Technology portfolio for the DoD's Trusted and Assured Microelectronics Initiative, developing a new trust approach to ensure enduring availability and assured access to state-of-the-art microelectronics.

Waleed Khalil (The Ohio State University, United States)
Location: Ball Room