ABSTRACT. In this work,the influence of HCl gas on the doping uniformity of 4H-SiC superjunction structure using CVD trench filling epitaxial growth method has been investigated. It is found that, a sufficient HCl flow rate is necessary due to non-uniform doping profiles at low HCl flow rates.

ABSTRACT. Silicon carbide (SiC) has emerged as promising material for high-voltage and high-power electronic device applications such as power transmission, new energy vehicles, and photovoltaics. As the voltage withstand ratings of devices increase, there is a pressing demand for high-quality thick-film SiC epitaxial layers with low defect densities. Critical epitaxial defects that can lead to device failures, such as triangular defects and carrot defects, have been effectively mitigated through advances in epitaxial growth processes[1-3]. Notably, surface defects characterized by small concave pits can induce localized current crowding, resulting in increased leakage current and compromised reliability of devices[4-7]. Extensive research on the control of pit defects predominantly focus on SiC epitaxial layers with 10–12 μm thickness[7-9]. However, the density of pits demonstrates exponential escalation with increasing epitaxial layer thickness. The surface pits remain a significant challenge, particularly in thick SiC epitaxial layers (above 30 μm).

In this research, the distribution and formation mechanisms of surface pits have been investigated by utilizing surface defect detection system and KOH etching technique. Small-sized pits are dominated (>95% of total defects), predominantly originating from threading dislocations (TDs) that disrupt step-flow growth. Given the limited flexibility in tuning drift layer process, this work is dedicated to buffer layer engineering to suppress pits formation. The effects of buffer layer parameters including C/Si ratio, growth rate, and doping condition have been systematically investigated. By implementing gradual doping transition and Si-rich buffer layer structure, the pit defect density is significantly reduced without compromising epitaxial integrity. This approach provides a viable pathway to achieve high-reliability, low-defect SiC epitaxial layers for next-generation power electronics.

In the experiments, the 4H-SiC epilayers were grown by a warm wall planetary chemical vapor deposition (CVD) system. The thickness of all SiC epilayers was ~30 μm. The surface pit morphology and photoluminescence image of the epilayer is shown in Fig. 1. According to statistical results, small pits (10 μm2<area <30 μm2) are predominant. The observed pit defects on the epitaxial surface are strongly correlated to TDs, potentially due to dislocation-induced perturbations in step-flow growth, as revealed by KOH etching. Experiments were subsequently conducted to investigate the influence of buffer layer process parameters on the reduction of surface pits. Existing techniques typically grow buffer layer with fixed doping concentration on SiC substrates. However, the method shows limited effectiveness in suppressing defect propagation and reducing defect density of the epilayer. Herein, the structural design combining gradual doping transition with the growth of Si-rich buffer layer is illustrated in Fig. 2(a). The implementation of non-linearly gradual doping profile can lead to smooth transition, preventing lattice mismatch-induced interfacial defects and stress. Coupled with silicon-rich ambient during buffer layer growth, this approach suppresses the formation of pits, or partially repairs existing defects, leading to shallower defect depths. The growth results of SiC epilayers under different buffer layer processes were compared, as shown in Fig. 2(b). Reducing the C/Si ratio of the buffer layer from 0.65 to 0.55 effectively decreases the surface pits. Subsequent integration of gradual doping process further reduces the density, achieving a 58.8% decrease in pit count compared to standard processes. In addition, the surface roughness of SiC epi-wafer was further analyzed (Fig. 3). This indicates that the modified growth process exhibits no adverse impact on the roughness and quality of the epitaxial wafer.

ABSTRACT. The crystallinity of cubic silicon carbide (3C-SiC) epilayers is improved through the use of a novel wafer bonding and regrowth technique resulting in a reduction of planar defects. The process involves the epitaxial growth of a 3µm thick 3C-SiC seed on silicon (Si) which is polished and bonded to a new handle wafer before the original substrate and defective interface region of the 3C-SiC epilayer is removed. Further epitaxial growth on this Bonded Switchback template results in higher quality 3C-SiC epilayers through the reduction of stacking fault defects and interface voids. The process can be applied to 3C-SiC grown on both on and off-axis substrates and the form of the new handle has no impact on the growth process enabling this technology to be applied to sapphire or hexagonal 4H-SiC substrates, which will overcome the thermal budget limitations of silicon substrates for 3C-SiC heteroepitaxy. The use of Bonded Switchback can improve material quality for applications in Power Electronics as well as see the heterogeneous integration of 3C-SiC into other device structures, potentially leading to a new range of hybrid 3C-SiC/Si devices without the high density of defects observed at the interface between these two materials.

ABSTRACT. Silicon carbide (SiC) is well known for its use as a substrate in power electronics and has emerged as a promising material for quantum and non-linear photonic circuits. Recent studies have demonstrated that crystalline SiC possesses exceptional optical properties, which are essential for the development of photonic integrated circuits (PICs). However, the development of this emerging photonic platform is hampered by the lack of high-quality commercial SiC-on-insulator (SiCOI) substrates. The demonstrations mentioned earlier are based on costly and non-commercial SiCOI prototypes, produced using the bonding and thinning technique. The aim of current developments is to fabricate a SiCOI wafer comprising a thin layer of high-quality monocrystalline SiC (mSiC) transferred onto a lower cost substrate using the Smart Cut™ technology. The quality of the transferred SiC layer was investigated as a function of the ion implantation method and final annealing temperature applied. As a perspective to this work, the fabrication of waveguides on SiCOI substrates using both implantation conditions will allow us to highlight the impact of the new process on device performance.

ABSTRACT. SmartSiC(TM) engineered substrates were introduced in 2021 as an interesting alternative and future competitor of bulk single crystalline SiC substrates for high voltage power electronics. Since then, the SmartSiC(TM) wafers have undergone numerous improvements, touching the base poly-SiC material, the parameters of SmartCut(TM) and bonding processes, as well as the front- and back-side surface preparation. In the present contribution, we demonstrate the influence of SmartSiC(TM) material developments on the quality of the epitaxial layers.

ABSTRACT. An accurate characterization of deep levels in SiC is essential for both power and quantum device applications. Deep Level Transient Spectroscopy (DLTS) has been the principal technique for this purpose. However, it is difficult to characterize deep levels with similar emission time constants, i.e., those that are energetically close. While Laplace DLTS (LDLTS) offers enhanced time-constant resolution, it requires a high signal‑to‑noise ratio (SNR) to achieve reliable deconvolution , which is often impractical in actual measurements. In this study, we propose a novel capacitance transient analysis based on Bayesian inference. The method was demonstrated to reduce the minimum SNR required to separate multiple deep levels whose emission time constants are close. Moreover, the method was applied to characterize deep levels in electron-irradiated 4H-SiC, and multiple energetically close deep levels were individually detected, which could not be resolved in conventional methods.

ABSTRACT. The effective minority charge carrier lifetime tau is a crucial parameter in power semiconductors that is closely tied to the device’s switching speed and power dissipation. Therefore, the parameter is fundamental for device performance. Electrical reverse recovery current or open circuit voltage decay measurements are well established to extract the effective lifetime of an entire device. These techniques are accessible and quick, but only provide very limited information needed for the development for future generations of power devices. We propose a method that can be used to measure and spatially resolve tau throughout the device’s cross section using a chopped electron beam of a scanning electron microscope (SEM). When a semiconductor is illuminated by the electron beam, electron hole pairs are created. In the depletion layer or in close proximity of the pn-junction, these charges are separated and induce an external current, known as electron-beam induced current (EBIC). A simple yet rough estimate of tau in the material can already be made from a fit of the exponential decay of the steady-state EBIC I_EBIC being proportional to exp(-x/L), as depicted in figure 1c. L = sqrt(D•tau) is the diffusion length and D is the diffusion constant, x being the distance from the edge depletion region. This estimate however is erroneous, since it assumes D to be constant throughout the sample and averages the exponential decay over position, thus losing desired spatial information. We employ a chopped scanning electron beam over a frequency range to resolve the effective lifetime of minority carriers spatially in both n-doped and p-doped regions of a diode. The lifetime may be computed as follows: At any specific point with sufficient EBIC or phase signal, the current exhibits a dependence on the chopping frequency. The physics of this behavior can be described by solving the time dependent continuity equation and considering an additional frequency dependent component exp(i•omega•tau), omega being the angular frequency and t being the time, in the solution [1]:

I_EBIC(x, omega, tau) = I_0•exp(−x/L(a+ib)) with a, b =1/sqrt(2)•sqrt(±1 + sqrt(1 + omega^2•tau^2))

When increasing the chopping frequency of the electron beam, I_EBIC gradually decreases (lowpass behavior) while the phase increases. Subsequently, tau is computed from the knee frequency f_knee=1/2*pi*tau of the current or phase [2-4]. By sweeping over a range of frequencies at every point of a planar device or cross section, the effective lifetime can potentially be determined and mapped. In our experiments, we use a SiC pn-junction with around 3•10^17/cm^3 Al-doping concentration on the p-side and 10^16/cm^3 N-doping in the epitaxial layer with a contact pad and back metallization (see schematic in figure 1a). We measure tau at 300 K close to the depletion region in p-type SiC. As seen in figure 2, tau decreases towards the depletion region because of increased recombination in very close proximity to the depletion region, yielding shorter diffusion lengths [5] and thus shorter lifetimes. This effective lifetime measurement compares well to similar techniques such as time-resolved photoluminescence [6], backing the credibility of our results. While this method is not fully automated and developed yet, this method will push the boundaries of SiC devices in the near future.

[1] McKelvey, J. P. (1966). Solid state and semiconductor physics. Harper & Row. 439-441. [2] Fuyuki, T., & Matsunami, H. (1981). Journal of Applied Physics, 52(5), 3428-3432. [3] Honma, N., et. al. (1986). Japanese journal of applied physics, 25(5R), 743. [4] Pietzsch, J. (1982). Solid-State Electronics, 25(4), 295-304. [5] Marcelot, O., & Magnan, P. (2019). Ultramicroscopy, 197, 23-27. [6] Tawara, T., et. al. (2004). Materials Science Forum, 457, 565-568.

ABSTRACT. In this work, deep levels across the entire 4H-SiC bandgap are investigated by combining deep-level transient spectroscopy (DLTS) and minority carrier transient spectroscopy (MCTS) on n-type and p-type as-grown samples, as well as a set of samples exhibiting point defects introduced by reactive ion etching (RIE). We can correlate electron traps detected by n-type DLTS signals ON1 (EC – 0.84 eV), ON2 (EC – 1.02 eV) and EH6/7 (EC – 1.41 eV) with electron traps detected by p-type MCTS signals ER2 (EC – 0.89 eV), ER3 (EC – 1.09 eV) and ER4 (EC – 1.59 eV). Additionally, MCTS reveals a new electron trap, ER1 (EC – 0.56 eV), which is not observed in DLTS. Interestingly, a hole trap, detected by p-type DLTS spectra HK0 (EV + 0.78 eV), overlaps with an electron trap detected by n-type MCTS signal, a phenomenon currently under investigation. This combined analysis aims to provide a more comprehensive understanding of electrically active defects in 4H-SiC.

ABSTRACT. Neutron irradiation in SiC power devices leads to both nuclear reactions and lattice damage. While detrimental for device reliability, neutron exposure is also exploited in techniques such as neutron transmutation doping (NTD), which relies thermal neutrons due to their higher capture cross-section. Understanding neutron-induced defect formation and its impact on carrier concentration and lifetime is essential for improving radiation hardness and evaluating the feasibility of NTD in SiC. In this study, we investigate the energy-dependent damage mechanisms in 4H-SiC by irradiating samples at two neutron facilities with distinct spectra: one dominated by thermal neutrons, the other with a broad distribution from thermal to fast energies. Defects were analyzed using photoluminescence, Raman spectroscopy, Schottky IVs, deep level transient spectroscopy (DLTS), and minority carrier transient spectroscopy (MCTS). Electrically active point defects and photoluminescence signatures of extended defects show clear differences in defect formation between thermal and fast neutron exposures.

ABSTRACT. Silicon carbide (SiC) is an exceptional material for high-power, high-temperature, high-frequency, and high-radiation applications [1]. Unipolar 4H-SiC devices, including Schottky barrier diodes (SBDs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), are already commercially available and widely adopted [2]. In contrast, bipolar devices like P-intrinsic-N (PiN) diodes leverage conductivity modulation via electron-hole conduction, achieving lower on-resistance than unipolar devices [3]. For power devices, carrier lifetime is a critical performance determinant. Especially, in 4H-SiC with a highly doped buffer layer, Auger recombination becomes more significant during the higher current condition [2]. While most studies report the Auger recombination coefficient (C) for low-doped n-type 4H-SiC under high injection, Tanaka’s group investigated p-type material [3,4]. However, data for highly doped n-type 4H-SiC under high injection remain unreported. Here, we calculate C using heavily N-doped 4H-SiC to address this gap. The sample evaluated in this research was an epitaxial layer with the N doping concentration (N_0) of 5 × 1018 cm−3 grown on the commercially standard n-type 4H-SiC substrate. The thickness of the epi layer was 10 μm. Time-resolved photoluminescence method (TR-PL) was used to characterize the carrier recombination. A yttrium aluminum garnet (YAG) laser with a wavelength of 266 nm and a spot size of approximately 0.13 cm–2 was used as the excitation light source. Sample temperatures were controlled within the range of 298–573 K using a hot plate. Figure 1 shows the excited carrier concentration (∆N) dependence of TR-PL decay curves at 298 and 573 K. As shown in both Fig. 1(a) and (b), as the excited carrier concentration increased, the decays became faster. This indicates that the carrier recombination is dominated by Auger recombination under the high injection level. Moreover, for each excited carrier concentration, the decay at 573 K was faster than that at 298 K. Generally, Auger combination velocity can be given as: █(R_Auger=C_n n^2 p+C_p np^2 "," )"(1)" where n (p) is electron (hole) concentration, C_n (C_p) is Auger recombination coefficient for the electron (hole)-dominated process, respectively. In this research, the highly doped sample whose doping density is almost the same as the highest excited carrier concentration was used, thus, n=N_0+∆N and p=∆N. Moreover, the hole concentration is much smaller than the electron concentration. Therefore, the probability of hole-hole-electron (h-e-e) transitions became relatively low. Considering all, the Auger lifetime, τ_Auger, can be obtained only by assuming that C_p≅0 using eq. (1) as: █(τ_Auger=1/(C〖(N_0+∆N)〗^2 ) "," )"(2)" To evaluate the auger recombination coefficient, since the Auger recombination is presented at the initial decay, we extracted the slopes, τ_initial, obtained from the peak to 10 ns of the decay curves. However, the radiative recombination was contained in τ_initial, we calculated Auger lifetimes using the following equation with the reported B of 1.0 × 10−12 cm3/s for the highest excited carrier concentration at each temperature, as shown in Fig. 2 [4]. █(1/τ_Auger =1/τ_initial -B(N_0+∆N)"," )"(3)" Figure 3 shows the temperature dependence of calculated C using eqs. (2) and (3). As shown in this figure, at room temperature, C = 3.7 × 10−31 cm6/s. Compared to the reported C of 7 × 10−31 cm6/s at N_0+∆N~〖"10" 〗^"18" cm−3 and 0.8 × 10−31 cm6/s at N_0+∆N~〖"10" 〗^"20" cm−3 by Ščajev’s group, ours is located in this range at N_0+∆N~〖"10" 〗^"19" cm−3 [5]. Therefore, the screening of the carrier–phonon interaction by free carriers will attribute to the decrease in C [6]. Furthermore, C increases with increasing temperature. The dashed line shows the fitting curve with C="1.6 × " 〖"10" 〗^"-33" T^"0.95" cm6/s. Generally, for indirect bandgap semiconductors such as SiC, Auger recombination under the conditions of energy (E) and momentum (k) conservation. However, as the temperature increases, phonon scattering becomes more significant. This leads to a relaxation of the momentum conservation, allowing slight deviations in k and consequently promoting Auger recombination. Ščajev’s group reported that the Auger recombination coefficient was independent of temperature [6]. In contrast, Galeckas’s group observed that the Auger recombination coefficient decreased with increasing temperature [1]. Therefore, the observed increase of the Auger coefficient with temperature in our results can be naturally understood considering the effects of phonon interactions.

ABSTRACT. Local electrical properties of a 4H-SiC(0001) 4°off macrostepped surface, obtained after liquid Si melting in a SiC/Si/SiC sandwich configuration, are investigated by Atomic Force Microscopy (AFM) in both DC and RF modes. In the same sample step risers and terraces properties are probed, analyzed and compared. The AFM-DC conductive mode, Scanning Spreading Resistance (SSRM) mode reveals homogeneous conductivity on the wide terraces of the 4H-SiC(0001) macrosteps and a noisier signal for the unreacted area with step risers. In addition, the AFM-RF scanning Microwave Impedance Microscopy (sMIM) mapping shows the lower conductivity of the unreacted areas than the terraces of the macrosteps. AFM results demonstrate that in both DC and RF the negative impact in the local electrical properties of the defect states at these risers of the 4H-SiC(0001).

ABSTRACT. 4H-SiC is increasingly recognized as a critical semiconductor material for next-generation power electronics due to its superior electrical and thermal properties [1]. As device integration and performance demands continue to rise, surface cleanliness has become essential for achieving high-quality and high-yield epitaxial layers on 4H-SiC substrates. Chemical mechanical polishing (CMP), cleaning, surface preparation, and epitaxial growth processes play crucial roles in the overall manufacturing of 4H-SiC substrates [2–4]. The RCA cleaning process, commonly used in Si semiconductor manufacturing, has been adapted for 4H-SiC to remove particles and perform surface preparation. However, due to the strong Si–C bonds in 4H-SiC, the material exhibits a chemically stable surface and shows a particle removal behavior different from that of Si. There has been insufficient study on the particle removal mechanism specific to 4H-SiC compared to Si. To effectively remove particles from the 4H-SiC surface and improve the quality of epitaxial layer growth, a deeper understanding of the cleaning mechanism on 4H-SiC is required. In this study, we investigated the adhesion and removal behavior of contaminant particles on the surface of 4H-SiC in various cleaning solutions, in comparison with Si, and explored the particle removal mechanism to enhance cleaning efficiency. 4H-SiC and Si wafers were used to investigate the wet cleaning mechanism through a comparison of their surface chemistry and particle adhesion behavior to understand the cleaning mechanism of 4H-SiC. Ammonium hydroxide-hydrogen peroxide-mixture (APM), sulfuric acid-hydrogen peroxide-mixture (SPM), diluted hydrofluoric acid (DHF), H2O2, and potassium permanganate (KMnO₄), which is a representative oxidizer for SiC were used. These cleaning solutions were applied to both 4H-SiC and Si substrates to compare oxidation and etching behavior and the resulting surface property transitions. Surface wettability was evaluated using the contact angle analyzer (Phoenix 300, SEO, Korea). Atomic force microscopy (AFM, NX20, Park Systems, Korea) was used to characterize the change in surface physical and chemical properties such as surface morphology by measuring surface roughness, and surface adhesion properties analyzing force–distance (F/D) curves between silica particle and 4H-SiC. X-ray photoelectron spectroscopy (XPS) (K-alpha plus, Thermo Scientific, USA) was employed to analyze surface chemical composition and oxidation states, with particular focus on variations in the O1s spectra. Figure 1 summarizes the results of surface chemical properties, including changes in roughness and contact angle, according to the oxidants and cleaning solutions after treatment. The results revealed that 4H-SiC surfaces showed limited surface oxidation and minimal hydrophilic conversion compared to Si. While Si underwent oxidation in oxidizing agents and subsequent etching by HF solution, 4H-SiC exhibited surface reactions resulting in a highly hydrophilic surface upon SPM treatment. These differences were confirmed through XPS as shown in Figure 2, which presents the O 1s spectra of 4H-SiC surfaces after treatment with DHF, SPM, and KMnO₄. According to the XPS results, both SPM and KMnO₄ treatments increased surface oxygen content and it indicates that –OH molecules adsorbed on the 4H-SiC surface. However, the degree of –OH uptake varied by oxidant, providing insight into differences in chemical reactivity. In addition, the surface chemical properties of 4H-SiC, which differ from those of Si, influence particle contamination and removal behavior. Although electrostatic interactions also contribute to particle adhesion on 4H-SiC, the overall adhesion mechanism and removal behavior differ from those on Si. However, while particle removal on Si is facilitated by etching, lift-off, and electrostatic repulsion mechanisms, such processes are absent on 4H-SiC due to its chemical inertness. Furthermore, the lack of sufficient electrostatic repulsion on the 4H-SiC surface hinders effective particle detachment, making it necessary to adopt cleaning methods that apply physical forces. In conclusion, the chemically stable nature of 4H-SiC surfaces results in a fundamentally different wet cleaning mechanism compared to Si. The reduced chemical reactivity and predominance of physical adsorption suggest that particle removal from SiC is driven more by mechanical forces than by chemical interactions. These results indicate that achieving effective particle removal and high-quality surface finishing of wide bandgap 4H-SiC wafers necessitates the development of customized cleaning processes, in which physical forces play a dominant role over traditional Si-based chemical cleaning approaches.

ABSTRACT. Previous studies have shown that charge pumping electrically-detected magnetic resonance (CP-EDMR) is a powerful technique for detecting paramagnetic point defects at the SiC-SiO2 interface of 4H-SiC MOSFETs [1-3]. In charge pumping, a spin-dependent recombination current, i.e., a charge pumping current (Icp) is generated from the source and drain (shorted together) to the body of the device by applying an oscillating voltage to the gate [4-5]. Consequently, point defects at the interface are alternatingly filled with holes and electrons as the gate voltage oscillates. A spin-dependent recombination current is then generated and detected through the body contact, when a trapped hole recombines with an electron at the interface, or vice versa. Furthermore, by changing the rise (tr) or fall (tf) times of the gate pulse, it is possible to stimulate hole and electron emission respectively, as first demonstrated by Groeseneken et al. [5]. This will be further exploited in this work.

ABSTRACT. Ion implantation of noble gases and hydrogen into silicon carbide (SiC) has gained growing attention due to its wide-ranging technological applications. Noble gas species such as helium, neon, or argon are used to engineer lattice defects, simulate radiation damage, form nano-bubbles and cavities, and modify surface stress profiles. Hydrogen plays an equally important role, especially in the passivation of electrically active defects at SiO₂/SiC interfaces and in controlled delamination processes such as smart-cut techniques. The accurate depth profiling of these elements is critical for understanding the defect formation mechanisms and optimizing process conditions for power electronics and nuclear-grade materials.

However, SIMS measurements of noble gases in SiC remain highly challenging due to their low ionization probability and the material’s strong resistance to ion sputtering. A partial solution, developed in the early 1990s, involved the use of CsX⁺ cluster ions, which significantly improved noble gas detection in silicon and metals [1]. This method, however, is largely ineffective for SiC, where the extremely low sputter yield limits secondary ion generation. As a result, even with CsX⁺ enhancement, detection limits rarely improve beyond 10²⁰ atoms·cm⁻³. This has discouraged research in this area, and there are virtually no published SIMS depth profiles of noble gases in SiC, highlighting the unresolved analytical difficulties.

To address the limitations of noble gas detection in SiC, a three-step surface conditioning procedure was established[2]. The process begins with high-energy Cs⁺ bombardment, which cleans and activates the near-surface region. This is followed by ultra-low energy Cs⁺ deposition, enriching the sample surface with cesium without inducing significant sputtering. In the final step, intermediate-energy sputtering is applied to gently mix the surface layer, promoting the formation of CsX⁺ cluster ions under steady-state conditions. This combined approach enhances ionization efficiency and stabilizes the signal during acquisition. When applied to noble gas-implanted SiC, it enabled a nearly two orders of magnitude improvement in detection limits, reducing them to the low 10¹⁸ atoms·cm⁻³ range, while preserving sufficient depth resolution for profiling thin structures. Figure 1 presents depth profiling results for silicon carbide implanted with helium, neon, and argon. Solid lines correspond to measurements performed using the surface engineering method, while dotted lines represent conventional SIMS measurements under standard conditions, clearly illustrating the substantial gain in detection sensitivity.

In the case of hydrogen, an additional step is required due to the high background signal originating from residual gases in the analysis chamber. To suppress this background and improve detection limits, titanium pre-sputtering is employed prior to measurement[3]. This process deposits a thin Ti layer on the immersion lens and surrounding surfaces, effectively acting as a getter for hydrogen and water vapor. When combined with the cesium-based surface engineering protocol, this approach enables reliable hydrogen detection in SiC at concentrations below 1 × 10¹⁷ atoms·cm⁻³.

Together, these combined approaches enable precise and quantitative detection of inert and light implanted species in one of the most challenging materials for SIMS, opening new avenues in process control, defect engineering, and device innovation.

Acknowledgements: This work was supported by the National Centre for Research and Development, project No. LIDER/8/0055/L-12/20/NCBR/2021.

[1] H. Gnaser, H. Oechsner, Surf. Interface Anal. 17, 646 (1991) [2] P.P. Michałowski, Measurement, in review (2025). [3] P.P. Michałowski, J. Anal. At. Spectrom. 35, 1047 (2020).

ABSTRACT. Silicon carbide (SiC) is a wide bandgap semiconductor material with exceptional properties for a variety of applications, particularly for high-voltage devices. SiC has proven to outperform traditional silicon (Si) based power electronic devices. In this work the OBIC (Optical Beam Induced Current) technique will be applied to examine the electric field distribution inside the structure of SiC bipolar diodes with different epitaxial layer thickness. To create electron-hole pairs inside the semiconductor, a 325 nm UV laser beam is used. The focused laser beam was moved on the surface of the device with steps of 2 microns. We have tested bipolar diodes with both 10 microns epilayer thickness and 100 epilayer thickness. The OBIC is measured by Keithley 2450 SMU (Source Measurement Unit) and is then mapped in 2-directions (X and Y) or just along one line in a chosen direction. The intensity of the photo-generated current is linked to the intensity of the average electric field and therefore to the reverse voltage applied to the detector under test. We obtained several OBICs by re-scanning the same location at different reverse voltages (up to 200 V) applied to the same SiC diode. The increased electric field caused by an increase in reverse voltage results in an increase of the OBIC at the same location. Synopsis TCAD simulations of the electric field are also reported for both diodes. In these simulations it is possible to observe the increase of the electric field at the edge of the devices that is observed by the OBIC measurements. In conclusion, OBIC technique aids in optimizing device design and improving overall performance.

ABSTRACT. Key material properties, such as carrier mobility and drift velocity, are fundamental for predicting device characteristics and gaining insight into the associated physical phenomena. In SiC, while the low-field mobility has been intensively studied, reports on high-field drift velocity are still very limited, especially on its temperature dependence. In this study, the temperature dependence of the drift velocities for electrons and holes parallel and perpendicular to the c-axis were characterized over a wide electric field range (1–200 kV/cm) by a conductance method using SiC(11"2" ̅0) samples.

ABSTRACT. We experimentally obtained the Shockley-Read-Hall (SRH) recombination coefficient, surface recombination velocity, and intrinsic carrier density in the SiC epilayer, and then, the simulation model was constructed. The device simulation (TCAD) using the model could effectively reproduce the experimental forward current conduction of the SiC PiN diodes, which were fabricated on various wafers.

ABSTRACT. Silicon carbide (SiC) power devices are widely used in fast-switching applications, balancing switching speed and on-state resistance. However, some applications prioritize thermal management, especially where devices operate continuously at nominal current -such as protection diodes in photovoltaic strings or Solid-State Circuit Breakers (SSCBs). In such cases, proper design of device area, nominal current density, and cooling is critical, particularly where the cooling system must be minimized. SiC’s superior thermal conductivity and lower on-state voltage enable higher current densities than silicon, typically 400–500 A/cm² for devices rated below 1200 V. This work investigates the thermal response of SiC diodes under current stress and varying ambient temperatures using an innovative junction temperature extraction technique, focusing on the role of diode structure and voltage class (1200, 1700, 3300 V) in self-heating transients.

ABSTRACT. SiC power devices are crucial in high-power applications like e-vehicle traction-inverters and on-board battery chargers. These applications require stringent electrical and thermomechanical reliability requirements, facing harsh environment in terms of temperature and humidity. To improve their robustness against corrosion and moisture, silicon nitride (SiN) and silicon dioxide (SiO2) are commonly used as passivation layers to protect the device. However, SiN is a hard and brittle compound. When it is submitted to thermal budget, SiN must withstand high thermo-mechanical stress due to the mismatch among the coefficients of thermal expansion (CTE) of device’s component. This might lead to cracks in the SiN, that can propagate into the interlayer dielectrics disrupting the electrical isolation and enhancing moisture infiltration and corrosion due to the high electric field [1-4]. The objective of this study is to compare, through thermo-mechanical finite element analysis (FEA) and electrical TCAD simulation, various passivation stacks to optimize thermo-mechanical stress and electrical robustness of SiC power MOSFET devices [5-6]. The study is concerning the region around the gate metal corner. As shown in Figure 1, the profile geometry of the metal in such area might induce cracks in SiN due to high tensile stress in the corner region. Smoothing such region by proper design can improve device robustness. For this purpose, we simulate SiN thicknesses values ranging from 1 to 0.3 µm, in a double passivation (SiN + Polyimide) scheme. The geometry of the region around the gate metal was simulated as a simplified 3D die strip. FEA estimates the stress induced on SiN by chip manufacturing. In particular, the SiN deposition was performed by PECVD at 400 °C and material characteristics depend on the process chemistry of SiH4, NH3 and N2 gases mix ratio. The final SiN stoichiometry is critically dependent on SiH4 / NH3 ratio (0.12 – 0.24 in our case), leading to a nitrogen- or silicon-rich material, respectively. Combining warpage measurement and Stoney equation for thin film, we estimate SiN intrinsic stress equal to – 152 MPa. The second component is the cooling down from 400 to 25 °C, which is driven by CTE mismatch. In our model, thermal and intrinsic stress are both accounted, thermal component will be prevalent. We reproduce the metal hardening with Chaboche model to avoid stress overestimation in SiN layer [5-6]. Considering the SiN is a brittle material, we use the maximum principal stress criterion to evaluate SiN layer robustness. As shown in Fig. 2, by decreasing SiN thickness, room temperature stress is increased (+571 and +1062 MPa at 1 and 0.3 µm). Such effect is explained by the increased stiffness, which limits the stress induced by metal, and by smoother fillet, which reduces the notch effect at the top corner. Moreover, the introduction of SiN smooths the electric field peaks at the corner gate metal, which is reduced by a threefold factor when the SiN thickness goes from 0.3 to 1 µm, as shown in Fig. 3a-c. Additional modeling is done to study the introduction of a further SiO2 layer between the gate metal and the SiN layer. The FEA models show that this configuration, called triple passivation, significantly reduces the maximum principal stress in the SiN layer from ~570 MPa to ~200 MPa. For such passivation scheme, the optimum condition on the mechanical stress reduction is found for a SiN thickness ~ 1 µm. Triple passivation introduction is also helpful for further reducing the E-field at the metal - passivation interface. Such passivation scheme is therefore expected to give benefits in enhancing the overall robustness and lifetime of SiC power devices, especially under harsh humidity and bias conditions.

ABSTRACT. Application-driven device design becomes crucial for a wide acceptance of SiC power MOSFET technology in power electronics, and the device’s susceptibility to oscillations, when connected in parallel configuration, is a key aspect for multi-chip SiC power MOSFET power modules design. During parallel operation, oscillations can occur due to uneven current distribution between parallel devices during switching transients originating from layout asymmetries, device performance mismatch, and/or nonuniform temperature distribution, ultimately leading to instability of the operation. In comparison to two SiC power MOSFET dies in parallel, the oscillations between 8 dies are significantly more complex, and different transfer functions are needed to evaluate the oscillations at turn-on and -off. Three device designs with different pitch size, channel length (Lch), channel implantation dose (Kch), JFET width (WJFET), and oxide quality (fixed charge concentration Qfix) were selected, and compared in terms of device performance metrics, i.e., conduction, switching, and oscillation susceptibility in an 8-die parallel configuration. In the final contribution, both turn-on and -off oscillations will be associated with Cgd, Cgs, Cds, gm(gs,ac), and gm(ds,ac), and the corresponding device design parameters, followed by a more detailed analysis to identify key device performance trade-offs and critical design parameters for multi-chip power modules, aiming to derive a device figure-of-merit for parallel operation of SiC power MOSFETs.

ABSTRACT. Bi-directional power devices, capable of conducting and blocking current in both forward and reverse directions, are essential building blocks for emerging applications such as current source inverters (CSIs) and matrix converters. Various approaches to implementing bi-directional power devices have been reported, including package-level integration and monolithic two-chip integration. Recently, our research group successfully demonstrated a cell-to-cell integrated SiC lateral bi-directional power MOSFET (L-BiD-MOSFET). Cell-to-cell integration enables exploration of novel device architectures while offering significant area savings. To further enhance the blocking performance of the cell-to-cell integrated lateral bi-directional devices, it is necessary to examine the layout design in conjunction with 3D TCAD simulations to analyze electric field concentrations. In this work, we correlate the measurement results of fabricated L-BiD-MOSFETs with TCAD simulations. Using 3D TCAD, we identify electric field concentration at the finger edge and propose an extended P-top design to mitigate these concentrations, ultimately improving breakdown voltage. The simulation results are then compared with the measured performance of the fabricated devices.