ABSTRACT. Silicon carbide is a wide-band-gap semiconductor that possesses specific physical properties which render it a compelling alternative to the existing semiconductor, silicon, which is currently utilised in electronics applications. In essence, the primary function of the SiC technology has been the fabrication of power devices for use in power converters, including those employed in electric vehicles and solar energy production. Silicon carbide (SiC) is known to exist in a variety of crystallographic structures (polytypes), the most prevalent of which is 4H-SiC. However, 6H, 3C and 15R polytypes have also been the focus of past studies. 4H-SiC has been shown to be particularly well-suited for use in power devices., due to its superior isotropy of physical parameters, such as carrier mobility and impact ionisation coefficients, when compared to other polytypes. As a consequence, 4H-SiC is currently employed in the large-scale manufacture of power devices. The mass market has resulted in the establishment of a significant industry dedicated to the production of SiC wafers. This has precipitated a rapid increase in the diameters of the wafers, concomitant with a strong decrease in the initial material costs. These factors, in conjunction with reliability concerns, have historically impeded the rapid incorporation of SiC in electronic products.

Consequently, 4H-SiC is used to produce power diodes and MOSFETs, which are designed for fast switching and low losses performances. However, a novel power application, the Solid State Breakers, is garnering interest and has the potential to represent the next significant market for SiC. In this particular instance, the approach to power device design optimisation is distinct, and JFET architectures are back as potential solution. On the other hand, a novel 800V HVDC distribution standard for data center is another market which could boost the use of SiC low and medium voltage devices. Another potential application for SiC in the future is the field of high voltage, with voltages exceeding 6kV. A significant number of applications necessitate these higher voltage power devices; however, these are characterised by substantially diminished volumes, which result to comparatively lower level of interest from the majority of SiC power semiconductor manufacturers to date for such products development. In addition to its applications in power devices, SiC demonstrates properties that render it appealing for other fields of application. We strongly believe that one of these fields, which shows great potential, is that of radiation detectors. The utilisation of such detectors is imperative in the domains of high-energy physics, cutting-edge medical apparatus, fusion energy production, and the exploration of space. These applications, being at the forefront of technological advancement, necessitate the incorporation of high doses detector systems. The 4H-SiC has been adapted for the optimisation of such devices, and the fabrication technology is comparable to that of power devices. Consequently, such devices are able to benefit directly from existing infrastructures and expertise in material and device production. Despite the fact that the corresponding markets are smaller than those of power electronics, the use of existing infrastructures already in place makes this complementary product a good opportunity to extend the offer of SiC semiconductors to electrification of the society. The primary additional requirements for radiation detectors, as compared to existing power products, are thick and low doped epitaxy (< 3e14cm- 2 ), in conjunction with larger area devices. However, these requirements are analogous to those necessary for the development of high voltage power devices.

The development of 4H-SiC technology has also the potential to yield significant benefits in the field of high-temperature electronics. Once more, the market is comparatively small in relation to that of power switching electronics, and reliability concerns are amplified. Furthermore, it is imperative to undertake substantial modifications to both the semiconductor technology and the package technology, unlike the previous radiation detectors case. A number of technological approaches, including bipolar transistors, MESFETs, JFETs and CMOS, have been the subject of studies at low TRL levels. The integration density of these devices remains comparatively low, with a number of thousands of transistors, in contrast to the integration density of silicon. The targeted temperature was principally 500°C, but temperatures of up to 800°C have been demonstrated in the context of brief operating periods. Potential end users are usually stopped by reliability concerns. They also typically ask for complex circuits, like microcontrollers and memories, to fit with their applications. Then, strong development and characterisation efforts are still needed to see such devices used in the industrial products. However, some niche market with strategic and high added value and can be found such as the 350°C SiC diodes developed for solar panels protection in spacecraft for Mercury and Sun exploration. High temperature catalytic gas sensors and Hall have been also developed and produced in small series. Again, cost was a concern but the new panorama regarding SiC wafer cost may change the end user’s certitudes.

In parallel to 4H-SiC, 3C-SiC has been the subject of extensive study in past years. The prospect of using 3C-SiC in sensors and MEMS applications is rendered attractive by the fact that it can be grown by heteroepitaxy on silicon or silicon on insulator (SOI). 3C-SiC, in both its monocrystalline and polycrystalline forms, has been demonstrated to exhibit a higher Young's modulus than silicon. However, it is not piezo-sensitive, which impacts the read-out strategy. Several recent applications have been developed, including cMUT transducers for the sensing of low concentrations of hydrogen, which are to be used in storage sites, and MEMS gas sensors for the monitoring of volcanic activity. Another application field of SiC, either 4H-SiC or 3C-SiC, is the biomedical sensing sector. Silicon carbide has been shown to exhibit a high degree of bio-compatibility, a property it shares with diamond. This property pushed researchers to investigate the integration of SiC biosensors, including multi-electrode arrays (MEAs) employed for cell culture, in conjunction with epitaxial graphene, microneedles for organ impedance and pH monitoring, and FET 3C-SiC nanowires. In this last case, the device is composed of monocrystalline 3C nanowire, polycrystalline SiC for electrodes and amorphous SiC for passivation, thereby using the full range of SiC properties. Beside sensors, the quality of 3C-SiC layers has historically been inadequate for the integration of transistor-based electronics, such as digital ICs or power devices. Consequently; novel approaches to the growth of 3C-SiC should be investigated with a view to achieving equivalent crystalline quality to that of 4H-SiC, if such a result is physically possible. SiC can also be used as a substrate, either for its thermal properties, or for its crystal and CTE match with other semiconductors for hetero-epitaxy. This is particularly true for the growth of Gallium Nitride (GaN), used for RF and power application. Up to now, except for specific high power RF applications, Silicon was preferred to SiC for hetero-epitaxy of GaN in power HEMT fabrication. The main reason was economic, thanks to the lower cost and higher diameter of Si substrates, compared to SiC. With the recent availability of 200mm SiC wafer, and the strong decrease of SiC substrate cost observed in the last 2 years, 200mm SiC substrate could now be considered as competitive for GaN HEMT production, under the assumption that highly resistive substrates can be produced at the cost of standard n doped + SiC substrates. Today, GaN HEMT technology is moving to 300mm Si substrate, but 300mm SiC substrates have been also recently demonstrated by several manufacturers. Then, SiC may remain in the race, all will be about costs. Another application of monocrystaline or polycrystaline SiC substrates is as thermal dissipator for low thermal conductivity semiconductor, for instance Gallium Oxide (Ga O ). 23 We have recently succeed with the transfer of thin layers of Ga O on top of polySiC substrates. We 23 also have identified transfer conditions allowing a vertical current flow between Ga O and SiC, opening 23 the path to vertical power devices. Alternatively, 4H-SiC thin films (few hundreds of nanometers) can be also transferred on Silicon on Insulator (SOI), to be used for waveguides in quantum non-linear photonics applications. The benefit of SiC in this application rely on a wide transparency range and a large non-linearity coefficient. We must also mention that in the past years, SiC substrate was also use for high quality graphene growth. Very impressive values of mobilities were obtained (>100 000 cm /Vs) but no clear applications arisen from this technology. Either the surface roughness, or the need 2 for graphene to be transferred, strongly limited the potential applications range.

Summarizing, the next short-term step for 4H-SiC material and device industry is to target high volumes power markets, like the Solid State Breakers or Data Centers. But other smaller markets will develop, like radiation detectors, since they use similar material and technology as the existing one for power electronics. The rapid progresses in wafer splitting and thin film transfer will also open the way to applications using SiC on Insulator for MEMS or photonics, or offering SiC as optimal substrate in terms of electrical and thermal properties for other semiconductors like GaN and Ga O . Last but not 23 least, quantum electronics is also a potentially relevant application for SiC in the future, in competition with Diamond.

ABSTRACT. Superjunction (SJ) technology allows improved efficiency in power devices when compared to traditionally singly-doped drift regions (Fig. 1a) and has been a staple of Silicon power devices since the early 2000s, e.g. Infineon’s CoolMOS, ST’s MDmesh, and On-Semi’s SuperFET. A superjunction is a charge balanced region of the device which overcomes the tradeoff of the thickness and doping of the drift region, allowing a lower overall specific on resistance (Ron,sp) for a similar specified breakdown voltage (VBD). These SJ regions typically consist of alternating p- and n-doped columns, where charge balance is more effective at higher aspect ratios, meaning narrow column width for deeper drift region thickness for higher voltages (Fig. 1b).[1] Fabrication of superjunction devices is routine for Si using multiepitaxial growth (ME) but remains a challenge for SiC power devices. Diffusion of dopants is an order of magnitude lower in SiC than for Si, making traditional ME commercially unfeasible, then requiring either high energy MeV implantations [2] or many epitaxial cycles [3]. While sidewall implantation methods mitigate the need for dopant diffusion, there are geometrical limitations.[4] Trench filling epitaxy (TFE), where trenches are etched and refilled by CVD, has so far been the most promising approach (Fig. 2). However, a better understanding of the processes involved in TFE is required to: a) achieve high aspect ratio trench filling and b) make the process adaptable to changing device designs. In this work, we examine how trench structure, annealing, epitaxy conditions and crystallographic orientation affects trench filling behavior as the start to developing a set of process design tools that can aid the realization of SiC superjunction devices (Fig. 3).[5, 6]

All processing was carried out on n+ 4H-SiC substrates off-cut by 4° in the [11-20] direction, which were coated with a 500 nm protective oxide before use. Trenches were etched by ICP-RIE trough a Ni etch mask. Both annealing and trench epitaxy experiments were conducted within an LPE ACiS M8 RP-CVD reactor at 1550 °C and 100 mBar chamber pressure. Samples are characterized by SEM, TEM, (c-)AFM, Raman, and XRD techniques.

Through control of ICP-RIE parameters and annealing conditions, a range of trench profiles with systematic variation in depth, width, sidewall angle and corner shape were produced. The effect of each of these features on trench filling with varied Cl:Si ratios is examined by mapping doping markers throughout the growth process. We report fast and voidless trench filling by optimization of the profile and Cl:Si ratio in tandem, which is governed by control of the growth rate and direction on each trench facet. Corner facets are introduced in a controlled manner by H2 etching and improve the end surface topography of the epilayer. An optimum Cl:Si ratio is also found to improve misalignment tolerance of the trench direction to the [11-20] substrate direction, whereby the epilayer growth direction remains close to vertical even at ±1.5° trench misalignment. Importantly, the effect of trench direction at large angle misalignments is also investigated. Epitaxy on trenches aligned to the [-1100] direction show that there is a separation of conformal “epitaxy” and step flow epitaxy resulting in unique growth at the trench tops, demonstrating the importance of trench direction. Substrate misalignment also shows an effect on doping incorporation, where small misalignments can cause material growth on different facets to exhibit differences in electrical conductance. The results presented herein provide a comprehensive materials analysis of SiC refill epitaxy as a toolkit for the fabrication of SiC superjunction devices.

[1] F. Udrea, et al, IEEE Trans. Electron Devices, 64, 713-727 (2017). [2] R. Ghandi, et al, ICSCRM 2024, Raleigh, USA, (2024) [3] T. Masuda, et al, IEDM 2018, San Francisco, CA, USA, 2018, pp. 8.1.1-8.1.4, [4] G. W C. Baker et al., IEEE Trans. Electron Devices, 69, 1924-1930 (2022). [5] G. Colston, et al, Appl. Phys. Lett., 124, 192102 (2024). [6] K. Turner, et al, Adv. Mater. Interfaces, 11, 2400466 (2024).

ABSTRACT. In this work,the influence of HCl gas on the doping uniformity of 4H-SiC superjunction structure using CVD trench filling epitaxial growth method has been investigated. It is found that, a sufficient HCl flow rate is necessary due to non-uniform doping profiles at low HCl flow rates.

ABSTRACT. Silicon carbide (SiC) has emerged as promising material for high-voltage and high-power electronic device applications such as power transmission, new energy vehicles, and photovoltaics. As the voltage withstand ratings of devices increase, there is a pressing demand for high-quality thick-film SiC epitaxial layers with low defect densities. Critical epitaxial defects that can lead to device failures, such as triangular defects and carrot defects, have been effectively mitigated through advances in epitaxial growth processes[1-3]. Notably, surface defects characterized by small concave pits can induce localized current crowding, resulting in increased leakage current and compromised reliability of devices[4-7]. Extensive research on the control of pit defects predominantly focus on SiC epitaxial layers with 10–12 μm thickness[7-9]. However, the density of pits demonstrates exponential escalation with increasing epitaxial layer thickness. The surface pits remain a significant challenge, particularly in thick SiC epitaxial layers (above 30 μm).

In this research, the distribution and formation mechanisms of surface pits have been investigated by utilizing surface defect detection system and KOH etching technique. Small-sized pits are dominated (>95% of total defects), predominantly originating from threading dislocations (TDs) that disrupt step-flow growth. Given the limited flexibility in tuning drift layer process, this work is dedicated to buffer layer engineering to suppress pits formation. The effects of buffer layer parameters including C/Si ratio, growth rate, and doping condition have been systematically investigated. By implementing gradual doping transition and Si-rich buffer layer structure, the pit defect density is significantly reduced without compromising epitaxial integrity. This approach provides a viable pathway to achieve high-reliability, low-defect SiC epitaxial layers for next-generation power electronics.

In the experiments, the 4H-SiC epilayers were grown by a warm wall planetary chemical vapor deposition (CVD) system. The thickness of all SiC epilayers was ~30 μm. The surface pit morphology and photoluminescence image of the epilayer is shown in Fig. 1. According to statistical results, small pits (10 μm2<area <30 μm2) are predominant. The observed pit defects on the epitaxial surface are strongly correlated to TDs, potentially due to dislocation-induced perturbations in step-flow growth, as revealed by KOH etching. Experiments were subsequently conducted to investigate the influence of buffer layer process parameters on the reduction of surface pits. Existing techniques typically grow buffer layer with fixed doping concentration on SiC substrates. However, the method shows limited effectiveness in suppressing defect propagation and reducing defect density of the epilayer. Herein, the structural design combining gradual doping transition with the growth of Si-rich buffer layer is illustrated in Fig. 2(a). The implementation of non-linearly gradual doping profile can lead to smooth transition, preventing lattice mismatch-induced interfacial defects and stress. Coupled with silicon-rich ambient during buffer layer growth, this approach suppresses the formation of pits, or partially repairs existing defects, leading to shallower defect depths. The growth results of SiC epilayers under different buffer layer processes were compared, as shown in Fig. 2(b). Reducing the C/Si ratio of the buffer layer from 0.65 to 0.55 effectively decreases the surface pits. Subsequent integration of gradual doping process further reduces the density, achieving a 58.8% decrease in pit count compared to standard processes. In addition, the surface roughness of SiC epi-wafer was further analyzed (Fig. 3). This indicates that the modified growth process exhibits no adverse impact on the roughness and quality of the epitaxial wafer.

ABSTRACT. The crystallinity of cubic silicon carbide (3C-SiC) epilayers is improved through the use of a novel wafer bonding and regrowth technique resulting in a reduction of planar defects. The process involves the epitaxial growth of a 3µm thick 3C-SiC seed on silicon (Si) which is polished and bonded to a new handle wafer before the original substrate and defective interface region of the 3C-SiC epilayer is removed. Further epitaxial growth on this Bonded Switchback template results in higher quality 3C-SiC epilayers through the reduction of stacking fault defects and interface voids. The process can be applied to 3C-SiC grown on both on and off-axis substrates and the form of the new handle has no impact on the growth process enabling this technology to be applied to sapphire or hexagonal 4H-SiC substrates, which will overcome the thermal budget limitations of silicon substrates for 3C-SiC heteroepitaxy. The use of Bonded Switchback can improve material quality for applications in Power Electronics as well as see the heterogeneous integration of 3C-SiC into other device structures, potentially leading to a new range of hybrid 3C-SiC/Si devices without the high density of defects observed at the interface between these two materials.

ABSTRACT. Silicon carbide (SiC) is well known for its use as a substrate in power electronics and has emerged as a promising material for quantum and non-linear photonic circuits. Recent studies have demonstrated that crystalline SiC possesses exceptional optical properties, which are essential for the development of photonic integrated circuits (PICs). However, the development of this emerging photonic platform is hampered by the lack of high-quality commercial SiC-on-insulator (SiCOI) substrates. The demonstrations mentioned earlier are based on costly and non-commercial SiCOI prototypes, produced using the bonding and thinning technique. The aim of current developments is to fabricate a SiCOI wafer comprising a thin layer of high-quality monocrystalline SiC (mSiC) transferred onto a lower cost substrate using the Smart Cut™ technology. The quality of the transferred SiC layer was investigated as a function of the ion implantation method and final annealing temperature applied. As a perspective to this work, the fabrication of waveguides on SiCOI substrates using both implantation conditions will allow us to highlight the impact of the new process on device performance.

ABSTRACT. SmartSiC(TM) engineered substrates were introduced in 2021 as an interesting alternative and future competitor of bulk single crystalline SiC substrates for high voltage power electronics. Since then, the SmartSiC(TM) wafers have undergone numerous improvements, touching the base poly-SiC material, the parameters of SmartCut(TM) and bonding processes, as well as the front- and back-side surface preparation. In the present contribution, we demonstrate the influence of SmartSiC(TM) material developments on the quality of the epitaxial layers.

ABSTRACT. Because of its more complex crystal structure and the diatomic lattice, silicon carbide (SiC) intrinsically exhibits a wider range of intrinsic and extrinsic point defects, compared to silicon (Si). Furthermore, the quality of the SiC-oxide interface is often associated with both, performance and long-term reliability issues. Defects in the bulk of SiC have been found to impact the effective carrier density and lifetime, influencing options in device design. However, the silicon carbide power MOSFET (metal oxide semi- conductor field effect transistor) is an already successful commercial device technology that allows higher efficiency and higher power density electronic applications, compared to mature silicon IGBT (insulated gate bipolar transistor) technology[1]. While the experimental investigation of point defects is often primarily targeted using simplified test structures, performance and reliability of power MOSFETs is determined using fully processed devices. Both research domains, so far, have benefited from each other, but a clear correlation of point defect parameters and their actual impact on device performance and long-term reliability is difficult to obtain. Apart from testing being performed in different maturity states of the devices, also the character- ization techniques vastly differ. Three main points will be discussed in this contribution: i) the time and frequency-dependency of the charge carrier trapping mechanisms in the different measurement tech- niques, ii) the location of the probing volume, and iii) the actual state of the accumulation of defects. MOS-interfaces allow probing electronic defect states at the oxide-semiconductor interface by ana- lyzing their response to an ac signal over a broad frequency-, bias- and temperature-range, for exam- ple by employing the conductance method[2]. The conductance method is a well-known characteriza- tion method for MOS capacitors but has not been applied to power MOSFETs directly. However, the temperature-, frequency-, and voltage-dependent behavior of the gate resistance Rgg(Vgs,f,T) of SiC power MOSFETs in a low frequency range has been shown to enable an ac-probing of defect states at the SiC-oxide interface also in fully processed devices[3, 4]. Implementing the defect information as extracted by high-low capacitance-voltage (CV) characteri- zation, constant capacitance deep level spectroscopy (CC-DLTS), and the conductance method for SiC MOS capacitors directly into the technology computer-aided design (TCAD) CV simulations using the Shockley-Read-Hall (SRH) trap model, is not always sufficient for describing the dynamics associated to the underlying defects[5, 6]. Finally, testing of fully processed devices often requires end-of-life testing, leading to destructive fail- ure. However, considering the acceleration factors of the respective testing procedure, failure in applica- tion may occur differently. Adjusting test parameters to intermediate stress levels allows the evaluation of defect-related reliability issues[7]. For all three of the challenges discussed in linking the impact of point defects to device performance and reliability, the domain boundaries and the suggestions to overcome them will be presented.

[1] M. Stecca et al, IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 10, no. 4, pp. 4275-4289 (2022). [2] P. Kumar et al., Proc. of IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, pp. 1-6 (2024). [3] S. Race et al., IEEE Transactions on Electron Devices, vol. 71, no. 12, pp. 7709-7715 (2024). [4] S. Race et al., Proc. of 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Hong Kong, pp. 9-12 (2023). [5] H. G. Medeiros et al., Proc. of IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, pp. 01-06 (2025). [6] M. Nagel et al., Proc. of International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM Europe), Nuernberg, Germany, pp. 82-89 (2025). [7] R. Kupper et al., International Conference on Silicon Carbide and Related Materials (ICSCRM), Raleigh NC, USA (2024).

ABSTRACT. An accurate characterization of deep levels in SiC is essential for both power and quantum device applications. Deep Level Transient Spectroscopy (DLTS) has been the principal technique for this purpose. However, it is difficult to characterize deep levels with similar emission time constants, i.e., those that are energetically close. While Laplace DLTS (LDLTS) offers enhanced time-constant resolution, it requires a high signal‑to‑noise ratio (SNR) to achieve reliable deconvolution , which is often impractical in actual measurements. In this study, we propose a novel capacitance transient analysis based on Bayesian inference. The method was demonstrated to reduce the minimum SNR required to separate multiple deep levels whose emission time constants are close. Moreover, the method was applied to characterize deep levels in electron-irradiated 4H-SiC, and multiple energetically close deep levels were individually detected, which could not be resolved in conventional methods.

ABSTRACT. The effective minority charge carrier lifetime tau is a crucial parameter in power semiconductors that is closely tied to the device’s switching speed and power dissipation. Therefore, the parameter is fundamental for device performance. Electrical reverse recovery current or open circuit voltage decay measurements are well established to extract the effective lifetime of an entire device. These techniques are accessible and quick, but only provide very limited information needed for the development for future generations of power devices. We propose a method that can be used to measure and spatially resolve tau throughout the device’s cross section using a chopped electron beam of a scanning electron microscope (SEM). When a semiconductor is illuminated by the electron beam, electron hole pairs are created. In the depletion layer or in close proximity of the pn-junction, these charges are separated and induce an external current, known as electron-beam induced current (EBIC). A simple yet rough estimate of tau in the material can already be made from a fit of the exponential decay of the steady-state EBIC I_EBIC being proportional to exp(-x/L), as depicted in figure 1c. L = sqrt(D•tau) is the diffusion length and D is the diffusion constant, x being the distance from the edge depletion region. This estimate however is erroneous, since it assumes D to be constant throughout the sample and averages the exponential decay over position, thus losing desired spatial information. We employ a chopped scanning electron beam over a frequency range to resolve the effective lifetime of minority carriers spatially in both n-doped and p-doped regions of a diode. The lifetime may be computed as follows: At any specific point with sufficient EBIC or phase signal, the current exhibits a dependence on the chopping frequency. The physics of this behavior can be described by solving the time dependent continuity equation and considering an additional frequency dependent component exp(i•omega•tau), omega being the angular frequency and t being the time, in the solution [1]:

I_EBIC(x, omega, tau) = I_0•exp(−x/L(a+ib)) with a, b =1/sqrt(2)•sqrt(±1 + sqrt(1 + omega^2•tau^2))

When increasing the chopping frequency of the electron beam, I_EBIC gradually decreases (lowpass behavior) while the phase increases. Subsequently, tau is computed from the knee frequency f_knee=1/2*pi*tau of the current or phase [2-4]. By sweeping over a range of frequencies at every point of a planar device or cross section, the effective lifetime can potentially be determined and mapped. In our experiments, we use a SiC pn-junction with around 3•10^17/cm^3 Al-doping concentration on the p-side and 10^16/cm^3 N-doping in the epitaxial layer with a contact pad and back metallization (see schematic in figure 1a). We measure tau at 300 K close to the depletion region in p-type SiC. As seen in figure 2, tau decreases towards the depletion region because of increased recombination in very close proximity to the depletion region, yielding shorter diffusion lengths [5] and thus shorter lifetimes. This effective lifetime measurement compares well to similar techniques such as time-resolved photoluminescence [6], backing the credibility of our results. While this method is not fully automated and developed yet, this method will push the boundaries of SiC devices in the near future.

[1] McKelvey, J. P. (1966). Solid state and semiconductor physics. Harper & Row. 439-441. [2] Fuyuki, T., & Matsunami, H. (1981). Journal of Applied Physics, 52(5), 3428-3432. [3] Honma, N., et. al. (1986). Japanese journal of applied physics, 25(5R), 743. [4] Pietzsch, J. (1982). Solid-State Electronics, 25(4), 295-304. [5] Marcelot, O., & Magnan, P. (2019). Ultramicroscopy, 197, 23-27. [6] Tawara, T., et. al. (2004). Materials Science Forum, 457, 565-568.

ABSTRACT. In this work, deep levels across the entire 4H-SiC bandgap are investigated by combining deep-level transient spectroscopy (DLTS) and minority carrier transient spectroscopy (MCTS) on n-type and p-type as-grown samples, as well as a set of samples exhibiting point defects introduced by reactive ion etching (RIE). We can correlate electron traps detected by n-type DLTS signals ON1 (EC – 0.84 eV), ON2 (EC – 1.02 eV) and EH6/7 (EC – 1.41 eV) with electron traps detected by p-type MCTS signals ER2 (EC – 0.89 eV), ER3 (EC – 1.09 eV) and ER4 (EC – 1.59 eV). Additionally, MCTS reveals a new electron trap, ER1 (EC – 0.56 eV), which is not observed in DLTS. Interestingly, a hole trap, detected by p-type DLTS spectra HK0 (EV + 0.78 eV), overlaps with an electron trap detected by n-type MCTS signal, a phenomenon currently under investigation. This combined analysis aims to provide a more comprehensive understanding of electrically active defects in 4H-SiC.

ABSTRACT. Neutron irradiation in SiC power devices leads to both nuclear reactions and lattice damage. While detrimental for device reliability, neutron exposure is also exploited in techniques such as neutron transmutation doping (NTD), which relies thermal neutrons due to their higher capture cross-section. Understanding neutron-induced defect formation and its impact on carrier concentration and lifetime is essential for improving radiation hardness and evaluating the feasibility of NTD in SiC. In this study, we investigate the energy-dependent damage mechanisms in 4H-SiC by irradiating samples at two neutron facilities with distinct spectra: one dominated by thermal neutrons, the other with a broad distribution from thermal to fast energies. Defects were analyzed using photoluminescence, Raman spectroscopy, Schottky IVs, deep level transient spectroscopy (DLTS), and minority carrier transient spectroscopy (MCTS). Electrically active point defects and photoluminescence signatures of extended defects show clear differences in defect formation between thermal and fast neutron exposures.

ABSTRACT. Silicon carbide (SiC) is an exceptional material for high-power, high-temperature, high-frequency, and high-radiation applications [1]. Unipolar 4H-SiC devices, including Schottky barrier diodes (SBDs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), are already commercially available and widely adopted [2]. In contrast, bipolar devices like P-intrinsic-N (PiN) diodes leverage conductivity modulation via electron-hole conduction, achieving lower on-resistance than unipolar devices [3]. For power devices, carrier lifetime is a critical performance determinant. Especially, in 4H-SiC with a highly doped buffer layer, Auger recombination becomes more significant during the higher current condition [2]. While most studies report the Auger recombination coefficient (C) for low-doped n-type 4H-SiC under high injection, Tanaka’s group investigated p-type material [3,4]. However, data for highly doped n-type 4H-SiC under high injection remain unreported. Here, we calculate C using heavily N-doped 4H-SiC to address this gap. The sample evaluated in this research was an epitaxial layer with the N doping concentration (N_0) of 5 × 1018 cm−3 grown on the commercially standard n-type 4H-SiC substrate. The thickness of the epi layer was 10 μm. Time-resolved photoluminescence method (TR-PL) was used to characterize the carrier recombination. A yttrium aluminum garnet (YAG) laser with a wavelength of 266 nm and a spot size of approximately 0.13 cm–2 was used as the excitation light source. Sample temperatures were controlled within the range of 298–573 K using a hot plate. Figure 1 shows the excited carrier concentration (∆N) dependence of TR-PL decay curves at 298 and 573 K. As shown in both Fig. 1(a) and (b), as the excited carrier concentration increased, the decays became faster. This indicates that the carrier recombination is dominated by Auger recombination under the high injection level. Moreover, for each excited carrier concentration, the decay at 573 K was faster than that at 298 K. Generally, Auger combination velocity can be given as: █(R_Auger=C_n n^2 p+C_p np^2 "," )"(1)" where n (p) is electron (hole) concentration, C_n (C_p) is Auger recombination coefficient for the electron (hole)-dominated process, respectively. In this research, the highly doped sample whose doping density is almost the same as the highest excited carrier concentration was used, thus, n=N_0+∆N and p=∆N. Moreover, the hole concentration is much smaller than the electron concentration. Therefore, the probability of hole-hole-electron (h-e-e) transitions became relatively low. Considering all, the Auger lifetime, τ_Auger, can be obtained only by assuming that C_p≅0 using eq. (1) as: █(τ_Auger=1/(C〖(N_0+∆N)〗^2 ) "," )"(2)" To evaluate the auger recombination coefficient, since the Auger recombination is presented at the initial decay, we extracted the slopes, τ_initial, obtained from the peak to 10 ns of the decay curves. However, the radiative recombination was contained in τ_initial, we calculated Auger lifetimes using the following equation with the reported B of 1.0 × 10−12 cm3/s for the highest excited carrier concentration at each temperature, as shown in Fig. 2 [4]. █(1/τ_Auger =1/τ_initial -B(N_0+∆N)"," )"(3)" Figure 3 shows the temperature dependence of calculated C using eqs. (2) and (3). As shown in this figure, at room temperature, C = 3.7 × 10−31 cm6/s. Compared to the reported C of 7 × 10−31 cm6/s at N_0+∆N~〖"10" 〗^"18" cm−3 and 0.8 × 10−31 cm6/s at N_0+∆N~〖"10" 〗^"20" cm−3 by Ščajev’s group, ours is located in this range at N_0+∆N~〖"10" 〗^"19" cm−3 [5]. Therefore, the screening of the carrier–phonon interaction by free carriers will attribute to the decrease in C [6]. Furthermore, C increases with increasing temperature. The dashed line shows the fitting curve with C="1.6 × " 〖"10" 〗^"-33" T^"0.95" cm6/s. Generally, for indirect bandgap semiconductors such as SiC, Auger recombination under the conditions of energy (E) and momentum (k) conservation. However, as the temperature increases, phonon scattering becomes more significant. This leads to a relaxation of the momentum conservation, allowing slight deviations in k and consequently promoting Auger recombination. Ščajev’s group reported that the Auger recombination coefficient was independent of temperature [6]. In contrast, Galeckas’s group observed that the Auger recombination coefficient decreased with increasing temperature [1]. Therefore, the observed increase of the Auger coefficient with temperature in our results can be naturally understood considering the effects of phonon interactions.

ABSTRACT. Local electrical properties of a 4H-SiC(0001) 4°off macrostepped surface, obtained after liquid Si melting in a SiC/Si/SiC sandwich configuration, are investigated by Atomic Force Microscopy (AFM) in both DC and RF modes. In the same sample step risers and terraces properties are probed, analyzed and compared. The AFM-DC conductive mode, Scanning Spreading Resistance (SSRM) mode reveals homogeneous conductivity on the wide terraces of the 4H-SiC(0001) macrosteps and a noisier signal for the unreacted area with step risers. In addition, the AFM-RF scanning Microwave Impedance Microscopy (sMIM) mapping shows the lower conductivity of the unreacted areas than the terraces of the macrosteps. AFM results demonstrate that in both DC and RF the negative impact in the local electrical properties of the defect states at these risers of the 4H-SiC(0001).

ABSTRACT. 4H-SiC is increasingly recognized as a critical semiconductor material for next-generation power electronics due to its superior electrical and thermal properties [1]. As device integration and performance demands continue to rise, surface cleanliness has become essential for achieving high-quality and high-yield epitaxial layers on 4H-SiC substrates. Chemical mechanical polishing (CMP), cleaning, surface preparation, and epitaxial growth processes play crucial roles in the overall manufacturing of 4H-SiC substrates [2–4]. The RCA cleaning process, commonly used in Si semiconductor manufacturing, has been adapted for 4H-SiC to remove particles and perform surface preparation. However, due to the strong Si–C bonds in 4H-SiC, the material exhibits a chemically stable surface and shows a particle removal behavior different from that of Si. There has been insufficient study on the particle removal mechanism specific to 4H-SiC compared to Si. To effectively remove particles from the 4H-SiC surface and improve the quality of epitaxial layer growth, a deeper understanding of the cleaning mechanism on 4H-SiC is required. In this study, we investigated the adhesion and removal behavior of contaminant particles on the surface of 4H-SiC in various cleaning solutions, in comparison with Si, and explored the particle removal mechanism to enhance cleaning efficiency. 4H-SiC and Si wafers were used to investigate the wet cleaning mechanism through a comparison of their surface chemistry and particle adhesion behavior to understand the cleaning mechanism of 4H-SiC. Ammonium hydroxide-hydrogen peroxide-mixture (APM), sulfuric acid-hydrogen peroxide-mixture (SPM), diluted hydrofluoric acid (DHF), H2O2, and potassium permanganate (KMnO₄), which is a representative oxidizer for SiC were used. These cleaning solutions were applied to both 4H-SiC and Si substrates to compare oxidation and etching behavior and the resulting surface property transitions. Surface wettability was evaluated using the contact angle analyzer (Phoenix 300, SEO, Korea). Atomic force microscopy (AFM, NX20, Park Systems, Korea) was used to characterize the change in surface physical and chemical properties such as surface morphology by measuring surface roughness, and surface adhesion properties analyzing force–distance (F/D) curves between silica particle and 4H-SiC. X-ray photoelectron spectroscopy (XPS) (K-alpha plus, Thermo Scientific, USA) was employed to analyze surface chemical composition and oxidation states, with particular focus on variations in the O1s spectra. Figure 1 summarizes the results of surface chemical properties, including changes in roughness and contact angle, according to the oxidants and cleaning solutions after treatment. The results revealed that 4H-SiC surfaces showed limited surface oxidation and minimal hydrophilic conversion compared to Si. While Si underwent oxidation in oxidizing agents and subsequent etching by HF solution, 4H-SiC exhibited surface reactions resulting in a highly hydrophilic surface upon SPM treatment. These differences were confirmed through XPS as shown in Figure 2, which presents the O 1s spectra of 4H-SiC surfaces after treatment with DHF, SPM, and KMnO₄. According to the XPS results, both SPM and KMnO₄ treatments increased surface oxygen content and it indicates that –OH molecules adsorbed on the 4H-SiC surface. However, the degree of –OH uptake varied by oxidant, providing insight into differences in chemical reactivity. In addition, the surface chemical properties of 4H-SiC, which differ from those of Si, influence particle contamination and removal behavior. Although electrostatic interactions also contribute to particle adhesion on 4H-SiC, the overall adhesion mechanism and removal behavior differ from those on Si. However, while particle removal on Si is facilitated by etching, lift-off, and electrostatic repulsion mechanisms, such processes are absent on 4H-SiC due to its chemical inertness. Furthermore, the lack of sufficient electrostatic repulsion on the 4H-SiC surface hinders effective particle detachment, making it necessary to adopt cleaning methods that apply physical forces. In conclusion, the chemically stable nature of 4H-SiC surfaces results in a fundamentally different wet cleaning mechanism compared to Si. The reduced chemical reactivity and predominance of physical adsorption suggest that particle removal from SiC is driven more by mechanical forces than by chemical interactions. These results indicate that achieving effective particle removal and high-quality surface finishing of wide bandgap 4H-SiC wafers necessitates the development of customized cleaning processes, in which physical forces play a dominant role over traditional Si-based chemical cleaning approaches.

ABSTRACT. Previous studies have shown that charge pumping electrically-detected magnetic resonance (CP-EDMR) is a powerful technique for detecting paramagnetic point defects at the SiC-SiO2 interface of 4H-SiC MOSFETs [1-3]. In charge pumping, a spin-dependent recombination current, i.e., a charge pumping current (Icp) is generated from the source and drain (shorted together) to the body of the device by applying an oscillating voltage to the gate [4-5]. Consequently, point defects at the interface are alternatingly filled with holes and electrons as the gate voltage oscillates. A spin-dependent recombination current is then generated and detected through the body contact, when a trapped hole recombines with an electron at the interface, or vice versa. Furthermore, by changing the rise (tr) or fall (tf) times of the gate pulse, it is possible to stimulate hole and electron emission respectively, as first demonstrated by Groeseneken et al. [5]. This will be further exploited in this work.

ABSTRACT. Ion implantation of noble gases and hydrogen into silicon carbide (SiC) has gained growing attention due to its wide-ranging technological applications. Noble gas species such as helium, neon, or argon are used to engineer lattice defects, simulate radiation damage, form nano-bubbles and cavities, and modify surface stress profiles. Hydrogen plays an equally important role, especially in the passivation of electrically active defects at SiO₂/SiC interfaces and in controlled delamination processes such as smart-cut techniques. The accurate depth profiling of these elements is critical for understanding the defect formation mechanisms and optimizing process conditions for power electronics and nuclear-grade materials.

However, SIMS measurements of noble gases in SiC remain highly challenging due to their low ionization probability and the material’s strong resistance to ion sputtering. A partial solution, developed in the early 1990s, involved the use of CsX⁺ cluster ions, which significantly improved noble gas detection in silicon and metals [1]. This method, however, is largely ineffective for SiC, where the extremely low sputter yield limits secondary ion generation. As a result, even with CsX⁺ enhancement, detection limits rarely improve beyond 10²⁰ atoms·cm⁻³. This has discouraged research in this area, and there are virtually no published SIMS depth profiles of noble gases in SiC, highlighting the unresolved analytical difficulties.

To address the limitations of noble gas detection in SiC, a three-step surface conditioning procedure was established[2]. The process begins with high-energy Cs⁺ bombardment, which cleans and activates the near-surface region. This is followed by ultra-low energy Cs⁺ deposition, enriching the sample surface with cesium without inducing significant sputtering. In the final step, intermediate-energy sputtering is applied to gently mix the surface layer, promoting the formation of CsX⁺ cluster ions under steady-state conditions. This combined approach enhances ionization efficiency and stabilizes the signal during acquisition. When applied to noble gas-implanted SiC, it enabled a nearly two orders of magnitude improvement in detection limits, reducing them to the low 10¹⁸ atoms·cm⁻³ range, while preserving sufficient depth resolution for profiling thin structures. Figure 1 presents depth profiling results for silicon carbide implanted with helium, neon, and argon. Solid lines correspond to measurements performed using the surface engineering method, while dotted lines represent conventional SIMS measurements under standard conditions, clearly illustrating the substantial gain in detection sensitivity.

In the case of hydrogen, an additional step is required due to the high background signal originating from residual gases in the analysis chamber. To suppress this background and improve detection limits, titanium pre-sputtering is employed prior to measurement[3]. This process deposits a thin Ti layer on the immersion lens and surrounding surfaces, effectively acting as a getter for hydrogen and water vapor. When combined with the cesium-based surface engineering protocol, this approach enables reliable hydrogen detection in SiC at concentrations below 1 × 10¹⁷ atoms·cm⁻³.

Together, these combined approaches enable precise and quantitative detection of inert and light implanted species in one of the most challenging materials for SIMS, opening new avenues in process control, defect engineering, and device innovation.

Acknowledgements: This work was supported by the National Centre for Research and Development, project No. LIDER/8/0055/L-12/20/NCBR/2021.

[1] H. Gnaser, H. Oechsner, Surf. Interface Anal. 17, 646 (1991) [2] P.P. Michałowski, Measurement, in review (2025). [3] P.P. Michałowski, J. Anal. At. Spectrom. 35, 1047 (2020).

ABSTRACT. Silicon carbide (SiC) is a wide bandgap semiconductor material with exceptional properties for a variety of applications, particularly for high-voltage devices. SiC has proven to outperform traditional silicon (Si) based power electronic devices. In this work the OBIC (Optical Beam Induced Current) technique will be applied to examine the electric field distribution inside the structure of SiC bipolar diodes with different epitaxial layer thickness. To create electron-hole pairs inside the semiconductor, a 325 nm UV laser beam is used. The focused laser beam was moved on the surface of the device with steps of 2 microns. We have tested bipolar diodes with both 10 microns epilayer thickness and 100 epilayer thickness. The OBIC is measured by Keithley 2450 SMU (Source Measurement Unit) and is then mapped in 2-directions (X and Y) or just along one line in a chosen direction. The intensity of the photo-generated current is linked to the intensity of the average electric field and therefore to the reverse voltage applied to the detector under test. We obtained several OBICs by re-scanning the same location at different reverse voltages (up to 200 V) applied to the same SiC diode. The increased electric field caused by an increase in reverse voltage results in an increase of the OBIC at the same location. Synopsis TCAD simulations of the electric field are also reported for both diodes. In these simulations it is possible to observe the increase of the electric field at the edge of the devices that is observed by the OBIC measurements. In conclusion, OBIC technique aids in optimizing device design and improving overall performance.

ABSTRACT. Key material properties, such as carrier mobility and drift velocity, are fundamental for predicting device characteristics and gaining insight into the associated physical phenomena. In SiC, while the low-field mobility has been intensively studied, reports on high-field drift velocity are still very limited, especially on its temperature dependence. In this study, the temperature dependence of the drift velocities for electrons and holes parallel and perpendicular to the c-axis were characterized over a wide electric field range (1–200 kV/cm) by a conductance method using SiC(11"2" ̅0) samples.

ABSTRACT. Critical defects in 4H-silicon carbide (SiC) epitaxial layers such as basal plane dislocations (BPDs) and stacking faults (SFs) can cause device failure [1]. In 4H-SiC wafers off-cut by 4° from [0001] toward [112 ̅0] it has been observed that BPD propagation from the substrate to the epi-layer only occurs when two requirements are met. First, a BPD’s Burgers vector b is collinear to the step-flow direction and second, the line direction u is within 10° of the step-flow direction [2,3]. However, in this work, it was observed that a BPD with b not collinear to the step-flow direction ([112 ̅0]) propagates from the substrate into the epi-layer forming a SF during growth (not carrier injection.) Direct defect imaging using transmission x-ray topography (XRT), depth resolved section XRT, and ultraviolet photoluminescence (UVPL), including spectral UVPL, was used to confirm the observations and analyze the formation and propagation mechanisms of the BPD and SFs. For this work, commercially grown 150 mm diameter 4H-SiC wafers with 60 m thick epi-layers were used. From whole-wafer XRT and UVPL imaging the overall defect density was found to be extremely low with over 99.9% BPD to threading edge dislocation (TED) conversion, 9 fall down inclusions, and 30 in-grown SFs. Fig. 1 shows three different images of the region with the novel defect using XRT. Using contrast analysis, it can be determined that b is not [112 ̅0] or [1 ̅1 ̅20], as the BPD is visible in all images. Additionally, the highlighted dot-like contrast in Figs. 1(b) and 1(c) indicates that there is a threading mixed dislocation (TMD) present where the BPD propagates from the substrate to epi-layer. The novel propagation mechanism of the non-step-flow BPD into the epi-layer occurs from a complex interaction of the BPD with the TMD at the substrate-epi interface, which locally creates steps in multiple directions, and allows the BPD to have a line direction mostly parallel to a rotated step direction. This makes it energetically favorable for the BPD to propagate rather than convert to a TED. Fig. 2 shows an overview of such an interaction. Details of this novel interaction mechanism, including simulations of the defect kinetics, will be presented. Spectral UVPL using various band pass filters was performed to reveal the nature of SF in the epi-layer. The chart in Fig. 3 suggest that both a single Shockley and Extrinsic Frank SF are present in the region of interest [4,5]. The Shockley fault arises from the BPD and the Frank fault is due to the deflection of the TMD on to the basal plane [6]. Successive UVPL imaging with prolonged UV stressing to generate carriers was performed, which causes the expansion of Shockley SFs via the recombination enhanced dislocation glide mechanism [7]. Figs. 4(b) and 4(c) show that four different Shockley faults are expanding in the epitaxial layer, which arise from the propagation of BPD from the substrate. Further details the propagation mechanics of this defect will be presented. Understanding of these interactions can provide insight regarding their origin and potential mitigation strategies to ensure high voltage device robustness.

[1] J. P. Bergman et.al., Materials Science Forum, vol. 353–356, July 2001 [2] H. Tsuchida et.al., physica status solidi (b), vol. 246, no. 7, pp. 1553–1568, 2009 [3] Z. Zhang et.al., Applied Physics Letters, vol. 87, no. 16, p. 161917, Oct. 2005 [4] S. G. Sridhara et al., Applied Physics Letters, vol. 79, p. 3944, Dec. 2001 [5] H. Tsuchida et al., Journal of Crystal Growth, vol. 310, no. 4, pp. 757–765, Feb. 2008 [6] M. Dudley et al., Applied Physics Letters, vol. 98, no. 23, p. 232110, June 2011 [7] A. Galeckas et al., Applied Physics Letters, vol. 81, no. 5, pp. 883–885, July 2002

ABSTRACT. Over the last 40 years since its emergence, Silicon Carbide (SiC) technology has evolved significantly, with SiC Schottky diodes becoming commodities and SiC MOSFETs now standard components found in a variety of power semiconductor applications.

Although it has achieved commercial success, SiC device technology continues to evolve, aiming to compete with its Si and GaN counterparts across the power electronics landscape. SiC Insulated Gate Bipolar Transistors (IGBTs), Thyristors, and Super Junction devices targeting high voltage applications have been demonstrated. Unfortunately, SiC’s expansion to lower voltage applications is more difficult due to high channel resistance of SiC MOSFETs. The search for different solutions has brought us back to the SiC Junction Field Effect Transistor (JFET); the technology that was proposed 15 years ago as an alternative to then immature SiC MOSFET. JFETS are free from mobility degradation and instabilities associated with SiC’s imperfect MOS interface. It allows much smaller conduction losses, especially in 650-750V voltage class where JFETs exhibit the lowest specific on-resistance of any switch technology. Such performance advantages, in addition to low cost, revived interest in JFETs from the world’s leading power device manufacturers and system designers. This paper explores the design aspects of Silicon Carbide Junction Field Effect Transistors, highlighting design approaches, advantages and disadvantages in the context of the application utilization.

Additionally, the paper will discuss SiC JFETs operating as part of the cascode, addressing the associated challenges and potential solutions. The findings aim to identify promising fields of utilization for SiC JFETs, contributing to the advancement of power electronics.

ABSTRACT. We experimentally obtained the Shockley-Read-Hall (SRH) recombination coefficient, surface recombination velocity, and intrinsic carrier density in the SiC epilayer, and then, the simulation model was constructed. The device simulation (TCAD) using the model could effectively reproduce the experimental forward current conduction of the SiC PiN diodes, which were fabricated on various wafers.

ABSTRACT. Silicon carbide (SiC) power devices are widely used in fast-switching applications, balancing switching speed and on-state resistance. However, some applications prioritize thermal management, especially where devices operate continuously at nominal current -such as protection diodes in photovoltaic strings or Solid-State Circuit Breakers (SSCBs). In such cases, proper design of device area, nominal current density, and cooling is critical, particularly where the cooling system must be minimized. SiC’s superior thermal conductivity and lower on-state voltage enable higher current densities than silicon, typically 400–500 A/cm² for devices rated below 1200 V. This work investigates the thermal response of SiC diodes under current stress and varying ambient temperatures using an innovative junction temperature extraction technique, focusing on the role of diode structure and voltage class (1200, 1700, 3300 V) in self-heating transients.

ABSTRACT. SiC power devices are crucial in high-power applications like e-vehicle traction-inverters and on-board battery chargers. These applications require stringent electrical and thermomechanical reliability requirements, facing harsh environment in terms of temperature and humidity. To improve their robustness against corrosion and moisture, silicon nitride (SiN) and silicon dioxide (SiO2) are commonly used as passivation layers to protect the device. However, SiN is a hard and brittle compound. When it is submitted to thermal budget, SiN must withstand high thermo-mechanical stress due to the mismatch among the coefficients of thermal expansion (CTE) of device’s component. This might lead to cracks in the SiN, that can propagate into the interlayer dielectrics disrupting the electrical isolation and enhancing moisture infiltration and corrosion due to the high electric field [1-4]. The objective of this study is to compare, through thermo-mechanical finite element analysis (FEA) and electrical TCAD simulation, various passivation stacks to optimize thermo-mechanical stress and electrical robustness of SiC power MOSFET devices [5-6]. The study is concerning the region around the gate metal corner. As shown in Figure 1, the profile geometry of the metal in such area might induce cracks in SiN due to high tensile stress in the corner region. Smoothing such region by proper design can improve device robustness. For this purpose, we simulate SiN thicknesses values ranging from 1 to 0.3 µm, in a double passivation (SiN + Polyimide) scheme. The geometry of the region around the gate metal was simulated as a simplified 3D die strip. FEA estimates the stress induced on SiN by chip manufacturing. In particular, the SiN deposition was performed by PECVD at 400 °C and material characteristics depend on the process chemistry of SiH4, NH3 and N2 gases mix ratio. The final SiN stoichiometry is critically dependent on SiH4 / NH3 ratio (0.12 – 0.24 in our case), leading to a nitrogen- or silicon-rich material, respectively. Combining warpage measurement and Stoney equation for thin film, we estimate SiN intrinsic stress equal to – 152 MPa. The second component is the cooling down from 400 to 25 °C, which is driven by CTE mismatch. In our model, thermal and intrinsic stress are both accounted, thermal component will be prevalent. We reproduce the metal hardening with Chaboche model to avoid stress overestimation in SiN layer [5-6]. Considering the SiN is a brittle material, we use the maximum principal stress criterion to evaluate SiN layer robustness. As shown in Fig. 2, by decreasing SiN thickness, room temperature stress is increased (+571 and +1062 MPa at 1 and 0.3 µm). Such effect is explained by the increased stiffness, which limits the stress induced by metal, and by smoother fillet, which reduces the notch effect at the top corner. Moreover, the introduction of SiN smooths the electric field peaks at the corner gate metal, which is reduced by a threefold factor when the SiN thickness goes from 0.3 to 1 µm, as shown in Fig. 3a-c. Additional modeling is done to study the introduction of a further SiO2 layer between the gate metal and the SiN layer. The FEA models show that this configuration, called triple passivation, significantly reduces the maximum principal stress in the SiN layer from ~570 MPa to ~200 MPa. For such passivation scheme, the optimum condition on the mechanical stress reduction is found for a SiN thickness ~ 1 µm. Triple passivation introduction is also helpful for further reducing the E-field at the metal - passivation interface. Such passivation scheme is therefore expected to give benefits in enhancing the overall robustness and lifetime of SiC power devices, especially under harsh humidity and bias conditions.

ABSTRACT. Application-driven device design becomes crucial for a wide acceptance of SiC power MOSFET technology in power electronics, and the device’s susceptibility to oscillations, when connected in parallel configuration, is a key aspect for multi-chip SiC power MOSFET power modules design. During parallel operation, oscillations can occur due to uneven current distribution between parallel devices during switching transients originating from layout asymmetries, device performance mismatch, and/or nonuniform temperature distribution, ultimately leading to instability of the operation. In comparison to two SiC power MOSFET dies in parallel, the oscillations between 8 dies are significantly more complex, and different transfer functions are needed to evaluate the oscillations at turn-on and -off. Three device designs with different pitch size, channel length (Lch), channel implantation dose (Kch), JFET width (WJFET), and oxide quality (fixed charge concentration Qfix) were selected, and compared in terms of device performance metrics, i.e., conduction, switching, and oscillation susceptibility in an 8-die parallel configuration. In the final contribution, both turn-on and -off oscillations will be associated with Cgd, Cgs, Cds, gm(gs,ac), and gm(ds,ac), and the corresponding device design parameters, followed by a more detailed analysis to identify key device performance trade-offs and critical design parameters for multi-chip power modules, aiming to derive a device figure-of-merit for parallel operation of SiC power MOSFETs.

ABSTRACT. Bi-directional power devices, capable of conducting and blocking current in both forward and reverse directions, are essential building blocks for emerging applications such as current source inverters (CSIs) and matrix converters. Various approaches to implementing bi-directional power devices have been reported, including package-level integration and monolithic two-chip integration. Recently, our research group successfully demonstrated a cell-to-cell integrated SiC lateral bi-directional power MOSFET (L-BiD-MOSFET). Cell-to-cell integration enables exploration of novel device architectures while offering significant area savings. To further enhance the blocking performance of the cell-to-cell integrated lateral bi-directional devices, it is necessary to examine the layout design in conjunction with 3D TCAD simulations to analyze electric field concentrations. In this work, we correlate the measurement results of fabricated L-BiD-MOSFETs with TCAD simulations. Using 3D TCAD, we identify electric field concentration at the finger edge and propose an extended P-top design to mitigate these concentrations, ultimately improving breakdown voltage. The simulation results are then compared with the measured performance of the fabricated devices.

ABSTRACT. This study successfully achieved the growth of heavily nitrogen-doped polycrystalline silicon carbide (poly-SiC) crystals via physical vapor transport (PVT) method. Notably, poly-SiC crystals with ultra-low resistivity of 12 mΩ·cm were obtained through process optimization, demonstrating significant advancement in electrical performance. The systematic investigation focused on three critical parameters - growth temperature, chamber pressure, and post-growth wafer processing - with their synergistic effects on crystal quality comprehensively analyzed through resistivity mapping, phase composition characterization and growth rate quantification. Experimental results revealed two dominant control mechanisms: 1) Growth temperature predominantly governs the resistivity of nitrogen-doped crystals through dopant activation efficiency, and 2) Chamber pressure serves as the primary determinant of crystal growth kinetics. By implementing a specially designed parameter decoupling strategy involving orthogonal experimental arrays and furnace structural modifications, we effectively resolved the complex inter-dependencies among temperature, pressure and raw material.

ABSTRACT. Carbide coated graphite components are indispensable in SiC and GaN epitaxy (epi) reactors due to their unique capability to withstand high temperatures and harsh chemicals. However, state-of-the-art carbide coating still suffers from premature cracking and chemical etching, which reduces the part lifetime while potentially causing defects in the epitaxy film. Such defects include the contamination of the epi layers with carbon and trace elements present in the graphite that get through the cracks or etching. Moreover, exposed graphite is easily corroded in gases such as hydrogen and ammonia, which are present in many epi processes, and release graphite particles detrimental to epi films. Indeed, the need to frequently replace them makes coated graphite components the costliest consumable in epi reactors. We report novel CVD SiC coatings exhibiting both enhanced mechanical and chemical stability. One approach is the use of SiC multilayer architectures as shown in Fig.1. The layers can vary in crystal orientation, porosity, thickness, and Si:C stoichiometry. The architectures can be optimized depending on the application. For example, standard, monolithic SiC coating is prone to pinhole etching in SiC epi reactors where HCl is present [1]. On the other hand, certain multilayer SiC structures can be tuned to mitigate pin-holing as shown in Fig. 2. Mechanically, multilayers could deflect crack propagation from reaching the graphite by having layers with different porosity or crystallinity. One type of SiC layer that shows superior hardness is (111) oriented SiC polycrystalline shown in Fig. 2. Another key requirement of carbide coatings is the ability to make the coating conformal across various steps, recesses, channels, etc., present in the machined graphite parts. For applications in electronics, the use of low temperature and low-pressure CVD coating can greatly enhance the conformality [2]. However, the same approach is impractical for protective coatings of graphite where much thicker coatings are called for. Therefore, we have developed conformal SiC coating of graphite at high temperatures (950 – 1200 ℃) and pressures (1 kPa), where the deposition rate typically exceeds 10 µm/h. We even show superconformal deposition, i.e. faster growth at the bottom of a trench than at the opening, attributable to chlorine-based inhibition chemistry at the trench opening [3]. Our findings in improving the coating conformality of SiC could potentially benefit numerous CVD processes for protective coatings using chlorinated precursors. This would allow uniform coatings deep down in holes for gas foil rotations or pyrometer reading spots, and in recesses in wafer carrier pockets. We also report the development of a new CVD tantalum carbide (TaC) coating of graphite for applications where even SiC coating reaches its limits. In particular, SiC coating cannot be used in vapor transport (PVT) furnaces for SiC single crystal growth and some parts of SiC epi reactors. A major challenge with TaC coating, however, is the difference in the coefficient of thermal expansion (CTE) of TaC and graphite. When the TaC coating fully fills the open pores of the graphite substrate, the more rapidly expanding TaC upon heating during application could lead to localized destruction of the graphite substrate. To overcome this challenge, a controlled partial TaC coating of the open graphite pores is achieved as shown in Fig. 4. The above advances in SiC and TaC coating of graphite presented are expected to improve the quality of SiC crystal growth while reducing the total cost of ownership of epi and PVT tools currently hampering both research and production.

[1] D-J. Kim and D-J. Choi, J. Am. Ceram. Soc.79, 503 (1996). [2] J. R. Abelson and G. S. Girolami, J. Vac. Sci. Technol. A 38, 030802 (2020) [3] J.-J. Huang, C. Militzer, C. Wijayawardhana, U. Forsberg ad H. Pedersen, J. Vac. Sci. Technol. A 41, 030403 (2023).

ABSTRACT. Silicon carbide is one of the most attractive and promising wide band-gap semiconductor materials with high breakdown voltage, high thermal conductivity, and high electron mobility. More and more SiC-power-devices such as MOSFETs and SBDs are fabricated with SiC epitaxial layer grown on n-type 4H-SiC substrates [1-3]. Nowadays, 6 inch 4H-SiC substrates are already in mass production and 8inch 4H-SiC substrates are also commercially available with a rapidly increasing capacity. 12 inch will be the next generation node for even larger diameter SiC substrates, and the most challenging point is how to expand the crystal diameter from 8 inch to 12 inch. Lateral growth is the key to expand the crystal diameter which is provided by radial temperature gradient. The difficulty lies in lateral growth of SiC crystal is how to keep a proper radial temperature gradient. When the temperature gradient decreases, poly crystal will be grown around the edge of crystal, whereas when the temperature gradient increases, larger grown-in thermal stress will be caused, at the same time, cracks could happen during the process of cooling down or crystal grinding. [4-5]. Growth of SiC crystals were carried out by PVT method. In this study, Virtual Reactor software was applied to do the thermal simulation calculations of the silicon carbide single crystal growth process and to guide the thermal filed design. Convex thermal field was designed for the expansion of SiC seed crystal diameter. The radial temperature gradient was about 0.3℃/cm to 0.6℃/cm. During lateral growth of SiC seed crystal, 20 mm enlargement of the seed was carried out for each expansion stage. After growth, crystal grinding, cutting, lapping, polishing was carried out to get larger size diameter seed wafers. The seed diameter expanded from 230 mm to 250 mm, 270 mm, 290 mm and 300 mm respectively during the whole expansion process. At last, 300 mm diameter seed was achieved. PVT method was used for the growth of 12 inch SiC crystals, in which Nitrogen and Hydrogen was used as the doping gas respectively for N type SiC crystals and high purity SiC crystals. After wafer processing, 12 inch N type SiC wafers and 12 inch high purity SiC wafers were successfully developed. It was the first time for the announcement of 12 inch high purity SiC wafers all over the world in December of 2024. At the same time, common parameters for 12 inch wafers were tested. Shown from Polarized light stress picture result, there are only a few micropipes all through the wafer. MPD being lower than 0.2/cm2 means good crystal quality. Morphology of wafers were tested by FM300, and the results that TTV<7µm, |Bow|<10µm and Warpage<15µm means good wafer processing quality.

ABSTRACT. Minority carrier lifetime serves as a critical parameter for evaluating 4H silicon carbide (4H-SiC) epilayers, directly influencing the conductivity modulation and on-resistance of high power 4H-SiC bipolar devices. However, the minority carrier lifetime distributions exhibit non-uniform in 4H-SiC epilayers. The epitaxial layer grown on the facet trace region (the oval-shaped dark facet region) shows higher lifetime. More recently, it has been shown that one possible reason is that the oval-shaped dark facet region has better crystal quality and longer diffusion length. In order to investigate the minority carrier lifetime distribution, surface roughness, bulk lifetime and defects of the oval-shaped dark facet region were discussed.

ABSTRACT. Recently, AR glasses based on silicon carbide have gained popularity among the public due to their high refractive index (2.6-2.8, significantly higher than glass's 1.8) and good transmittance. Its appearance is no different from glasses, but compared with traditional AR glasses lenses, it is lighter and thinner, with a single piece weight of only a few grams and a thickness of less than 1mm. It has achieved breakthroughs in multiple technical dimensions such as rainbow free and large field of view single piece full-color display. Meta researched the application of silicon carbide 5 years ago and released an AR waveguide based on silicon carbide last year, Moldnano also showcased the world's first silicon carbide AR eyeglass lenses last year. Now, domestic and foreign manufacturers have shifted from 6-inch to 8-inch silicon carbide substrates, and pioneering companies have developed cutting-edge technology for 12 inch substrates, which will lead to exponential growth in AR glasses production capacity. In the future, these advances will continue to drive down the cost of AR, and the future prospects of silicon carbide grade AR glasses are becoming increasingly clear. A high refractive index can achieve a large field of view. High transmittance means low absorption. This article investigates the effects of different crystal forms 4H/6H and impurity contents of silicon carbide on refractive index and transmittance. Using an ellipsometer to test the refractive index of silicon carbide chips, it was found that the crystal type has a slight effect on the refractive index. The refractive index of 6H chips in the visible light band is slightly higher than that of 4H chips. This difference is due to the difference in dielectric constant between different crystal forms of silicon carbide. The effect of impurity concentration on refractive index is negligible, which is due to the fact that under the same crystal structure and high-purity chips, the difference in impurity content is not significant. The transmittance of silicon carbide chips was tested using a UV visible spectrophotometer, and the transmittance of different crystal types was basically the same, with a slight increase with wavelength; However, it was found that the transmittance of 4H crystal structure has a blue shift of about 30nm compared to 6H crystal structure, which is related to the different bandgap widths of different crystal structures. The bandgap width of 4H SiC is about 3.2eV, while that of 6H SiC is about 3.0eV. Due to different impurity contents, there may be some differences in transmittance. Low impurity contents correspond to high transmittance, which is caused by impurity absorption. Therefore, silicon carbide chips with low purity are not suitable for making AR lenses.

ABSTRACT. This paper investigated the dislocation structure in 4H-SiC epitaxial layers using reflection X-ray topography and photoluminescence imaging under UV excitation. We examined the influence of the facet trace region in a 4H-SiC substrate on the dislocation structure in the 4H-SiC epitaxial layer deposited on the substrate. It was found that the epitaxial layer grown on the facet trace region showed significantly different behaviors in terms of the BPD propagation into the epilayer and the interfacial dislocation formation compared to that grown on the other regions in the substrate.

ABSTRACT. High temperature solution growth of 4H-SiC single crystals is being developed for large diameter crystal growth, but longstanding issues such as step bunching during step-flow growth, solvent inclusions, and polytype formation remain unresolved. In this study, we investigated spiral growth behavior induced by threading screw dislocations under low supersaturation conditions, using in-situ interferometric observation with a thin film solvent system (Si–40 mol% Cr, 0.2–0.5 mm thickness). Spiral hillocks with diameters of 5–10 μm appeared on on-axis (000-1) seed crystals with an areal density of ~2000/cm² and coalesced through domain competition, leading to macrostep formation. With a 0.2° off-angle seed, transition from step-flow to spiral growth was observed via dynamic fringe patterns. A high initial growth rate of 11 μm/min was recorded, which rapidly decreased when a 0.5 mm-thick solvent film was employed. Growth rate and step energy were evaluated based on steady-state diffusion-limited models and spiral growth theory, using COMSOL Multiphysics to estimate interfacial carbon concentration and temperature.

ABSTRACT. Our research group is developing a new liquid-phase epitaxial (LPE) growth technique using a solvent dispersed with SiC fine particles. Such a solvent includes supersaturation of SiC due to the Gibbs-Thomson effect. We have also reported that a 4H-SiC epitaxial layer exceeding 20 µm can be grown at 1873 K for 1 minute from a Si-Cr solvent containing dispersed α-SiC fine particles with a particle size of 0.5 µm. However, a quantitative evaluation of the growth rate has not yet been achieved. In this study, we investigated the growth behavior in different solvent systems using in-situ interferometric measurements, aiming to clarify the growth mechanisms in this LPE method and the effect of the solvent matrix composition on the growth kinetics.

ABSTRACT. Nitrogen is commonly doped to obtain n-type 4H-SiC crystals, which have been commercialized for the development of power electronics in recent years. Now the uniformity of electrical resistivity becomes an important issue for the growth of n-type 4H-SiC crystals. In this work, the effects of the radial thermal gradient and growth facet on the distribution of the electrical resistivity are investigated for an n-type 4H-SiC crystal with a diameter of 150 mm during its physical-vapor-transport growth. It is found that the resistivity at the center of the crystal is low in the early growth stage. As the crystal grows, the growth facet expands. The resistivity of the growth facet decreases. The change in the distribution of the resistivity in the crystal is initially governed by the radial thermal gradient and then influenced by the spiral growth mode of the growth facet. In the non-facet region of the crystal step-flow growth occurs, where the doping of nitrogen is primarily affected by the temperature and C/Si ratio. In the facet region, the volume fraction of nitrogen in the mixture of argon and nitrogen input into the growth system mainly governs the doping of nitrogen during the spiral growth. The insights gained in the current work may help the fabrication of n-type 4H-SiC crystals with uniform resistivity.

ABSTRACT. Electrochemical etching (ECE) is a well-established technique for fabricating porous semiconductors, with numerous applications reported over the past decades—including the ELTRAN® process for SOI wafer production [1] and the silicon-on-nothing (SON) process for MEMS device fabrication [2]. A persistent challenge in ECE lies in achieving reliable pore initiation and surface pre-conditioning. Uniform pore nucleation and growth often require careful substrate pre-treatment, such as masked KOH etching [3], metal-assisted photochemical etching (MAPCE) [4], or focused ion beam (FIB) milling [5]. However, these methods typically involve additional lithographic steps, noble metal deposition, or are difficult to integrate into industrial process flows.

This work presents a simple and CMOS-compatible technique for initiating homogeneous pore formation on the silicon face (Si-face) of 4H-SiC using reactive ion etching (RIE). Electrochemical etching was subsequently performed on RIE pre-treated samples to assess the influence of surface modification on pore nucleation behavior, such as surface roughness.

Experiments were carried out on 2.5 × 2.5 cm² pieces diced from 4-inch, nitrogen-doped 4H-SiC wafers (4° off-axis, 0.02 Ω·cm, Si-face roughness < 0.1 nm). After an HF dip, samples underwent RIE in a parallel-plate plasma etcher (STS) using 300 W table power, 25 sccm O₂, and 5 sccm SF₆ at atmospheric pressure for 10, 20, and 30 seconds. ECE was conducted in an electrochemical cell from AMMT (Fig. 1.), with samples acting as separating element between the anodic and cathodic compartments. Pore formation occurred on the side facing the cathode in an aqueous etching solution, containing HF and ethanol (5.52 mol/L HF, 1.7 mol/L ethanol), without the need for UV illumination due to the high conductivity of the material. Surface roughness was characterised by profilometric analysis (Bruker Dektak), AFM (Bruker Dimension Edge) and SEM imaging (Hitachi SU8030 in combination with Alicona MEX software).

An increase in roughness from 1.3 nm (10 s RIE) to 4.0 nm (30 s RIE) was observed (Table I.). In Fig. 2. representative results from AFM and SEM image analysis are shown which are in line with results obtained from surface profilometric analysis (Table I.). A significantly lower peak current at the onset of the ECE current profile is observed for the 20 and 30 s RIE-treated samples compared to the 10 s RIE-treated sample(Fig. 3), suggesting a strong correlation between surface roughness and the subsequent etching process, which is in agreement with the literature [6]. SEM micrographs (Fig. 4.) show increasing pore nucleation density and decreasing pore diameter (black dots) with longer RIE treatment, indicating a more uniform porosification. Cross-sectional SEM images (Fig. 4. g–i) were binarised and analysed to estimate the orientation distribution of the pores (Fig. 5). The resulting polar plots reveal increasing alignment with longer RIE times, suggesting that even a modest surface roughness of 4 nm can effectively promote homogeneous pore initiation during ECE of Si-face of 4H-SiC.

[1] T. Yonehara, K. Sakaguchi, in: F. Balestra, A. Nazarov, V.S. Lysenko (Eds.), Progress in SOI Structures and Devices Operating at Extreme Conditions, Springer Netherlands, Dordrecht, 2002, pp. 39–86. [2] M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J.L. Regolini, D. Dutartre, P. Ribot, D. Lenoble, R. Pantel, IEEE Transactions on Electron Devices 47 (2000) 2179–2187. [3] V. Lehmann, Journal of the Electrochemical Society 140 (1993) 2836. [4] M. Leitgeb, C. Zellner, M. Schneider, U. Schmid, ECS Journal of Solid State Science and Technology 5 (2016) P556. [5] P. Schmuki, U. Schlierf, T. Herrmann, G. Champion, Electrochimica Acta 48 (2003) 1301–1308. [6] G. Gautier, F. Cayrel, M. Capelle, J. Billoué, X. Song, J.-F. Michaud, Nanoscale Res Lett 7 (2012) 367.

ABSTRACT. The increasing demand for high-performance power electronic devices, crucial for applications ranging from electric vehicles to renewable energy systems, places significant emphasis on the quality and cost-effectiveness of silicon carbide (SiC) epitaxial wafers [1]. Achieving epitaxial films with minimal structural defects, sharp doping profiles, and smooth surface morphologies is paramount for device performance and reliability. Moreover, enhancing the efficiency of the epitaxial growth process is essential for reducing manufacturing costs and increasing production throughput. This work introduces a comprehensive and innovative approach to SiC epitaxy, integrating more synergistic strategies specifically designed to optimize the foundational buffer layer and the overall growth process, thereby addressing key challenges in the field. In bibliography several research groups reported their activity on buffer layer developing: Japanese research group (H. Itoh et al.) developed thick and highly doped buffer layer to increase the BPD-TED conversion [2]; American research group (T. Rana et al.) observed that a ramped doping transition from substrate to buffer layer is beneficial for BPD reduction compared to that of abrupt substrate to buffer layer doping transition. Furthermore, they observed that higher growth rates are beneficial for BPD reduction anyway on the other side pit density increased [3]; finally, more than one research groups showed epitaxy result by using “buffer interruptions” technic before the drift layer and they obtained very promising results. ASM® research activity involves the strategic implementation of dynamic growth rate control during the buffer layer deposition. Recognizing the critical role of the initial epitaxial layers in dictating the quality of the subsequent active layers, this technique employs transitions in the growth rate of the buffer layer to promote effective surface stabilization, facilitate uniform nucleation, and significantly suppress the propagation of substrate-related imperfections, such as step-bunching and the emergence of detrimental dislocations. Addressing the critical need for enhanced manufacturing productivity, the second strategy explores a 'fast buffer' growth method, by employing a significantly elevated growth rate for buffer layers up to 3 µm in thickness a substantial process time savings is realized. The development of a high growth rate buffer deposition presented some challenges in terms of resultant defectivity; it was observed how variation in process temperature and C/Si ratio in the buffer growth step largely affect the resulting defectivity. Indeed, regarding the C/Si ratio window at a given process temperature, the limit is given by nucleation of Si droplets when the surface density of Si precursor species exceeds a given Si/H2 threshold. Subsequently, the C/Si ratio of the buffer layer was minimized, seeking the lowest value that ensured high film quality in terms of defect density. Once that all the deposition conditions were settled a comprehensive comparative analysis indicated that epilayers grown with processes featuring fast buffer growth exhibit thickness and doping uniformity, as well as defect densities, that are comparable to those achieved with conventional growth rates. This accelerated deposition offers a direct route to enhanced manufacturing efficiency, enabling higher production volumes without compromising the fundamental characteristics of the initial epitaxial layer, a crucial factor for industrial scalability. The third innovative strategy involves the introduction of a controlled growth interruption immediately following the buffer layer deposition. By temporarily halting the introduction of process gases while maintaining the wafer within the growth chamber under precisely defined conditions for a specific duration, a critical stage for interface management is introduced. This pause in growth is strategically implemented to potentially influence the defect structure at the buffer layer surface and the subsequent interface with the active layer. The aim of this controlled growth interruption is to impede the propagation of threading dislocations and other substrate-related defects into the overlying device layers, thereby contributing to an overall improvement in the crystalline quality and performance potential of the final epitaxial film. In conclusion, the integrated application of dynamic growth rate control for optimized buffer layer initiation, the implementation of a high efficiency “fast buffer” growth mode for increased throughput, and the introduction of a controlled growth interruption for enhanced interface quality represents a step forward in SiC epitaxy. This comprehensive approach offers promising pathways towards achieving SiC epitaxial layers with superior structural integrity, enhanced manufacturing efficiency, and ultimately, improved performance and reliability for the next generation of power electronic devices that are critical for energy efficiency and sustainability.

ASM® is a registered trademark of ASM IP Holding B.V.

[1] T. Kimoto and Y. Yonezawa, Mater. Sci. Semicond. Process. 78, 43 (2018). [2] H. Hito et al. “High-Quality SiC Epitaxial Wafer “EpiEra” Realizing High-Reliability Large-Current Power Devices “, SEI Technical Review - Number 91 – October 2020, pp 48-51. [3] T. Rana et al. “Study of Defect in 4H-SiC Epitaxy at Various Buffer Layer Growth Conditions”, Defect and Diffusion Forum, 16662-9507, Vol. 425, pp 63-68.

ABSTRACT. Solution growth process of SiC is carried out with in situ observation of the meniscus. We have been able to observe the reflected image of the observation hole made by the established meniscus due to contact between the seed crystal and the solution surface.Keeping the contact situation between the seed crystal and the solution under suitable conditions is very important due to the solution surface valuation depending on the induction frequency.

ABSTRACT. Control of the particle size and distribution of source powders used in Physical Vapor Transport (PVT) processes enables the maintenance of temperature distribution within the source powder and the Si/C ratio of sublimated gases, facilitating both stable single crystal growth and high growth rates [1-4]. Modulating the modality of the source powders improves packing density, allowing for a greater loading of source powder and easier control of temperature distribution of source during growth, prompting studies employing powders with a wide range of source powder sizes [5,6]. Recently, by-products from the CVD-SiC process have been considered as alternative source powders for PVT growth due to their high purity, which results from strictly controlled processing environments, and the potential for reduced source costs through recycling [7]. In recent studies, larger sources such as 2 mm-sized granules or plate-like sources exceeding several tens of mm have been used instead of conventional powders in the hundreds of microns range, demonstrating significant improvements in growth rates without detrimental effects on impurity levels, crystal polytype mixing, or defects [7,8]. In this study, we investigate the effect of mean size and distribution of mm-sized granules on compact morphology, pore structure, and growth rate during PVT growth. CVD-SiC by-product granules were classified into five size ranges and applied as sources under identical PVT growth conditions. Their characteristics and growth rates are summarized in Table 1. The average particle size of each raw material powder was prepared with a difference of about 2 mm, and the MP powder has a particle size distribution of 300 μm to 900 μm, which is similar to that of commercial powder. As shown in Figures 1(b)–(e), all sources exhibited a granular. While the packing density remained consistent regardless of granule size in mm-sized granules, growth rates increased with larger granule sizes, suggesting that packing density has limited influence on growth rate when using mm-sized sources. The rocking curve values of all grown crystals were below 50 arcsec, indicating that granule size had no significant effect on crystal quality when mm-sized sources were applied. Post-growth source residues were analyzed via micro-CT to observe morphological changes during the growth process. While all powders showed some morphological change, the extent and nature of the change varied with granule size. As shown in Figures 1(f)–(j), MP powders in several hundred micron meters formed narrow vertical channels typical of conventional source powders, whereas GA–GD sources in several millimeters exhibited a decreasing degree of such narrow channel formation with increasing granule size. This highlights the importance of controlling narrow channel formation in the upper and interior regions of the source compact to enhance growth rates. Recent studies have also shown that the vertical directionality of macro-channels contributes to gas transport rates[9], and in this study, the mm-sized granule source formed both vertical and additional connected horizontal macro-channels, leading to significantly enhanced sublimation rates. This demonstrates the critical role of macro-channel diversity in influencing crystal growth rates[10]. This study examined the effect on the growth rate of single crystals, focusing on the change in the morphology of the mm-sized granule sources during the mid to late stages of crystal growth. Given that the growth rate changes most drastically during the initial growth stage, it is also important to understand early-stage morphological changes. Moreover, different granule sizes may exhibit distinct behaviors during growth [11], necessitating further investigation into the effects of growth time in various granule size. Additional details will be presented in the forthcoming conference.

ABSTRACT. PVT has been the industry-tested and commercial growth process for the production of N-type SiC substrates and Semi-insulating substrates. These two different substrates with differing electrical behavior enables specific device types to be fabricated, such as diodes, MOSFETs, and GaN-on-SiC HEMTs. For Bipolar devices, n-channel devices are vastly preferred due to lower hole mobility than eletron mobility in SiC. Therfore, n-channel bipolar devices have thus far relied on complicated processing of epitaxial P-type layers and subsequent back-grinding removal of the original N+ substrate, the combined processing being prohibitively expensive. The lack of commercial P-type substrates has largely been due to the difficulty of incorporating Aluminum into the lattice during PVT growth. Precursors to Aluminum sublimation have proven difficult to work with and control at separate temperatures from SiC sublimation, requiring complex hotzone designs and/or furnaces with multi-zone control [1, 2]. Ultra-low Resistivity (ULR) N+ substrates have also been sought after, but doping at higher concentrations of nitrogen than ~2E19 leads to the creation of unacceptable levels of Stacking Faults, decreasing the quality and yield of devices. Critical to enabling lower resistivities is a way of co-doping to further reduce the resistivity without decreasing the quality of substrates. By co-doping with a lattice-strain-compensating element, through source-level doping and co-sublimation, the limitations in dopant incorporation can be overcome to produce a ULR substrate. Pallidus, Inc. has developed, through its novel source material synthetic route, a method to produce specialty SiC crystals of high quality. By starting at the source material and incorporating the soluble dopants into the SiC lattice in the source material, controlled co-sublimation of both the SiC and the dopant can enable the most uniform incorporation of dopant throughout the growing boule. Starting with in-house synthesized source materials, Pallidus’s process uses shaped source charges, PVT growing 6” boules, and fabricating substrates therefrom. Both P-type and ULR variants, as well as standard N-type variants, have been successfully fabricated. These new substrate types (P-type and ULR) can enable new device architectures, and also enhance the performance of existing devices. For example, Bipolar devices such as IGBT’s and Thyristors are enabled to be grown directly on P-type substrates with n-channel drift layers. With ULR substrates, existing N+ device architectures can see enhanced efficiency and/or lower processing costs and higher yields due to lower resistance. The controllability of the dopant incorporation and the method of producing source materials via the PDC route, and the impact on crystal growth performance will be discussed. Substrates exhibit suitable quality for high-yielding device fabrication. Hall measurements as a function of temperature, as well as epitaxy and XRT results, will be shared for P-type substrates. Examples of dopant incorporate tunability are shown in Figure 1 for ULR, and Figure 2 for P-type crystals. An example 6“ wafer is shown in Figure 3.

[1] Straubinger, T.L., et al., J. Crys. Gro. 240 (2002) 117-123 [2] Eto, K. et al, J. Crys. Gro. 470 (2017) 154-158

ABSTRACT. This study provides valuable insight into the synthesis and optimization of SiC powders from various Si sources. High-purity α-phase SiC powder derived from the used Si wafer has enormous potential for SiC wafer manufacturing in line with the needs of modern power electronics. The used Si wafer exhibits exceptional quality, such as being very effective in producing SiC wafers due to its large particle size and very high purity. Through this, it will contribute to securing Si-based material technology that secures a method of improving SiC wafer and device characteristics by controlling characteristics from Si raw materials to SiC devices.

ABSTRACT. Bipolar degradation in 4H-SiC devices, driven by the recombination-enhanced dislocation glide (REDG) mechanism, causes expansion of basal plane dislocations (BPDs) into stacking faults (SFs). Although BPDs in epitaxial layers have been reduced, threading edge dislocations (TEDs) converted from BPDs remain a reliability concern. We propose a UV irradiation-based screening method for early detection of latent BPD-related defects. To validate this approach, we quantitatively compared UV-induced and forward-bias-induced excess minority carrier densities by evaluating threshold conditions for SF expansion. Carrier distributions were computed for both stress types using numerical solutions of transport and diffusion equations. We introduce the concept of critical duration, the minimum time that carrier density must exceed the SF expansion threshold. Our results indicate that matching the UV-induced hole density to that under forward bias at the n⁻/n⁺ interface over the critical duration provides a practical criterion for optimizing UV screening conditions for defect detection.

ABSTRACT. This paper explores the critical role of implantation depth in the effectiveness of suppressing bipolar degradation through proton implantation. Targeted implantation at depths corresponding to the most active basal plane dislocations (BPDs) has demonstrated significant success in suppressing degradation. We analyze the width of stacking faults observed in electroluminescence (EL) images to estimate the activation depth of BPD-induced degradation. Based on this analysis, we define the effective range, in both depth and safe operating current density, over which proton implantation remains effective.

ABSTRACT. A thorough understanding of surface and interface features in silicon carbide (SiC) materials, including surface roughness, 3D topography, and dopant/carrier distribution, is crucial for establishing quality control processes that ensure superior device performance and reliability. This abstract introduces two effective surface characterization techniques for SiC: interferometric 3D optical profilometry and scanning spreading resistance microscopy (SSRM). The complementary nature of these methods offers a powerful synergy for cross-validation due to their distinct working principles, obtainable data, and measurable scales. Interferometric 3D optical profilometry operates in either white light interferometry (WLI) or phase shift interferometry (PSI) mode to generate quantitative 3D topographic data from sample surfaces. In WLI mode, the centroid positions of white light wave packets, resulting from constructive interference between the reference and measurement beams, are simultaneously acquired across the areal detector. Meanwhile, PSI mode enables the calculation of the monochromatic interferogram's phase at each pixel, achieving sub-nanometer vertical resolution, although the lateral resolution remains at the sub-micrometer level due to the diffraction limit. SSRM measures the spreading resistance in the immediate vicinity of the contact between a conductive probe tip and the sample. This allows for 2D mapping of electrical properties such as dopant/carrier distribution, defect-induced conductivity perturbations, and cross-interface profiles with sub-10 nanometer lateral resolution. Notably, SSRM can access electrical property information beneath an insulating layer by applying high pressure (in the GPa range) with a diamond probe tip. The synergistic application of these complementary techniques is expected to be instrumental in the field of SiC metrology, overcoming individual limitations and providing a more comprehensive understanding of critical material characteristics.

ABSTRACT. To ensure the reliability of SiC power devices, suppression of bipolar degradation is one of the most important issues. Since bipolar degradation is caused by the expansion of single Shockley stacking-faults (1SSFs) from basal plane dislocations (BPDs) in 4H-SiC crystals, reducing BPD densities in SiC crystals is effective in suppressing it. To address this issue, we have developed an original crystal growth method to produce n+ 4H-SiC crystals with low BPD density using our ceramic processing technology [1-2]. In this study, we discuss the behavior of bipolar degradation in PiN diodes fabricated with the 4H-SiC substrate produced by our novel crystal growth method. Fig. 1 shows a schematic of our crystal growth process. SiC powder with additives that produce liquid phase upon heating and promote crystal growth, and a 6-inch SiC substrate produced by a sublimation method (seed crystal) are contained in a graphite crucible. The multiple crucibles containing the SiC powder and substrate are heat-treated in a batch process at temperatures above 2000 °C in a mixed atmosphere of argon and nitrogen. These steps produce an n+ 4H-SiC layer with a thickness of ~100 – 200 μm on the seed crystal. We refer to this n+ 4H-SiC layer as an “NGK-grown crystal” to distinguish it from an n- drift layer formed in the subsequent process. To estimate the global BPD density of a 6-inch substrate, X-ray topography (XRT) was performed on both the seed crystal and the NGK-grown crystal. With the average BPD density in the seed crystal at 737 cm-² (Fig. 2(a)) and 168 cm-² in the NGK-grown crystal (Fig. 2(b)), we successfully obtained a substrate with low BPD density. PiN diodes (Fig. 3) were fabricated in the following steps. First, we prepared two substrates: one without an NGK-grown crystal and another from the same ingot but with an NGK-grown crystal. An n- drift layer was formed on both substrates, with a thickness of 9.4 μm and a doping concentration of 8 × 1015 cm-3. Al ions to create a p-type layer were then implanted at room temperature, followed by activation annealing at 1650 °C for 10 minutes. Ni electrodes were formed on the backside of the substrates, and Ti/Al electrodes (2.0 × 2.0 mm2) consisting of a pad part and a comb part were formed on the surface of the p-type layer. Subsequently, annealing was performed at 750 °C to ensure ohmic contact. Finally, the substrates were diced into chips of 4.5 × 4.5 mm2. Before fabricating the PiN diodes, we implemented SICA inspection to select chips that had no BPDs in the drift layer. Current stress tests were conducted on these diodes, applying a pulse current with a pulse width of 6 ms, a current density of 425 A/cm2, and a pulse frequency of 10 times per second for 2 hours. To remove the influence of the thermal effect, stress tests were performed while adjusting a pulse width and a current density to maintain the same temperature. After the tests, electroluminescence (EL) images were obtained to evaluate the expansion of stacking faults. Fig. 4 shows the EL images of PiN diodes after the current stress tests. The dark triangular regions in the EL images correspond to the expanded 1SSFs from BPDs on the substrate. In the substrate without an NGK-grown crystal (Fig. 4(a)), the expansion of 1SSFs was observed at two locations. On the other hand, in the substrate with the NGK-grown crystal (Fig. 4(b)), no expansion of 1SSFs was observed. After performing measurements on 5 chips fabricated from each substrate, we found that the number of 1SSF expansions per unit area was 73.3 cm-2 in the substrate without an NGK-grown crystal, and 6.7 cm-2 in the substrate with the NGK-grown crystal. This indicates that bipolar degradation is suppressed in the presence of the NGK-grown crystal. The benefit of the NGK-grown crystal is similar to that of an n+ buffer layer formed by chemical vapor deposition (CVD) [3], but its superior productivity in crystal growth is considered as its major advantage.

ABSTRACT. In SiC power devices, it is well known that various defects in both substrates and epitaxial layers adversely affect device performance and reliability. These defects in the epitaxial layer can also be detected by evaluating the carrier lifetime. Microwave Photoconductivity Decay (µ-PCD) is one of the techniques for measuring carrier lifetime, determining lifetime by detecting changes in conductivity due to the recombination of excess carriers through microwave reflectivity. In this study, we focused on defects and their surroundings, measured the carrier lifetime in SiC epitaxial wafers using the µ-PCD method, and investigated the decay curves of microwave reflectivity at defects. In addition, the potential and effectiveness of defect detection and identification through lifetime measurement using the µ-PCD method was verified. The results from the lifetime mapping image, these defects such as polytype inclusions and stacking faults all appear as dark contrast, suggesting a short lifetime at and near the defects. From the decay curves of microwave reflectivity for the polytype inclusion, the stacking fault and the reference area (free of polytype inclusions and stacking faults), in the initial decay phase, it is observed that the slope for the polytype inclusion is the steepest, the stacking fault shows an intermediate value, and the reference has the least steep slope. In the later decay phase, the polytype inclusion has the gentlest and longest tail, whereas the stacking fault and reference have similar slopes to the initial part of the decay curve. These results show that polytype inclusions have unique decay curves compared to stacking faults and references, suggesting that polytype inclusions have electrical properties that adversely affect devices as killer defects.

ABSTRACT. Stacking faults (SFs) are well-known to be a limiting factor for the device yield of power electronic devices fabricated from SiC. They can occur in 4H-SiC substrates and epitaxial layers as Shockley and Frank type stacking faults, as single or multiple stacking faults and form complexes such as the carrot defect [1,2]. Previous studies have reported [3, 4] that some stacking fault types can affect device performance and cause failure of devices, however by which specific SF types cause electrical failure remain insufficiently understood. For example, Baierhofer et al. [5] indicated that only 66% of the defects identified by PL imaging as SFs without polytype inclusion will kill a MOSFET device. Further, these defects result in different failure mechanisms. This finding indicates the necessity for a more detailed subclassification of these defects. With our contribution, we shed light on the issue, showing that differences in the properties and especially in the electrical behavior of SFs can already be seen after implantation and wafer annealing. This enables a detailed distinction between different SF classes without the need for a finally processed device and the corresponding electrical characterization. For our study, we prepared eleven 150 mm SiC Wafers with 13 µm standard 1200 V n-type epitaxy and a doping concentration of 9E+15 cm-3 which is standard for Trench MOSFET device fabrication. After epitaxy and trench formation, they received implantation steps with different parameters and subsequent annealing at 1700°C for 30 min. These were investigated repeatedly with various imaging methods utilizing the DIC and PL channel of the Lasertec SICA88 tool at different steps of the process. Surface and PL images were recorded on the substrates, after epitaxy and again after ion implantation and annealing, respectively. The effect of implantation on the appearance of the SFs can be seen in Fig. 1. Before the implantation, the SFs under investigation appear similar as dark triangles in the PL channel. Then, a patterned nitrogen contact (n+) as well as aluminum FFR (p+) and aluminum contact (p+) implantations with different implantation angles and temperatures was applied. After the implantation steps and high temperature annealing at 1700°C, the SFs show changed luminescent behaviors. The SFs can be divided into four different groups of luminescence types based on the appearance of the PL image after implantation. Type A defects show a bright luminescence in the implanted regions. For type B, the SF appears dark with a dark surrounding area. Type C defects were only slightly visible after implantation with a luminescence signal similar to the defect free implanted area. Type D defects appear like Type A but with a darker area around the luminescent triangle. Only defects in implanted areas were investigated, to determine the effect of this particular process step on the SFs. Figure 2 shows the relative fractions of occurrence of the four types of 400 defects in total as well as for the individual wafers. In total, about 50 percent of the dark triangle SFs were categorized as type D with a darker surrounding area after the implantation. The fractions of the different defect luminescence types varied between the tested wafers. The origin of these variations is currently under investigation. It may either be related to the implantation parameters or to the properties directly after epitaxy. The potential connection between implantation conditions like dose and wafer tilt as well as implant annealing temperature will be determined by systematic variation of the implantation parameters. Spectral PL will give insights into whether the different types of SFs can already be identified at the stage after epitaxy before ion implantation. A correlation to electrical testing of the devices and reliability tests will finally give insight into the electrical impact of the four types of stacking faults.

ABSTRACT. Semiconductors with a large band gap are often considered as materials for creating high-temperature electronics devices . Therefore, it becomes important to investigate the effect of temperature on various characteristics of these devices, for example, radiation resistance. The article presents a study of the effect of irradiation temperature on the radiation resistance of GaN when irradiated with protons and electrons. The carrier removal rate is determined. It is shown that, as in the case of SiC, there is a significant decrease in the carrier removal rate when irradiated at 200 C, compared to irradiation at room temperature.

ABSTRACT. This study presents the evolution of threading screw dislocations (TSDs) defects in n-type 8-inch SiC single crystals grown by the physical vapor transport technique. As shown in Figure 1, two sets of cross-sectional samples along the [112(_)0] and[1(_)100] directions were processed on the crystal with 4° off-axis toward [112(_)0], respectively. The surface morphology of the cross-sectional sample was characterized by X-ray topography (XRT). Under the g=0004 diffraction vector, the boundary (Line 1 in Figure 2) between the facet and non-facet regions on the [112(_)0] cross-sectional sample was faintly visible. It was noted that the extension direction of most TSDs in the non-facet region had an angle with the [0001] direction towards [112(_)0]. In contrast, the deflection of the TSDs extension direction in facet region is opposite to the former, closer to the vertical extension along the [0001] crystal direction, which is attributed to the growth mechanism of the facet region is a spiral growth mechanism, while that of the non-facet regions is a step flow growth mechanism[1-3]. We studied the TSDs at the growth interface and found that there was no obvious TSD proliferation phenomenon at the growth interface. In addition, the vast majority of TSDs in the seed was inherited into the crystal. Obvious polytype boundary was observed in the upper halves of the [112(_)0] cross-sectional sample. Raman spectroscopy characterization confirmed that the region above the black line was 6H-SiC, while the region below that was 4H-SiC. The TSDs were also found in the 6H polytype region, mostly due to proliferation at the polytype transformation interface. We compared the distribution of TSD in the facet and non-facet regions, the 4H-SiC and 6H-SiC regions, the region close to the crystal center and the edge region of the longitudinal slice, respectively. The results showed that TSD tended to be distributed in the crystal center area, and the possible reasons for this phenomenon were proposed. The distribution of TSD defects on 8-inch 4H-SiC wafers was also observed at the g = 0008 diffraction vector, and stress anomalies were noted in some of the aggregated TSDs at positions corresponding to the stress diagrams, and micropipes were observed by optical microscopy at the corresponding positions of wafers of subsequent slice numbers(Fig. 3). The similar phenomenon was observed on wafers of other crystals, suggesting that the dense TSDs may merge into micropipe defects as growth proceed. Through the study of the evolution trend of TSD in large-sized SiC crystals, our work provides more ideas on how to further reduce defects in SiC crystals

ABSTRACT. Advancements in analysis techniques for SiC power semiconductors have contributed to improved product yield and quality by enabling the identification of defect causes. In fact, as technologies for rapid defect analysis of SiC substrates have progressed, the overall quality of SiC power devices has improved. Alongside these developments, the miniaturization of SiC power device structures is also under consideration, highlighting the need for detailed analysis of dopant layers and depletion regions that contribute to diode characteristics. In many cases, analytical techniques developed for Si semiconductors can be adapted to analyze SiC structures. However, since the level of miniaturization in SiC devices does not yet match that of Si devices, there is limited investment in high-precision and expensive analytical equipment. Various methods exist for analyzing PN junctions, and transmission electron microscopy (TEM) is one such technique that offers high spatial resolution. However, TEM is suitable for atomic-level observation at specific locations and requires complex sample preparation, making it unsuitable for routine analysis. Another method is electron beam-induced current (EBIC) measurement using nanoprobing, which is widely used for Si semiconductors. [1.2] However, due to the high cost of the required equipment, it is not always appropriate for SiC power device analysis. In this study, we developed a simplified EBIC holder and investigated the observation of PN junctions in SiC power devices—particularly the depletion region—using this more accessible method. Figure 1 shows a schematic diagram of a simple EBIC holder. In EBIC measurements, the current generated by electron beam irradiation in a scanning electron microscope (SEM) is detected. Here, we explain the setup using a cross-sectional holder as an example. A cross-section prepared by cleaving or ion beam processing is placed on the back side electrode of the holder. An electrode is then brought into contact with the opposite surface (in this case, the sample surface), and the current flowing into this contact electrode is detected. Figure 2 presents results obtained using this holder. The SEM used for these observations was the JEOL JSM-IT800i. Figure 2(a) shows a secondary electron image taken at an accelerating voltage of 0.5 kV, in which the region corresponding to the P-layer appears with bright contrast. Figures 2(c), (d), and (e) show EBIC images obtained in the same field of view at different accelerating voltages. The depletion region appears clearly as a bright contrast area. As the accelerating voltage increases, the region with bright contrast in the EBIC image expands. This is believed to be due to the increased penetration depth of the primary electron beam, as illustrated in Figures 2(f), (g), and (h). Figure 3 schematically represents this relationship. When observing the depletion layer between the P and N regions using EBIC, it is considered that the lower accelerating voltages provide information closer to the actual depletion region. Zhou et al. have reported similar observations in solar cells [3]. Similarly, in SiC, using a low accelerating voltage allows for a more accurate evaluation of the actual depletion region. In this study, we fabricated a simple EBIC holder and verified its effectiveness. In this presentation, we will discuss the low-accelerating-voltage EBIC measurements in combination with the VC measurements of the P-layer.

ABSTRACT. Today, the constant demand for increasingly efficient systems in energy management, both in terms of conversion and modulation, has led to the replacement of silicon with materials offering significantly superior performance, among which silicon carbide (SiC) stands out. Currently, SiC is one of the leading materials for the fabrication of high-performance power devices, allowing the combination of compact designs with exceptional operational capabilities. From a production standpoint, the industry is moving toward 200mm wafers size and innovative solutions such as Advanced SiC substrate using Polycrystal, aimed at reducing overall technology costs. However, in the development of materials and devices, these still maturing technologies must confront the presence of intrinsic substrate defects, which act as true killer agents for device reliability. Technological progress involves not only substrates but also packaging systems, which serve the dual function of conducting the high currents generated and effectively dissipating the resulting heat. The field has now gone beyond the realm of academic research and has entered the world of commercial device manufacturing. However, the issue of defects and their impact on performance and reliability remains one of the main concerns for the future of SiC power devices [1]. In today’s power electronics market, which is increasingly dominated by SiC-based devices and continues to grow by defining ever-new power device architectures, often mimicking those developed in silicon, the intrinsic advantages of SiC materials have been well recognized for many years. Among these advantages are a wider bandgap, which results in a higher electric breakdown field, a lower intrinsic carrier density, and higher thermal conductivity, allowing more effective heat dissipation from the active area of the device towards the package system. While SiC has many intrinsic advantages for power devices, it also has materials defects that are challenging. The focus of this paper is on the effects of extended defects such as propagated dislocations and stacking faults, as opposed to point defects, that have been shown to adversely affect SiC devices by introducing leakage paths, reduced conductivity in the device drift region [2] and bipolar degradation phenomena [3-5]. The integrated development of the device system involves multiple factors that contribute to enhancing overall performance, starting precisely from the quality of the SiC substrate. Numerous studies have analyzed the evolution of defects within materials and their effects on device reliability, highlighting the critical importance of controlling and mitigating such imperfections to ensure increasingly reliable and efficient devices and modules [6]. Starting with this consideration we proposed an innovative methodology to investigate defects. In this work, engineered defects are introduced through a nanoindentation procedure in 4H-SiC p-n junction diodes and Schottky diodes. We conduct a systematic study of engineered defects introduced through nanoindentation, monitoring the resulting changes in device performance and correlating the results with nanoindentation, micro- photoluminescence (PL), micro-Raman, and electroluminescence analyses, as well as with physical investigations using SEM and TEM. A nanoindentation load range between 3 mN and 15 mN was explored. In Figure 2b, PL analysis on nano-indented regions is reported displaying distinctive signal at wavelength of 424 nm growing in intensity with increasing of nanoindented load. Scanning Electron Microscopy and Transmission Electron Microscopy analysis are adopted for the morphological and crystallographic investigation of defects; electrical characterizations of junction diodes are performed to investigate the conduction mechanism, both at RT and versus measurement temperature. Electrical parameters such ideality factors, leakage current and series resistance, are extracted for the processed diodes and compared to virgin one. Activation energy of about 1.7 eV and 0.2 eV are extracted for defects in virgin and in mechanically processed devices, respectively for p-n junction. Photo and Electro-optical characterizations were performed adopting Emission Microscopy measurements evidencing a diffuse photons emission in the visible range from the full area in virgin device and an emission in the visible and in the near infrared ranges from nanoindentation sites in processed devices. Performed analysis evidenced that both extended and point defects are mechanically introduced. Thanks to the experiments carried out, a promising path is paved for defect engineering at microscale, spatially defined positions in end-of-processing devices. Additionally, accelerated tests were performed to observe the effects induced by temperature and humidity under H₃TRB (High Humidity High Temperature Reverse Bias) conditions, revealing the impact of induced defects on the electrical degradation of the devices.

ABSTRACT. With outstanding electronic properties such as high breakdown field strength, high operating temperatures, high thermal conductivity, and high carrier saturation drift velocity, silicon carbide (SiC) is becoming the choice for fabrication of high-power electronic devices. Various device types such as diodes (JBS, SBD, PiN) and transistors (MOSFET, JFET, IGBT) have been developed chiefly on n-doped substrates. Among these, the SiC insulated gate bipolar transistors (IGBTs) have demonstrated great performance advantages and application prospects as high-voltage switches. Especially, n-channel IGBTs show superior performance than p-channel IGBTs due to higher mobility of electrons than holes but require fabrication on p-doped substrates.

However, the fabrication of n-channel IGBTs is constrained by the quality of the p-type SiC substrate, which is essential for their device performance. Usually, p-type SiC is manufactured using an aluminum (Al)-containing compound placed in the SiC powder region as dopant. Since the vapor pressure of Al is significantly higher than that of the SiC gas species during crystal growth, the Al source is released excessively in the early stage of crystal growth and gets depleted for the later growth stage. As a result, it is hard to achieve stable and continuous p-type doping. In addition, the high concentration of Al at the seed/newly grown crystal interface affects the crystallization quality and leads to large defect nucleation. So far, Suo et al. [1] achieved 3-inch N-Al co-doped p-type SiC crystals with regions having BPD etch pit density of 300 cm-2. 4-inch p-type 4H-SiC is obtained by Wang et al. [2] with dislocation etching pit density of 888.89 cm-2. Compared to actual BPD densities (total line length per unit volume), BPD etch pit densities (number per unit area) can be undercounted by a factor of 14 or greater for 4 offcut wafers [3]. Nevertheless, significant improvement in quality of p-type SiC wafers and further lowering of defect densities is necessary for development of devices such as n-channel IGBTs.

In this study, 6-inch high quality p-type 4H-SiC wafers are achieved by PVT method. Optical image of the wafer shows a uniform blue color indicative of stable and uniform Al doping (Fig.1(a)). The wafers were examined by synchrotron X-ray topography in transmission and grazing incidence geometries to map the defect content and distribution. Initial analysis indicates average defect densities are on par or better than commercial 6-inch n-type wafers with basal plane dislocation (BPD) density ~2.1*104 (line length/cm-2); threading screw/mixed dislocation (TSD/TMD) ~1588 cm-2; threading edge dislocation (TED) density ~1335 cm-2. Large areas of the wafer, especially the middle region of the wafer is characterized by very low density of BPDs. As shown in the grazing incidence images of some regions in Fig. 2(a) and (b), only one or two short segments of BPDs can be observed within the 15 μm penetration depth and over an area of size 1.75*2.34 mm. In fact, the average BPD density for the middle 3.5 cm diameter region is as low as 963 cm-2 while that for the middle 7 cm diameter region is still low at 2440 cm-2. The extent of prismatic slip due to radial thermal gradients is also vastly reduced compared to typical n-type wafers (Fig.1(b) and (c)). Further optimization of the growth process is underway to lower threading dislocation densities as well as further lower BPD densities. Additional details about the defect distributions in these high quality p-type wafers will be discussed.

ABSTRACT. Silicon carbide (SiC) is a wide-bandgap (WBG) semiconductor material with a wide bandgap (~3.3 eV), high critical electric field (~3 MV/cm), and excellent thermal conductivity (~4.56 W/cm°C), making it superior to conventional semiconductor materials in power electronics. These properties make SiC particularly attractive for applications in industries such as electric vehicles and renewable energy, as its low thermal resistance and high breakdown voltage reduce switching losses [1]. However, various defects generated during the fabrication process of 4H-SiC devices act as major limiting factors for device performance. Deep-level defects such as Z1/2, RD1/2 can significantly degrade conduction characteristics by shortening carrier lifetime, while also increasing leakage current, thereby deteriorating the reliability and efficiency of the devices [2], [3]. Generally, although a reduction in carrier lifetime can improve switching speed, it results in a trade-off by worsening the on-state characteristics due to increased conduction losses [4]. Therefore, to optimize both the static and dynamic characteristics of 4H-SiC-based devices, it is essential to precisely analyze the impact of defects on the electrical properties and to establish effective defect management strategies. In this work, 4H–SiC superjunction (SJ) MOSFETs were designed to investigated how deep-level defects affect device performance under both static and dynamic operating conditions. The SJ MOSFETs exhibited a breakdown voltage of 4.2 kV, a threshold voltage of 4.2 V, and a specific on-resistance of 1.67 Ω·cm² (Fig. 1). To prove the role of point defects, Deep-level transient spectroscopy (DLTS) was employed to characterize 4H-SiC based PN structures with varying P-region widths (Fig. 2). Expanding the P region was found to raise concentrations of Al-related SH1* and irradiation-induced RD1/2 defects while suppressing Z1/2 (carbon vacancy) defects, yielding reduced leakage currents. Based on these findings, the impact of point defects on MOSFET operation was evaluated: higher defect densities were associated with increased on-resistance, and reduced carrier lifetimes in the body diodes led to shorter reverse recovery times (Fig.3). These results demonstrate that precise engineering of the P-region geometry and associated defect profiles can optimize both static and dynamic characteristics of 4H–SiC SJ MOSFETs, offering valuable guidelines for the development of high-performance SiC power devices.

Acknowledgment This work was supported by the Technology Innovation Development Program – Development of next-generation power semiconductor based on Si-on-SiC structure (RS-2022-00154720) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea), Development of 8-inch SiC Wafer-based Multi-Sensor SoC Platform (RS-2023-00266246) funded by the National Research Foundation (NRF, Korea), and also funded by Kwangwoon University in 2025.

References [1] She, Xu, et al. IEEE Transactions on Industrial Electronics 64.10 (2017): 8193-8205. [2] Kawahara, Koutarou, Tsunenobu Kimoto. Journal of Applied Physics 106.1 (2009). [3] Lin, Tianxiang, et al. IEEE Electron Device Letters 44.4 (2023): 578-581. [4] Nakayama, Koji, et al. IEEE transactions on electron devices 59.4 (2012): 895-901.

ABSTRACT. Wide-bandgap semiconductor-based electronics are constantly being developed, with 4H-Silicon Carbide (4H-SiC) leading the way in next generation power devices. In particular within power electronics, SiC carries intrinsic advantages with higher thermal operation and lower switching losses compared to Silicon-based (Si) electronics [1]. The fundamental understanding of 4H-SiC crystal growth is also expanding in-line with an increasing commercialization of 4H-SiC wafers, with more key actors and larger facilities ramping up production and thus, increasing the global availability. But scaling up comes with consequences, increasing throughputs can come at the expense of quality. In this work we investigate a defect seemingly overshadowed by more typical and apparent defects, in example Micropipes and dislocation. Expanding the understanding of 4H-SiC defectivity with novel results on Bulk Inclusion (BI) tracing and sizing, and the consequences following its presence. We deep-dive into the consequences of such defects, showing how they affect yield in thin 4H-SiC bonded layer technology. The mere presence of them close to the wafer surface, depending on their size, causes traceable decorations in grown epitaxial layers and directly impacts device yield. We show the ability to pin-point them in the wafer volume (3D) using commercial optical defectivity inspection tool, sizing and, classifying them with respect to their impact on consecutive product or device steps. In addition, many commercial systems used today also has an interaction-volume in orders of several um, that could mis-bin presence of such defects as surface contaminations, possibly giving rise to misrepresented yield approximations, unnecessary wafer scrap and, wafers being graded to low. Herein we visualize such datasets extracted from wafers analyzed in entire ingots, data retrieved from routine procedures, showing unique patterns and positional propagation with respect to their size, see Fig. 1. We also present how they generate dislocations-centers during crystal growth using 3D visualizing of ingots projected onto 2D-planes, which together with dislocation maps of same ingot, show significant TSDs generation as a function of BI, as shown in Fig. 2. In addition, we look to how this dislocation propagation continues in epitaxial layers, show how these types of defects are detectable near-surface in photoluminescence(PL)-sensitive systems on bare substrate where they are easily misconceived as stacking faults and/or Micropipes. This defect can, at various quantities and sizes, be found in all commercially available 4H-SiC products today and easily be a reason for unexplained yield-loss, epitaxial defectivity without explicit origin, and seemingly desultory dislocation propagation. The feedback has been critical in crystal growth process optimization. To learn how to avoid this elusive killer-defect, the first step is to recognizing it is there to begin with, and to which severity.

ABSTRACT. We suggest an automation of identification process of the Burgers vector and line vector of threading dislocations in 4H-SiC wafer. This method is based on template matching of experimental and simulated images of polarized light microscopy for dislocations. One can identify the Burgers vector completely by combining this template matching method with X-ray topography analysis. This automation will enable comprehensive defect analysis and killer defect identification.

ABSTRACT. SiC wafers, including state of the art, can contain various defect types, some of which degrade device on-state performance, reduce device reliability, as well as lower the breakdown voltage. It is thus critical to identify, delineate and mitigate defects in SiC wafers. In order to evaluate defects in hundreds of SiC wafers, reliable wafer scale methods for mapping defects are required in addition to rapid and reliable automated defect quantification. Although wafer scale techniques for mapping defects are establish [1], [2], [3], they generate gigabytes of data, and manually cataloging every defect is not feasible. Several reports over past two decades has made it possible to manually identify the various defect types, but creating an automated process is difficult as the defect size, shape, and appearance may vary significantly, requiring complex mathematical routines. There have been few models to successfully mapping basal plane dislocations from Ultra-Violet Photoluminescence (UVPL), [4], but these models are generally applicable to specific measurement tools, and broad applicability is challenging. Additionally, other defects such as inclusions, stacking faults, and threading dislocations often present as smaller, less consistent changes in intensity with complex shapes. This presents the development of machine learning models to map defects in SiC from UV-PL and x-ray topography (XRT) images with the aim of developing a model capable of mapping the full range of defects and broad applicability to multiple measurement techniques.

Our previous work demonstrated that machine learning models are effective at mapping multiple types of defects at the wafer scale [5]. In particular, it was found that a convolutional neural network (CNN) was effective at precisely detecting local features, however, false positives were common. This new work focuses on using a U-Net based machine learning model, which consists of an encoder – decoder pipeline coupled to skip connections to analyze both global and local features simultaneously (Fig. 1). The U-Net model compared to a CNN based model is an order of magnitude faster at mapping wafers and greatly reduces the number of false positives (Fig. 2). The U-Nets architecture is readily adaptable to detect and distinguish between different defect types — specifically, dislocations, stacking faults, and inclusions (Fig. 3).

Work performed at the U.S. Naval Research Lab was sponsored by the O_ce of Naval Research and the DOD Microelectronics Commons program.

[1] R. E. Stahlbush, K. X. Liu, Q. Zhang, and J. J. Sumakeris, “Whole-Wafer Mapping of Dislocations in 4H-SiC Epitaxy,” Materials Science Forum, vol. 556–557, pp. 295–298, Sep. 2007, doi: 10.4028/www.scientific.net/MSF.556-557.295. [2] P. Berwian et al., “Imaging Defect Luminescence of 4H-SiC by Ultraviolet-Photoluminescence,” Solid State Phenomena, vol. 242, pp. 484–489, Oct. 2015, doi: 10.4028/www.scientific.net/SSP.242.484. [3] P.-C. Chen et al., “Defect Inspection Techniques in SiC,” Nanoscale Research Letters, vol. 17, no. 1, p. 30, Dec. 2022, doi: 10.1186/s11671-022-03672-w. [4] S. Harada, K. Tsujimori, and Y. Matsushita, “Automatic Detection of Basal Plane Dislocations in a 150-mm SiC Epitaxial Wafer by Photoluminescence Imaging and Template-matching Algorithm,” Journal of Electronic Materials, vol. 51, no. 1, pp. 243–248, Jan. 2022, doi: 10.1007/s11664-021-09284-x. [5] J. C. Gallagher, N. A. Mahadik, R. E. Stahlbush, K. D. Hobart, and M. A. Mastro, “Using a Convolutional Neural Network to Map Defects in Wide Bandgap Semiconductors at a Wafer Scale,” in NAECON 2024 - IEEE National Aerospace and Electronics Conference, Dayton, OH, USA: IEEE, Jul. 2024, pp. 306–309. doi: 10.1109/NAECON61878.2024.10670671.

ABSTRACT. The mass production technology of SiC wafers has matured in both bulk growth by sublimation and mechanical processing including CMP, and has been proven to reduce crystal defect density and achieve high reproducibility. However, when CVD epitaxial growth is performed on wafers after CMP processing, in-grown stacking defects caused by interfaces, which are difficult to detect in preliminary visual inspections, occur probabilistically [1, 2]. The origin of this phenomenon remains unclear, whether it is due to processing damage or substrate quality variations. The objective of this study is to establish a novel non-destructive inspection method that can separate and evaluate the effects of residual machining damage and bulk crystal quality.

ABSTRACT. We propose LLS (Laser Light Scattering) as a macro inspection method that complements conventional visual inspection and defect analysis. The LLS has been conventionally used to detect sub-surface damage (SSD) after CMP of SiC surfaces [1, 2], but this method simultaneously captures scattering characteristics caused by bulk crystal quality, and clarifies the correlation between processing behavior and crystal quality.

ABSTRACT. 4H-SiC has emerged as the most viable material for power devices owing-to high thermal conductivity and wide band gap. As the device operating conditions like voltage and current increase its sensitivity to crystallographic defects becomes more critical. Structural defects in active regions of 4H-SiC epitaxial layers can cause variations in operating conditions and will disrupt the overall performance of the devices. Among the structural defects in 4H-SiC epitaxial layers the stacking faults (SFs) still remain major concern and have increased attentions as the very thick (over than 200 m) epilayer thickness is needed for high voltage applications. Therefore, a deep insight into the SFs, in both theoretical and experimental approaches, is still essential. In the present study we have discussed typical Shockley-type SFs (SSFs) and Frank-type SFs (FSFs)in 4H-SiC epitaxial layers: Theoretical modeling along with calculating the stacking fault energies (SFEs) and electronic band structures have been done to provide the insight into these SFs. The calculated results were discussed with photoluminescence (PL) emissions from the SFs and structures investigated by high-angle annular dark-field high-resolution scanning transmission electron microscope (HAADF HR-STEM). In this study, we report SFEs and the energy of the split-off band minimum below the conduction band minimum (CBM) of (5,2), (4,2), and (4,1) FSFs, for the first time. We employed Quantum Espresso for calculation of SFEs and electronic band structures of perfect 4H-SiC, (3,1) SSF, and (5,2), (4,2), and (4,1) FSFs. We applied Pedrew Bruke Ernzerhof (PBE) in generalized gradient approximation (GGA) as exchange correlation function and projector augmented wave (PAW) pseudopotentials. Additionally, we also used vienna ab initio simulations package (VASP) for calculating the electronic band structures of perfect 4H-SiC and SF structures based on the most sophisticated plane wave (PW) methods, which is reported to give most realistic values of electronic properties [3]. We utilized the well-known Alias, i.e., shear deformation method becasue it allows the full implication of periodic boundary conditions [4]. In this method, instead of using vacuum we shear the supercell by length of burgers vector and allow the full variable cell relaxation (VC-relax) which minimizes the energy of the system. Fig. 1 shows relaxed structures of 4H-SiC without and with SFs used in DFT calculations. SFEs of these SFs were calculated using Alias model. The values of SFE for the (3,1) SSF was calculated to be 15.38 mJ/m2, which agreed well with the reported and experimental values [5]. In case of the SFEs of FSFs (5,2), (4,2), and (4,1), we determined their SFEs as shown in Table 1. Note that the SFEs for (5,2) and (4,2) FSFs are as small as 5.41 and 2.56 mJ/m2, respectively. However, the SFE of (4,1) FSF is as large as 17.31 mJ/m2. The determined SFEs can support experimental results on observations of the corresponding SFs in current 4H-SiC epitaxial wafers in the industries. Electronic band structures for the 4H-SiC with and without the SFs were investigated. For perfect 4H-SiC there is no band split at M or K points but for the (3,1) SSF and (5,2), (4,2) FSFs there were conduction band splittings at M point which created the shallow level states, explained by quantum-well method in literature [5]. The split-off was strictly confined to the M point. However the (4,1) FSF showed the wide split-off, starting from K point, of the states in conduction band. Fig. 2 shows electronic band structures for the 4H-SiC without and with the SF (not shown for the (4,2) and (4,1) FSFs, which will be presented at the site). The determined energy of the split-off band minimum below the CBM, i.e., EB was mentioned in Table 1 compared to the previous report.

This work was supported by the Technology Innovation Program (No. 25A02037, 25A02099) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

[1] W. J. Choyke, H. Matsunami, and G. Pensl (Eds.), Silicon Carbide: Recent Major Advances (Springer, Berlin, 2004). [2] P. Friedrichs, T. Kimoto, L. Ley, and G. Pensl (Eds.), Silicon Carbide, Volume 1: Growth, Defects, and Novel Applications (Wiley-VCH, Weinheim, 2010). [3] A. V. Sinelnik and A. V. Semenov, Condens. Matter Phys. 24, 23706 (2021). [4] S. L. Shang, W. Y. Wang, B. C. Zhou, Y. Wang, K. A. Darling, L. J. Kecskes, S. N. Mathaudhu, and Z. K. Liu, Acta Mater. 67, 168 (2014). [5]. H. Sakakima, S. Takamoto, A. Hatano, and S. Izumi, J. Appl. Phys. 127, 125703 (2020). [6] U. Lindefelt and H. Iwata, "Electronic Properties of Stacking Faults and Thin Cubic Inclusions in SiC Polytypes," in Silicon Carbide, edited by W. J. Choyke, H. Matsunami, and G. Pensl (Springer-Verlag, Berlin, 2004). [7] H. Iwata, U. Lindefelt, S. Öberg, and P. R. Briddon, J. Appl. Phys. 93, 1577 (2003).

ABSTRACT. 4H-SiC Epitaxial layers have several kinds of structural defects including threading dislocations (TDs), basal plane dislocation (BPD), stacking faults (SFs), stacking fault complex (SFC), and so-called carrot defect [1]. The carrot defect, which was named to its appearing visual shape when observed in surface imaging techniques [2], has surface morphological feature [3]. The carrot defect is regarded to the killer defect, which can degrade device performance very significantly [1,3]. The carrot defect is in fact composed with several structural defect, i.e., prismatic stacking fault (PSF) + Frank-type SF (FSF) on the basal plane + stair-rod dislocation + threading mixed dislocation (TMD) [4]. The surface morphological feature is the surface groove and there is the PSF beneath the surface groove [4]. In this study, we investigated detailed microstructures of the carrot defect with TWO grooves using high-resolution transmission electron microscope (HR-TEM), field emission scanning electron microscope (FE-SEM), and photoluminescence (PL) mapping. Fig. 1(a) shows the investigated carrot defect near the head region. We could observe surface morphological feature with two grooves at the side boundaries of the carrot defect. In order to investigate inner structure cross-sectional TEM specimen preparation was performed by focused ion beam (FIB) at the mentioned region. Fig. 1(b) shows low-magnification TEM image and we could observe several structural defect contrasts clearly as marked by regions 1 and 2. Figs.1(c) and 1(d) showed magnified image for the regions 1 and 2, respectively. Here, we clearly recognized two surface grooves and vertical defects beneath the grooves. In addition, many basal plane defects and bulky defect. The bulky defect was marked to the region 3 in Fig. 1(d), which was connected to the vertical defect reaching to the surface groove. Fig. 2(a) shows HR-TEM image for the surface groove region in Fig. 1(d). The vertical defect structure had width of about 25 nm. Fig. 2(b-d) show diffraction patterns obtained from the marked regions 1, 2, and 3, respectively, in Fig. 2(a). From the diffraction pattern we could know that the region 1 is 3C-SiC and the region 3 is 4H-SiC. The diffraction pattern from the region 2 is mixed of both patterns. The mixed region of 3C-SiC and 4H-SiC showed periodic features for the 12 layers as marked by the dotted lines in Fig. 1(a). The 12 periodic spacing feature is due the stacking sequences of 3 and 4 from 3C-SiC and 4H-SiC. Note that the common multiple of 3 and 4 is 12. The surprising finding from Fig. 1 and 2 was that the SiC between two grooves is 3C-SiC polymorph not the 4H-SiC. This implied that the vertical defect lines beneath the grooves are different from the well-known PSF in the general carrot defect. It should be noted that the conventional PSFs in the carrot defects showed the zig-zag feature but the vertical defect in Figs. 1 and 2 appeared beneath the grooves were vertical to the c-plane without the zig-zag feature. Fig. 3 is HR-TEM image for the bulky defect region marked as 3 in Fig. 1(d). In fact, it was very complex microstructure with several polymorphs of 3C-SiC, 4H-SiC, 6H-SiC, and 2H-SiC. Also, the 3C-SiC polymorph showed many SFs and twin structures. In conclusion, we investigated the carrot defect with two surface grooves and the region between the two grooves was 3C-SiC not the 4H-SiC. At the beneath of the grooves, vertical defect structure was found, which was different from conventional PSF in the carrot defect. Detailed discussion will be given at the conference site.

This work was supported by the Technology Innovation Program (No. 25A02037, 25A02099) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

[1] T. Kimoto, Jpn. J. Appl. Phys. 54, 040103 (2015). [2] T. Kimoto et al., IEEE Electron Device Lett.,46, 471 (1999). [3] J. Hassan et al., J. Crystal Growth 312, 1828 (2010). [4] M. Benamara et al., Appl. Phys. Lett., 86, 021905 (2002).

ABSTRACT. This study proposes a novel SiC wafer reutilization process using laser splitting and bonding techniques in SiC power device fabrication. The process involves splitting a wafer with device structures, polishing and bonding the split wafer without devices to achieve a thickness suitable for device fabrication, and then reusing it for further device fabrication. Preliminary experiments demonstrated the technical feasibility of this process, showing that bonded wafers can be split at desired depths without damage. Additionally, MOSFETs fabricated on wafers that underwent thinning by laser splitting exhibited no adverse effects on their electrical characteristics compared to those thinned by conventional grinding. These findings suggest that the proposed process is promising for the efficient utilization of SiC wafers in power device manufacturing.

ABSTRACT. In the development of SiC MOSFET application, trench structure has been used for next generation device, which required strict geometry for better device performance. Fig. 1 shows common SiC trench etch process flow, and SiO2 is etched using Applied Centura TM Etch Super-e reactor. However, for the high aspect ratio SiC trenches, the thicker SiO2 mask etching with vertical profile faced challenges, including photolithography for thicker photoresist (PR) with sub-micro level and high selectivity of PR to SiO2 during etching. Then we propose a new film stack (Fig.2) with thin PR and use Advanced Patterning Film (APF TM) as mask for thick SiO2. Fig.3 shows good SiO2 HM profile: profile angle is above 88.5 degree, with 4um thickness. DARC, APF and SiO2 HM are all etched in Applied Centura TM Etch Super-e. Compared to PR mask, APF show higher selectivy to SiO2, which provides larger process window during HM open and benefits to eliminate SiO2 sidewall stration. After SiO2 mask opened, SiC trench etching also faced challenges to get ideal profile. Compared to previous silicon STI etching, it is challenging to control SiC trench bottom profile due to material characteristics [1]. With parameter optimization in etching recipe, flat trench bottom can be achieved without micro trench. But the sharp corner at the trench base is not ideal for device which has potential to lead to premature gate dielectric breakdown [2]. All SiC trench etch is processed in Applied Centura TM Etch DPS-DTM. Fig.4 shows the typical flat shape bottom with vertical profile, but corners still show sharp right angle. Based on this, adding single step post treatment can make flat bottom profile to concave shape, which show better performance (Fig.4). To achieve further rounded bottom corner, we proposed a looping method which provide highly tunable knobs for different rounding radius (Fig.5). This looping method is targeted for round bottom corner by changing SiO2 mask profile and shrinking critical dimension (CD) which impacts etching trajectory. In order to achieve larger rounding radius (corner rounding radius=CD/2), dep/etch ratio has to be adjusted according to different CD/Pitch size and corner radius (Fig.6). In this case, a looping method has been developed for rounding tunable flexibility: • Step 1: Generate additional film onto trenches mask to shrink top CD, which narrows and changes the plasma entry path. • Step 2: A strong etching step to etch trench bottom which is exposed to directional ion flux. But the other areas at the bottom will be etch limited. • Repeating step 1 and step 2 several times, a rounding bottom will be achieved. According to the desired rounding radius, the number of cycles and parameters in the cycle can be adjusted to find the appropriate ratio. Rounded bottom profile achieved with different CD, indicates that this is an effective method for bottom rounding (Fig. 7). Dep/etch ratio is critical to controlling ideal rounding profile. A heavier dep or higher etch will lead to undesired bottom profile (Fig.8).

ABSTRACT. The precise control and monitoring of ion implantation parameters, such as tilt-, and twist angle, is critical in fabrication of 4H-SiC power devices, especially for achieving controlled junction depth and ensuring reproductivity in high volume manufacturing [1]. In applications such as MOSFETs and JBS diodes, improper tilt alignment during implantation affects dopant distributions. Therefore, a non-destructive and contactless characterization tool is required, to resolve the implantation-induced damage, detect variations in implantation conditions and monitor the stability of implanters. Photo-modulated reflectance (PMR) has proven to be an effective optical technique for monitoring the implantation parameters in semiconductors [2][3]. In general, the PMR signal correlates with ion implantation-induced damage, which is directly related to key implantation parameters such as dose, sample tilt angle and implantation temperature. In this work, we present results measured by the Semilab PMR-2200C tool, which is dedicated to monitor ion implantation processes in 4H-SiC and Si device fabrication [4]. The principle of operation of the PMR technique is based on the illumination of the sample with two laser sources of different wavelengths: probe (blue) and pump (UV). The intensity of the pumping laser is modulated at a frequency of 2 kHz, thus periodically generating charge carriers and inducing localized heating in the material. These effects lead to a quasi-static change in the refractive index of the material. The probe laser uses lock-in technique to detect the relative change of reflectance, which is defined as the PMR signal. Samples were prepared by Nissin Ion Equipment Co. Four wafers were implanted with 500 keV Al⁺ ions to a dose of 5×10¹³ cm⁻² at room temperature. One of the wafers was implanted at the XRD-determined channelling angle, to define the 0° tilt angle position with respect to the crystallographic c-axis (0001 direction). Two additional wafers were quartered and implanted with different tilt angles between -1° and 1°, by using a shadow mask to isolate different the regions. The last sample was implanted with non-channelling orientation. Our findings, depicted in Fig. 1. shows that the channelling condition induce the least damage region, thus the PMR signal reach here the lowest value. This confirms that ions penetrate deeper into the crystal lattice along aligned crystallographic directions, causing less lattice atom displacement. Measurements were performed at 4 sites on each quadrant near the midpoint of region and sample, over 8 cycles. The error bars represent the deviation, reflecting the reproducibility of the PMR signal. The quasi-symmetrical, smooth shape of the PMR signal, with its minimum around the channelling tilt angle shows the sensitivity of the method to detect the sample orientation. The tilt angle resolution is ±0.1° based on the results of the PMR signal, allowing accurate detection of the miscut around the channelling tilt – a critical parameter for proper SiC epitaxial growth. Note that the implanted sample with random ion beam orientation shows higher PMR signal, compared to the near-channelling cases. Fig. 2. and 3. show the wafer maps of the PMR signal obtained by 345 sites. The different quadrants are clearly separated based on the PMR signals. The maps reveal inhomogeneity across the regions, which likely comes from the variation of implantation condition. In conclusion, PMR is proved to be a sensitive tool for monitoring small tilt angle variations in ion implanted SiC wafers even in the near-channelling alignment region, thus offering to determine the required tilt angle and potential for inline process control in industrial environments.

ABSTRACT. Silicon carbide (SiC), a key third-generation semiconductor, offers excellent properties such as wide bandgap and high thermal conductivity, making it suitable for advanced electronic and power devices. Traditional diamond multi-wire sawing (DMWS) -incurs large kerf loss and surface defects when slicing 8-inch SiC wafers[1].Here, picosecondlaser slicing coupled with ultrasonic exfoliation is proposed as a lowloss alternative. Experiments on 8-inch SiC wafers demonstrated successful separation . Optimal parameters yielded surface roughness of ~4 μm and kerf loss of only 12 μm. The influence of scanning speed (100–400 mm·s⁻¹) and average power (8–17 W) was quantified; the best window (300 mm·s⁻¹, 11–14 W) produced Sa ≈ 4 μm and kerf loss = 12 μm, 38 % lower than DMWS. The findings provide practical guidance for improving SiC laser slicing quality and contribute to the development of advanced wafer processing technologies.

ABSTRACT. Super-junction (SJ) is known to alleviate the tradeoff between breakdown voltage and specific on-resistance by applying the concept of charge balance. However, the most common fabrication method of SJ structure, Multiple Epitaxy and Implantation (MEI), is time-consuming and costly and money due to the process complexity [1]. On the other hand, hydrogen pretreatment is applied before epitaxial growth, which implanted atoms (usually Aluminum) might escape into the epitaxial chamber. In this work, we examine each step of the MPE process and propose suggestions to simplify the process. Fig.1 shows the main process steps of the experiment, representing one cycle of MEI process. Two 4H-SiC n-type epi-wafers with a 11-μm-thick- epi-layer and doping concentration of 8.01015 cm-3 were used. Al ion implantation with energy up to 2.5 MeV was carried out on half of the wafer, expected that there weren’t any Al atoms distributed within the surface layer of 0.3 μm. Next, one wafer underwent a 1700℃ post-implantation annealing (PIA) process. Surface etching of around 0.2 μm by H2 treatment was performed and the subsequent n-type epi-layer with thickness of 2.5 μm was grown on the two wafers. Table. 1 lists the sample ID and split conditions. Quality of the re-grown epi-layer was analyzed by Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. For DLTS analysis, Ti-contacted Schottky barrier diodes were fabricated. Fig.2 shows that whether or not PIA was performed, the epi-layer re-growth did not affect the Al distribution. There is no Al in the re-grown epi-layer, which proves that after neglecting the low-energy ion implantation step, there will be no Al atoms escape into the epitaxial chamber. Fig. 3 shows that the surface roughness (Rq) of the four samples is similar. Fig. 4 shows the result of DLTS measurement. All samples exhibit weak Z1/2 signal. The NI-NA sample has another signal at 400K, which assumed to be RD1/2 and may be produced during epitaxial growth [2]. Next, I-NA sample have a strong signal at 440~460K. Since the samples went through Al implantation, we assume the signal comes from ON1 and ON2a [3]. Last, the I-A sample shows an abnormal signal peaked at 500K. Compare to the previous sample, we supposed that annealing may convert the defect into new ones, resulting in the signal combining ON2a and ON2b [4-5]. Since the defect concentrations for some samples of I-A and I-NA are similar, if we skip PIA and keep on the MPE cycle, the defect concentration will not be affected, only the type of defect is altered. Fig. 5 shows the optical images of the molten KOH etched surface. There is no significant difference in threading edge dislocation (TED) and threading screw dislocation (TSD) density between two samples. In this work, we examined the impact of each process step of the MEI process on the quality of the subsequent epi-layer. Skipping the low energy implantation can avoid Al escape into the epitaxial chamber during growth of the subsequent n-epi layer. Surface roughness and the density of dislocation in the subsequent epi-layer are independent of PIA or not. The slightly increased deep-level defects can be improved by epitaxial process. Once p-pillar ion implantation and subsequent epitaxy can be performed sequentially, the cost and process complexity could be reduced greatly.

ABSTRACT. Ultraviolet (UV) laser annealing has emerged as a promising technique for localized, high-temperature processing of wide bandgap semiconductors such as silicon carbide (SiC), offering significant advantages over conventional rapid thermal annealing (RTA). Fluence optimization in UV laser annealing is critical for achieving high-performance ohmic contacts in SiC-based electronic devices. Ultraviolet (UV) laser annealing offers superior absorption in SiC compared to visible wavelengths, enabling highly localized thermal processing with minimal thermal diffusion. This is particularly beneficial for thin substrate applications, where conventional thermal treatments may cause substrate warping or device degradation. The shallow penetration depth of UV lasers ensures precise control over the annealed regions and facilitates effective dopant activation, resulting in improved electrical performance1,2. In this study, we investigate the formation of NiAl ohmic contacts on heavily nitrogen-doped 4H-SiC substrates using UV laser annealing at a wavelength of 355 nm. A 70 nm-thick NiAl layer was deposited onto the backside of the SiC substrate and subjected to laser annealing under varying fluence conditions (0.8 to 3.0 J/cm²). Post-annealing analysis revealed that the resulting reacted layer exhibited a substantial thickness increase, reaching up to approximately 200 nm. This unexpected expansion was attributed to multiple contributing factors, including Si out-diffusion from the substrate, enhanced interfacial reactivity induced by aluminum, and the formation of carbon clusters at the metal/SiC interface. X-ray diffraction (XRD) confirmed the emergence of secondary phases such as Al₂SiO₅ at high fluence levels, while transmission electron microscopy (TEM) revealed the presence of amorphous carbon accumulation, indicating SiC decomposition during laser exposure. Electrical characterization using the circular transfer length method (CTLM) demonstrated optimal ohmic behavior at a fluence of 2.3 J/cm², yielding a low specific contact resistance and a sheet resistance of approximately 0.35 Ω/cm². However, excessive fluence resulted in interfacial degradation and a loss of electrical performance, highlighting the critical importance of fluence optimization. We also explored the differences in laser annealing effects between front-side and backside irradiation, considering the influence of heat diffusion pathways and surface absorption behavior. Although the comparative effect of crystallographic polarity (Si-face vs. C-face) has not yet been experimentally evaluated, it is hypothesized that significant differences in silicide growth kinetics may arise due to their distinct surface chemistries and reactivities. Ongoing work will focus on this polarity-dependent silicide formation to provide further insights into the interfacial mechanisms and their impact on contact reliability. This study provides a comprehensive framework for optimizing UV laser annealing conditions for robust ohmic contact formation on SiC-based power devices. These findings underscore the importance of carefully controlling laser fluence and minimizing oxygen contamination during UV laser annealing. The results confirm that optimized UV laser annealing at 355 nm is a promising technique for forming stable and low-resistance ohmic contacts in 4H-SiC devices, including those fabricated on thin substrates.

ABSTRACT. Conventional diamond blade dicing typically results in a high density of chipping. To mitigate this issue, the blade's traveling speed needs to be significantly reduced—as low as around 2 mm/sec—which leads to unacceptably low productivity in mass production environments. Various alternative approaches, including laser dicing, scribing, and plasma technologies, have been explored; however, these methods remain impractical for widespread industrial application. In contrast, vertical vibration ultrasonic blade sawing offers several distinct advantages. It enables much higher dicing speeds—up to 20 mm/sec—while effectively eliminating chipping. Microcracks are expected to form just beneath the blade due to the hammering effect of the vertical ultrasonic vibration of the blade. Subsequently, the rotation action of blade will be followed to eliminate the cracked parts of the work piece. This process will lower the stress imposed from the blade to the work piece. As such, vertical vibration ultrasonic blade achieves faster machining and lower chipping density. Additionally, the vertical ultrasonic vibration technique greatly extends blade life. A single diamond blade can dice up to 45 wafers—approximately 15 times longer than conventional blades. Given these advantages, vertical ultrasonic blade sawing currently represents the most promising and practical solution among the available dicing technologies.

ABSTRACT. Silicon carbide (SiC) is a highly promising material for next-generation power devices due to its wide band-gap and high breakdown electric field. However, its high hardness and chemical inertness, pose significant challenges for conventional polishing techniques. Chemical mechanical polishing (CMP) process, which uses a slurry containing oxidizing chemicals and free abrasives, is commonly used for the final polishing of SiC wafer, but it has very low throughput and incurs high costs for purchasing and disposing of slurry. To address these issues, slurry-less electrochemical mechanical polishing (ECMP) was proposed by our research group. In ECMP, anodic oxidation first forms a soft oxide layer on the substrate surface; fixed abrasives that are softer than the substrate but harder than the oxide then remove only this layer, enabling high-efficiency damage-free polishing [1]. Replacing free abrasives with fixed abrasives eliminates problems of uneven distribution and agglomeration, while significantly increasing abrasive density and material removal rate (MRR). In slurry-less ECMP, the MRR is governed by the interplay between the surface-oxidation rate and the removal rate of the oxide layer. When oxidation proceeds faster than removal, the oxide film thickens, eventually suffering dielectric breakdown and degrading surface roughness. To obtain a high-quality finish, conventional practice suppresses oxidation in the final stage by lowering the current density, but this inevitably sacrifices MRR. Previous studies show that replacing the neutral NaCl electrolyte with alkaline KOH resolves this trade-off. The KOH solution produces an OH- rich layer on the substrate surface, which accelerated the etching reaction and continuously strips the oxide layer before dielectric breakdown can occur. Consequently, excellent surface quality was maintained even at high current densities. Moreover, the alkaline environment neither diminishes the overall oxidation rate-so MRR remained high-nor promotes corrosion of system components, further enhancing process reliability. To compare slurry-free ECMP characteristics of SiC under different electrolytes, polishing experiments were performed in constant-current mode with the setup shown in Fig. 1 and the experiment conditions listed in Table I. Following Ref. [2], the concentration of KOH electrolyte was determined to be 6 wt%. Figure 2 (a) shows the voltage response during ECMP. At a given current density, KOH requires a lower operating voltage than NaCl because the OH⁻‑driven etching reaction [2] produces a thinner oxide film and thus a lower interfacial resistance. Figure 2 (b) shows scanning white light interferometry (SWLI) images of the SiC surface before and after ECMP. Although both electrolytes markedly reduced the surface roughness, the sample polished in KOH still exhibited higher roughness and deeper scratches. These results suggest that the in-situ oxide layer served as a mechanical buffer between the abrasives and the SiC substrate. With NaCl, a moderately thick oxide layer redistributed the load on the abrasives, thereby suppressing scratches and further lowering surface roughness. Assuming that this hypothesis is correct, increasing the current density in KOH from 15 mA/cm2 to 25 mA/cm2 should thicken the oxide layer enough to achieve a low-roughness, scratch-free finish. Figure 3 shows the SWLI images obtained after ECMP using 6wt% KOH at 25 mA/cm2. A surface roughness comparable to that achieved with NaCl, while the MRR improved from 9.1 µm/h to 11.6 µm/h. Future work will systematically optimize the current density in KOH to further reduce surface roughness while maximizing MRR.

ABSTRACT. One of the keys of the success of silicon carbide (4H-SiC) over the other wide band gap semiconductors is the possibility to form SiO2 by thermal oxidation. This processing step is very important in SiC device technology. In fact, thermal oxidation followed by post-oxidation-annealings (POAs) is used for the gate insulator in 4H-SiC MOSFETs, can be adopted as a sacrificial process to remove surface defects, or to optimize the carrier lifetime by carbon interstitials injection. A modified Deal–Grove model, based on the established Si oxidation process, has been often invoked to describe SiC oxidation kinetics. Accordingly, the oxide thickness X is given by X2+AX=B(t+tau), where t is oxidation time, tau is related to an initial thickness, B and B/A are parabolic and linear rate constants, respectively. Despite the abundance of published papers on the topic, the oxidation data reported in literature exhibit wide variations and the mechanism of oxidation and/or oxynitridation after POA remain not yet fully understood. Commonly, POAs are performed in NO or N2O, where N2O has the advantage of nontoxicity with respect to NO. The nitridation in N2O is affected by the decomposition of the molecule, which critically depends on the annealing parameters. During POA in N2O, simultaneous oxidation takes place, whose activation energy has not determined yet. Finally, it is not yet established how the different oxidation or nitridation conditions may impact on the stress of the underlying SiC epilayer and if there is a correlation with the electrical quality of the interfaces. In this work, the thermal oxidation in “dry” O2 and N2O of n-type 4H-SiC (0001) epilayers was studied in the temperature range 1100-1200°C. After thermal annealing in O2 or N2O, the grown oxide thickness has been determined by measuring by AFM the step height of lithographic patterns defined in the oxide by wet etching. Then, MOS capacitors have been fabricated on epitaxial samples with a doping concentration of ND=1.8×1016cm-3 and characterized by C-V measurements performed at 1 kHz to assess the SiO2/SiC interface electrical properties. Finally, the strain induced by thermal oxidation processes was estimated by Raman spectroscopy using a laser with an excitation wavelength of 532 nm. The oxide growth kinetics of the (0001) face was described using the Deal-Grove model, determining an activation energy of 1.12 eV. Noteworthy, the oxide thickness formed after annealing in N2O is significantly lower than that obtained in O2. The activation energy associated with the N2O oxidation is consequently higher (2.50 eV). The C-V curves of the SiO2/4H-SiC MOS capacitors obtained with different oxidation and POAs conditions exhibited only a moderate hysteresis, while POA in N2O or oxidation in N2O produces an increase of the oxide thickness (decrease of the accumulation capacitance) with respect to the reference condition of 1150°C 2h in O2. Notably, POA in N2 leads to the best results in terms of Dit reduction close to the conduction band edge, even better than POA or oxidation in N2O for longer time. Finally, the transverse optical mode (FTO) E2 was used to evaluate the strain induced on the 4H-SiC by the processing. Raman mapping carried out on an untreated 4H-SiC sample, (“unstrained” reference) displayed an E2 peak distribution at 776.55 ± 0.04 cm-1. The oxidation in N2O and the oxidation in O2 followed by POA in N2, induced a higher red-shift and consequently a higher tensile strain on 4H-SiC compared to the O2 treatment. No evolution of the E2 peak position has been observed after thermal treatment in Ar, bringing back such strain effects to the formation of SiO2 film and not to the process temperature. These analyses allowed to speculate that tensile stress have a role in reducing the Dit, by increasing the distance between the active traps at the interface. However, to corroborate this hypothesis, a more systematic analysis of different oxidation conditions will be required.

ABSTRACT. To study the impact of proton implantation on carrier lifetime control, a process was conducted using protons with an energy of 200 keV and a dose of 1×1014 cm-2 on epitaxial 4H-SiC samples. Schottky diodes were then fabricated on these samples to assess variations in electrical performance under different annealing temperatures. Based on the variations observed in these samples through photoluminescence (PL) spectroscopy, conducted at both room temperature and 11 K, we decided to investigate the formation and evolution of deep levels within the bandgap through electrical measurements. The starting sample is a 4H-SiC substrate on which a monocrystalline epitaxial layer with a thickness of 5.5 µm and a doping concentration of 1.5×1016 cm−3 was grown. These samples then underwent proton implantation followed by different thermal treatments at 500°C, 800°C, and 1050°C for 30 minutes. PL measurements performed at both room temperature and 11 K revealed significant wavelength shifts. At room temperature, bandgap emission was observed at 382 nm, while green luminescence shifted from 525 nm to 500 nm as annealing temperatures increased. Low-temperature PL spectra showed ultraviolet emission at 390 nm, with additional peaks at 404 nm and 420 nm, indicating phonon interactions. [1] Subsequently, on the same samples, Schottky diodes with nickel metallization on both the front and back sides were created to be analyzed. Five samples were used for this study (Fig. 1): one with only epitaxial growth, one with only implantation, and three with different thermal treatments. C-V and I-V measurements were performed to characterize the properties of the Schottky diodes. C-V measurements revealed that the depletion capacitance of the diodes is higher in the sample with only epitaxy. The thermionic emission model was used to determine the barrier height and ideality factor from the I-V measurements (see Table 1). Various types of defects (point-like and band-like) were observed in the five samples by performing deep level transient spectroscopy (DLTS) temperature scans from 100 K to 600 K. Z1/Z2, a typical carbon vacancy defect in 4H-SiC epitaxy, was present in the sample with only epitaxy with an activation energy of 0.564 eV [2] and in every sample with some modifications in energy and shape. RD1/2, with activation energies between 0.869 and 0.941 eV [3], was observed only in the implanted sample and in samples annealed at 500°C and 800°C. EH6/7 was observed in the sample annealed at 1050°C with an activation energy of 1.24 eV [2][5]. The DLTS spectrum of the sample annealed at 1050°C showed the elimination of RD1/2, a defect due to implantation radiation [3]. Furthermore, peak intensity increased in samples with high-temperature annealing. A study was conducted to distinguish band-like and point-like defects by varying the filling pulse length[4]. By increasing the filling pulse from 10 µs to 100 µs, it was possible to observe an increase in peak intensity while maintaining the same peak position in the implanted-only sample, suggesting the presence of band-like defects. On the contrary, the epitaxy-only sample showed no peak intensity variation, suggesting point-like defects (Z1/Z2) (Fig. 3 and Fig. 4). The formation of defect clusters due to implantation radiation (RD1/2) and subsequent annealing is vividly captured in low-temperature photoluminescence measurements. As the temperature increases, a notable shift in emission at 450 nm is observed (Fig. 2). This shift is consistent with the phenomenon where clusters formed during implantation break apart, favoring the emergence of smaller defects. [6] In summary, the integration of DLTS and PL techniques reveals a comprehensive picture of defect dynamics in proton implanted 4H-SiC. DLTS uncovers the presence and evolution of deep levels, providing insights into activation energies and defect types influenced by implantation and annealing processes. Concurrently, PL measurements at varying temperatures highlight emission shifts, reflecting the transformation and fragmentation of defect clusters. Exploring additional annealing temperatures and further optimizing the implantation process could provide even greater control over the recombination centers within the epitaxy. This interesting line of research opens the way for the development of not only faster but also more efficient SiC power devices, marking a significant jump forward in semiconductor technology.

ABSTRACT. Silicon carbide (SiC), a wide-bandgap semiconductor, has attracted considerable attention for next-generation power devices and high-power LED applications due to its excellent thermal conductivity, high breakdown electric field, and wide temperature stability. However, optimizing the performance of SiC devices requires the formation of low-resistance contacts between the metal electrode and SiC, which is critically depends on the quality of the silicide layer.[1] Traditionally, silicide formation on the SiC surface has relied on high-temperature rapid thermal annealing (RTA), typically performed at temperatures above 900°C for several minutes to promote the reaction between the deposited metal layer and the SiC substrate.[2] While RTA enables the formation of low-resistance Ni₂Si phases at sufficiently high temperatures, it also presents significant limitations, including thermal damage to the substrate, formation of large graphite-like carbon clusters at the interface, and poor adhesion. These issues become more pronounced for thinned SiC wafers, which are increasingly used in advanced vertical device structures and are particularly sensitive to high thermal budgets [2]. To address these challenges, this study introduces laser annealing as an alternative approach and systematically investigates the relationship between localized heat effects and key process parameters. Laser annealing is recognized as a technique capable of delivering high energy to localized regions within a short time, thereby enabling effective formation of silicide (NiSix) with minimal thermal damage to the substrate. This approach is particularly advantageous for wide-bandgap semiconductors such as SiC, as selective laser annealing allows for more precise process control and reduced carbon clustering compared to RTA [3]. In this study, to investigate the mechanism of Ni silicide formation, we conducted experiments on SiC substrates using different laser wavelengths and analyzed the SiC–Ni silicide interface as well as the resulting electrical properties. All experiments were conducted on the C-face of n-type 4H-SiC substrates with Ni/V thin film (~75 nm). An annealing process was performed by varying the energy density (1.5–3 J/cm2) using a wavelength range of 248–355 nm. The chemical bonding states of the formed Ni silicide layers were first analyzed by Raman spectroscopy to compare the annealing effects of different laser wavelengths and energy densities. Subsequently, scanning electron microscopy (SEM) and transmission electron microscopy (TEM) were used to observe the interfacial morphology and structures. The results revealed that higher pulse numbers and shorter laser wavelengths led to an increase in carbon cluster formation within the silicide layer. Specifically, accumulated carbon clusters were observed at the SiC/silicide interface, and non-uniformly distributed carbons were detected throughout the silicide. These findings suggest that carbon behavior during silicide formation is strongly influenced by the laser processing conditions. Figure 1 shows cross-sectional TEM images of Ni/V layers deposited on n-type 4H-SiC substrates after laser annealing with three different laser wavelengths. As shown in Figure 1(a), the sample was annealed using a 248 nm wavelength laser. Among the three samples, this condition resulted in the thickest Ni silicide layer and the most pronounced structural changes. Significant accumulation of carbon clusters was observed at the interface between the Ni silicide and the SiC substrate.[4] Notably, a defective SiC layer is observed between the substrate and the carbon clusters, indicating that the higher thermal budget induces additional interfacial reactions and damage.[5] Carbon clusters are also irregularly distributed throughout the silicide layer, rather than being confined to the interface. These carbon-rich features are consistent with the formation of thick (5–6 nm) continuous graphite layers and large (30–70 nm) carbon clusters reported after high-temperature laser or RTA processing [2]. In contrast, Figure 1(b) shows the sample annealed with a 308 nm wavelength laser. While the overall microstructure is similar to that in (a), the thickness of both the Ni silicide and the defective SiC layer at the interface is reduced. The carbon clusters at the interface are also smaller compared to those in (a). Nevertheless, irregularly distributed carbon clusters are still present within the Ni silicide layer, similar to the 248 nm case. Figure 1(c) shows the sample annealed with a 355 nm wavelength laser. In this case, the accumulation of carbon clusters at the interface is less uniform, and the defective SiC interlayer is relatively thinner than in the other samples. These results indicate that as the laser wavelength increases, both the size of the carbon clusters and the thickness of the mixed (defective) interlayer decrease. These observations confirm that higher laser energy densities and shorter wavelengths promote more extensive interfacial reactions, leading to thicker silicide layers, larger and more dispersed carbon clusters, and the formation of defective SiC interlayers. Careful optimization of the laser annealing parameters is therefore essential to minimize interfacial defects and achieve reliable, low-resistance ohmic contacts on SiC substrates. Further investigation into the pulse-dependent structural evolution of SiC–Ni silicide to advance laser annealing parameter optimization will be presented during the conference.

ABSTRACT. With the growing application of wide bandgap semiconductor materials such as silicon carbide (SiC) in power electronics, the development of efficient and low-damage processing methods has become a research focus. Traditional diamond wire sawing has limitations in efficiency and material loss, positioning laser-modified slicing combined with precision grinding as a promising alternative. However, due to the intrinsic anisotropy of 4H-SiC, significant differences exist between the C-face and Si-face in terms of hardness and fracture toughness. These differences may lead to distinct grinding behaviors and tool wear characteristics. In this study, we investigated the comparative grinding response of C-face and Si-face on laser-sliced high-purity semi-insulating 4H-SiC wafers, with the aim of elucidating the underlying mechanisms and informing the development of face-specific grinding strategies.

ABSTRACT. High-κ dielectrics are attractive candidates for SiC power MOSFETs for voltage classes of less than 3.3 kV due to their reduced ON resistances (RON,SP ), minimal hysteresis during switching, and improved ruggedness when compared to their SiO2 counterparts. However, there are still several challenges when implementing various dielectrics in commercial grade SiC MOSFETs. Most of the high-κ insulators suffer from undesired polycrystalline phase formation due to the high temperature budgets (Tprocess > 1000°C) needed for the manufacture of SiC power MOSFETs. In addition, such materials often come with undesired flat band voltage (VFB) shifts in MOS gate stacks to SiC channels, hindering their true potential as the next generation gate dielectrics. Finally, such materials often offer insufficient conduction and valence band offset to 4H-SiC resulting in excessive leakage current during on-state operation. Among various high-k dielectrics, SiNx nonetheless stands out as a promising candidate due to its processing compatibility with the high thermal budgets necessary for SiC MOSFET manufacturing (Tmax > 1000° C) and wide enough conduction band offset (ΔEC) to 4H-SiC (ΔEC > 1.5 eV) necessary for reliable device operation. In here we present for the first time our detailed investigation on SiNx based dielectrics based on 1.2 kV rated SiC power MOSFETs. We have assessed SiNx as stand-alone gate insulator material and its thickness dependence on the flat band voltage (VFB) of MOS structures. Two methodologies are proposed to tune the VFB of SiNx containing gate dielectric stacks, namely the use of a high-k + SiNx stack and thermal oxide + SiNx stack. Critical characteristics of the proposed stacks, i.e., VFB, electrical leakage density, hysteresis and interface trap density (DIT) are compared in MOSCAPs. An in-depth comparison of the subthreshold and output characteristics of the 1.2 kV rated SiC power MOSFETs with aforementioned gate stacks is finally provided. Fig. 1 shows the C-V characteristics of the SiNx based MOSCAPs with various dielectric thicknesses. VFB of the SiNx gated MOSCAPs lie within the negative gate voltages that translate into negative VTH for the studied thickness levels and an undesired normally on MOSFET device. This observation hint at the limitations of stand-alone application of SiNx dielectric for SiC MOSFETs. Fig. 2 shows the C-V characteristics of the proposed bilayer high-k + SiNx stack and thermal oxide+ SiNx stack respectively. Both stacks have VFB values translating into positive VTH in the MOSFETs. Fig. 3 shows the DIT characteristics and electrical leakage densities of the bilayer stacks. High-k + SiNx stack shows improved interface properties compared to thermal oxide+ SiNx stack, whereas both stacks offer > 9 MV/cm dielectric breakdown fields. Proposed dielectrics are implemented in 1.2 kV rated SiC power MOSFETs. Their subthreshold characteristics and linear region of the output characteristics are compared at room temperature as well as at 150 °C. Fig. 4 shows the room temperature comparison of subthreshold characteristics with VDS = 20V and the linear region of the output characteristics obtained with VGS = 15 V. Both configurations offer positive VTH values yielding normally off operation. High-k + SiNx stack shows improved characteristics in terms of subthreshold slope as well as on state resistance compared to thermal oxide + SiNx stack. Fig. 5 shows the comparison at 150°C. Thanks to the reduced VTH shift from room temperature values, high-k + SiNx stack provides improved subthreshold characteristics compared to thermal oxide + SiNx stack. Overall, the high-k + SiNx approach offers distinct advantages in the subthreshold and on-state characteristics compared to thermal oxide + SiNx stack due to its superior interface properties as well as the potential to offer higher COX to improve operational reliability and stability. Therefore, it stands out as a promising candidate for next generation SiC power MOSFETs.

ABSTRACT. Dopant atoms in SiC were evaluated by Atom Probe Tomography (APT). APT is a method with excellent spatial resolution and quantification capabilities, and it provides three-dimensional elemental distributions. In this study, we evaluated the concentration and distribution of phosphorus atoms ion-implanted in SiC followed by annealing and it is found that phosphorus atoms are obviously aggregated.

ABSTRACT. This study investigates a novel avalanche stress method for evaluating impact ionisation phenomena in power devices. In a previous work we proposed and applied this method to 1200 V bulk 4H-SiC Junction Barrier Schottky diodes. In this study, we extend this method by investigating new voltage ratings (>1700V), new engineered substrate (SmartSiCTM) and also PiN diodes.

ABSTRACT. This work presents a trench-based superjunction platform technology scalable across a wide voltage range, from 1.2 kV to 3.3 kV. Demonstrated structures include both full SJ implementations at 1.2 kV and Semi-SJ devices rated at 1.7 kV, 2.3 kV, and 3.3 kV. The platform supports both MOSFETs and Schottky diodes, achieving trench depths up to 9 μm. Key process innovations include tilted implantation profiles optimized for uniform charge balance, along with advanced termination designs ([1-3])to maintain high breakdown voltages with minimal area overhead

ABSTRACT. Silicon carbide (SiC) has emerged as a highly promising semiconductor material for power devices due to its wide bandgap, low intrinsic carrier concentration, high breakdown electric field and other advantageous physical properties[1]. Because of the low oxidation rate of SiC, the field oxide (FOX) of SiC devices is formed by chemical vapor deposition (CVD) instead of thermal oxidation. Recently, it has been reported that the use of LOCal Oxidation of SiC (LOCOSiC) to form the FOX results in better oxide quality and LOCOSiC FOX has also been shown to provide improved isolation capability [2] and enhanced radiation hardness [3][4]. In this work, LOCOSiC FOX has been applied to commercial 650V JBS SiC power devices on 6-inch wafers for the first time. We have verified the blocking characteristics, conduction characteristics, switching performance, and reliability of LOCOSiC devices compared to standard CVD devices. Fig. 1 shows the cross-sectional schematic and process flow of the devices, and the cross-sectional image around the FOX edge inspected by Scanning Electron Microscope (SEM) is shown in Fig. 2. A smooth topography is obtained. Fig. 3 shows the statistical distribution of breakdown voltage (VBD), extracted at reverse leakage current of 100 A. The VBD of the LOCOSiC devices is 90 V lower than that of the CVD devices, which is attributed to excessive consumption of the ion implantation in the Floating Guard Ring (FGR) region during the oxidation process. This problem can be mitigated by increasing the implantation energy of the FGR. Fig. 4(a) shows the statistical distribution of the forward voltage (VF) and Fig. 4(b) shows the Ideality factor (n) and effective Schottky barrier height (bn,eff). The VF of the LOCOSiC device is slightly higher than that of CVD device because of poorer n and higher bn,eff, which may be attributed to the stress of the Si3N4 layer [5]. To address this issue, we propose a process improvement (LOCOSiC-modify), which involves reducing the Si3N4 thickness to 100 nm and applying a 20-nm-thick sacrificial oxidation before metal deposition. The LOCOSiC-modify device exhibits a significant improvement in forward characteristics, with its characteristics closely match that of the CVD device. In a JBS device, during the on/off switching transient, a reverse recovery phenomenon occurs, causing both high voltage and high current simultaneously, leading to significant power consumption. In LOCOSiC devices, carriers recombine rapidly through the defect layer under FOX, resulting in a lower carrier lifetime and better reverse recovery performance. Compared to the CVD device, the maximum reverse recovery current (Irr) and the reverse recovery time (trr) were reduced by 22% and 13%, respectively, as shown in Fig. 5 and Table I. High Temperature Reverse Bias (HTRB) is a standard reliability test item for SiC devices, especially for edge termination structures. In this work, 77 devices were tested at a temperature of 175 °C under a reverse bias voltage of 100% of the rated withstand voltage level, 650 V. The detailed variations in device parameters before and after stress for 1000 hours are summarized in Fig. 6. The key parameters, such as VBD, VF, and reverse leakage current (IR) of all samples changed less than 5% indicating that the defect layer of LOCOSiC process does not degrade the HTRB reliability. In summary, LOCOSiC isolation technology was used in commercial devices for the first time. With process optimization and process flow improvement, LOCOSiC devices exhibit identical conduction and blocking characteristics and superior switching performance compared to CVD devices and passed the HTRB test, demonstrating excellent performance and reliability.

ABSTRACT. SiC is still undergoing development to improve its crystal quality, aiming to achieve electrical yields above 90% on 200 mm wafer scale. At present, the main challenge is the presence of crystallographic defects in both substrates and epitaxial layers. A primary focus is to evaluate the "killer ratio" of each defect type, categorizing them into negligible and harmful defects, with the latter negatively impacting the device’s final electrical performance. This classification facilitates thorough product screening before final application. Reliability testing is a critical component in the semiconductor industry, concentrating on assessing the performance, durability, and quality of electronic components and devices under various conditions. These tests are typically customized based on specific technology, device, and possible failure mechanisms during production and qualification. Examples of such tests include High Temperature Reverse Bias (HTRB), High Temperature Gate Bias (HTGB), Dynamic Reverse Bias (DRB), and Body Diode Stress (BDS). These tests help establish lifetime and durability models for the devices. Although SiC MOSFET devices offer promising performance in terms of high voltage blocking, high-temperature operation, and fast switching frequencies, several challenges remain. Beyond electrical failures caused by defects introduced during front-end processing steps such as implantation, oxidation, and thermal annealing—which can lead to issues like threshold voltage instability primarily due to a suboptimal MOS interface [1]—it is important to assess how epitaxial defects affect device electrical performance. To investigate failures in SiC devices (e.g., 650V MOSFETs) following reliability testing, Emission Microscopy (Em.Mi.) is used to pinpoint the exact failure location. Once the emission site, indicative of a possible epitaxial defect, is identified, the device layers are removed via chemical wet etching. Subsequently, molten KOH etching is applied to expose surface defects on the SiC, enabling correlation between the emission failure and the underlying material structure. The KOH etching of delayered devices was conducted at 500°C for 10 minutes, followed by optical microscopy to classify defects and establish any correlation with the device failure sites. Over time, a classification system for dislocations observed in KOH-etched SiC has been developed through numerous experiments on n-type epitaxial layers with a typical doping concentration of about 1.6×1016 atoms/cm³. Literature indicates that this doping level is ideal for accurate defect detection and classification [2–3]. Figure 1 (a-d) presents the case of a threading screw dislocations (TSD) related failure. The morphological characteristics of the SiC surface after full device delayering were examined using SEM and AFM, as shown in Figure 1a. A low-magnification SEM image (10 kV) reveals the hotspot area corresponding to the Emission Microscopy (Em.Mi.) emission, with a FIB cross-section serving as a reference to identify this region at higher magnification. In Figures 1b and 1c, SEM analysis at higher magnification (3 kV) reveals a triangular-shaped defect at the hotspot site, indicating a dislocation originating from the substrate and propagating into the epitaxial layer. AFM imaging (Figure 1d) further confirms surface pitting associated with this defect. As noted in [4], small depressions measuring 0.5–1 μm appear at the locations of TSD. These depressions result from uneven step flow around dislocations during growth and are typically shallow, with depths between 3 and 20 nm. The shape and depth of these features are strongly influenced by growth conditions, including in situ etching and cooling. When deeper depressions form, geometric effects such as electric field crowding can adversely affect device performance, potentially causing failure. Furthermore, KOH etching at the die level has shown a clear link between device failures and the presence of TSDs. This method effectively uncovers that electrical failures are closely tied to the initial material quality. Although KOH molten etching is a destructive process, it remains a cost-effective and straightforward technique for evaluating dislocation density [5]. The etching is conducted in molten KOH within a nickel crucible heated to 500°C for 5 minutes. The etching duration varies significantly depending on the material’s doping level, resulting in different etching times and optimized temperatures for the substrate and the epitaxial layer. Dislocation exposure, which can severely affect device performance, is a highly effective technique for correlating defects with failure. Figure 1(e-h) presents also a micropipe related hard failure caused by a crystallographic defect. The drain current leakage monitoring, depicted in Figure 1e, reveals a sudden increase after about 0.5 hours, indicating a hard failure where the device becomes entirely unusable. Leakage currents between the drain and gate (with the source disconnected) and between the gate and source (with the drain disconnected) are also shown. Both current profiles indicate a short circuit between terminals (IDGO and IGSO). Moreover, the IDSS test (drain leakage with gate and source shorted and grounded) demonstrates similar short-circuit behavior. The Em.Mi analysis pinpoints the emission site across the device. Further examination involved delayering, with all chemical etching performed in wet conditions using 40% hydrofluoric acid (HF) on a chemical bench. Layers were sequentially removed until the SiC epitaxial surface was exposed. A hexagonal hole is shown at the bottom of Figure 1e. Subsequent KOH etching revealed a structured defect, which was analyzed by SEM, as presented in Figure 1 (f-h).

ABSTRACT. Silicon carbide (SiC) has been increasingly used in high-voltage, high-power applications. Low conduction loss is desired and there are many efforts to improve the on-current and specific on-resistance of SiC device, for example through process improvements [1-3], cell topologies [4], and charge modulations [5]. Previously, we demonstrated a >2.5x on-current improvement in 1200 V-rated 4H-SiC based MOSFET through the application of p-well voltage [6]. In this work, we extend this concept to 3300 V-rated 4H-SiC VDMOSFET, achieving ~2x on-current enhancement.

ABSTRACT. SiC MOSFETs have been widely used in high-frequency applications due to high-speed switching characteristics. However, as the switching speed increases, the di/dt of the device also increases. The high di/dt causes an unwanted potential shift due to the parasitic inductance, ultimately leading to false turn-on [1]. In half-bridge inductive switching, the false turn-on mechanism of the switching device is well established. On the other hand, the displacement current movements in the high-side (HS) device operating in freewheeling mode through the body diode have not been identified [2]. In this paper, the current hump phenomenon of the SiC MOSFETs, caused by the HS MOSFET’s false turn-on during the low side turn-on transient in the inductive switching circuit, was analyzed. In addition, the effect of the HS MOSFET’s false turn-on dependence under different parasitic inductance and load current level was analyzed. Double pulse tests were used to confirm the false turn-on phenomenon and Sentaurus TCAD simulation was used to analyze the internal behavior of the device [3]. The effect of the parasitic inductance at the HS MOSFET’s gate-to-source will be verified with two case experiments as shown in Figure 2. Figure 3 shows the measured turn-on waveforms of the 1.2 kV SiC MOSFET varying the lead length. As expected above, because the parasitic inductance (HS gate-to-source) of the full lead length condition is larger than that of the half lead length, a more significant potential shift occurs due to the di/dt. Due to this potential shift, the HS gate-to-source voltage exceeds the threshold voltage (VTH), resulting in a false turn-on of the MOSFET, while simultaneously, the shoot-through current flows to the low-side (LS). Given that the LS switching MOSFET must also accommodate the unintended shoot-through current along with the reverse recovery current of the HS body diode, increases in both the drain current and gate-to-source voltage of the low-side are observed. Figure 4 shows the measured turn-on switching waveforms of the 1.2 kV SiC MOSFETs with the various load current level (5.37, 10.7, and 21.5 A, respectively). Here, the LS MOSFET’s switching speed decreases as the load current (IL) increases. This originated from the different plateau volage. The gate plateau voltage (VLP) and the gate current (ILG) of the LS MOSFET during the turn-on transient can be expressed as:

VLP = VTH + ILD/gm (1) ILG = Von-VLG/RG = Von-VLP/RG (when VLG = VLP (2)

During the LS turn-on, the LS gate plateau voltage (VLP) increases as the load current (IL) increases and the LS gate current (ILG) decreases as the VLP increases prolonging the transient time (slow switching speed). However, as shown in Figure 1, the potential shift in the high-side gate-to-source voltage (VHGS) due to the parasitic inductance is a function not only of the change in the time but also of the change in the current at each terminal. Consequently, although the turn-on switching speed decreases with the increasing load current, the magnitude of the freewheeling current at the HS increases. Since the influence of the load current level is more dominant than that of the switching speed, the VHGS exhibits a larger peak value as the load current increases. This demonstrates that, despite the slower turn-on switching speed at the higher load current levels, the false turn-on occurs more readily.

[1] M. Mandal, S. K. Roy and K. Basu, APEC, 2024, pp. 2456-2460. [2] K. Sobe, T. Basler and B. Klobucar, PCIM Europe, 2019, pp. 1-7. [3] H. Kang, E. M. Findlay and F. Udrea, IEEE Transactions on Electron Devices, 2020 vol. 67, no. 6, pp. 2478-2481

ABSTRACT. We present TCAD-based modeling of the physical properties of 3C-SiC/4H-SiC (3C/4H) heterostructures, which have been successfully fabricated using the simultaneous lateral epitaxy (SLE) method. Material parameters for both 3C-SiC and the 3C/4H heterointerface were implemented into TCAD to simulate the C–V characteristics of MOS structures. A key consideration in the modeling is the spontaneous polarization of 4H-SiC, which induces a negative fixed charge at the heterointerface. For p-type structures, the C–V characteristics are similar between 3C-SiC and the 3C/4H heterostructure, due to the small valence band offset and the presence of hole carriers. In contrast, n-type MOS structures on the 3C/4H heterostructure exhibit a significant reduction in capacitance, attributed to the formation of a hole layer and thick depletion regions at the heterointerface. These findings highlight the impact of polarization-induced charge and band discontinuity on carrier distribution and device behavior, providing valuable insights for the design of power SiC MOSFETs utilizing 3C/4H heterostructures.

ABSTRACT. This paper investigates the impact of cell topology on switching performance of 4H-SiC vertical double diffusion MOSFETs (VD-MOSFETs) by comparing devices with strip and hexagonal layout. Measuring result reveals that high channel density of hexagonal layout can reduce Ron,sp for 20.8%, but higher capacitance of hexagonal layout also leads to poor switching characteristics, as tr and tf may increase for 56ns and 27ns respectively, turn-on/turn-off switching loss energy (Eon/Eoff) would increase for 10% and 45.8%.

ABSTRACT. The conduction performance of 4H-SiC MOSFETs is heavily affected by the processing of the SiO2/4HSiC interface [1]. In particular, the field effect channel mobility (µFE) and the ON-resistance (RON) [2,3] can be improved by post-oxidation- or post-deposition-annealing (PDAs) in NO [4]. However, although mobility is enhanced, introducing nitrogen during PDA can create trapping states at the SiO2/4H-SiC interface, potentially negatively affecting the stability of the threshold voltage (Vth) [5,6]. In this context, it is crucial to investigate the evolution of not only the interface state density near the 4H-SiC conduction band (Dit), but also those near the valence band, as well as the near-interface oxide traps (NIOTs) that may form during extended PDAs in NO. To achieve this goal, MOS capacitors are not appropriate devices to be studied, but lateral MOSFETs allow to explore the whore 4H-SiC band gap. In this paper, experimental and computed capacitance-voltage (C-V) measurements were obtained on different lateral MOSFETs fabricated PDA with different duration at 1175 °C in NO [7] in order to investigate the electrical evolution of both Dit across the whole semiconductor wide band gap at the SiO2/4H-SiC system. The MOSFETs were characterized acquiring the capacitance–voltage (C-V) curves, in a CASCADE Microtech probe station equipped with a Keysight B1505A parameter analyzer. The C-V and the Dit were computed using a MATLAB home designed script. Fig. 1 shows the C-V curves collected at 1 kHz from negative toward positive gate bias (VG) values measured on the MOSFETs subjected to PDAs in NO for 10, 20, 50, and 120 min respectively. As can be noticed, the slope of the C-V curves increases with increasing the NO annealing duration. This behavior indicates an evolution of the Dit profile correlated to the NO annealing duration. Fig.2 shows the energy position of the discrete energy level taken from literature among bulk defects (such as carbon clusters, silicon or carbon vacancies etc.) [8] and interface defects produced by the NO molecule [9]. Table I summarizes the characteristics of the Dit centers prerogatives used for the MATLAB iterative loop simulation. This method allowed to evaluate the modification produced by the PDA across the whole 4H-SiC band gap modifying each single discrete center. Fig.3 shows – as an example – the fitting of one experimental C-V curve (PDA at 120 min) using the MATLAB iterative loop simulation. Fig.4 summarizes the calculated Dit profiles on the whole band gap for the different PDAs on the different MOSFETs. As can be seen, the NO PDAs duration induced a reduction in the exponential tail of the Dit profile close to the 4H-SiC conduction band edge, but it is also reduced the states below the mid-gap and close to the valence band edge. These mixed experimental-computed results are coherent with an increase of the field effect channel mobility (µFE) and a reduction of the Vth instability once the PDA is long enough as previously reported [10]. With these findings it is possible to conclude that prolonged NO PDAs indices benefits not only close to the conduction band edge, but also close to the valence band in contradiction to some early studies that pointed out a detrimental effect in 4H-SiC band gap bottom [11]. A fine control of the NO PDA is still required to improve the MOSFET interfacial transport and mitigating the threshold voltage instability.

ABSTRACT. Silicon carbide (SiC) Schottky barrier diodes (SBDs) have become key components in power electronics due to their excellent high-voltage and high-temperature tolerance and fast switching capability[1]. However, increasing the device area to improve the current-carrying capability leads to an increase in reverse leakage current (IR), a decrease in yield and a decrease in high-temperature conductivity[2-3]. This paper addresses these issues by developing 750V/100A and 1200V/100A SiC SBDs on 6-inch wafers, achieving breakthroughs in current density, cost-effectiveness, and thermal stability. The simplified cross-section of the SiC SBD structure is shown in Fig. 1(a) and the picture of samples are shown in Fig. 1(b) and (c). The yield of the 750V/100A and 1200V/100A SiC SBD on 6-inch wafer is 85.4 % and 76.4 %, respectively. The innovative use of epitaxial etching technology to prepare the termination P+ region significantly reduces the manufacturing cost compared to the traditional ion implantation process while realizing excellent termination protection. With this technology, the reverse leakage currents in the range of 3 ~ 20 μA (typical valus is 13 μA ) for 750V/100A devices with reverse voltage (VR) is 750V and 6 ~ 30 μA (typical value is 14 μA) for 1200V/100A devices with VR = 1200V can be realized. By optimizing the deposition process and interface treatment of titanium (Ti) Schottky metal, 750V/100A devices showed a VF of 1.68 V (at 30°C) at 100 A, corresponding to a current density of 465 A/cm², while 1200V/100A devices showed a VF of 1.75 V (at 30°C) and a current density of 257 A/cm². The ideal factor n for both is as low as 1.01 and 1.04, respectively, indicating effective control of interfacial defect density. The static characteristics and temperature stability of devices are evaluated at various temperatures from 30 °C to 240 °C. The forward characteristic curves at small currents are shown in Fig. 2(a) and Fig. 2(c). The Schottky barrier height (SBH) is 1.31 eV for 750V/100A SiC SBD, while the 1200V/100A SiC SBD has SBH = 1.14 eV, demonstrating excellent Schottky contact characteristics. As shown in Fig. 2(b) and 2(d), due to the degradation of the body electron drift velocity with the increased temperature, VF shows significant positive temperature coefficients, rising to 2.54 V (ΔVF=0.86 V) for the 750V/100A device and 3.19 V (ΔVF=1.44 V) for the 1200V/100A device at 240 °C. Fig. 3(a) and 3(b) present the reverse characteristics of these two devices. They can operate normally at the extreme temperature of 240°C, and the IR is 1.3 mA at VR = 750 V for the 750V/100A device, and 1.8 mA at VR = 1200 V for the 1200V/100A device. These temperature-dependent properties outperform the silicon-based device, proving the effectiveness of the termination protection structures and the high temperature stability of the silicon carbide material. Thus, the device not only has high application potential in new energy vehicles, photovoltaic inverters and industrial motor drives, but can also be used in high-temperature environments such as aerospace.

[1] T. Kimoto, J. Appl. Phys. 54, 040103 (2015). [2] H. Fujiwara, M. Konishi, T. Ohnishi, T. Nakamura, K. Hamada, T. Katsuno, Y. Watanabe, T. Endo, T. Yamamoto, K. Tsuruta, and S. Onda, Mater. Sci. Forum 679–680, 694 (2011). [3] T. Nakamura, T. Miyanagi, I. Kamata, & H. Tsuchida, Mater. Sci. Forum 527–529, 927 (2006).

ABSTRACT. The measurement of thin silicon dioxide (SiO₂) layers on silicon carbide (SiC) substrates is crucial because these layers serve a variety of critical functions in electronic and optoelectronic devices. Silicon carbide’s superior electrical and thermal properties make it a preferred material for high-power, high-frequency, and high-temperature applications [1]. When deposited on SiC, thin SiO₂ films act as preconditioning layers, and gate oxides, precise measurement of these oxide layers is important to ensure both optimal functionality and extended device longevity. In addition, monitoring the efficiency of SiO2 hard mask etching is key to check if the oxide has been totally removed or if there is any (very) thin oxide left because this could hinder a subsequent process step. Previous studies [2] report that spectroscopic reflectometry often lacks sufficient sensitivity for measuring SiO₂ layers thinner than 50 nm—and especially below 10 nm. In contrast, spectroscopic ellipsometry (SE) serves as a sensitive, absolute measurement technique which measures the change of the polarized light upon reflection from a sample. The results are presented by a spectra pair where  is the ratio of the absolute value of the Fresnel reflection coefficients in the p and s directions and  is the phase shift between the p and s components. When the incidence angle is near the Brewster angle of the SiC substrate, SE achieves robust sensitivity, as the polarization component in the plane of incidence diminishes and ideally undergoes a sudden 180° phase change () when the layer thickness is 0 nm. With increasing layer thickness, the slope of phase change () is flattening (Fig. 1) providing sensitivity for the very thin layer thickness measurement. Selecting an incidence angle around the Brewster angle is thus critical for obtaining accurate measurements. Measuring thin SiO₂ films on SiC surfaces becomes more complex due to the anisotropic properties of the substrate [3]. These properties can introduce backside reflections that appear as interference fringes in the spectroscopic data (example: 2.9 nm SiO2 layer on 4H-SiC substrate) (Fig. 2). To address this issue, a precisely configured microspot system is essential for reducing or eliminating backside reflections, thereby minimizing spectral interference. The samples in this study comprised native oxide on 4H-SiC or etched oxide hard masks on 4H-SiC with oxide layers ranging from 1 nm to 10 nm in thickness. The instrument used was an SE-2000 spectroscopic ellipsometer equipped with an automatic goniometer and an Ultra Microspot option. In practice, the Ultra Microspot employs a pinhole in front of the light source to further decrease the measurement spot size and mitigate unwanted reflections. During ellipsometry data evaluation, parametric models are applied to describe the anisotropic backside reflections. Incorporating additional parameters, such as the substrate thickness, can yield deeper insights into the sample. However, this added complexity can render the modeling approach impractical for routine industrial applications, even though it remains scientifically valuable. Overall, this study emphasizes the combined importance of using a microspot system and optimizing the incidence angle to overcome the inherent challenges of measuring thin SiO₂ films on SiC.

ABSTRACT. Nowadays, the requirement for electronics in high-temperature and high-radiation environments has been increasing. Recently, 4H-SiC semiconductors, which have a wide band gap, higher breakdown field strength and thermal conductivity, have become a potential candidate for high temperature and high radiation applications. In this work, a 4H-SiC 2-bit decoder circuit was fabricated and measured to realize CMOS image sensors and CPUs for harsh environments. From the measurement results, the output signals show correct logical values, and the 4H-SiC CMOS 2-bit Decoder Circuit successfully operated. The relation between circuit output characterization and device characterization were also discussed.

ABSTRACT. Semiconductor devices that have the ability to operate in harsh environments have so many important applications. Short channel MOSFET is able to increase current value. However, at the short channel MOSFETs, we need to consider the short channel effects. In this work, for suppressing the short channel effects, LDD structure (lightly doped drain structure) was introduced in 4H-SiC MOSFETs. Moreover, we investigated the effect of the LDD structure in 4H-SiC n-MOSFET with different LDD lengths. By introducing the LDD structure, drain currents were sufficiently saturated and ideal characteristics were obtained. Finally, we show the possibility of the LDD structure for advanced 4H-SiC integrated circuits.

ABSTRACT. Silicon Carbide (SiC) MOSFETs are increasingly widespread and researched in power device applications due to their many advantages, and trench structures can further enhance their properties. The vertical channel in trench MOSFETs increases integration density, heat dissipation and channel mobility, simultaneously reducing on-resistance, enabling the production of more efficient devices with lower power consumption [1, 2]. Trench structures are fabricated in a multi-step process, involving different etching steps [3]. Trench formation in SiC is usually carried out using dry etching processes. During the process, SiO2 serves as masking material, and the shape of the hard mask (HM) has a significant influence on the shape of the final SiC trench [1]. A certain sidewall angle (~90°) is required for trenches to obtain a high charge carrier mobility, to minimize the interface states between the SiC sidewall and the gate oxide, and to avoid cavities during the subsequent polysilicon filling. In addition to the shape, the depth of the trenches is also a critical parameter to obtain the length of the channel that allows the desired properties to be achieved [1, 2]. There are many process steps where it is important to monitor whether the structure meets the requirements for an optimal trench MOSFET device. Optical critical dimension metrology (OCD) offers a fast, non-destructive, non-contact method to investigate the geometrical parameters of the structure (sidewall angle (SWA), depth, critical dimension (CD) parameters, etc.). This is a model-based method; thus, an accurate theoretical model of the trench structure has to be built for accurate evaluation. To characterize the trenches, Spectroscopic Polarized Reflectometry measurements are performed on the wafers, the measured spectra are also simulated by a fast and accurate model. Then the critical dimensions are extracted through nonlinear regression, by fitting the model parameters to match modelled and measured spectra. With an optimized evaluation algorithm, this allows fast full-wafer mapping and tight process control in many steps of the process. In this contribution, we present the advantages and results of OCD evaluation of two types of structures. Several samples were fabricated according to the process described in Rusch et al. [1]. The SiC trenches have 0.8 μm width, 1.3 μm depth and 2 μm periodicity. In the first example (Fig. 1), the wafer has already gone through the HM etching process and the characterization of the dimensions of the oxide mask is performed. The HM defines the shape and width of the final trench; therefore, this process step is critical to monitor. The second example (Fig. 2) is a case of SiC trench etch monitoring right before hard mask removal. The presented optical method allows the monitoring of both the SiC trench etch depth and the remaining HM thickness; therefore, in this step, it is possible to contain the etch process. The OCD models were built based on scanning electron microscope (SEM) measurements performed near the OCD measurement site. Fig. 1 and Fig. 2 show the SEM and OCD structures and the good agreement between theoretical and measured reflectometry spectra. The sidewall angle map for the oxide trench and the depth map for the etched silicon carbide are shown in Fig. 3. The etching process was not fully optimized for these samples, allowing a wider parameter range across the wafer and more data for result validation. The results show the expected parameter uniformities across the test samples. The presented optical metrology enables nanometer level precision and real-time, inline process monitoring, thereby contributing to yield improvement of SiC trench MOSFET device fabrication.

[1] Oleg Rusch, Kevin Brueckner and Tobias Erlbacher, Solid State Phenomena, 359, 193-200 (2024). [2] Xiaoyu Tan, Guoming Lin, Ankuan Ji, Yuanwei Lin, Materials Science in Semiconductor Processing, 188, 109172 (2025). [3] Tsunenobu Kimoto and James A. Cooper, Fundamentals of Silicon Carbide Technology (2014).

ABSTRACT. The ‘Ladder’ MOSFET architecture was previously shown to significantly reduce the specific on-resistance (Ron,sp) of 1.2kV planar SiC MOSFETs by incorporating an additional channel and JFET region orthogonally within the layout, thereby increasing channel density [1]. Applying the Ladder design to 1.2kV MOSFETs with a deep P-well offers further improvements in Ron,sp. This is because the Ladder structure also enhances JFET density, as illustrated in Fig. 1, leading to a reduction in JFET resistance. This reduction is particularly beneficial for deep P-well MOSFETs, where the JFET resistance contributes more significantly to the total Ron,sp due to the deeper P-well junction engineered for enhanced device robustness [2]. 3D TCAD simulations were performed to optimize the design rules for both Nominal and Ladder layouts with deep P-well prior to fabrication. Fig. 2. illustrates the final 3D TCAD structures for both device configurations with the static electrical characteristics of the simulated devices presented in Table 1. The Ladder MOSFET demonstrated a 14% reduction in Ron,sp compared to the Nominal MOSFET, with a Ron,sp of 2.87 mohmcm2 and 2.51 mohmcm2 for the Nominal and Ladder MOSFETs, respectively. The reduction in Ron,sp results from the inclusion of the Ladder region, which provides an additional current pathway. This is illustrated in Fig. 2. cross-section ‘A-B’, where the total current density is plotted, showing the current flow through both the additional channel and the JFET in the Ladder region. The blocking characteristics were also simulated for both devices and the Ladder MOSFET demonstrated no degradation in the breakdown voltage (BV) compared to the Nominal MOSFET. The Nominal and Ladder MOSFETs were fabricated on the same wafer using the same set of masks and implantation recipes at Clas-SiC Wafer Fab. UK. A self-align process was used to form the P-well/Channel. The deep P-well structure was formed by performing channeling implantation during the JFET and P-well implantations. Channeling implantation is performed by tilting the wafer at a 4° angle, aligned with the (0001) direction of the 4H-SiC substrate and oriented toward the <11̅20> direction. This approach allows the dopants to penetrate deeper into the 4H-SiC epilayer without requiring excessively high implantation energy, which could otherwise cause additional damage to the crystal structure [2]. After fabrication, wafer thinning was also performed to reduce the thickness of the substrate from 360 µm to 175 µm to minimize the substrate resistance. Fig. 3 shows a SEM (Scanning electron microscopy) image of a Ladder MOSFET taken after fabrication, which shows that the Ladder region was successfully formed. Finally, selected Nominal and Ladder devices were diced and packaged in TO-247s for further evaluation. A comprehensive study was conducted comparing the Nominal and Ladder MOSFETs. The overall improvement in the tradeoff between Ron,sp and Vth is shown in Fig. 4. The wide distibution in the Vth is due to the assymetric channel design. In order to conduct a more fair comparison, a Nominal and Ladder MOSFET with similar Vth were directly compared. The Vth of the selected Nominal and Ladder MOSFETs are 2.22 V and 2.12 V, respectively as seen in Fig. 5. The Ron,sp for these devices is 4.61 mohmcm2 and 3.84 mohmcm2, respectively as seen in Fig. 6., which is a 20% reduction in the Ron,sp with the Ladder MOSFET. The Ladder design does not degrade the breakdown voltage (BV) and only leads to a marginal increase in the leakage current in the blocking mode of operation as shown in Fig. 7. Overall, the Ladder design greatly improves the Ron,sp for deep P-well MOSFETs.

ABSTRACT. This study proposes a refilled PMOS SiC trench MOSFET (RPTMOS) design with integrated parasitic PMOS clamping transistors to mitigate single-event burnout (SEB) susceptibility. Through systematic TCAD simulations, we analyze the transient lattice temperature, electric field distribution, and current density dynamics under heavy-ion irradiation (LET = 19.0 MeV·cm²/mg, Drain DC Bias VD = 500 V). The optimized structure features a grounded parasitic PMOS clamp formed by the P-connect, P-bottom, and N-drift regions, which enables efficient hole extraction and suppresses electric field crowding at the gate oxide corner. Comparative simulations reveal that the proposed design reduces peak lattice temperatures and elevates the SEB withstand voltage by ~20%. Parametric studies further demonstrate that increasing the P-connect thickness (200 Å → 400 Å) significantly enhance radiation hardness, proves the pivotal contribution from the parasitic PMOS. The findings offering a viable pathway for radiation-hardened SiC power devices in aerospace and high-energy applications.

ABSTRACT. Silicon carbide (SiC) power MOSFETs are experiencing rapid technological and commercial development. Their major advantages over their silicon counterparts come from some material features that are considered superior to those of silicon [1-2]. Higher critical electric field, higher thermal conductivity, better resistance to mechanical stress and current capacity render it an ideal candidate for high voltage power electronics. The rise of their application in electric traction for the automotive sector[3] poses new reliability challenges driven by the safety of use and the long-term quality of the product. One of the main contributors for the reliability performance of the device is the edge termination design, determining breakdown voltage (BV), the capacity to withstand electric dynamic stress and the robustness to harsh environmental conditions such as extreme temperatures, humidity, charge and impurity contamination [4-8]. This work is focused on comparing different guard ring designs with different features to estimate their performance in terms of reliability. With the help of technical computer-aided-design (TCAD) a comparison between single ring (SR), variable lateral doping (VLD) ring and floating ring (FR) is performed and their ruggedness is evaluated. The comparison is based on the Electric Field distribution at the junction breakdown relative to the MOSFET topology, the absolute value of the Electric Field peaks and the response to the presence of charges in the dielectric layers of the MOSFET. The biggest qualitative difference between the three solutions is the Electric Field distribution close to the gate metallization at the edge of the device, where some reliability issues are known to occur. The SR solution performs the worst. This solution has the highest maximum field value out of all, moreover this value occurs right below the metallization and a lot of stress on the dielectric layers on top of the SiC (Oxides and Nitrides) and on the PiQ. The VLD solution eliminates some of the stress on a large part of the thick oxide and decouples the metallization above from the high Electric Field values occurring on the SiC at the breakdown. This produces a flatter Electric Field distribution along the edge and in the dielectric layers with peaks occurring in correspondence of the doping the gradients. The peak values are also reduced with respect to the SR but still occur near parts of the external metallization. Finally the FR exhibits much lower Electric Field peaks and a tamer distribution lacking the distinct large differences of the other two solutions, especially in the layer far from the SiC surface. The field is pushed far from the metallization and into the inert thick oxide and SiN layers. The analysis is completed with a comparison of the performances of the termination ruggedness to the presence of charges on the passivation layers. In this regard SR is very solid and only feels the effect of large concentrations of negative charges while for positive charges the breakdown of the junction termination is unchanged. The VLD solution on the other hand responds to both positive and negative charges. The injection of positive charges on the SiN/TEOS interface the BV of the VLD drops to lower values while with negative charges the opposite occurs. The FR shows similar sensitivity to positive charges as the VLD but a reduced one to negative charges.

[1] P. Alexakis et al., IEEE Trans. Electron Devices, vol. 61, no. 7, pp. 2278–2286, (2014) [2] P. Losee et al., Proc. 26th ISPSD, pp. 297–300, (2014). [3] R. Tanaka et al., Proc. 26th ISPSD, pp. 75–78, (2014). [4] Z. Chen et al., IEEE Trans.Power Electron., vol. 29, no. 5, pp. 2307–2320, (2014) [5] X. Huang et al., in Proc. 27th APEC, 2012, pp. 1688–1691. [6] M. Riccio et al., Microelectron. Rel., vol. 53, nos. 9–11, pp. 1739–1744, Sep./Nov. 2013 [7] D. Cimmino et al., Electronics 2020, 9, 1884; doi:10.3390/electronics9111884 [8] J. Leppannen et al., Microelectronics Reliability 123 114207 (2021)

ABSTRACT. Short-circuit (SC) robustness is a key reliability metric for power MOSFETs. Earlier studies only broadly suggested that SG-MOSFETs and planar MOSFETs exhibit similar SC performance, particularly in terms of short-circuit withstand time (SCWT), without a detailed investigation of the underlying semiconductor physics. In this work, however, TCAD simulations reveal structural differences in their SC behavior, especially after SC failure. Through a comprehensive analysis of the physical mechanisms, this study identifies and explains key distinctions that were previously overlooked.

ABSTRACT. An analytical model is developed that accurately predicts the reverse recovery (RR) current waveform of SiC p-i-n diodes given only the thicknesses, dopings, lifetimes, and mobilities of the anode, cathode, and mid-region. Improvements in prediction are obtained by assuming that depletion of the plasma is limited by the drift velocity of carriers in the electron-hole plasma rather than by carrier diffusion at the plasma edges. Model verification is performed using simulation. Optimized 4H-SiC p-i-n diodes are designed with differing mid-region thicknesses varying from 50μm to 150μm by 25μm increments, yielding breakdown voltages (BV) between 6kV and 17kV. RR simulations are performed on the optimized diodes with the reverse voltage varying between 1/8 to ½ the simulated BV and ramping rates between 10A/μs to 10kA/μs. A forward current density of JF=100A/cm2 is used throughout all simulations to ensure sufficient conductivity modulation in the mid-region. The current-zero crossing time (t0), voltage zero-crossing time (t1), peak reverse-current time (t2), peak reverse current (JPR), total reverse recovery time (t3 and trr), reverse recovery charge (QRR), and snappiness (tB/tA) are extracted from the simulation and quantitatively compared with the model’s predictions using the mean absolute percent error (MAPE). Baliga’s most recent RR model is also used as a baseline to assess the improvements in the developed analytical model’s prediction. [1] QRR is found to agree within 20% with the simulation at low ramping rates and within 6% as ramping rates increase. JPR is found to agree within 16% with the simulation at low ramping rates and 2.3% as ramping rates increases. tRR agrees within 16% at low ramping rates and 9.9% as ramping rates increase. An average 90% reduction in error was found for QRR, 85% reduction in error was found for JPR, and 76% reduction in error was found for tRR compared to Baliga’s model. An inspection of the simulated results reveals that these improvements arise from a more accurate modeling of the growth of the depletion layers, and from including the decay of the conductivity-modulated region through recombination during RR. Surprisingly, the model predicts that the depletion layer arising at the anode grows faster than the depletion layer arising at the cathode regardless of the doping type of the mid-region. This result is confirmed by simulation. The model is used to estimate the high-level lifetime (τHL) from the extracted QRR of a fabricated 13kV 4H-SiC P-i-N diode. [2] The model fit gives a 1.5x-2.2x larger τHL than that extracted by the authors from the slope of the QRR-IF curves. This is expected as extracting τHL from the slope of the QRR-IF curve underestimates τHL by assuming no recombination during RR. The model reproduces the trend of QRR increasing with the ramp rate, a feature Baliga’s model does not reproduce, although the increase predicted by the model is not as large as that seen in the data. This model has applications both in facilitating the design of more performant SiC p-i-n diodes through a better understanding of the physical processes driving the RR dynamics and in a more accurate extraction of the high-level lifetime from RR waveforms. Future work should include the effect of voltage overshoots due to parasitic inductances and model the effect of the low-lifetime region that occurs in implanted SiC p-i-n diodes.

[1] B. J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, (2019) pp. 249-255. [2] K. Nakayama et al , Materials Science Forum, 778-780, pp 841-844 (2014)

ABSTRACT. This work presents a systematic study of series resistance in 4H-SiC CMOS devices using the Transfer Length Method (TLM). N+ and P+ test structures with varying contact spacings were fabricated to extract sheet resistance and contact resistivity over a wide temperature range. The measurements demonstrate that P+ ohmic contact exhibits contact resistivity over three orders of magnitude higher than N+ counterpart, which is primarily due to the higher Schottky barrier height and more pronounced incomplete ionization associated with aluminum (Al) doping. A temperature-dependent resistance model is developed to incorporate these effects, enabling accurate prediction of resistance behavior at high temperatures.

ABSTRACT. We report the fabrication and performance of Schottky barrier diodes based on 4H-SiC for use as solid-state radiation detectors. Devices were in-house fabricated with ohmic and Schottky contact formation (50/100 nm Ti/Au and 50 nm Ni). The resulting detectors exhibit ultra-low leakage currents at room temperature, i.e., 10 pA at 200 V, with values rising only to the nA range at 300 °C and μA levels at 500 °C. Radiation detection performance was validated through alpha particle spectroscopy using Am-241 sources. The fabricated devices achieved an energy resolution of 21 keV (0.38%) at 5.486 MeV, approaching the intrinsic limit. To explore the potential of SiC for reactor dosimetry, we built a confocal optically detected magnetic resonance (ODMR) system to investigate high-fluence fission spectrum neutron irradiation on the effects of color centers.

ABSTRACT. We report on the results of optimizing a pulsed-ODMR measurement conditions for the SiC-Vsi quantum sensor in order to improve the ODMR contrast.

ABSTRACT. Recent advances in color-center technology show promising results towards room-temperature sensor applications using the silicon vacancy (VSi) in 4H-SiC [1]. For the monolithic integration of such sensors, an integrated light source is needed for the excitation of the VSi [2], which poses challenges due to the wide and indirect bandgap of 4H-SiC. We propose a lateral 4H-SiC tunneling diode as light emitter for VSi excitation, which shows white light in Zener breakdown containing the wavelength necessary for off-resonant excitation at 730 nm [3]. The devices discussed here are fabricated using a subset of steps of the 2 µm 4H-SiC CMOS process at Fraunhofer IISB shown in Fig. 1 and described in [4]. A schematic cross-section of the diode’s structure is shown in Fig. 1. The implanted n+ and p+ regions overlap to form a p+n+-junction within the overlapping region. The static electrical characteristic is given in Fig 2, featuring Zener tunneling current under reverse bias. For the electroluminescent characterization, the diodes were operated at constant current biases of up to 85 mA in forward and up to -10 mA in reverse bias in continuous wave operation. Under forward bias (LED operation, blue in Fig. 2 and Fig. 5 a)) the diode’s n+ doped region emits a spectrum with peaks at 391 nm and at 470 nm, attributed to the N donor to valence band transition and the N donor to D1 defect transition as shown in Fig. 3 and schematically depicted in Fig. 6 a). This radiation is known from literature [5]. Under reverse bias, light emission is observed at voltages beyond 27.4 V (green in Fig. 2). In those operation points the diode emits white light as shown in Fig 4. The spectrum shows only a broad peak at 492 nm with a full width half maximum breadth of 303 nm. At 730 nm, which is commonly used as off-resonant excitation of the VSi [3], 43.1% intensity relative to the peak value remains. At low injection currents, the peak intensity of the tunnel emission scales linearly with the injected current up to 4 mA. Above, self-heating of the device results in constant voltage bias across the junction at any injected current. The linear relationship between the peak intensity and injection current shows that the threshold current density for tunneling enhanced light emission is zero. The tunneling enhanced light emission is localized to the region exactly at the tunneling junction, which is shown in Fig 5 b). Therefore, the emission happens in the region with the highest electric field in the pn-junction. Despite the tunneling generation current, only a negligible number of free carriers is available for direct recombination into the valence band within the space charge region, which is confirmed by the absence of the peak at 391 nm corresponding to a donor valence band transition. Within the region of high electric field, tunneling can happen from the valence band into any unoccupied defect within the bandgap, such as the nitrogen donor state. Since there are no holes available for optical transitions into the valence band, the only possible optical transitions are the ones between the nitrogen level and the aluminum acceptor state, which are available due to the overlapping doping profiles. The transition happens only when the acceptor state is unoccupied. This cascade of transitions is illustrated in Fig. 6 b). Since the acceptor states close to the valence band edge cannot be at the same position as the nitrogen donor level, from which the electron recombines, an additional tunneling process during recombination is necessary. If the position of the acceptor state close to the valence band edge is shifted along the direction of the electric field, it also has a different energy level. Therefore, the energy of the emitted photon depends heavily on the distance between the acceptor state and the donor state, the density of the acceptor states, the electric field strength, and the direction in which the defect is located. In the tunneling enhanced light emission regime, optical transitions in 4H-SiC Zener diodes happen between states within the bandgap. Due to the strong band bending, the states available for recombination have an energy distribution along the electric field, which leads to a broad spectrum below the bandgap energy of 4H-SiC. In this spectrum, the spectral component for the excitation of VSi at 730 nm is contained with a relative intensity of 43.1% of the peak intensity.

ABSTRACT. β-Ga2O3 has emerged as a promising ultra-wide bandgap (UWBG) semiconductor for next-generation power electronics, owing to its large bandgap (~4.8 eV), high critical electric field (~8 MV/cm), and availability of cost-effective large-area single-crystal substrates [1]. While numerous studies have demonstrated high-voltage transistors and Schottky diodes using β-Ga2O3 [2-4], its circuit-level implementation for AC–DC conversion remains largely unexplored, especially using heterojunction pn diodes with oxide-based heterojunctions. In this work, we demonstrate the first β-Ga2O3-based full-wave rectifier circuit utilizing NiO/ β-Ga2O3 heterojunction pn diodes, fabricated on a (100)-oriented Sn-doped single-crystal β-Ga2O3 substrate. The fabrication process, illustrated in Fig. 1(a), integrates four diodes, a resistor, and a capacitor to construct a compact bridge-type full-wave rectifier. Fig. 1(b) and (c) present an optical image and the schematic of the fabricated circuit. The core rectifying elements are NiO/β-Ga2O3 heterojunction pn diodes, which exhibit strong rectification and suppressed junction capacitance. The I–V characteristics of the NiO/β-Ga₂O₃ pn diodes (Fig. 2a) show sharp rectification with a turn-on voltage of approximately 1.45 V, consistent across multiple samples. The uniformity and steep slope in the forward region confirm the reproducibility of the oxide heterojunction and its suitability for consistent power conversion. In addition, the C–V measurements (Fig. 2b) indicate a low and nearly flat capacitance profile (~4–5 pF) under reverse bias, attributed to the wide depletion region at the pn junction. This low junction capacitance improves high-frequency performance by reducing capacitive losses and enhancing the diode’s ability to respond quickly to fast voltage transitions. The circuit was tested under a sinusoidal AC input of ±10 V across three different frequencies—10 kHz, 500 kHz, and 10 MHz. As shown in Fig. 3, the average output voltage increased from 0.5 V at 10 kHz to 1.21 V at 10 MHz, demonstrating improved rectification efficiency at higher frequencies. This frequency-dependent increase in Vout is attributed to reduced junction capacitance, which enables faster diode response and a more complete transfer of charge per cycle. However, this improvement in output voltage comes at the cost of increased ripple. The measured ripple voltage (Vout,ripple) increased from 54 mV at 10 kHz to 260 mV at 10 MHz. This is likely due to the limited filtering capability of the integrated 1 μF capacitor at higher frequencies, where the capacitor discharges more significantly between conduction phases. These results highlight a key trade-off between rectification efficiency and output voltage ripple in high-frequency oxide-based pn diode circuits. To validate the circuit design and analyze diode-level contributions, SPICE simulations were performed using a β-Ga2O3 diode model calibrated against experimental I–V measurements. As shown in Fig. 4a, the simulated diode exhibits excellent agreement with the measured characteristics across both forward and reverse bias regions, accurately capturing turn-on behavior and sub-picoampere leakage currents. Using this model, we simulated the full-wave rectifier under a ±10 V AC input at high frequency. The simulated output waveform (Fig. 4b) yielded a DC level of 1.21 V and ripple of 0.26 V, which matches closely with the experimental values at 10 MHz. These results confirm the validity of the compact model and its utility for future circuit-level co-design of β-Ga2O3-based power ICs. This work represents the first circuit-level demonstration of a full-wave rectifier based on β-Ga2O3 pn diodes, paving the way for monolithic integration of UWBG rectifiers in compact AC–DC power ICs. Our results validate the applicability of NiO/β-Ga2O3 pn diodes for high-frequency rectification and establish a framework for future oxide-semiconductor-based power electronics.

ABSTRACT. κ-phase gallium oxide (κ-Ga₂O₃) has recently garnered attention as a promising material for next-generation electronic and optoelectronic devices, owing to its spontaneous polarization, ferroelectricity, and potential for high breakdown field and electron mobility. However, the stabilization of the κ-phase and improvement of its crystalline quality remain major challenges due to its metastable nature and lack of bulk substrates. In this study, we demonstrate the two-step epitaxial growth of κ-Ga₂O₃ thin films on 4H-SiC substrates using mist chemical vapor deposition (mist CVD), with a particular focus on the impact of temperature-varied buffer layers on phase stability, surface morphology, and crystallinity. In the first step, gallium oxide buffer layers were deposited at various temperatures ranging from 350 °C to 700 °C. X-ray diffraction (XRD) analysis revealed that the crystalline phase of the buffer layer transitioned from amorphous to pure κ-phase, and eventually to mixed κ + β phases with increasing temperature. Optimal κ-phase formation with (001) orientation was observed in the 450–650 °C range. Atomic force microscopy (AFM) and scanning electron microscopy (SEM) showed that surface roughness and grain morphology were strongly dependent on buffer growth temperature, with dense grains and moderate roughness achieved near 550 °C. In the second step, κ-Ga₂O₃ thin films were grown at a fixed temperature of 500 °C on these buffer layers. The structural properties of the resultant films showed clear dependence on the underlying buffer layer characteristics. Films grown on amorphous buffer layers (350–400 °C) exhibited poor crystallinity and small prismatic grains, whereas those grown on crystalline κ-phase buffer layers demonstrated significant improvement in crystal quality, as confirmed by XRD rocking curve measurements. Interestingly, films on mixed-phase buffers (700 °C) achieved the highest crystal quality due to grain growth competition, though with deteriorated surface smoothness caused by hillock formation. This work underscores the effectiveness of a two-step mist CVD process with controlled buffer temperature for tailoring the microstructure and crystalline quality of κ-Ga₂O₃ thin films. The results provide valuable insight into process optimization for future device applications such as high-power electronics and ferroelectric devices.

ABSTRACT. Quantum-information science is now pushing beyond proof-of-principle experiments toward secure communication, scalable processors, and large-scale quantum networks. Achieving those goals demands quantum hardware that not only provides reliable spin initialization, coherent manipulation, and high-contrast optical readout, but also couples seamlessly to photonic channels so the devices can be woven into distributed‐network architectures. Silicon-carbide vacancies exemplify these advantages. In 4H-SiC the negatively charged silicon vacancy (VSi−) hosts an electronic ground state of total spin S=3/2. Spin-selective optical transitions allow fast preparation and fluorescence readout, while the four-level manifold can be addressed either as a conventional qubit, e.g. ∣ms=±1/2⟩, or as a genuine ququart that leverages all sub-levels [1-2]. The richer level structure offers additional control pathways but also introduces leakage channels that are absent in spin-1/2 systems, making a detailed, quantitative analysis of the spin-3/2 dynamics indispensable for any qubit- or qudit-based application of SiC defects. Our simulations are built on a versatile spin-dynamics engine that represents the density operator in user-defined bases and efficiently tracks observable populations during pulse sequences(Fig. 1). Using experimental parameters—static magnetic field, microwave frequency, power, and pulse timing—we model single-qubit control protocols that form the backbone of most defect-based experiments: continuous-wave Rabi oscillations for drive-strength calibration, Ramsey interferometry for dephasing characterization, and Hahn-echo sequences for T2 extension. The primary objective is to identify pulse conditions that maximize coherence and minimize leakage, thereby streamlining subsequent quantum-control routines. A central theme of this study is the contrast between treating the two adjacent spin sub-levels as an isolated qubit and respecting the full four-level (ququart) structure. By running time-domain simulations over a range of drive strengths, detunings, and pulse durations, we try to expose how population cycling among the four levels can subtly distort Rabi line-shapes, Ramsey fringe contrast(Fig. 2), and Hahn-echo decay—effects that remain invisible within a two-level approximation. Simulated fluorescence transients are compared with in-house measurements on single VSi− centers, validating the model and revealing parameter regimes where ququart dynamics must be taken into account. This simulation-based approach contributes to the predictive analysis of quantum gates and to the refinement of experimental design for implementing both qubits and ququarts in spin-3/2 systems. By quantifying leakage pathways and their dependence on control parameters, the framework delivers practical guidance for pulse optimisation and paves the way for future spin–photon protocols in wide-bandgap semiconductors. As quantum technologies continue to evolve, such simulation-based tools will be essential for bridging the gap between theoretical models and experimental realizations.

ABSTRACT. In this work, we experimentally investigated and compared the optical properties of Si and SiC photonic crystal nanocavities under controlled oxidation using ozone gas. While a resonant wavelength of the Si nanocavity was significantly shifted by 0.6 nm due to ozone oxidation, that of the SiC nanocavity was changed by only 0.09 nm, which is six times smaller than the wavelength shift observed in the Si nanocavity. Moreover, the linewidth of the Si nanocavity was broadened by a factor of 2, whereas that of the SiC nanocavity remained nearly unchanged even after the oxidation. These results demonstrate the superior optical robustness of the SiC nanocavity against oxidation.

ABSTRACT. Ultraviolet-C (UV-C) photodetectors based on wide-bandgap semiconductors such as silicon carbide (SiC) are of increasing interest for harsh-environment sensing applications due to their high thermal stability, radiation hardness, and intrinsic solar blindness. However, integration into CMOS backend-of-line (BEOL) processes remains challenging, particularly due to the thermal budget limitations imposed by conventional contact formation techniques [1]. In this work, we present a CMOS-compatible fabrication strategy for lateral 4H-SiC UV-C photodiodes, designed to achieve high performance while adhering to standard CMOS backend constraints. By employing junction engineering, optimized ohmic contacts, and a lateral device architecture, the resulting photodiodes exhibit excellent responsivity, low leakage current, and reproducible doping profiles confirmed through electrical characterization [2]. A lateral device structure was adopted to ensure CMOS backend compatibility and reduce fabrication complexity compared to conventional vertical geometries. This configuration enables shorter inter-electrode distances, leading to faster photo-response and compact layouts. Devices with active areas ranging from 0.01 mm² to 0.64 mm² were fabricated to evaluate layout-dependent performance. The fabrication process maintained strict CMOS-compatibility by avoiding high-temperature steps after metallization and utilizing photolithographically defined lift-off techniques for all metal patterning. This approach minimized surface damage, enabled precise active area definition, and ensured backend process compatibility. Ti/Al was used for the p-type region due to its reliable contact behavior, and NiAl (2.6 wt% Al) was applied for the n-type region to form low-resistance, stable ohmic contacts [3]. Both contacts were patterned with backend-compatible techniques to ensure high fidelity and minimal thermal impact. The photodiodes were characterized using current-voltage (I–V) and capacitance-voltage (C–V) measurements. Fig. 1 shows I–V characteristics of a representative device with a 0.31 mm² active area under both dark and UV-C illumination (λ = 250 nm). The devices demonstrated low dark current in the order of 10⁻¹² A at –5 V reverse bias, along with stable rectifying behavior. Under UV-C illumination (250 nm), the devices exhibited a peak external responsivity of ~271.6 mA/W at –5 V. As summarized in Table I, the responsivity increases with emitter area, showing layout-dependent behavior and validating the scalability of the lateral design. The non-linear increase suggests enhanced photon collection efficiency and reduced electrode shadowing in larger layouts. The maximum measured responsivity of 271.6 mA/W at 0.64 mm² corresponds to an external quantum efficiency of approximately 85%, indicating excellent device performance. The lateral configuration and short carrier drift paths also contribute to fast transient response, making the devices suitable for high-speed UV-C detection. C–V analysis enabled estimation of the p-type doping concentration. A 1/C²–V analysis revealed acceptor concentrations (NA) ranging from 1.6 × 10¹⁶ to 2.7 × 10¹⁶ cm⁻³ in high-performance devices, consistent with junction design targets [4]. Given the heavily doped n-side, the depletion region extends primarily into the p-type side, enabling accurate extraction of NA. These values are aligned with optimized design for high responsivity, controlled junction depth, and minimized series resistance, while preserving compliance with CMOS backend constraints. In conclusion, high-performance lateral 4H-SiC UV-C photodiodes were fabricated using a fully CMOS-compatible process. The combination of lift-off patterning, low-temperature ohmic contacts (Ti/Al and NiAl), and optimized junction design enabled backend integration without compromising device performance. These devices are well suited for deployment in harsh environments such as space, high-temperature industrial monitoring, and UV sterilization feedback systems. Future work will focus on monolithic CMOS integration and development of passivation layers to improve reliability under prolonged UV exposure.

Acknowledgments This work was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (RS-2023-00266246)

[1] J. Romjin et al, Microsyst. Nanoeng. 8, 114 (2022). [2] S. Hou et al, IEEE J. Electron. Devi. 8, 116 (2020). [3] C. D. Matthus, A. J. Bauer, L. Frey and T. Erlbacher, Mat. Sci. Semicon. Proc. 90, 205 (2021). [4] J. Abautret et al, J. Appl. Phys. 113, 183716 (2013)

ABSTRACT. Gallium nitride (GaN), as a third-generation wide bandgap semiconductor material, is widely used in the field of optoelectronic and power electronic device fabrication due to its excellent properties such as high breakdown field and high temperature resistance. Traditional processing methods have problems such as complex processes, large material loss, and difficulty in achieving uniform separation over large areas. Therefore, laser-modified slicing technology has become a low-damage and high-efficiency alternative. In this study, we successfully achieved the delamination of a 10×10 mm bulk GaN using picosecond laser. The surface roughness was measured to be ~25 μm, and the kerf loss was ~60 μm, which is much smaller than that of the traditional line-cutting method. The research results provide practical guidance for improving the quality of GaN laser slicing and contribute to the development of advanced wafer processing technology.

ABSTRACT. Beta-phase gallium oxide (β-Ga2O3) has attracted considerable attention as a promising next-generation semiconductor for high power devices and ultraviolet photodetectors due to its ultra-wide bandgap (~4.8 eV). The anisotropic crystal structure of β-Ga2O3 facilitates easy cleaving of single crystals along the (100) plane, enabling the fabrication of electronic devices from mechanically exfoliated flakes and thereby simplifying electrical characterization. However, surface trap states introduced during the cleaving process lead to unstable device performance, as evidenced by significant threshold voltage hysteresis, hindering accurate evaluation of the intrinsic electrical properties of β-Ga2O3. In this study, we demonstrate highly stable thin film transistors (TFTs) fabricated from exfoliated β-Ga2O3 flakes by effectively repairing cleaved surfaces through rapid thermal processing (RTP). Applying RTP annealing in air immediately after exfoliation effectively reduces oxygen vacancies on the cleaved surface, minimizing surface trap states. Consequently, TFTs fabricated from these annealed flakes exhibit negligible threshold voltage hysteresis, facilitating precise and reproducible characterization of intrinsic electrical properties. This work establishes exfoliated flake-based TFTs combined with RTP surface treatment as a reliable platform for simple and rapid evaluation of intrinsic bulk β-Ga2O3 crystal properties.

ABSTRACT. Silicon carbide (SiC) spin defects combine long spin coherence, room-temperature functionality, and photonic compatibility—making them a leading candidate for solid-state quantum technologies. These properties position SiC as a key enabler for scalable, robust quantum computing [1-9].

This poster showcases the development of a compact, desktop-format quantum computer demonstrator based on divacancy spin defects in SiC [10,11]. Designed as a hands-on educational tool, the system features two qubits and allows users to explore the implementation of quantum gates and basic algorithms in an intuitive, accessible format.

A central challenge in SiC-based quantum systems is the near-infrared (NIR) emission spectrum of most defect centers [1,2,10,11]. While advantageous for long-distance photonic entanglement and distributed quantum architectures, it complicates optical readout due to limitations in the efficiency and timing resolution of compact NIR detectors. Addressing this requires careful defect engineering and photonic integration on the chip and system level, which are key focus areas of this work.

This poster accompanies a talk by co-author Matthias Niethammer. Together, the talk and poster provide a comprehensive view of our approach to advancing SiC as a practical and scalable platform for quantum computing. While large-scale systems are still in development, our work marks an important step toward that vision—and demonstrates that the future of quantum computing may well be built on SiC.

[1] D. Shafizadeh, et al,, Phys. Rev. B 111, 165201 (2025) [2] N.T. Son, et al, Appl. Phys. Lett. 116, 190501 (2020) [3] N. Morioka, et al., Nat. Commun. 11, 2516 (2020) [4] R. Nagy, et al., Nat. Commun. 10, 1954 (2019) [5] P. Udvarhelyi, et al., Phys. Rev. Appl. 13, 054017 (2020) [6] J. Ul Hassan, et al., Appl. Phys. Lett. 118, 144003 (2021) [7] T. Ohshima, et al., npj Quantum Inf. 6, 85 (2020) [8] M. Niethammer, et al., Nat. Commun. 10, 5569 (2019) [9] M. Widmann, et al., Nat. Mater. 14, 164 (2015) [10] Q. Li, et al, National Science Review, Volume 9, Issue 5 (2022) [11] N. T. Son, J. Appl. Phys. 025703, (2022)

ABSTRACT. Betavoltaic (BV) cells are emerging as a promising next-generation energy source, offering long-term stable power generation through the use of radioactive isotopes [1]. BV cells operate independently without external power, maintain performance in extreme environments, and have a lifetime that extends with the half-life of the isotopes, enabling semi-permanent operation. Among the semiconductor materials, GaN as a wide-band gap semiconductor has been considered as a promising material for BV cells because GaN-based BV cells can enable higher theoretical output voltage and energy conversion efficiency, along with strong radiation hardness ensuring stable operation [2]. In this study, we focused on the fabrication process of GaN PiN BV cells (Fig.1) and the evaluation of their electrical properties and power performance. The BV cells were characterized under 17 keV e-beam irradiation, which corresponds to the average energy of the Ni-63 radioisotope, using a probe workstation equipped with a scanning electron microscope (Fig.2). Key parameters, including short-circuit current (Isc) and open-circuit voltage (Voc), were extracted from the measured I-V characteristics to evaluate the power performance of the BV cells (Fig.3). Additionally, we analyzed device characteristics under varying e-beam accelerating voltages within the energy spectrum range of Ni-63 beta decay (Fig.4). BV cells have potential as long-term, stable power sources for applications such as space exploration, implantable medical devices, and remote sensor systems. Therefore, BV cells are expected to emerge as a reliable and efficient alternative to conventional batteries.

ABSTRACT. Point defects in silicon carbide are emerging as promising candidates for scalable quantum applications. Among them, the k-site silicon vacancy (V2) in 4H-SiC has been used to demonstrate several key steps towards quantum computing and quantum network applications, including single-shot readout of a coupled 29Si spin [1] and spin-photon entanglement generation [2]. Here, we present our progress in designing, characterizing and optimizing high-fidelity quantum gates on V2 center electron spin in nanopillar devices [3]. For this, we build on our experience with gate-set tomography (GST) on NV centers in diamond [4]. Precisely characterized high-fidelity gates would form an important step towards potential quantum internet technologies based on qubits in SiC.

[1]​ X-Y Lai et al., Phys. Rev. Lett. 132, 180803 (2024). [2] ​R-Z Fang et al., Phys. Rev. Lett. 132, 160801 (2024). [3] G.L. van de Stolpe et al., npj Quantum Inf. 11, 31(2025) [4] ​H.P. Bartling et al., Phys. Rev. Applied 23, 034052 (2025).

ABSTRACT. Diamond exhibits high thermal conductivity to provide efficient cooling for the new generation of power devices based on SiC technology. Microwave plasma chemical vapor deposition (MPCVD) process utilizing hydrogen and methane gases is commonly used to grow heteroepitaxial diamond. However, the growth process of diamond involves continuous bombardment and diffusion of highly energetic gas species (e.g., H, H2) on substrate, which would induce degradation of the chemical and mechanical properties of SiC substrate. We proposed an Al2O3 layer using atomic layer deposition (ALD) to be used as a diffusion barrier during growth of hetero-epitaxial diamond on SiC substrate. Nucleation on this new template plays a critical role in the deposition of diamond. Diamond nucleation on various materials have preliminary been studied [1–3], nevertheless, the fundamental mechanism of nucleation on oxide-based substrates has not been fully understood yet. In this study, finite element analysis (FEA) at the reactor scale is performed to evaluate plasma density distribution above the substrate under several process conditions. Reactant adsorption, desorption and surface reaction are taken into account by a surface chemistry model coupled with FEA model. Through experimental observations, the formation of diamond crystals is confirmed and the nucleation kinetic terms are evaluated. In 120-Torr H2 experiments, increasing microwave power from 3000 W to 5000 W not only elevating fraction of available sites (e.g., dangling bonds) for nucleation on Al2O3 film by 9.57 %, but also rises the rate of sites formation by 3 times, hence increases nucleation density. The diamond growth kinetic parameters are estimated by utilizing conventional deposition theories using experimental data [4]. We demonstrate that the process optimization for nucleation and growth of hetero-epitaxial diamond on ALD oxides template would be realized through reactor-scale simulation coupled kinetic model. References:

[1] X. Hu, Y. Peng, X. Wang, X. Han, B. Li, Y. Yang, M. Xu, X. Xu, J. Han, D. Wang, K.Y. Cheong, Nucleation growth mechanism of diamond on 4H-SiC substrate by microwave plasma chemical vapor deposition, Mater Today Commun. 31 (2022). [2] S. Mandal, E.L.H. Thomas, T.A. Jenny, O.A. Williams, Chemical Nucleation of Diamond Films, ACS Appl Mater Interfaces. 8 (2016) 26220–26225. [3] J. Yun, D.S. Dandy, A kinetic model of diamond nucleation and silicon carbide interlayer formation during chemical vapor deposition, in: Diam Relat Mater, 2005: pp. 1377–1388. [4] P.W. May, Y.A. Mankelevich, From ultrananocrystalline diamond to single crystal diamond growth in hot filament and microwave plasma-enhanced CVD reactors: A unified model for growth rates and grain sizes, Journal of Physical Chemistry C. 112 (2008) 12432–12441.

ABSTRACT. Al-rich AlGaN heterostructures have received considerable attention for applications in harsh environmental conditions due to their outstanding thermal stability, exceptional chemical robustness, and high breakdown electric field properties. These characteristics are particularly advantageous for electronics operating in extreme environments, such as aerospace, automotive, and industrial applications. In this research, we successfully developed and optimized a fabrication methodology for an Al-rich AlGaN HEMT structure comprising Al0.85Ga0.15N/Al0.5Ga0.5N layers. We thoroughly characterized the electrical performance of the fabricated device over a broad temperature range, extending from room temperature to 300 °C. As the operating temperature was elevated from room temperature to 300 °C, the measured sheet resistance increased notably from 7,260 Ω/sq to 14,600 Ω/sq. This significant rise was primarily attributed to increased carrier scattering mechanisms, such as phonon scattering, which substantially reduced carrier mobility. Interestingly, the specific contact resistance displayed an inverse behavior, decreasing from 8×10⁻³ Ω·cm² to 3×10⁻³ Ω·cm² as temperature increased. This reduction is explained by the enhancement of thermionic emission at elevated temperatures, effectively lowering the barrier height at the metal-semiconductor interface, thus improving contact characteristics under high-temperature conditions. The fabricated Al-rich AlGaN HEMT demonstrated stable current-voltage (I-V) performance across the entire evaluated temperature range. Specifically, the maximum drain current exhibited only a modest decrease of approximately 10%, highlighting the device's superior thermal robustness. Additionally, the on-resistance increased minimally, approximately 7.6% (from 224 Ω·mm at room temperature to 239 Ω·mm at 300 °C), underscoring the device's excellent resistance stability. Under pulsed measurement conditions, the fabricated HEMT structure showed negligible trapping phenomena, even without surface passivation or the addition of field plates. This advantageous characteristic is primarily attributed to the high Al mole fraction present in the Al0.85Ga0.15N barrier layer, which creates a significant energy barrier capable of effectively blocking electron injection from the gate electrode region. As a direct consequence, the device exhibited remarkable gate robustness, supporting substantial forward gate voltage capabilities. The maximum forward gate voltage measured reached up to 9.8 V at room temperature and maintained a high value of 8.6 V even at 300 °C, confirming the robustness and reliability of the Schottky barrier at elevated temperatures.

Ackowledgement This research was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(Ministry of Science and ICT) (RS-2024-00431359) and the Technology Innovation Program (or Industrial Strategic Technology Development Program-Alchemist Project) (RS-2024-00432559, Development of Space grade Monolithic AlGaN/Diamond Ultimate semiconductor) funded By the Ministry of Trade, Industry & Energy(MOTIE, Korea).

[1] B. Klein, A. Allerman, A. Armstrong, M. Rosprim, C. Tyznik, Y. Zhu, C. Joishi, C. Chae, S. Rajan, Al-Rich AlGaN Transistors with Regrown p-AlGaN Gate Layers and Ohmic Contacts. Adv. Mater. Interfaces 2024, 12, 2301080. https://doi.org/10.1002/admi.202301080

ABSTRACT. As Si continues to hit its limits for some power applications, especially those where density and fast switching are required GaN and SiC, both contenders to replace Si technologies for power devices [1]. In speical, enhancement-mode (E-mode, normally off) GaN transistors in both GaN-on-Si and GaN-on-SiC are crucial for safe and efficient power switching. Fig. 1 shows schematic structure of E-mode high electron mobility transistor (HEMT) device with critical processes in the HEMT process. In general, p-GaN/AlxGa1-xN stacked structure has been ethced by based on a Cl2 chemistry [2]. In this experiment, we tryed to control the etching conditions by oxygen (O2) gas in the Cl2 chemistry, this could controls of a byproduct of the Al and Cl reaction in the bottom AlxGa1-xN layer. Frist, we have investigated an optical emission spectroscopy (OES) tool to know of Al etch and optimize the selective etching process in structures composed of p-type gallium nitride (p-GaN, top)/aluminum gallium nitride (AlxGa1-xN). Fig. 2 shows optical emission spectra (OES, Nanotech, opti-L20) of oxygen species as a etching function time at wave-length of (a) 615.9nm , b) 777.4 nm and (c) 844.6 nm. Where the samples with Al etched in a chamber at pressure of 4mTorr, power of 700W and bias of 65V. Finally we fabricated e-mode HEMT device with optimization etch conditions. Fig. 3 shows a cross-sectional TEM image and elemental TEM-energy-dispersive X-ray spectroscopy (EDS) maps of after 80nm p-GaN etch and Fig. 4 shows atom probe tomography (ATP) analysis [3] of contact area after E-mode HEMT fabrication. In summary, by monitoring the optical emissions during the etching process, we could control the etch conditions that increase a selectivity of material p-GaN/AlxGa1-xN of p-GaN-based enhanced (E)-Mode HEMT devices [4]. Adding O₂ gas into the Cl₂-based etching process in inductive couple plasma (ICP) etch tool, this changes the reaction dynamics, forming Al-O reactive species and increase in etching selectivity. We could increase the etching-selectivity of p-GaN/AlxGa1-xN from ~1x to 10x. This process showed a turn-on voltage of 1.34 V in normally-off HEMT devices (see Fig. 5). This result may give a guide line of epi-layers (thickness and Al composition % of AlxGa1-xN, concentration of Mg in p-GaN and thickness of p-GaN) and optimization process for e-mode HEMT device

ABSTRACT. In use, a SiC MOSFET operates as a switch, with drain-source subjected to a voltage pulsating at the switching frequency. Staic HTRB test aims to warranty the device against degradation of blocking capability. But the test does not include the effect of the fast switching edges. Voltage stresses may adversely affect the device through injecting carriers into traps. Depending on device design and fabrication, there could be traps of different depths particularly around the gate and edge termination. The process of carrier transport is also temperature dependent. Previous studies focussed on the mechanisms associated with a static electric field caused by a constant drain-source voltage (Vds>0) when the gate is reverse biased (Vgs<0). The transients associated with the switching edges contain harmonic components over a wide spectrum and may cause effects not present in the static HTRB test. This paper reports a study on the effect of the dynamic reverse bias (DRB) stress that is applied to the device during switching. The effect is measured by the degradation of the device breakdown voltage (BV), while other measurements such as threshold voltage are also used to help reveal the underpinning mechanisms. The study confirms the usefulness of dynamic reverse bias testing during device development, although this is not yet required by some standards. Monitoring the degradation during test provides useful insight into the causes and the potential of improvement in device design and fabircation.

ABSTRACT. SiC MOSFETs are widely adopted in the power electronics field as highly efficient devices compared to Si-based devices. However, these devices are known to exhibit inherent degradation modes, one of which is alternating current bias temperature instability (AC-BTI). It has been reported that applying bipolar AC stress (alternating positive and negative voltages) to the gate of a SiC MOSFET induces a drift of threshold voltage (Vth) [1-5]. The magnitude of Vth drift (ΔVth) is known to depend on the test temperature; however, previous studies show inconsistent results regarding the temperature dependence of ΔVth. While one study reports that ΔVth increases with rising temperature [1], another study reports a decrease in ΔVth with rising temperature [2]. These inconsistencies suggest that temperature dependence of ΔVth varies with specific characteristics of the device. Nevertheless, prior studies have only evaluated this phenomenon at temperatures above room temperature. This study investigated temperature dependence of ΔVth in SiC MOSFETs through AC-BTI tests across a wide temperature range, including both below and above room temperature.

AC-BTI tests were conducted using an AC-BTI test system with devices placed inside a temperature chamber (Fig.1(a)). Tests alternated between applying AC stress (+20 V/-10 V, 500 kHz) and measuring Vth , both performed at several specified temperatures (see (2) below for details). The specific test conditions are as follows: (1) Test circuit diagram: See Fig. 1(b) (2) Environmental temperature during the test: -40°C, -10°C, 25°C, 90°C, 150°C (3) Number of AC stress cycles: 10¹¹ (4) Vth measurement: Triple sense protocol [6] (see Fig.2) (The values of Vth_up were used to compare ΔVth across different conditions) (5) Thermal stabilization time before Vth measurement: 5 minutes (6) DUT: Four types of commercially available SiC MOSFETs (see Table I)

Figure 3 shows the results of AC-BTI tests conducted under various temperature conditions. In all conditions, ΔVth increased as the number of AC stress cycles increased. The lower graph illustrates the relationship between ΔVth at the end of the test (1E+11 cycles) and the test temperature. For DUT-B, C, and D, ΔVth became larger as the test temperature decreased. On the other hand, DUT-A exhibited an increase in ΔVth toward lower temperatures, as seen in the other devices, but uniquely exhibited an increase in ΔVth at higher temperatures.

The Vth drift caused by AC-BTI can be explained by several mechanisms, including the Photon-Assisted Electron Injection model (Model A) [3-4] and the Recombination Enhanced Defect Reaction model (Model B) [5]. Both models suggest that electron and hole recombination via SiC/SiO₂ interface traps during gate switching (from accumulation to inversion) is a contributing factor to ΔVth. The key difference between the two models is the type of energy released after recombination: Model A attributes ΔVth to photons, while Model B attributes it to phonons.

Based on the above mechanisms, the reason why ΔVth increased more at lower temperatures in the present tests appears to be related to the release time of holes trapped at the interface. At lower temperatures, the release time of holes trapped at the interface is longer, which reduces the number of holes released before recombination with electrons. Consequently, more recombination leads to the larger ΔVth. Since photon generation due to recombination is temperature-independent, these results can also support Model A, which is photon-related. On the other hand, the reason for the large ΔVth at high temperatures for DUT-A may be better explained by Model B, which is phonon-related. At high temperatures, the increased generation of phonons may have caused creation of interface defects, resulting in the increased ΔVth.

The temperature dependence of ΔVth varies between DUTs, suggesting that factors such as device structure and interface states may influence the results. In any case, this study reports AC-BTI test results at sub-room temperatures, demonstrating that ΔVth becomes larger at lower temperatures. These findings indicate that testing devices exclusively at temperatures above room temperature may overlook worst-case scenarios for applications operating at lower temperatures.

[1] “How Infineon controls and assures the reliability of SiC based power semiconductors,” Infineon Technologies AG (2020). [2] X. Zhong et al., IEEE Transactions on Power Electronics, Vol.37, No.2, pp. 1998-2008 (2022). [3] Y. Enjoji et al., ICSCRM 2023, Mo.C.11 (2023). [4] H. Yano, et al., ICSCRM 2024, Vol.8, pp.367-358 (2024). [5] M.W. Feil et al., IRPS 2023, 3B.1, pp.1-10 (2023). [6] JEITA standards, JEITA EDR-4713 Amend.1 “Guidelines for Compound Power Semiconductor Device Reliability Test Method Amendment 1”, Appendix E (2023).

ABSTRACT. Silicon Carbide (SiC) MOSFETs are widely employed in automotive applications, but their threshold voltage (Vth) instability remains a significant concern, potentially degrading system power efficiency and reliability [1]. The Vth instability of SiC MOSFET under AC gate switching stress (GSS) or surge current stress has been extensively investigated separately [2,3]. However, in practical applications, devices may experience a surge current and subsequently need to continue switching operations. The impact of such combined surge current and AC gate switching stress on Vth instability has been rarely reported. This paper investigates the cumulative effect of sequential AC gate switching and surge current stress on the Vth shift in planar SiC MOSFETs, uncovering the distinct degradation mechanisms associated with these two stress factors. Commercially available 650-V planar-gate SiC MOSFETs (RDS(on) = 60 mΩ, ID@25°C = 29 A) were selected as the devices under test (DUT). Figure 1 shows the half-sinusoidal waveforms of surge current (ISD), ranging from 30 A to 70 A for the DUT biased at VGS of 0 V. The Vth was monitored after each surge current stress, as shown in Fig. 2. The Vth increased slightly after the initial 30-A surge stress and remained nearly constant during subsequent, higher-current stresses. To further investigate Vth stability under combinded stress conditions, devices were submitted to AC gate switching following the surge current stress. An ultrafast (≤10 μs) Vth measurement technique was developed to accurately track Vth changes during these tests. For comparison, two distinct measurement-stress-measurement (MSM) procedures were designed (detailed in Fig. 3) to evaluate how the sequence of applying these two stresses affects Vth shift and recovery. Figure 4 compares the Vth shifts during 1 MHz AC gate switching for a fresh device versus one previously subjected to a 40 A surge. Notably, the subsequent Vth recovery processes also exhibited minimal difference between the two devices, as shown in Fig. 5. These findings (Fig. 4 and 5) suggest that applying surge stress first has a negligible impact on Vth instability during subsequent AC gate switching and on the subsequent recovery dynamics. In contrast, when the device was first subjected to AC gate switching (109 cycles) and then stressed with a 40-A current surge, the resulting Vth shift is ~0.2 V larger than that observed under surge-only, AC-only, or the previously described surge-first sequence (Fig. 6 comparison). Furthermore, the Vth shift induced by surge stress following AC gate switching shows minimal recovery over a 10-minute period. The Vth shift in SiC MOSFETs is mainly attributed to the presence and charging of trap states at the SiO2-SiC interface or within the gate oxide. The distinct Vth shift behaviors observed for the two stress sequences can be explained as follows: During a surge test at VGS of 0 V, partial channel current allows electrons to be captured by existing traps states near the SiO2-SiC interface (Fig. 7), increasing the net negative charge beneath the gate and causing a positive Vth shift. Conversely, AC gate switching stress (Fig. 8) involves a rapid changing electric field that can generate new acceptor-like interface defects, also contributing to a positive Vth shift [4]. Therefore, when AC gate switching occurs first, these newly created traps capture additional electrons during the subsequent surge stress, leading to a more significant positive Vth shift. We infer that the surge-first stress sequence does not generate substantial new traps, hence the Vth shift during subsequent AC switching remains similar to that induced by AC stress alone. These findings offers insights into Vth shift mechanisms in SiC MOSFETs under varied operational stresses and provide valuable guidance for circuit designers. Specifically, they highlight the need to account for the potential exacerbation of Vth shift by prior gate switching, particularly when using negative gate bias for turn-off in high-speed, high-power applications.

ABSTRACT. Silicon Carbide (SiC) MOSFETs have emerged as critical components in high-power and high-temperature applications, offering significant advantages over traditional silicon-based devices. Particularly, their superior electrical properties, such as higher breakdown voltage, lower on-resistance, and enhanced thermal conductivity, make them an ideal choice in the field of power electronics. However, under demanding conditions, such as in automotive applications, the reliability of the gate oxide remains a critical concern for SiC MOSFETs due to the intrinsically higher density of defects at the SiC/gate dielectric interface compared to Si devices that adversely affect their long-term durability and threshold voltage VTH stability [1]. Whereas an increase in VTH results in increased conduction losses during application, a decrease of VTH will lead to higher leakage currents and makes the device more susceptible to parasitic turn-on. In this regard, bias temperature instability (BTI) and gate switching instability (GSI) have been identified as the most significant degradation processes [2]. Thus, developing reliability testing strategies is essential for ensuring the durability, performance, and long-term stability of devices under real-world operational conditions. Static stress tests are widely implemented to understand gate oxide stability and robustness, this includes time-dependent dielectric breakdown (TDDB), direct current bias temperature instability (DC-BTI), high-temperature gate bias (HTGB), marathon testing, gate voltage step-stress test, etc. On the other hand, dynamic stress test methodologies are still evolving, such as alternating current bias temperature instability (AC-BTI), gate switching stress (GSS), dynamic gate switching (DGS), etc. These types of testing strategies are complementary in nature and should be combined to gain deeper insight into the reliability of the gate oxide. This study compares the gate oxide stability as well as the degradation modes regarding long-term VTH stability of the next generation of commercial 1200V SiC MOSEFTs with planar and trench gate technology, Table 1 gives an overview of the tested devices. Here, we apply a combination of static stress tests such as TDDB and DC-BTI with dynamic stress methodologies, e.g. AC-BTI [3] and DGS. As a part of pre-characterization, the gate leakage current was measured until the devices failed; this information is important for establishing the test parameter for TDDB. The trench type SiC MOSFETs exhibit lower leakage current at the same voltage compared to planar type. This is primarily due to the lower effective electric field in trench devices, which is a result of the thicker oxide layer typically used in trench type devices. To investigate TDDB, 10 devices were tested for three different gate oxide voltage levels and all the measurements were carried out at 175 ºC. The leakage current was monitored continuously during the TDDB measurement period. For both planar and trench devices we observe a slight decrease in the gate leakage current until a certain time t0 attributed to rather trivial charge trapping (as shown in Figure 1). However, beyond t0, i.e. during the so called “wear-out” phase [4], the trench devices show a significantly higher and longer decrease in leakage current until device failure at tfail compared to the planar devices. This decrease in gate leakage current during the “wear-out” phase is attributed to large electron trapping and may result in VTH drifts [4]. Thus, the trench devices are expected to have a larger number of electron trap sites at the interface or in the dielectric layer. Figure 2 shows the Weibull distribution obtained from trench and planar devices. The shape parameters from the Weibull distributions obtained from trench and planar device are greater than 1, indicating the main reason for failure is aging related. Based on the Weibull distribution, the extracted t63% as a function of applied gate voltage is plotted in Figure 3 for both types of devices. The planar type demonstrates a lower predicted lifetime in comparison to trench. However, robust gate oxide reliability does not implicitly imply robust Vth stability. In order to understand the impact of stress on BTI and GSI we additionally perform DGS and static HTGB. Furthermore, the influence of the “wear-out” phase on VTH stability was estimated by combining static stress with AC-BTI. This study highlights the differences and similarities between the stress response of planar and trench type devices and illustrates the key reliability strategies to implement based on the device type.

ABSTRACT. Single Event Burnout (SEB) is a destructive failure mode in power devices, triggered by heavy ion-induced charge flow. To support SEB mechanism studies, we developed a high-bandwidth measurement technique using a tabletop pulsed-laser system. A 400 nm, 130 fs laser induced two-photon absorption in a SiC Schottky Barrier Diode, and transient voltages were captured with a 10 GHz Bias Tee and 15 GHz oscilloscope. The filtered waveform showed a fast rising edge and exponential decay, with a 10.5 ns rise time. This method enables precise observation of laser-induced transients and is applicable to SEB-related evaluation.

ABSTRACT. Despite the superior performance offered by silicon carbide, there are still critical aspects that need to be investigated. Among these, the stability of gate leakage currents and threshold voltage is particularly relevant [1-3]. It is widely accepted that, under positive bias, the gate leakage current is determined by Fowler-Nordheim tunnelling, a process that strongly depends on the electric field. However, a clear description of the changes in gate leakage current induced by long-term operation and charge trapping has not been given in the literature. This paper aims at filling this gap, by showing the following relevant results: a) when submitted to constant voltage stress, SiC MOSFETs may show a threshold voltage variation; analysis of the VTH(t) data can provide quantitative information on the amount of positive and negative charge stored in the dielectric; b) as a function of stress time, the gate leakage current can show a non-monotonic variation, related to positive/negative charge trapping; c) such variations are related to a change in the electric field responsible for Fowler-Nordheim tunnelling at the SiC/SiO2 interface. d) To support these hypotheses, an analytical model has been proposed: the model takes the threshold voltage variation as an input parameter and is able to accurately predict the variation of gate leakage current as a function of time for the whole duration of the stress. Good qualitative agreement with experimental data is found. The analyzed devices are planar n-channel 4H-SiC MOSFETs, having a gate oxide thickness of 40 nm and a gate oxide area of 1.2∙10^(-1) cm^2. The stress experiments were carried out at 200 °C, by submitting the devices to constant voltage stress at different voltages (31 V, 33 V, 35 V, 37 V). During the stress, I_D V_G characteristics of the devices were monitored, by performing a dc V_GS sweep from -10 to +22 V and back with V_DS=0.1 V. The resulting threshold voltage shifts are shown in Figure 1. The variations in gate leakage current are depicted in Figure 2. The threshold voltage variations over time were fitted by a polynomial formula, with the aim of obtaining an analytical relation between threshold voltage and time (the goal of the fits is to minimize the error between the fitted and experimental data, the polynomial relation does not have any intended meaning); the resulting data were used to extract the amount of positive and negative trapped charge (Eq. 4, Figure 3). Charge trapping results in a change in the field responsible for FN conduction, as schematically shown in Figure 4 and analytically computed in Figure 5. The variation in gate current density was calculated by using the Fowler-Nordheim formula (Eqs. 1-7), by considering the change in electric field induced by electron and hole trapping (Eq. 4 and 5). The resulting current densities were then scaled, in order to match the initial level (coefficient c in Eq. 1). The scaling factor c was found to be slightly voltage dependent. In Figure 6 the final matching is shown, considering trap locations located at x_e=3 nm for electrons and x_h=25 nm for holes from the SiO2/SiC interface. In summary, we propose a methodology for modeling the variations in gate leakage current induced by charge trapping; the methodology is based on the quantitative evaluation of the amount of trapped positive and negative charge which is extracted from the VTH shift, and of the consequent impact on FN current. Good qualitative agreement with experimental data is demonstrated.

ABSTRACT. Silicon carbide (SiC) has increasingly attracted attention as an outstanding material for power devices in recent years. However, the reliability of SiC-based devices is becoming a critical concern in the development of next-generation wide bandgap semiconductor technologies. One key challenge is mitigating delamination phenomena caused during the formation of ohmic contacts at the back side of the wafer. In particular the formation of Ni based ohmic contacts as this material is widely used for backside metallization in n-type 4H-SiC semiconductors [1]. Understanding the root causes of delamination and developing strategies to prevent it is essential for improving device robustness and reliability.

The formation of an Ni based ohmic contact on SiC is achieved by laser annealing of NiAl layer deposited on the backside of the SiC wafer. This process results in a surface carbon layer on top of the NiSi layer, which limits film adhesion of subsequent contact layers. This study investigates the effectiveness of surface cleaning procedures to enhance adhesion properties while maintaining the electrical performance of the ohmic contact. All tests were conducted on 350 µm thick n-type 4H-SiC wafers covered with a 60 nm NiAl layer (with 2.6 wt% Al) processed under inert atmosphere with varying laser conditions. These setups utilized a frequency-tripled Nd:YAG (neodymium-doped yttrium aluminum garnet) nanosecond laser with a wavelength of 355 nm. We applied various cleaning methods like laser annealing, ion etching, HF wet cleaning, and dry etching to remove the free surface carbon on top of NixSiy layer. These cleaning methods were evaluated based on their impact on mechanical adhesion and electrical performance after the application of a second metallization layer.

In order to evaluate the impact of carbon removal via the different cleaning methods on the delamination behavior, the pull test (Fig 1) is used for quantifying the mechanical adhesion. CTLM (Circular Transmission Line Measurement) structures are applied for measuring the specific contact resistance at the interface between SiC and the NixSiy layer (Fig 2). Additional structural characterization methods such as X-ray fluorescence (XRF), scanning electron microscopy by focused ion beam (FIB) prepared cross-section (Fig 3), sheet resistance measurements, atomic force microscope (AFM) and energy dispersive X-ray spectroscopy are used to distinguish between changes in the atomic composition, and structural effects and how they contribute to the adhesion between the SiC and NixSiy layer. We present our findings on the correlation of surface carbon cleaning and delamination effects of the backside metal. This work contributes to the fundamental understanding of interface behavior in SiC systems and provides a practical approach for enhancing the reliability of wide bandgap power devices.

We would like to extend our sincere thanks to 3D-Micromac AG with whom we have collaborated for our work specifically laser annealing and cleaning procedures.

[1] C. Hellinger, doctoral thesis, Empirisches Modell zur Bildung von nickelbasierten Ohmkontakten auf n-Typ 4H-SiC durch Laserbearbeitung (2023) p.3

ABSTRACT. The advancement in transportation, such as electric vehicles, has increased the demand for silicon carbide (SiC) power modules due to their superior switching loss, speed, and current density over silicon modules. However, managing parasitic elements in SiC power module design is crucial due to the high di/dt and dv/dt feature and often challenging due to compact packages. Expert-based iterative design can only cover a limited design space and may result in a local optimum as it is a time-consuming manual process. Recent research has focused on automatic layout design methods which are, however, limited in the number of design variables to achieve desired performance. This paper presents a robust surrogate model-based optimization methodology for exploring power module design spaces, capable of simultaneously optimizing multiple objectives with several design variables. The approach both accelerates the design process compared to conventional simulation methods and identifies design solutions that may be challenging to discover through knowledge-based approaches alone.

ABSTRACT. The automobile industry has shown much interested in power semiconductors owing to their power density and rough operating environment. Recently, the demand for wide-bandgap (WBG) devices, which are in spotlight in industries such as customer electronics and renewable energy, is increasing considering it can improve efficiency and power density owing to high thermal conductivity, wide bandgap, high saturation velocity, high electron mobility, and high breakdown voltage. However, despite these advantages, thermal reliability problems are still a challenge in WBG devices such as silicon carbide (SiC) and gallium nitride. Therefore, it is important to safely satisfy reliability test and accurately estimate the junction temperature, which is an indicator of the thermal reliability on the power modules. Despite the limitations of contacting measurements like Infrared camera, thermocouples and optical fibers, Temperature Sensitive Parameter (TSP) is highly effective indicators for monitoring the virtual junction temperature of power module. Typically, the temperature measurement of a semi-conductor device is necessary for two steps: calibration, which is used to determine the relationship between the electrical parameter and temperature, and dissipation, which power device is operated by a current that creates high heat losses. In case of Insulated Gate Bipolar Transistor (IGBT), many TSPs is utilized for monitoring junction temperature: forward voltage (VF), threshold voltage (VTH), gate-emitter voltage (VG-E), saturation current (Isat). Especially, the measurement of the VF of a body diode passing low current is frequently used in the electronics field and for method as temperature sensors. Of particular interest is the good linearity of the temperature measurement. The voltage dependence about temperature is generally close to -2 mV/°C for Si devices [1]. Additionally, SiC MOSFET is mainly adopted the VF as TSP because it has more linear characteristics which is not as good as Silicon device according to temperature than other parameters. For calibration of the VF as TSP, the ambient temperature is established by an external system like an oven or thermally controlled cold plate. Then a measuring current and gate off voltage is applied for measuring voltage versus body diode and turning off switching device. For SiC MOSFET, some current can flows although gate-source voltage is zero (VGS=0V) which means short configuration caused by body effect [2]. The potential passing current is composed of two types: a current through the body diode and a current through the channel. When the VGS applies from 0V to recommended operating voltage and then back to 0V, the electrons are trapped in the interface between the SiC layer and the gate oxide layer. It causes variation of the conductivity of the channel and so affects two type current involved about temperature measurement procedure, which finally makes the VF value unstable and distorts the estimated temperature. Thus, sufficient negative-source gate voltage must be applied to block the current through the channel. For evaluating reliability of power module, power cycling test is frequently conducted because it is accelerated lifetime test and caused thermo-mechanical stress to confirm durability of packaging components and switching device. The conducting current is decided by rated current and the number of parallel devices and operating voltage commonly follow recommended voltage from datasheet. However, depending on device characteristics, negative VGS determines VF value and saturating voltage level is different. Typically, the recommended operating off voltage of SiC MOSFET device ranges -6v from -2V, while minimum voltage is -8V rated. Additionally, as the temperature range is wide and high, accurate temperature estimation is very critical during this reliability test. In this test, VF is temperature parameter, inaccurate measured voltage causes unsuitable load and inconsistent results. Thus, we closely analyzed the forward voltage of the SiC MOSFET to examine the accuracy of temperature estimation during the power cycling test. Before the test, the DUT of power module is electrically tested as the gate voltage becomes progressively more negative from 0V to -8V in same sensing current. As a result, the body diode voltage becomes higher until VGS = -6V as shown Fig. 1 (a), which means that the current through channel part is not perfectly eliminated. As VGS becomes more negative (-6 V to -8 V), VF appears to be constant, but a closer look at the voltage intervals (0.2 V) reveals a very small difference as shown in Fig. 1 (b). Judging from these data, it raises questions about whether the body diode is fully operational at a negative VGS condition and whether it is accurate in estimating junction temperature in the power cycling test. Additionally, the slope of the calibration data of a typical SiC MOSFET device, i.e., the K-factor, has a value of about 2.5 mV/K. It means that the resolution range of the estimated junction temperature varies greatly depending on the negative VGS set during power cycling test, and as the power cycling test progresses, the VF value changes for each sample due to deterioration, so the temperature estimation becomes increasingly inaccurate. Therefore, this paper examines how the VF value deteriorates at negative VGS as the power cycling test conducts. We conducted the power cycling test for half-bridge circuit power module which contains 6 samples for high side and low side. To conduct sufficient damage around switching device, we conduct 50k cycle for PCsec in accordance with AQG 324 considering operating maximum temperature [3]. The experiment voltage condition is set as recommended voltage (18V/-3V) by chip datasheet to satisfy purpose of this reliability test which reflects operating environment. As a result of comparing the VF @100mA data before and after the reliability test, it showed an average decrease of about 1% in 12 test samples after 50k cycles. However, when negative VGS becomes lower, the variation by degradation showed an average decrease of about 0.02% which comparatively is much smaller. It means that temperature monitoring is poor during the power cycling tests when applying the typical operating voltage and that sufficiently low negative VGS must be applied to accurately estimate the temperature. Thus, we present guidelines on the negative VGS conditions that should be applied during the power cycling test.

ABSTRACT. In this paper we will describe the fabrication of a two-step inductively coupled plasma (ICP) etch process to make various microstructures using contemporary quality 4H-SiC. The microstructures of interest are a nominal base-line design of a seismometer, a simple beam, and a ‘chiplet’ or ‘interposer’ for packaging. The first two structures will be tested in the linear elastic regime using a modified Dektak stylus profilometer to measure deflection versus force. ANSYS modeling will utilize the measured stress-strain data to determine the Young’s modulus. Future work on these devices will include SEM imaging, thermal oxidation, TEOS SiO2 and TaSi2 depositions, and thermal cycling to 800 °C. In the past few years, NASA Glenn has increased the maximum operable temperature of complex 4H-SiC electronics by optimizing the back end of the line (BEOL) processes and materials. TaSi2 interconnects, with a relatively low CTE, were tailored to be low stress at temperature. Bond pads used iridium interfacial stack (IrIS) metal [1] of TaSi2/Pt/Ir/Pt, with a high CTE and residual stress, but were structurally anchored to the SiC. Interconnects were buried with LPCVD TEOS SiO2 and Si3N4 with no high CTE metal on top. These unique solutions have demonstrated 60 days operation at Venus surface conditions [2] and (in air ambient) over a year operation at 500 °C [3] and over 100 hours at 800 °C [4,5]. MEMS sensors are needed for the same conditions and our group will leverage these advancements in electronics, making the sensors in SiC with the same BEOL robust steps and materials, enabling monolithic integration of sensors with electronics and a unique SiC-based solution. Si-based bulk micromachined seismometers have been demonstrated for off world missions such as Mars [6,7]. To test the feasibility of the process flow of a SiC-based variant a simplified seismometer is shown in Fig. 1. This paper will discuss deflection normal to the surface. Future work will measure in-plane deflection optically with a shaker table, similar to the intended operation, comparing g-force and frequency response. Fig. 2 show a simple cantilever beam in 4H-SiC. The majority of past work on free standing SiC cantilever beams has been in 6H [8]. This new process uses two reactive ion etches (RIE), an inductively coupled plasma (ICP) etch on the frontside [9] with no trenching at the edges and a parallel plate RIE on the backside to release the device, and is more representative of current materials and processes. Fig. 3 show the ‘chiplet’. Presently, alumina-based high temperature packaging is large at 1x1 inch for our 5x5 mm die. Package leakage grows exponentially starting at 450 °C [10] and is the only observed leakage seen at 800 °C for our JFET-R device. In addition, at the moment many of the bond pads are used just to provide VSS, VDD, and GND and are kept separate to minimize current through any one bond pad or power bus. Connecting power on-chiplet and/or putting multiple chips on a chiplet or interposer would greatly decrease the number of traces leaving the chiplet and allow less leakage between the same pitch traces to the package.