Investigation on Bipolar Degradation caused by In-grown Stacking Fault in 3.3 kV SiC-MOSFET
ABSTRACT. This study investigates bipolar degradation in 3.3kV SiC-MOSFETs, focusing on leakage current degradation (IDSX) caused by in-grown stacking faults (SF). High current stress tests were conducted on over 1,500 chips, identifying 45 with IDSX degradation. Detailed analysis using photoemission microscopy and photoluminescence (PL) imaging revealed that the IDSX degradation was linked to in-grown SFs, where Shockley stacking fault has expanded under high current stress. This study confirms that in-grown SFs can cause IDSX degradation, suggesting that such defects are significant contributors to the bipolar degradation phenomena in SiC-MOSFETs.
Impact of threading dislocations on carrier lifetimes in 4H-SiC epilayers
ABSTRACT. The minority carrier lifetimes in the drift layer significantly affect conduction and switching losses in 4H-SiC PiN diodes and IGBTs. In low-doped 4H-SiC epilayers, the minority carrier lifetimes are often controlled by carbon vacancies, specifically the Z1/2 center. To address this, carbon diffusion processes are often employed to reduce the concentration of carbon vacancies. In this study, we investigate another limiting factor of carrier lifetimes in n-type epilayers, namely threading dislocations (TDs), as part of efforts to further improve carrier lifetimes and their uniformity on the wafers.
Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach
ABSTRACT. SiC power devices exhibit superior performance compared to conventional silicon-based counterparts. However, during the epitaxial growth of SiC, basal plane dislocations (BPDs) propagate from the substrate into the epitaxial layer. Further complications arise from the fact that BPDs dissociate into pairs of partial dislocations (PDs) on the basal plane, accompanied by Shockley-type stacking faults (SSFs), which expand when low-energy holes interact with the Si-core. The expansion of these SSFs leads to bipolar degradation. Proton implantation has emerged as a promising technique for suppressing the formation of SSFs. In this study, we evaluate the impact of proton implantation depth on the suppression range measured from the epitaxial surface. Furthermore, we investigate the underlying suppression mechanisms by analyzing the atomic and electronic structures surrounding the SSFs.
Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC
ABSTRACT. Energy-Filtered Ion Implantation (EFII) is a novel ion implantation technology [1] which has many applications in 4H-SiC power device manufacturing. EFII is used for drift zone doping on SiC epitaxial wafers, enabling doping uniformity below 3%. Our recent work reported its application for suppressing 1SSF expansion in 4H-SiC. Further, it can be used for carrier-lifetime engineering by ion implantation in the drift layer [2]. Understanding the influence of EFII on introduction of deep levels in epitaxially (CVD) grown 4H-SiC is necessary due to the broad spectrum of energies associated with the implanted ions. This work investigates the deep level defects introduced by the EFII process on commercial 4H-SiC epitaxial wafer from different vendors. The experiments contains various concentrations of implanted Nitrogen in the range 1E14 - 1E16 cm-3, up to a depth of 8μm into the entire drift layers as blanket implant. All implantations were performed at 19 MeV Nitrogen. Implanted and un-implanted regions underwent identical activation annealing steps. Schottky (Ni/SiC) contacts were used for DLTS and semi-transparent (20nm thick) Ni contacts at the same locations for MCTS measurements. Samples with implanted nitrogen concentration of 1E15, 5E15, 1E16 cm-3 were probed up to 1μm depth and the peaks are analyzed qualitatively and quantitatively.
1/C² vs V plot for all the implanted samples reveal homogenous doping profile over the probed depth. DLTS spectrum reveals nine peaks in all EFII implanted samples. Energy levels of each peak and their trap concentration (NT) for implanted nitrogen samples are tabulated and compared. All EFII implanted samples show same defect peaks. The dominant peaks are assigned to Z1, Z2 and EH6/7 respectively, which are often performance-limiting defects in SiC devices. The overlapping peaks T5, T6 will be resolved with further investigation. As the EFII process involves 1700°C anneal with carbon capping layer facilitates carbon injection, leading to a Ci complex and hence defect peaks T5, T8 could relate to ON family of defects [4]. The trap concentration values reveal that the dominant trap concentration are in the range of 0.3 - 2E13 cm-3 as seen on as-grown CVD material [6]. This suggests that the EFII implants with MeV energy does not create significant point defects. The MCTS results show three acceptor traps which are shallow in nature among which B´´ is the prominent trap and no D centres were detected in any of the samples. Other results covering the full range of implant concentration, depth profile of traps will be included in the manuscript. The identification of these stable deep levels after high-temperature annealing is a significant step towards understanding the traps generated from particular process steps and thus to determine their influence on performance and long-term reliability of EFII-processed SiC materials.
Investigation of Photoluminescence Emission and Characteristic Wavelength of Various Large-Height Shockley-Type Stacking Faults in 4H-SiC Epitaxial Layers
ABSTRACT. Various kinds of stacking faults (SFs) have been reported in 4H-SiC epitaxial wafers. Identification of SFs and structure determination have been investigated by using characteristic photoluminescence (PL) emissions from SFs and high-angle annular dark-field high-resolution scanning transmission electron microscope (HAADF HR-STEM) [1-3]. In the IEC standard document [4], seven representative SFs, which are four kinds of Shockley-type SFs (SSFs) and three kinds of Frank-type SFs (FFSs) with corresponding characteristic PL wavelengths (C-PLWs) are described although some of C-PLWs are arguable. The four representative SSFs are single (3,1), double (6,2), triple (5,3), quadruple (4,4) SFs and the three FSFs are (5,2), (4,2) and (4,1) SFs. Table 1 summarizes C-PLWs for the seven representative SFs from IEC standard [4] and recent our reports [1-3, 5]
There are lots of SF variations with the Zhdanov notation numbers of “3” and “2” like (3,2), (3,3), (3,1), (3,3,3,3), (3,3,3,3,2), (3,3,3,3,3,2), (3,2,2,3), (3,3,3,2,3,2), and (3,2,3,3,3,2) SFs. The C-PLWs for these SSFs were ranged between 420-430 nm [2].
In this study, we investigated various kinds of (3,X) SSFs with large height more than 20 layers by HAADF HR-STEM and PL spectra analyses. In order to support the determined C-PLWs by PL measurements theoretical calculations of band structures for the perfect 4H-SiC with and without the SFs were carried out. Furthermore, we determined band offset between the perfect 4H-SiC and the 4H-SiC with the SFs.
Fig. 1 shows HAADF HR-STEM images for the (3,2,2,3,2,2,2,2,2,2,3,2,3,2), (3,3,2,2,2,2,2,2,2,2,3,3), (3,2,3,2,2,3,3,2), and (3,3,2,2,2,2,2,2,2,2,4,2) SFs. All these SFs are SSFs becasue the sum of the Zhdanov notation numbers of each SF is multiple number of 4 [1]. Fig. 2 shows PL spectra for the SSFs observed in Fig. 1. The SSFs (3,2,2,3,2,2,2,2,2,2,3,2,3,2), (3,3,2,2,2,2,2,2,2,2,3,3), and (3,2,3,2,2,3,3,2) showed C-PLWs of 425, 427, and 428 nm, respectively. The observed C-PLWs of these SFs belong to the range of 420~430 nm, which well agreed with the previous report [2].
However, very surprisingly, the Shockley-type SF (3,3,2,2,2,2,2,2,2,2,4,2) showed C-PLW of 457 nm, which was exactly same to the C-PLW of the Frank-type SF (4,2) mentioned in Table 1. In fact, we expected it to be the FSF (4,2) based on the PL spectrum result before confirming the SF structure by HAADF HR-STEM observation.
This result implied a very importnat conclusion that the C-PLW from the SF was determined by a fractional part of the SF with the corresponding longest PL wavelength of the fractional part (4,2) not by the whole SF structure. From this conclusion, we can understand the C-PLWs of SFs in Fig. 2 (a), (b), and (c) of 425, 427, and 428 nm, which were determined by fractional part of (3,2) and (3,3). Theoretical DFT calculations for the band structures and band offset results to support the observed C-PLWs characteristics will be presented and discussed.
This work was supported by the Technology Innovation Program (No. 25A02037, 25A02099) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).
[1] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Mater. Sci. Semicond. Process. 175, 108247 (2024).
[2] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Appl. Phys. Lett. 124, 152109 (2024).
[3] M. Na, S.-K. Hong, W. Bahng, H. Jung, C. Oh, D. Jang, D. Kim, T. Iqbal, J. Park, Y. G. Park, Appl. Surf. Sci. 703, 163425 (2025).
[4] International Electrotechnical Commission (IEC), Semiconductor Devices, Part 3, IEC 63068-3:2020, IEC, 2020.
[5] Will be presented at ICSCRM 2025.
Breaking the performance limits in 4H-SiC semi-superjunction devices through asymmetric pillar engineering
ABSTRACT. The optimal static performance limit of symmetric semi-superjunction (semi-SJ) designs can be theoretically surpassed by adopting asymmetric pillar widths and doping concentrations. By deriving exact expressions of electric field for arbitrary asymmetric semi-SJ geometries based on Poisson's equation, we demonstrate that the trade-off between specific on-resistance and breakdown voltage can be further improved by widening the n-pillars while lowering their doping density. This asymmetric configuration mitigates the adverse effects of incomplete ionization and mobility degradation in the n-pillars, while the increased pillar width enhances conductance. These effects collectively compensate for the resistance increase associated with reduced doping, resulting in a net decrease in resistance. Meanwhile, the breakdown voltage is preserved due to suppressed electric field concentration at the pillar interfaces, achieved through increased p-pillar doping to satisfy the charge balance condition. As a result, the specific on-resistance is reduced by approximately 13-19% over the target voltage range of 2.2-5.2 kV without compromising in the case of symmetric design.
Impact of Void Formation on Semi-Superjunction SiC Schottky Rectifiers for Trench-Filling-Based Fabrication Process
ABSTRACT. Silicon carbide (SiC) power devices are increasingly adopted in high-voltage applications due to their wide bandgap, high critical electric field, and excellent thermal conductivity. However, as voltage ratings increase, SiC unipolar devices face a fundamental trade-off between on-resistance and breakdown voltage, limiting further performance improvements. The superjunction (SJ) architecture- featuring vertically charge-balanced P/N pillars has been successfully implemented in silicon devices using multi-epitaxial growth and implantation to break the unipolar limit, though low dopant diffusivity makes this technically and economically challenging in SiC [1]. Consequently, trench filling epitaxy has been investigated [2], in which trenches formed in a N-type epitaxial layer are refilled with P-type using the same chemical vapor deposition (CVD) epitaxial reactors. Despite potential advantages as a practical and cost-effective means to form deep p-pillars for high voltage (≥3.3 kV) devices, the previous study [2] identified that the formation of voids in near-vertical trench geometries. Seen in Fig. 1, the void size shrinks with increasing sidewall angle. However, the ideal sidewall angle of 8° imposes minimum pillar widths in order to accommodate the geometry, and prevent inhibiting pinch off effects. These process-related trade-offs underscore the need to understand the impact on device performance of voids in the p-pillars, and the design compromises that would facilitate their removal.
In this study, TCAD simulations are used to investigate the design trade-offs of a semi-SJ SiC Schottky rectifiers, considering the effect of void creation and side wall angle. First, a series of void-free, charge balanced structures (NA=ND) were designed, covering variations, depicted in Fig 1b, in doping, trench sidewall angle, pillar width (PW), and bottom thickness (TB). For each geometry, a series of TCAD simulations informed response surface models to determine the best Ronsp under a given BV with varying doping concentrations, resulting in the unipolar limit (Ronsp-BV) plots, of Fig. 2, and the implantation dose window results of Fig.3. A figure-of-merit (FOM) defined as BV2/Ronsp was used to identify the optimal device from each geometry, resulting in the summary graph of Fig. 4. These results serve as the initial baseline prior to introducing void-related process variations.
Voids were introduced into the TCAD structures, their shape determined by the results of [2]. While the previous N-pillar doping was retained, the p-pillar doping was reoptimized to find the new, increased, value that would compensate for charge lost from the void. Representative structures with PW=2 μm, TB=2 μm and varying trench angle are shown in Fig. 3 in which the devices with trench angles of 0°, 4°, and 8°, resulted in decreases in breakdown voltage by 60.8 V, 76.6 V, and 57.0 V respectively. Corresponding implantation dose windows, defined as allowable trench doping maintaining at least 80% of peak BV, increased by 93.7%, 65.2%, and 36.3%. This is attributed to the reduction in effective charge density within the P-pillar caused by the void. Fig. 5 summarises the optimal device for every geometry after the introduction of a void. Across all geometries, the introduction of a void results in an average breakdown voltage reduction of 52.7 V and an increase in dose window by an average of 52.0%.
Having established the trade-offs in all SJ designs with and without voids, it is possible to consider the practical implications from Fig.1 and [2]. In Fig 6, an “ideal”, but practically unrealisable, superjunction device is shown, with TB = 2 µm, PW = 2 µm, a trench angle of 0°, and no void. Also plotted are the two realisable compromise approaches. The approach taken in [2], to increase trench angle to 8° to avoid void formation, results in a minimum 20% increase in resistance, and a reduction in the blocking voltage of 23 V. Alternatively, maintaining the device geometry and increasing the doping around the void ,will lead to a 76 V reduction in blocking voltage, but no appreciable resistance penalty. Other scenarios, combining the void’s presence with increased sidewall angle, or the wider PW of 3 µm, all result in further resistance and blocking voltage penalties. In summary, the issue of void creation during trench fill epitaxy is most optimally solved by introducing a sidewall angle sufficient to prevent the formation of the void in the first place. However, the alternative approach, of compensating for the void’s presence with increased p-pillar doping, is viable with minimal further loss in device performance. These findings support the feasibility of void-aware SSJ design as a viable path toward robust and manufacturable high-voltage SiC devices for future commercial applications.
Body diode performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET
ABSTRACT. This work investigates the body diode and reverse recovery performance of 3.3 kV 4H-SiC MOSFETs, focusing on a planar semi-Superjunction (semi-SJ) structure featuring sidewall p-implantation through a deep trench refilled with SiO₂. The semi-SJ design is compared with a conventional planar MOSFET and a planar full-SJ device incorporating vertical p-pillars. The proposed semi-SJ design reduces on-state resistance by up to 23% and improves breakdown voltage by 500 V over the planar MOSFET. The full-SJ achieves a 47% reduction in on-state resistance and a breakdown voltage of 5.3 kV. Body diode behaviour was evaluated under varying gate biases; reduced conductivity modulation in the semi-SJ leads to the highest forward voltage drop (4.3 V at 50 A), while the full-SJ demonstrates superior third-quadrant performance. However, the deeper p-pillars in the full-SJ result in higher drain-source capacitance and a 3.5× increase in reverse recovery charge, leading to increased switching losses and ringing. Based on the RON X QRR figure of merit, the semi-SJ offers a balanced trade-off between conduction and switching performance, while also providing reduced fabrication cost compared to other SJ technologies.
Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET
ABSTRACT. SiC DMOSFET conventional integral diodes differ from those fabricated in Si by exhibiting much faster reverse recovery (RR), while exhibiting greater snappiness and a larger forward voltage drop, which can lead to large voltage overshoots and increased power loss. Charge balance (CB) and Superjunction (SJ) drift layers improve the on-state performance of the SiC DMOSFET by improving the trade-off between RON,sp and BV. However, the improved on-state performance of the CB and SJ can be counteracted by degraded RR performance, as observed in the Si SJ integral diode through excessive oscillations during RR due to the rapid changes of the SJ capacitance with voltage [1]. SiC DMOSFET with SJ and CB drift regions and a breakdown voltage of 3.3kV have previously been fabricated and characterized [2]. RR measurements are comparatively performed on the integral diode of these MOSFETs and key RR performance parameters are extracted. The temperature is varied from 77K to 423K, the reverse voltage from 500V to 1kV, and the ramping rate from 25A/μs to 93A/μs. All switching is performed at JF=50A/cm2. Expected RR behavior is for QRR,sp to increase with temperature due to increases in the minority carrier lifetime with temperature [3]. However, the SJ device exhibits an anomalous 1.4x-3.5x increase in QRR,sp at 77K compared to room temperature. The anomalous increase remains at JF=20A/cm2 but disappears at JF=7.5A/cm2. The strong linear dependence of QRR,sp on the ramp rate at 77K indicates an increase in stored charge at 77K, as it is the swept-out charge Q0 that is strongly dependent on the ramp rate. Analytical calculations of the depletion capacitance at zero bias show a 4% decrease at 77K compared to room temperature, which cannot explain the large increase in QRR,sp. Static I-V characterization reveals the onset of current-controlled negative resistance (CCNR) solely for the SJ device at 77K and JF=50A/cm2. The CCNR indicates substantial filling of the traps in the damage layer, allowing holes to be injected into the n-pillar. [5] The absence of similar behavior in the CB and conv. device suggests this behavior drives the excessive QRR,sp at 77K. While at 77K, the SJ device exhibits a QRR,sp 1.9x-3x of the CB device, at other temperatures it is generally faster, exhibiting a QRR,sp of 0.41x-1.15x of the CB device. For both the SJ and CB devices, the best snappiness (tB/tA) behavior is observed at room temperature. The SJ devices are consistently snappier than the CB devices, in all scenarios and temperatures tested. At room temperature, tB/tA for the SJ device is between 0.23x-0.56x of the CB device, as is expected since the SJ pillars must fully deplete before they can support significant voltage. This constraint on the SJ also leads to an increase in JPR with the SJ devices demonstrating a JPR of 1.8x-2.8x compared to the CB devices. With the exception of the anomalous behavior of the SJ at 77K, the weak dependence of QRR,sp on the ramp rate indicates the RR for both the SJ and CB devices is junction-capacitance dominated as it is for the conv. SiC integral diode. [3] The combination of the significantly improved snappiness of the CB device, the reduced JPR, and the increasing QRR,sp and JPR with temperature favor the usage of a CB integral diode over an SJ integral diode in circuit applications. Although CB diodes exhibit worse forward recovery characteristics than conv. diodes [6], the CB integral diode demonstrates similar RR performance [4].
Insight into Bias-Temperature Instability of SiC MOSFETs using Charge Pumping and Triple-Sense Threshold Measurements
ABSTRACT. Bias-temperature instability (BTI) is one of the primary sources of parameter drift in silicon and SiC MOSFETs and consequently largely determines device lifetime. Most studies of BTI in SiC MOSFETs characterize the threshold voltage (VT) but not the interface trap density (Nit), leaving uncertainty about the relative contributions of carrier capture and trap creation to the VT shift. In this study, to lend insight into the physical mechanisms responsible for BTI in SiC MOSFETs, we characterize the evolution of Nit during bias-temperature stress (BTS) using the charge pumping (CP) technique. We also characterize the shift in VT and hysteresis using the triple-sense method [1] for comparison with the Nit changes, demonstrating the utility of this technique for reliable characterization of VT and hysteresis.
The devices studied are lateral, 4H-SiC MOSFETs fabricated on 4° off-axis 4H-SiC epitaxial wafers, with an implanted acceptor concentration of 2×1017 cm-3 in the channel, a thermal gate oxide formed on the Si face followed by NO annealing, and a channel length and width of 2 μm and 200 μm, respectively. The bias and measurement sequence during positive BTS is shown in Fig. 1(a). After each BTS interval, three ID-VGS sweeps are performed, from which three sense measurements of VT are obtained. For positive BTS, sweep #1 is a down-sweep from inversion to retain the electrons trapped at fast interface traps, sweep #2 is an up-sweep starting in accumulation to rapidly eliminate the trapped electrons by recombination, and sweep #3 is a down-sweep from inversion again. Thus, sweep #1 captures the maximum VT shift due to temporarily charged acceptor interface traps, sweep #2 minimizes the effect of acceptor interface traps by conditioning the interface with an accumulation bias, and sweep #3 allows measurement of the quasi-permanent hysteresis by comparing it with sweep #2. Fig. 1(b) shows representative ID-VGS curves resulting from the triple sense method in this study. The triple-sense measurement after each BTS interval is followed by CP, using a gate pulse amplitude of 15 V, a rise/fall time of 1 µs, and a high/low time of 10 µs.
Fig. 2(a) shows the ID-VGS curves for sweep #3 after each positive BTS interval for a cumulative stress time (tstress) ranging from 0 s to 1000 s, for a bias stress field of 7.3 MV/cm in the oxide and a temperature of 175°C. This stress condition is highly accelerated while maintaining normal BTI degradation physics. The ID-VGS curve shifts in the positive direction monotonically with increasing tstress. As shown in Fig. 2(b), the VT shift is accompanied by an increase in hysteresis between sweeps #2 and #3, suggesting an increase in interface and/or border trap density. Fig. 3 shows the change in Nit as a function of tstress measured by CP. The Nit increases with tstress as a power law with an exponent of 0.42, demonstrating that new interface traps are indeed created during positive BTS. Spectroscopic CP (sCP) was also performed following the same procedure in [2] before and after the entire stress duration to evaluate changes in the Dit energy profiles, as shown in Fig. 4. The Dit increases on both sides of the bandgap, but primarily deeper in the bandgap.
Fig. 5(a) shows the change in VT from sweep #2 versus tstress, and Fig. 5(b) shows the change in hysteresis (ΔVhyst) between sweeps #2 and #3. Data are shown for VT corresponding to different drain currents. In addition, a quantity ΔVit was calculated using ΔVit = qΔNit/Cox and overlaid in each plot for comparison. This quantity represents the expected change in hysteresis due to newly created interface traps switching charge state when switching between inversion and accumulation. In Fig. 6(a), ΔVT,2 is ~3× greater in magnitude than ΔVit, indicating that most of the VT shift during positive BTS is due to electron capture in border traps, as opposed to interface trap creation. On the other hand, ΔVhyst when measured at low drain current converges with ΔVit, demonstrating that the newly created interface traps during positive BTS are responsible for an increase in hysteresis, which was also measured by the triple sense method.
Solid state defect emitters with no electrical activity in 4H-SiC
ABSTRACT. Point defects in semiconductors play a pivotal role in determining the electrical and optical properties of the host material. Understanding the physical fundaments of point defects in semiconductors was a key to arrive at the concept of opto-electronics devices, photovoltaics and energy storage devices, and very recently, state-of-the-art quantum information processing realisations [1] which have been shaped the socio-economical environment at global scale. Point defects may introduce defect levels (DLs) within the host semiconductor's fundamental band gap, thereby influencing its electrical conductivity, i.e., electrically active point defects [2]. Notably, these in-gap DLs and associated states also impact the optical properties of the material by reducing the optical excitation threshold energy compared to the perfect semiconductor's optical gap [3]. As a consequence, a common assumption is that solid-state defect emitters modify the host material's electrical conductivity [4]. We show below that this common assumption is not generally valid.
In Fig. 1, we depict the possible optical transition mechanisms within semiconductors. Many point defects introduce multiple deep DLs into the fundamental band gap that could dramatically modify the electrical properties of the host because these deep levels often participate in carrier trapping and recombination events. In these defects, the optical transition could occur between the occupied and unoccupied DLs in the gap (see Fig. 1a). Alternatively, the optical transition can occur between localized DLs and the band edge, either valence band maximum (VBM) or conduction band minimum (CBM) (e.g. Ref. [5]). The respective excited states may be called pseudo-acceptor and pseudo-donor states as they show a Rydberg-series of the excited states converging towards the ionization threshold (see Fig. 1b). We note that the optical excitation threshold energies are lower than the electrical gap between the occupied and unoccupied states participating in the optical transition because of the attracting electron-hole interaction in the excited state. By harnessing this excitonic effect, we suggest a category of point defects that act as emitters and are electrically inactive in the ground state at the same time. A defect may introduce just one occupied DL below VBM without disturbing the bands close to VBM, so the defect is electrically inactive in the ground state and its positive charge state is not stable. This defect can be optically excited where the hole is localized in the resonant DL whereas the electron occupies a state split from CBM that builds up a pseudo-donor excited state. The exciton binding energy in the excited state could shift the excitation energy below the optical band gap of the host semiconductor with establishing a solid state defect emitter (see Fig. 1c). We label these defects as EIDE after the expression of electrically inactive defect emitters in the context.
In this study, we demonstrate the principles of EIDE on a tri-carbon interstitial cluster in 4H silicon carbide (SiC) which produces an ultraviolet emission below the gap of 4H-SiC. First-principles calculations were carried out using density functional theory (DFT) with the hybrid HSE06 functional, combined with ΔSCF methods to describe excited states within a 576-atom supercell. Phonon-assisted photoluminescence was simulated using Huang-Rhys theory based on PBE calculations. Excitonic effects were accounted for through GW+BSE calculations.
Our results reveal that the given defect has zero-phonon-line (ZPL) emission with characteristic local vibration modes in the photoluminescence (PL) spectrum which agrees well with a previously reported defect emitter, the so-called DII center in 4H-SiC [6,7] (see Figs. 1e,f). The optical excited state is a pseudo-donor type and it does not show electrical activity. The effect is mediated by the attractive electron-hole interaction in the optical excited state of the defect enhanced by the resonant defect states which is strikingly paramount in indirect semiconductors.
This example expands our understanding of the interplay between defect-induced optical and electrical effects: we demonstrate the existence of defects that introduce optically active but electrically inactive states. This phenomenon may be observed in rather indirect than direct band gap semiconductors where all the defect levels lie outside to the fundamental band gap but reside very close to the band edges that may alter the minimal optical excitation energy without influencing the electrical conductivity. By exploiting the attractive interaction between electrons and holes in the optical excited state, these defects can show significant optical activity without exerting any discernible impact on the electrical conductivity. This finding might pave the ways to realize new generation opto-electronics devices. Additionally, due to their unique nature of being optically active yet electrically inactive, EIDEs may offer distinct advantages for quantum technologies, enabling photostable single-photon emission when isolated. Compared to well-known quantum emitters, which can undergo temporary or permanent photoionization during quantum optical manipulation, EIDEs remain electrically neutral and cannot be photoionized. This inherent neutrality eliminates charge-state instability, making them particularly suitable for integration with electronic components in quantum chip platforms.
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Parametrization of Emitter Photoluminescence and Color Center Quantification with Neural Networks
ABSTRACT. Color centers providing a spin-photon interface such as the silicon vacancy VSi in 4H-SiC bear promising applications for quantum technology devices [1-3]. Many device concepts include color centers close to the surface or close to interfaces [4], e.g. inside of waveguides for integrated photonics. Therefore, the parasitic influence of interfaces, including surface-related photoluminescent emitters, plays a major role in the device performance and complicates the material and device engineering process. The latter requires characterization and a deep understanding of surface emitter distributions, as well as a quantification of the color center generation yield close to the surface. To date, systematic approaches for surface emitter parametrization are missing and the color center generation yield quantification relies on g(2) autocorrelation measurements which is a highly time-consuming technique [5]. Approaches based on machine learning were so far limited to emitters deep in the bulk [6] due to a lack of training data including a sophisticated model of the surface emitter statistics. Real measurement data is naturally missing the corresponding ground truth required for supervised deep learning approaches and is usually not available to the extent required for network training.
In this work, we first present a novel approach based on brute-force fitting for systematic parametrization of surface emitter photoluminescence (PL) mappings. We apply this approach on ion-irradiated (see example shown in figure 1a) as well as pristine 4H-SiC epilayers and show that we can achieve a statistical insight into emitter distributions with only the photoluminescence mapping information required. We find distributions for the measured emitter point spread function width (figure 1b), as well as for the emitter brightness (figure 1c) and residual background (figure 1d). The brightness distributions for both samples reveal contributions from irradiation-independent surface emitters, from a class (bright emitters) assigned to VSi(h) color centers, as well as an unexpected additional, not yet identified emitter class of reduced brightness.
Subsequently, we demonstrate how to use the extracted statistical information to generate accurate synthetic training data for deep learning approaches, including a synthetic ground truth for supervised deep learning techniques.
Finally, we present the performance of our machine learning approach to color center yield quantification for the shallow implanted VSi(h) color centers close to the sample surface, which is many times faster than the state-of-the-art g(2) autocorrelation technique: From the original PL mapping (figure 2a), the network infers the position and brightness of the single emitters (figure 2b). Given the characteristic brightnesses of specific emitter classes, as shown in figure 1c, we can deduce the number of VSi(h) emitters from the network output.
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[6] D. Kim, S. Paik, J. Park, S.-J. Hwang, S. Onoda, T. Ohshima, D.-H. Kim and S.-Y. Lee, Adv. Quantum Technol. 7 (11), 2400173 (2024).
Interface NIR SPS: Newly observed single photon sources in SiC
ABSTRACT. Color centers/defects in semiconductors are promising single photon sources for realization of quantum information processing. It is known that SPSs exist at a SiO2/SiC interface, which exhibit bright emission and can be formed simply through thermal oxidation. However, the emission spectra of these interface SPSs are inhomogeneous, making it difficult to identify their origin and to find a way for practical use. We recently reported that such interface bright SPSs are almost eliminated by oxidation at high temperature. Even with that sample, weak background emission is detected from the interface. Similar phenomena have also been reported by other groups. In this study, we investigated the origin of the background emission using confocal microscopy. We identify that the background emission originates from a distinct class of interface SPSs emitting in the near-infrared (NIR). Remarkably, these SPSs exhibit highly uniform spectral characteristics across different locations and samples, which is totally different from the interface bright SPSs previously reported. Furthermore, we show that their density can be controlled via the NO annealing process.
Theoretical study of group III–VII impurity-vacancy centers in 4H-SiC as a potential qubit
ABSTRACT. In quantum applications including cryptography, computing, and sensing, spin defects in semiconductors are regarded as attractive candidates as a qubit. As a host for spin defects, silicon carbide (SiC) is appealing owing to its well-established crystal growth, availability of n- and p-type doping, and micro-scale processing technologies. As examples of spin defects, a coherent control of single spins for the silicon vacancy (V_Si) and the nitrogen-vacancy center (N_CV_Si) has been demonstrated. The oxygen-vacancy center (O_CV_Si) has been theoretically predicted to have a high-spin ground state of S = 1 and near-infrared photoemission. Although several other candidates in SiC have been studied, many possible defects remain to be explored. In the present study, we systematically investigated the impurity-vacancy centers (i.e., XV centers) in 4H-SiC based on ab initio calculations.
Reliability Challenges of SiC MOSFETs Under Continuous Dual-Bias Stress in EV Security Systems: A Lifetime Prediction Study
ABSTRACT. Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have become preferred components for electric vehicle (EV) traction inverters due to their exceptional electrical and thermal properties [1]. Conventional operation employs negative gate-source voltage (VGS < 0 V) to mitigate parasitic turn-on phenomena in half-bridge configurations during switching transitions. Some modern electric vehicle security systems, however, mandate continuous power supply to high-voltage subsystems (including gate drivers and DC-link capacitors) during stationary conditions which are called Sentry Mode. This operational requirement subjects SiC MOSFETs to concurrent negative VGS (-3 to -5 V typically) and elevated drain-source voltage (VDS ≈ 400-900 V) throughout not only operational but also prolonged stationary periods of vehicle. Such persistent dual-bias stress introduces critical reliability concerns that current accelerated lifetime testing methodologies (typically assessing single stress factors) fail to adequately address [2,3], creating a significant knowledge gap in degradation modeling under combined electrical stress conditions.
To clarify these concerns, dual-bias time-dependent dielectric breakdown (DB-TDDB) test was proposed and implemented. The experimental configuration employed in this study is illustrated in Fig.1. During testing, a negative gate-source voltage (VGS=-40.5V) was applied to the device under test (DUT) while maintaining a VDS of 880V. Complementary TDDB characterization was conducted under negative gate bias conditions (VGS=-40.5 V, Tj = 175℃). To determine the acceleration factor, constant-voltage TDDB testing (VGS=40.5V) was performed under three junction temperature conditions (Tj=125℃, 150℃, 175℃). Each test group consists of 60 samples, and testing should continue until at least 63% cumulative failure rate (38 pcs failed). The Weibull distributions of time-to-breakdown are shown in Fig.2.
To characterize gate oxide (GOX) stress states under various accelerated conditions,Silvaco TCAD simulations were performed to analyze the GOX electric field distribution under varying VGS and VDS. Simulation results revealed two distinct patterns. Under standard reverse bias condition, the maximum GOX electric field (Emax) is localized in the JFET region. In contrast, implementation of the proposed DB-TDDB framework induces a spatial shift of Emax to the source region, as quantitatively compared in Fig.2. This spatial redistribution of Emax indicates that negative gate voltage operation induces a nonlinear coupling effect between gate and drain voltages. To account for this interaction, we developed a dual-acceleration-factor E-model expressed as:
TTF=A_0*exp(E_a/kT)*exp(-γ_1 E_ox )*exp(-γ_2 V_DC ) (1)
Given the computational complexity of deriving GOX electric fields directly from VDS, an empirical voltage normalization approach was implemented to quantify VDS acceleration factors. In this model, A0 is a constant, while Ea represents the temperature acceleration factor. The parameters γ₁ and γ₂ correspond to the acceleration factors for gate-voltage and Drain-bias, respectively. Notably, the activation energy (Ea = 0.532 eV), derived through the thermochemical linear E-model [4], represents a temperature-dependent parameter governed by the gate oxide's bond dissociation energy under Boltzmann thermal activation theory. Acceleration coefficients were quantified through negative and dual-bias TDDB tests: VGS acceleration factor: γ₁ = 3.9 cm/MV and VDS acceleration factor: γ₂ = 0.5/kV. Weibull analysis (shape parameter β = 2.52) enabled lifetime extrapolation, projecting a 1 ppm cumulative failure rate at 5.11×10¹³ hours under automotive operational profiles (VDS = 880 V, VGS = 18V, Tj = 100℃). This lifetime performance exceeds by orders of magnitude the 20-year service life requirement specified in AEC-Q101 Rev-H qualification standards for automotive power electronics. The complete experimental matrix, including extracted 63% time-to-failure (TTF) distribution parameters and model fitting results, is systematically summarize in Table 1 and visually presented in Fig.4.
In conclusion, we have developed an improved E-model lifetime prediction based on proposed DB-TDDB method that comprehensively integrates both negative gate-source and drain-source coupling stress under actual operational conditions. Through several groups of gate oxide lifetime assessment experiments executed according to this framework, key acceleration factors were quantitatively extracted. Subsequent lifetime prediction based on multivariable stress analysis derived an operational lifespan expectation under combined electrical-thermal loading conditions.
[1] C.Wu, R.Rout, Yu.Wang, Y.Lin and J. Hu, IEEE Asia Pacific Conference on Circuits and Systems (2024) p.317
[2] G. Rescher, G. Pobegen, T. Aichinger and T. Grasser, IEEE Trans. Electron Devices, 65 (2018)
[3] S. Mbarek, F. Fouquet, P. Dherbecourt, M. Masmoudi and O. Latry, Microelectronics Reliability, 64 (2016)
[4] K. Matocha, IEEE Transactions on Electron Devices, 55 (2008)
Reliability Analysis and Test Results of SiC Baseless Power Module in bidirectional EV-Charging application
ABSTRACT. The DC Fast charger mission profile requires a high number of daily charging sessions. Each charging session led to a power cycle that induces a fatigue effect on the components where materials are coupled with different expansion coefficient and Young’s modulus. Mechanical fatigue is proportional to the thermal excursion experienced by the material, therefore, depending on the temperature profile, the mechanical fatigue may occur on the wire bonding and/or on the die attach.
In this work, several SiC mosfets in base-less modules from different manufacturers have been submitted to power cycle test with several minutes cycle duration. We tested different die size on the same set-up and we confirmed that it does not affect life. We fitted the results with the most popular models. For a specific manufacturer we compared long time cycle test results with a seconds cycle test on the same module. The normalized results have been analyzed and compared with the coefficients proposed in literature. Data seems to be in accordance with the simple power law coefficient indicating that tON does matter in any duration.
Room temperature bonding of SiC chip and Cu heat sink substrate
ABSTRACT. In this study, a room temperature bonding method using activated Cu atomic layer was proposed, and the effectiveness is experimentally verified. The strong bond strength between SiC and Cu of approximately 52 MPa was demonstrated at room temperature. These results show that the proposed room temperature bonding method has great potential for the efficient heat dissipation of high-power SiC devices
Adverse effects of proton implantation in 4H-SiC epilayers on stacking fault expansion
ABSTRACT. Since proton implantation of SiC devises has recently been reported to be effective in suppressing the bipolar degradation phenomenon, we investigated the effect of proton implantation on the expansion of stacking faults of 4H-SiC epilayers by the EVC (Expansion-Visualization-Contraction) method. The experimental results confirmed the suppression of bar-shaped 1SSFs (Shockley-type stacking faults) expansion into the epitaxial layer. However, we have also found the 1SSFs expanded from the proton implanted layer toward the epi/sub interface, implying that crystal structure disorder caused by proton implantation damage can be the starting point of 1SSF expansion.
Application of UV photoluminescence spectrum mapping for stacking faults that were expanded from the in-grown stacking fault on a thick 4H-SiC epilayer
ABSTRACT. It has been explained that the cause of bipolar degradation of SiC MOSFETs is mainly the bar-shaped 1SSFs (single Shockley stacking faults) expand from the BPDs (basal plane dislocations). However, when in-grown SF (stacking fault) was tested by the EVC (Expansion Visualization Contraction) method [1], a bar-shaped SFs also extended from in-grown SF, when irradiated with UV, but remained mostly bar-shaped SFs without fully contracting compared to 1SSF even when heated. Judging from the results of the EVC method, it is different from pure 1SSF. Therefore, we investigated the spectrum of the extended bar-shaped SFs by mapping measurements using a third harmonic YAG laser beam for SF extension. We report that the in-grown SF was 3C-SiC, and we observed a region of expanded bar-shaped SF in the same PL wavelength range that is thought to be affected by the 3C-SiC in addition to the 1SSF.
Structural Transformation Within Bar-Shaped Stacking Faults in 4H-SiC Epitaxial Layer and Substrate
ABSTRACT. Stacking faults (SFs), like other structural defects in 4H-silicon carbide (4H-SiC), are propagating from the SiC substrate into the epitaxial layer or generating during the epitaxial layer growth [1]. Some types of SFs in 4H-SiC expand under ultraviolet (UV) illumination or current stress. Bipolar degradations of SiC PiN diodes and MOSFETs resulted from the expansion of triangular SF into the elongated bar-shaped SF and its structure was known as (3,1) single Shockley-type SF [2].
In this study, we investigated the structural transformation within bar-shaped SFs in 4H-SiC epitaxial wafer and substrate. The structural transformation of SFs was systematically investigated based on the photoluminescence (PL) mapping, etch pit formation and evaluation from dislocations, reflection X-ray topography (XRT), and high-angle annular dark-field high-resolution scanning transmission electron microscope (HAADF HR-STEM) observations. In addition, we theorical calculation of stacking fault energy (SFE) by employing ab initio density function theory (DFT).
Multiple line features with different PL intensity were found inside the bar-shaped SFs in the PL map image as shown in Fig. 1(a). Some studies showed the PL map images with the similar line features inside the SFs, but it has not been discussed what do the lines mean. Fig. 1(b) shows optical microscope image after molten KOH etching of the same bar-shaped SF in Fig. 1(a). Replica picture for the observed lines in PL map image of Fig. 1(a) was superimposed on the etch pit image of Fig. 1(b).
Very surprisingly, we could find oval-shaped etch pits at every inner line ending on the layer surface in addition to oval-shaped etch pits for two partial dislocations at the top and bottom edges of the bar-shaped SF. This strongly meant that the previous lines inside bar-shaped SF in the PL map image indicate partial basal plane dislocations (BPDs) dividing the single bar-shaped SF into many different SF regions. In order to confirm the existing partial BPDs, XRT images were obtained from the same bar-shaped SF region as shown in Fig. 1(c). The previous replica picture for the observed lines in PL map image was superimposed on the XRT image as shown in Fig. 1(d). Some BPDs were observed in the XRT image in Fig. 1(c), which coincides with the locations of the lines in PL map image and etch pits. As mentioned, etch pits were formed at every inner line of the PL map image, however, BPDs were not observed at every etch pit positions. This implied that a net displacement vector relating to the some partial BPDs did not satisfy visible imaging condition i.e., g·r=0 (g: diffraction vector, r: displacement vector of defect), although such BPDs inevitably formed inner lines both PL map and etch pits.
To support our investigation, we carried out PL spectrum mapping inside the bar-shaped SF to determine the characteristic PL emission wavelength depending on the SF types across the regions divided by the previous inner lines. Four different characteristic PL emission wavelengths were detected; 425, 427, 428, and 431 nm (in the order of wavelength). This strongly meant again that there are several different types of SFs inside the single bar-shaped SF.
In order to confirm the different SF structures inside the single bar-shaped SF, finally, the structures of SFs in the both epitaxial layer and substrate were investigated using HAADF HR-STEM. In the substrate region contacting to the epitaxial layer, bar-shaped SF was confirmed, but the length of it was shorter than that in the epitaxial layer as schematically shown in in Fig. 2(a). Representative observed positions in the epitaxial layer, substrate, and partial dislocation are illustrated in Fig. 2(a).
The SF structures at the A' region in the substrate and the A region in the epitaxial layer were determined to the same structure (3,3,3,3) SFs as shown in Fig. 2(b) and (c), respectively. It meant that the bar-shaped SF in the epitaxial layer was replicated from the SF in the substrate. Fig. 2(d) showed the SF structure at the B region in the epitaxial layer, divided by the partial BPD at the C position, and it was determined to a (3,3,2,2,3,3) SF, which is different from the SF in the region A. The continuous structural transformation of the SF structures from the A to the B regions could be confirmed in Fig. 2(e), which was observed at the partial BPD (the position C). Other many numbers of variations and structural transformations of SFs were found at the both epitaxial layer and substrate (not shown here). The representative of such SF structures was (3,2,3,2,2,3,3,2), (3,3,2,2,2,2,2,2,3,2,3,2), and (3,3,2,2,2,2,2,2,2,2,3,2,3,2), all of which showed characteristic PL emission wavelength at 428 nm. We reported that numerous variations of SFs, both Shockley and Frank type, with emission wavelengths in the range of 420–430 nm and miniscule differences in wavelengths were formed in 4H-SiC epitaxial layers [3].
Our investigation and systematic finding in this study meant that the structural transformation of SF was driven by dislocation behaviors, not by external energy like as current stress or UV irradiation. More detail understanding and insight to structural transformation of SF with PL emission wavelengths in the range of 420–430 nm in the epitaxial layer and substrate including theorical calculation of SFE by DFT will be represent at the conference.
This work was supported by the Technology Innovation Program (No. 25A02037, 25A02099) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).
[1] T. Yamashita, S. Hayashi, T. Naijo, K. Momose, H. Osawa, J. Senzaki, K. Kojima, T. Kato, H. Okumura, J. Cryst. Growth 490, 89–96 (2018).
[2] T. Kimoto, H. Watanabe, Appl. Phys. Express. 13, 120101 (2020).
[3] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Appl. Phys. Lett. 124, 152109 (2024).
Giant Etch Pit Formation and Origin Formed at the Typical Triangular Stacking Fault Area on 4H-SiC Epitaxial Layer Surface by KOH Etching
ABSTRACT. 4H-SiC substrates and epitaxial layers have many different kinds of structural defects like micropipe (MP), threading screw dislocation (TSD), threading edge dislocation (TED), basal plane dislocation (BSF), basal stacking fault (BSF), and prismatic stacking fault (PSF).
MP, TSD, TED, and BPD are easily evaluated by simple molten KOH etching by forming the etch pits on the top surface where the defects terminated. Evaluating, recognizing and classifying the origins of etch pits are possible based on shapes and sizes of the etch pits [1,2].
In this study, we report “giant” etch pit formation and its origin formed on 6-inch 4H-SiC epitaxial wafer investigated by KOH etching. PL mapping, FE-SEM, TEM, HRTEM, and HAADF HR-STEM.
The giant etch pit is oval-shaped as like the conventional BPD etch pit but it is really bigger than the normal etch pits formed on TSD, TED, and conventional BPD. Fig. 1 shows FE-SEM images of the etch pits and PL mapping images from stacking fault (SF). The oval-shaped BPD etch pits (mentioned to the P-BPD) shown in Fig.1 (a-c) are the etch pits formed from two partial BPDs at the boundary of the SF, in fact. The formation of oval-shaped etch pits from two partial dislocations at the SF can be confirmed by comparing to the corresponding SF PL map images in Fig. 1 (d-f). These results meant that the partial BPDs at the SF can form the oval-shaped etch pits as like those formed on the conventional perfect BPDs. In addition to the oval-shaped etch pits from two partial BPDs, surprisingly, a very big etch pit (mentioned to the giant etch pit) was formed between the two P-BPD etch pits of the typical triangular SF as shown in Fig. 1(c).
In order to investigate the origin of giant etch pit, FIB TEM specimen was prepared at the front position of the giant etch pit as mentioned in Fig. 1(c). Fig. 2(a) is low-magnification TEM image showing two basal SFs (BSF-1 and BSF-2), and one PSF. Here, the PSF was not reached to the top surface but terminated inside the epitaxial layer. Fig. 2(b) shows HRTEM image for the two BSFs and one PSF in (a). From the HAADF HR-STEM observations, two BSFs were determined to (5,2) and (4,1) Frank-type BSFs as shown in Fig. 2(c). In addition, the PSF was started at the meeting point of the two Frank BSFs. Fig. 2(d) shows HAADF HR-STEM image at the region of PSF end-pint inside the layer mentioned in Fig. 2(a). The PSF-end was connected to a Frank-type (2,1) SF, therefore, a partial BPD must be existed at the left-end of this Frank-type (2,1) SF. This BPD must reach to the top surface of the epitaxial layer and can form the BPD etch pit. At the right-end of the Frank-type (2,1) SF, there should be a stair-rod dislocation, which connected to the PSF [3], should be reached to the top surface of the epitaxial layer, too. The PSF showed stairs-like feature and there were (2,1) Frank-type BSFs at every step of the stairs. Therefore, we could conclude that the BPD at the (2,1) Frank-type SF formed the giant etch pit but the PSF itself might contributed the formation of the giant etch pit considering the size of pit.
This work was supported by the Technology Innovation Program (25A02037) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).
[1] Y. Z. Yao, Y. Ishikawa, Y. Sugawara, H. Saitoh, K. Danno, H. Suzuki, Y. Kawai, and N. Shibata, Jpn. J. Appl. Phys. 50, 075502 (2011).
[2] Y. Cui, X. Hu, X. Xie, and X. Xu, Cryst. Eng. Comm. 20, 978 (2018).
[3] M. Benamara, X. Zhang, M. Skowronski, P. Ruterana, G. Nouet, J. J. Sumakeris, M. J. Paisley, and M. J. O’Loughlin, Appl. Phys. Lett. 86, 021905 (2002).
Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs
ABSTRACT. A body diode (BD) is also widely utilized as a free-wheeling diode instead of the Schottky barrier diode. Utilization of BD can contribute to cost reduction of SiC components and miniaturization of total system application, but there is a disadvantage that switching losses increases due to the reverse recovery current caused by minority carrier accumulation in the case of using a BD. High-temperature activation annealing can potentially introduce carrier lifetime killer without additional processes or equipment, making it cost-effective. However, few studies have reported on the application of the method to SiC-MOSFETs. Therefore, this study focuses on the generation of carbon vacancies through high-temperature activation annealing and investigates the effect of different activation annealing temperatures (1750°C, 1800°C, and 1900°C) on electrical characteristics. We found that at 1900°C, reverse recovery charge is reduced by approximately 70% compared to 1750°C and 1800°C. DLTS analysis confirms that higher annealing temperatures increase the densities of Z1/2 and EH6/7 centers, indicating more carbon vacancies.
Reliable and Manufacturable 1200V SiC Planar MOSFET with Leading-Performance Ron,sp 1.95m·cm2
ABSTRACT. This paper demonstrates a reliable (tighter than 175°C AEC-Q101 criteria) and manufacturable (enhanced-stress >1400V, yield >92%) SiC 1200V planar MOSFET with leading specific resistance Ron,sp 1.95mΩ·cm². The results of this work are attributed to shrunk cell pitch, retrograde implantation profile, atomic scale planarized surface after high-temperature ion implant activation, reduced carbon cluster during gate-dielectric formation, and thin SiC substrate with eliminated damage layer.
SiC devices are key components for high-power and fast-switching energy systems [1]. They have been widely in Electric Vehicles and Energy Storage Systems [2]. However, its high material cost, particularly SiC epitaxial substrate, limits its potential in industrial and consumer markets. While trench MOSFET offers a solution by reducing Ron,sp through alternative crystalline direction [3], its reliability concerns and loss of attractiveness at >1700V applications limit its future outlook [4]. This paper presents a highly reliable planar MOSFET structure with leading performance and high manufacturability through implementing various process innovation and optimization.
Fig. 1 shows Ron,sp of the 1200V SiC planar MOSFET, compared leading IDM’s in the world, either planar or trench MOSFET’s, this work has the best result of Ron,sp 1.95mΩ·cm². The high driving current (Fig. 2), combined with suppressed resistance loading, indicates a proper Ni2Si Ohmic source-contact (Fig. 3). At drain-contact (not shown), damage-free layer is achieved by customized backside grinding and polishing. By using an optimized in-house SiC epitaxy process, we achieve stable CP yield >92% (Fig. 4) at enhanced stress >1400V. High efficiency of BPD conversion in buffer layer (Fig. 4 inset) and well-controlled retrograde doping profile (TCAD simulation shown in Fig. 5a) help suppress IDSS drain leakage current. On the other hand, the p-type dopant diffusivity near SiC surface was found to cause significant fluctuation of threshold voltage, Vth. TCAD model after careful calibration was then used to cope with Vth variation issue. Fig. 5b shows the SEM of the innovative structure compared with TCAD Fig. 5a on top. Fig. 6 reveals planarized surface at atomic scale after high-temperature ion implant activation using customized carbonized compound protection. The Ra 3.5Å surface roughness in channel region reduces thermally assisted current scattering at interface during device turning-on while keeping optimized channel electron mobility. Furthermore, interfacial quality between gate-dielectric and SiC is improved by eliminating carbon cluster formation and significantly enhance gate-dielectric lifetime, as shown in Fig. 7. Reduced trap-assisted tunneling further reduces IGSS gate leakage current. With the above-mentioned process knobs, the fully integrated SiC planar MOSFET of this work exhibits not only leading Ron,sp but also exceptionally good reliability. Fig. 8 benchmarks key device parameter shifts and variation after 175oC AEC-Q101 1khrs reliability testing. The key parameter shifts of this work are comparable or better than commercial SiC planar MOSFET products used in power inverters.
In this work, reliable and manufacturable 1200V SiC planar MOSFET with leading-performance Ron,sp 1.95m·cm2 is achieved. Device platform offers applications in automotive, various green energy systems, and other applications.
Comparison of Mo, Mo-carbide and Mo-silicide Schottky contacts on 4H-SiC
ABSTRACT. The Schottky-barrier diode (SBD) on 4H-SiC is a well-established technology, which offers undoubted advantages (namely fast switching, low forward voltage drop, high temperature operations) in apllications. However, further enhancements are necessary to fully exploit the potential of 4H-SiC. To this end, various approaches have been explored to improve the properties of the metal/4H-SiC interface, with particular attention to the metal choice and its interaction with 4H-SiC during thermal annealing for the Schottky contact formation. In recent years, molybdenum (Mo) has attracted interest due to its good thermal stability and ability to form contacts with low Schottky barrier height, which is beneficial for minimizing the conduction power losses. As matter of fact, a wide variability in the Schottky barrier height has been observed in Mo/4H-SiC Schottky contacts, depending on factors such as surface passivation treatments, temperature of the metal deposition and metal stack composition, with the barrier heigth varying between 1.0 and 1.5 eV. Based on the ternary phase diagram of the Mo-Si-C system, solid-state reactions can occur between Mo and both silicon (Si) and carbon (C), leading to the formation of carbides and silicides and opens the possibility to further explore and tune the Schottky barrier properties to 4H-SiC, potentially broadening the range of achievable barrier height values. In this study, we investigate the morphological and electrical properties of Mo silicide and carbide-based/4H-SiC contacts. The two contacts show good rectifying properties, with low value of Schottky barrier height. Their properties will be discussed and compared to highlight specific characteristics of the contacts.