ABSTRACT. The development of silicon carbide (SiC) technology began in earnest in 1987 with the founding of Cree, Inc. in Durham, North Carolina, USA. Prior to this, significant advancements in SiC crystal growth had already been achieved across Japan, Europe, and the United States. The maturation of SiC technology to its current state was the result of sustained, collaborative efforts among global academic institutions and industrial entities.

The evolution of SiC faced numerous pivotal transitions, including the shift from the 6H to the 4H polytype, the scaling of wafer diameters, advancements in ion implantation techniques—including selective implantation, the introduction of carbon cap technology for activation anneals and post oxidation anneal in Nitric Oxide. A major milestone occurred in 2015 with the establishment of PowerAmerica, which played a crucial role in democratizing access to SiC technology for smaller companies without internal fabrication capabilities, thereby accelerating innovation across the industry.

However, the true inflection point arrived in 2018 when Tesla adopted SiC MOSFETs in its electric vehicle drive trains. This strategic decision proved transformative, driving unprecedented demand for SiC in the EV sector—demand that continues to be effectively limitless. The volume requirements from EV adoption have subsequently driven down manufacturing costs, bringing them closer to silicon-based device levels and enabling broader penetration into other industrial markets.

Despite these advances, critical technical challenges remain. These include the low inversion layer mobility (~25 cm²/V·s) in commercial SiC MOSFETs, the presence of surface defects in epitaxial layers that precipitate premature failures and constrain device scalability, and the absence of sufficiently robust screening methodologies to guarantee parts-per-million failure rates over 20-year lifespans in automotive applications.

After nearly four decades of development, the journey is far from complete. The industry is now poised to replace silicon-based power devices across the 300 V to 6.5 kV range and push SiC technology further into the 30-40 kV domain, targeting IGBTs and thyristors with improved reliability and cost-effectiveness for industrial and grid-scale applications. SiC is expanding into high-voltage, high-reliability, and cost-competitive domains, becoming the backbone of future industrial and power infrastructure. The next era will be shaped by applications across sustainability, aerospace, extreme environments, and railway systems. The future will also witness the integration of low-voltage SiC CMOS with 1000 V-class LDMOSFETs and vertical DMOSFETs, paving the way for high-power smart circuits. Further advancements will require improvements of surface electron mobility and aggressive scaling to reduce cell pitch and specific on-resistance for both planar and trench MOSFET architectures.

While there is growing interest in ultra-wide bandgap (UWBG) materials, their prospects of practical application in power electronics remain limited. It is doubtful that robust safe operating areas can be realized without dual-type selective implantation and a suitable gate dielectric, both of which are essential for reliable MOSFET operation. Although cascoded JFET-like structures may offer some opportunities, they inherently lack scalability for high-current parallel operation.

The outlook for SiC remains extremely promising, provided that the industry maintains a rigorous focus on device reliability and ruggedness.

ABSTRACT. Bipolar degradation is one of the most important reliability issues for SiC power devices and is caused by stacking fault (SF) expansion from basal plane dislocations during device operation. To solve this issue, we have recently developed a proton implantation technique [1–5]. Then, we also found that helium ion implantation has the same effects as shown in Fig. 1, which shows electroluminescence (EL) images of PiN diodes with and without helium ion implantation after current stress with 425 A/cm² for 2 hours [6]. Effectiveness of helium ion implantation indicates that point defects induced by ion implantation suppress expansion of SF, because helium hardly makes bonds to other elements. We named the ion implantation technique to suppress the bipolar degradation as stacking fault knocking-down by high-energy ion implantation (SF-KHII™).

Other groups have also reported suppression of SF expansion by ion implantation [7–11], and some groups have discussed that the main role of the point defects induced by ion implantation is carrier lifetime reduction, even though we have not observed significant reduction of carrier lifetime after ion implantation in our initial report and have observed pinning of dislocations in case of SF contraction [1,3]. Therefore, we observed point defect and carrier lifetime distributions in PiN diodes with proton or helium ion implantation as performed to super junction devices [12]. Figure 2 shows point defect distributions in the depth direction of the devices using relative cathodoluminescence (CL) intensity of the L1 luminescence to the band edge luminescence [13]. Proton- and helium-ion-implanted devices show significant L1 luminescence at the deep regions (~9 µm), which correspond to the implanted depth of proton and helium ion.

Carrier lifetime distribution has also been observed by our original microscopic time-resolved free carrier absorption (TR-FCA) system shown in Fig. 3 [14]. Figure 4 shows distributions of (a) 1/e lifetime, which is defined as the period corresponding to the signal decrease from 1 to 1/e, and (b) 1/e² lifetime, which is defined as the period corresponding to the signal decrease from 1/e to 1/e². As shown in this figure, carrier lifetime in the deep regions significantly reduced by proton and helium ion implantation as expected by the point defect distributions shown in Fig. 2. These results indicate that the carrier lifetime reduction inside the devices by ion implantation will play a significant role to suppress bipolar degradation.

Recent reports have also discussed that point defects in substrates diffused from the substrates to epilayers are effective to suppress bipolar degradation. We have also observed the effects of point defects in substrates: one of our reports is for point defects in substrates induced by high energy (7.9 MeV) implantation from the substrate side [16,17]. Therefore, although the proton implantation into substrates near the surface before epitaxial growth had a risk of inducing other stacking faults [5], point defects present in the bulk of substrates will be effective to suppress SF expansion. These results indicate that not only the point defects in epilayers but also those in substrates play a role in suppression of bipolar degradation. Thus, point defect engineering in SiC epilayers and substrates will open a way to realize highly reliable SiC power devices.

This study was supported by the New Energy and Industrial Technology Development Organization (NEDO) (Project No. JPNP20004).

[1] S. Harada et al., Sci. Rep. 12, 013542 (2022). [2] M. Kato et al., Sci. Rep. 12, 018790 (2022). [3] S. Harada et al., Appl. Phys. Express 16, 021001 (2023). [4] M. Kato et al., Jpn. J. Appl. Phys. 63, 020804 (2024). [5] M. Kato et al., Mater. Sci. Semicond. Process. 175, 108264 (2024). [6] T. Li et al., Appl. Phys. Express 17, 086503 (2024). [7] K. Ishibashi et al., presented at ICSCRM2024. [8] N. Shikama et al., presented at ICSCRM2024. [9] K. Konishi et al., presented at ICSCRM2024. [10] J. Nishio et al., Jpn. J. Appl. Phys. 63, 101015 (2024). [11] K. Takenaka et al., Jpn. J. Appl. Phys. 64, 02SP43 (2025). [12] T. Fukui et al., Jpn. J. Appl. Phys. 62, 016508 (2023). [13] M. Kato et al., Jpn. J. Appl. Phys. 64, 010901 (2025). [14] K. Nagaya et al., J. Appl. Phys. 128, 105702 (2020). [15] H. Uehigashi et al., Solid State Phenom. 362, 13 (2024). [16] T. Li et al., will be presented at this conference. [17] K. Nagaya et al., will be presented at this conference.

ABSTRACT. This study investigates bipolar degradation in 3.3kV SiC-MOSFETs, focusing on leakage current degradation (IDSX) caused by in-grown stacking faults (SF). High current stress tests were conducted on over 1,500 chips, identifying 45 with IDSX degradation. Detailed analysis using photoemission microscopy and photoluminescence (PL) imaging revealed that the IDSX degradation was linked to in-grown SFs, where Shockley stacking fault has expanded under high current stress. This study confirms that in-grown SFs can cause IDSX degradation, suggesting that such defects are significant contributors to the bipolar degradation phenomena in SiC-MOSFETs.

ABSTRACT. The minority carrier lifetimes in the drift layer significantly affect conduction and switching losses in 4H-SiC PiN diodes and IGBTs. In low-doped 4H-SiC epilayers, the minority carrier lifetimes are often controlled by carbon vacancies, specifically the Z1/2 center. To address this, carbon diffusion processes are often employed to reduce the concentration of carbon vacancies. In this study, we investigate another limiting factor of carrier lifetimes in n-type epilayers, namely threading dislocations (TDs), as part of efforts to further improve carrier lifetimes and their uniformity on the wafers.

ABSTRACT. SiC power devices exhibit superior performance compared to conventional silicon-based counterparts. However, during the epitaxial growth of SiC, basal plane dislocations (BPDs) propagate from the substrate into the epitaxial layer. Further complications arise from the fact that BPDs dissociate into pairs of partial dislocations (PDs) on the basal plane, accompanied by Shockley-type stacking faults (SSFs), which expand when low-energy holes interact with the Si-core. The expansion of these SSFs leads to bipolar degradation. Proton implantation has emerged as a promising technique for suppressing the formation of SSFs. In this study, we evaluate the impact of proton implantation depth on the suppression range measured from the epitaxial surface. Furthermore, we investigate the underlying suppression mechanisms by analyzing the atomic and electronic structures surrounding the SSFs.

ABSTRACT. Energy-Filtered Ion Implantation (EFII) is a novel ion implantation technology [1] which has many applications in 4H-SiC power device manufacturing. EFII is used for drift zone doping on SiC epitaxial wafers, enabling doping uniformity below 3%. Our recent work reported its application for suppressing 1SSF expansion in 4H-SiC. Further, it can be used for carrier-lifetime engineering by ion implantation in the drift layer [2]. Understanding the influence of EFII on introduction of deep levels in epitaxially (CVD) grown 4H-SiC is necessary due to the broad spectrum of energies associated with the implanted ions. This work investigates the deep level defects introduced by the EFII process on commercial 4H-SiC epitaxial wafer from different vendors. The experiments contains various concentrations of implanted Nitrogen in the range 1E14 - 1E16 cm-3, up to a depth of 8μm into the entire drift layers as blanket implant. All implantations were performed at 19 MeV Nitrogen. Implanted and un-implanted regions underwent identical activation annealing steps. Schottky (Ni/SiC) contacts were used for DLTS and semi-transparent (20nm thick) Ni contacts at the same locations for MCTS measurements. Samples with implanted nitrogen concentration of 1E15, 5E15, 1E16 cm-3 were probed up to 1μm depth and the peaks are analyzed qualitatively and quantitatively. 1/C² vs V plot for all the implanted samples reveal homogenous doping profile over the probed depth. DLTS spectrum reveals nine peaks in all EFII implanted samples. Energy levels of each peak and their trap concentration (NT) for implanted nitrogen samples are tabulated and compared. All EFII implanted samples show same defect peaks. The dominant peaks are assigned to Z1, Z2 and EH6/7 respectively, which are often performance-limiting defects in SiC devices. The overlapping peaks T5, T6 will be resolved with further investigation. As the EFII process involves 1700°C anneal with carbon capping layer facilitates carbon injection, leading to a Ci complex and hence defect peaks T5, T8 could relate to ON family of defects [4]. The trap concentration values reveal that the dominant trap concentration are in the range of 0.3 - 2E13 cm-3 as seen on as-grown CVD material [6]. This suggests that the EFII implants with MeV energy does not create significant point defects. The MCTS results show three acceptor traps which are shallow in nature among which B´´ is the prominent trap and no D centres were detected in any of the samples. Other results covering the full range of implant concentration, depth profile of traps will be included in the manuscript. The identification of these stable deep levels after high-temperature annealing is a significant step towards understanding the traps generated from particular process steps and thus to determine their influence on performance and long-term reliability of EFII-processed SiC materials.

ABSTRACT. Various kinds of stacking faults (SFs) have been reported in 4H-SiC epitaxial wafers. Identification of SFs and structure determination have been investigated by using characteristic photoluminescence (PL) emissions from SFs and high-angle annular dark-field high-resolution scanning transmission electron microscope (HAADF HR-STEM) [1-3]. In the IEC standard document [4], seven representative SFs, which are four kinds of Shockley-type SFs (SSFs) and three kinds of Frank-type SFs (FFSs) with corresponding characteristic PL wavelengths (C-PLWs) are described although some of C-PLWs are arguable. The four representative SSFs are single (3,1), double (6,2), triple (5,3), quadruple (4,4) SFs and the three FSFs are (5,2), (4,2) and (4,1) SFs. Table 1 summarizes C-PLWs for the seven representative SFs from IEC standard [4] and recent our reports [1-3, 5] There are lots of SF variations with the Zhdanov notation numbers of “3” and “2” like (3,2), (3,3), (3,1), (3,3,3,3), (3,3,3,3,2), (3,3,3,3,3,2), (3,2,2,3), (3,3,3,2,3,2), and (3,2,3,3,3,2) SFs. The C-PLWs for these SSFs were ranged between 420-430 nm [2]. In this study, we investigated various kinds of (3,X) SSFs with large height more than 20 layers by HAADF HR-STEM and PL spectra analyses. In order to support the determined C-PLWs by PL measurements theoretical calculations of band structures for the perfect 4H-SiC with and without the SFs were carried out. Furthermore, we determined band offset between the perfect 4H-SiC and the 4H-SiC with the SFs. Fig. 1 shows HAADF HR-STEM images for the (3,2,2,3,2,2,2,2,2,2,3,2,3,2), (3,3,2,2,2,2,2,2,2,2,3,3), (3,2,3,2,2,3,3,2), and (3,3,2,2,2,2,2,2,2,2,4,2) SFs. All these SFs are SSFs becasue the sum of the Zhdanov notation numbers of each SF is multiple number of 4 [1]. Fig. 2 shows PL spectra for the SSFs observed in Fig. 1. The SSFs (3,2,2,3,2,2,2,2,2,2,3,2,3,2), (3,3,2,2,2,2,2,2,2,2,3,3), and (3,2,3,2,2,3,3,2) showed C-PLWs of 425, 427, and 428 nm, respectively. The observed C-PLWs of these SFs belong to the range of 420~430 nm, which well agreed with the previous report [2]. However, very surprisingly, the Shockley-type SF (3,3,2,2,2,2,2,2,2,2,4,2) showed C-PLW of 457 nm, which was exactly same to the C-PLW of the Frank-type SF (4,2) mentioned in Table 1. In fact, we expected it to be the FSF (4,2) based on the PL spectrum result before confirming the SF structure by HAADF HR-STEM observation. This result implied a very importnat conclusion that the C-PLW from the SF was determined by a fractional part of the SF with the corresponding longest PL wavelength of the fractional part (4,2) not by the whole SF structure. From this conclusion, we can understand the C-PLWs of SFs in Fig. 2 (a), (b), and (c) of 425, 427, and 428 nm, which were determined by fractional part of (3,2) and (3,3). Theoretical DFT calculations for the band structures and band offset results to support the observed C-PLWs characteristics will be presented and discussed.

This work was supported by the Technology Innovation Program (No. 25A02037, 25A02099) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

[1] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Mater. Sci. Semicond. Process. 175, 108247 (2024). [2] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Appl. Phys. Lett. 124, 152109 (2024). [3] M. Na, S.-K. Hong, W. Bahng, H. Jung, C. Oh, D. Jang, D. Kim, T. Iqbal, J. Park, Y. G. Park, Appl. Surf. Sci. 703, 163425 (2025). [4] International Electrotechnical Commission (IEC), Semiconductor Devices, Part 3, IEC 63068-3:2020, IEC, 2020. [5] Will be presented at ICSCRM 2025.

ABSTRACT. A fundamental step toward realizing a green society is the enhancement of the static performance of power semiconductor devices, such as MOSFETs, particularly with respect to specific on-resistance (Ron,sp) and breakdown voltage (VB). For high-voltage applications, the superjunction (SJ) structure presents a promising solution. This design incorporates well-aligned, highly doped n- and p-type layers in the drift region to effectively reduce Ron,sp while maintaining VB [1].

There are two types of SJ structures: the full-SJ structure [Fig. 1(a)], which employs the entire drift layer as an SJ structure, and the semi-SJ structure [Fig. 1(b)], which combines SJ and non-SJ regions. In particular, the semi-SJ structure has gained attention for its potential to alleviate fabrication challenges, including high-energy ion implantation [2], multiple epitaxial growth processes [3], and trench-filling epitaxial techniques [4]. In this paper, we present theoretical investigations on the performance of symmetric 4H-SiC SJ devices, with a particular focus on comparing full-SJ and semi-SJ structures.

In the calculations, Ron,sp is evaluated by incorporating the effects of incomplete ionization in the n-pillars, the depletion width under zero bias, and the doping-dependent carrier mobility [5]. To estimate VB, Poisson’s equation is revisited, and exact expressions for the electric field are derived for both full- and semi-SJ structures [6]. VB is defined as the point at which the ionization integral reaches unity, based on experimentally measured impact ionization coefficients [7,8] and incorporating the anisotropy of impact ionization [6].

Figure 2 shows the minimum value of Ron,sp against VB for full-SJ devices with various pillar widths (w) ranging from 0.3 to 10 µm. Nitrogen or phosphorus are considered as dopants for the n-type pillars, typically used in epitaxial growth or ion implantation processes for 4H-SiC. Notable differences in Ron,sp are observed only for narrow pillar widths, where high doping levels are required for optimal performance and incomplete ionization becomes more pronounced due to the lower ionization rate of phosphorus-doped SiC (inset of Fig. 2). In contrast, wider pillars demand lower optimal doping levels, which reduces the incomplete ionization effect and results in minor performance variation across dopants. These findings suggest that both nitrogen and phosphorus can be effectively used for flexible doping profile control in SJ pillar formation.

Figure 3 summarizes the performance of semi-SJ devices with a fixed SJ-pillar width of w = 2 µm for various SJ-pillar depths. The Ron,sp of semi-SJ is higher than that of full-SJ with the same VB, and approximates the non-SJ limit, as the SJ component decreases. Additionally, the dominant breakdown path shifts from BOC to DC (Fig. 4), as the structure transitions from full-SJ to non-SJ. This shift is attributed to the reduction of the peak electric field at point O, which arises from the lower doping concentration required in the SJ layer. The adjacent non-SJ region exhibits an electric field profile that intensifies towards the SJ region, influencing the constant electric field component of the SJ region. As the non-SJ layer becomes deeper, the electric field enhancement must be offset by reducing the peak field at point O, thus requiring a further decrease in the SJ layer doping. As a result, the ionization integral along the DC path eventually exceeds that along the BOC path, leading to a change in the dominant breakdown mechanism.

[1] T. Fujihira, Jpn. J. Appl. Phys. 36, 6254 (1997). [2] R. Ghandi et al., in 2023 35th ISPSD (IEEE, Hong Kong, 2023), pp. 13–15. [3] R. Kosugi et al., in 2014 26th ISPSD (IEEE, Waikoloa, HI, 2014), pp. 346–349. [4] R. Kosugi et al., in 2019 31st ISPSD (IEEE, Shanghai, China, 2019), pp. 39–42. [5] R. Ishikawa et al., Physica Status Solidi (b) 260, 2300275 (2023). [6] D. Iizasa et al., J. Appl. Phys. 137, 065706 (2025). [7] Y. Zhao et al., Jpn. J. Appl. Phys. 58, 018001 (2019). [8] D. Stefanakis et al., IEEE Trans. Electron Devices 67, 3740 (2020).

ABSTRACT. The optimal static performance limit of symmetric semi-superjunction (semi-SJ) designs can be theoretically surpassed by adopting asymmetric pillar widths and doping concentrations. By deriving exact expressions of electric field for arbitrary asymmetric semi-SJ geometries based on Poisson's equation, we demonstrate that the trade-off between specific on-resistance and breakdown voltage can be further improved by widening the n-pillars while lowering their doping density. This asymmetric configuration mitigates the adverse effects of incomplete ionization and mobility degradation in the n-pillars, while the increased pillar width enhances conductance. These effects collectively compensate for the resistance increase associated with reduced doping, resulting in a net decrease in resistance. Meanwhile, the breakdown voltage is preserved due to suppressed electric field concentration at the pillar interfaces, achieved through increased p-pillar doping to satisfy the charge balance condition. As a result, the specific on-resistance is reduced by approximately 13-19% over the target voltage range of 2.2-5.2 kV without compromising in the case of symmetric design.

ABSTRACT. Silicon carbide (SiC) power devices are increasingly adopted in high-voltage applications due to their wide bandgap, high critical electric field, and excellent thermal conductivity. However, as voltage ratings increase, SiC unipolar devices face a fundamental trade-off between on-resistance and breakdown voltage, limiting further performance improvements. The superjunction (SJ) architecture- featuring vertically charge-balanced P/N pillars has been successfully implemented in silicon devices using multi-epitaxial growth and implantation to break the unipolar limit, though low dopant diffusivity makes this technically and economically challenging in SiC [1]. Consequently, trench filling epitaxy has been investigated [2], in which trenches formed in a N-type epitaxial layer are refilled with P-type using the same chemical vapor deposition (CVD) epitaxial reactors. Despite potential advantages as a practical and cost-effective means to form deep p-pillars for high voltage (≥3.3 kV) devices, the previous study [2] identified that the formation of voids in near-vertical trench geometries. Seen in Fig. 1, the void size shrinks with increasing sidewall angle. However, the ideal sidewall angle of 8° imposes minimum pillar widths in order to accommodate the geometry, and prevent inhibiting pinch off effects. These process-related trade-offs underscore the need to understand the impact on device performance of voids in the p-pillars, and the design compromises that would facilitate their removal. In this study, TCAD simulations are used to investigate the design trade-offs of a semi-SJ SiC Schottky rectifiers, considering the effect of void creation and side wall angle. First, a series of void-free, charge balanced structures (NA=ND) were designed, covering variations, depicted in Fig 1b, in doping, trench sidewall angle, pillar width (PW), and bottom thickness (TB). For each geometry, a series of TCAD simulations informed response surface models to determine the best Ronsp under a given BV with varying doping concentrations, resulting in the unipolar limit (Ronsp-BV) plots, of Fig. 2, and the implantation dose window results of Fig.3. A figure-of-merit (FOM) defined as BV2/Ronsp was used to identify the optimal device from each geometry, resulting in the summary graph of Fig. 4. These results serve as the initial baseline prior to introducing void-related process variations. Voids were introduced into the TCAD structures, their shape determined by the results of [2]. While the previous N-pillar doping was retained, the p-pillar doping was reoptimized to find the new, increased, value that would compensate for charge lost from the void. Representative structures with PW=2 μm, TB=2 μm and varying trench angle are shown in Fig. 3 in which the devices with trench angles of 0°, 4°, and 8°, resulted in decreases in breakdown voltage by 60.8 V, 76.6 V, and 57.0 V respectively. Corresponding implantation dose windows, defined as allowable trench doping maintaining at least 80% of peak BV, increased by 93.7%, 65.2%, and 36.3%. This is attributed to the reduction in effective charge density within the P-pillar caused by the void. Fig. 5 summarises the optimal device for every geometry after the introduction of a void. Across all geometries, the introduction of a void results in an average breakdown voltage reduction of 52.7 V and an increase in dose window by an average of 52.0%. Having established the trade-offs in all SJ designs with and without voids, it is possible to consider the practical implications from Fig.1 and [2]. In Fig 6, an “ideal”, but practically unrealisable, superjunction device is shown, with TB = 2 µm, PW = 2 µm, a trench angle of 0°, and no void. Also plotted are the two realisable compromise approaches. The approach taken in [2], to increase trench angle to 8° to avoid void formation, results in a minimum 20% increase in resistance, and a reduction in the blocking voltage of 23 V. Alternatively, maintaining the device geometry and increasing the doping around the void ,will lead to a 76 V reduction in blocking voltage, but no appreciable resistance penalty. Other scenarios, combining the void’s presence with increased sidewall angle, or the wider PW of 3 µm, all result in further resistance and blocking voltage penalties. In summary, the issue of void creation during trench fill epitaxy is most optimally solved by introducing a sidewall angle sufficient to prevent the formation of the void in the first place. However, the alternative approach, of compensating for the void’s presence with increased p-pillar doping, is viable with minimal further loss in device performance. These findings support the feasibility of void-aware SSJ design as a viable path toward robust and manufacturable high-voltage SiC devices for future commercial applications.

ABSTRACT. This work investigates the body diode and reverse recovery performance of 3.3 kV 4H-SiC MOSFETs, focusing on a planar semi-Superjunction (semi-SJ) structure featuring sidewall p-implantation through a deep trench refilled with SiO₂. The semi-SJ design is compared with a conventional planar MOSFET and a planar full-SJ device incorporating vertical p-pillars. The proposed semi-SJ design reduces on-state resistance by up to 23% and improves breakdown voltage by 500 V over the planar MOSFET. The full-SJ achieves a 47% reduction in on-state resistance and a breakdown voltage of 5.3 kV. Body diode behaviour was evaluated under varying gate biases; reduced conductivity modulation in the semi-SJ leads to the highest forward voltage drop (4.3 V at 50 A), while the full-SJ demonstrates superior third-quadrant performance. However, the deeper p-pillars in the full-SJ result in higher drain-source capacitance and a 3.5× increase in reverse recovery charge, leading to increased switching losses and ringing. Based on the RON X QRR figure of merit, the semi-SJ offers a balanced trade-off between conduction and switching performance, while also providing reduced fabrication cost compared to other SJ technologies.

ABSTRACT. SiC DMOSFET conventional integral diodes differ from those fabricated in Si by exhibiting much faster reverse recovery (RR), while exhibiting greater snappiness and a larger forward voltage drop, which can lead to large voltage overshoots and increased power loss. Charge balance (CB) and Superjunction (SJ) drift layers improve the on-state performance of the SiC DMOSFET by improving the trade-off between RON,sp and BV. However, the improved on-state performance of the CB and SJ can be counteracted by degraded RR performance, as observed in the Si SJ integral diode through excessive oscillations during RR due to the rapid changes of the SJ capacitance with voltage [1]. SiC DMOSFET with SJ and CB drift regions and a breakdown voltage of 3.3kV have previously been fabricated and characterized [2]. RR measurements are comparatively performed on the integral diode of these MOSFETs and key RR performance parameters are extracted. The temperature is varied from 77K to 423K, the reverse voltage from 500V to 1kV, and the ramping rate from 25A/μs to 93A/μs. All switching is performed at JF=50A/cm2. Expected RR behavior is for QRR,sp to increase with temperature due to increases in the minority carrier lifetime with temperature [3]. However, the SJ device exhibits an anomalous 1.4x-3.5x increase in QRR,sp at 77K compared to room temperature. The anomalous increase remains at JF=20A/cm2 but disappears at JF=7.5A/cm2. The strong linear dependence of QRR,sp on the ramp rate at 77K indicates an increase in stored charge at 77K, as it is the swept-out charge Q0 that is strongly dependent on the ramp rate. Analytical calculations of the depletion capacitance at zero bias show a 4% decrease at 77K compared to room temperature, which cannot explain the large increase in QRR,sp. Static I-V characterization reveals the onset of current-controlled negative resistance (CCNR) solely for the SJ device at 77K and JF=50A/cm2. The CCNR indicates substantial filling of the traps in the damage layer, allowing holes to be injected into the n-pillar. [5] The absence of similar behavior in the CB and conv. device suggests this behavior drives the excessive QRR,sp at 77K. While at 77K, the SJ device exhibits a QRR,sp 1.9x-3x of the CB device, at other temperatures it is generally faster, exhibiting a QRR,sp of 0.41x-1.15x of the CB device. For both the SJ and CB devices, the best snappiness (tB/tA) behavior is observed at room temperature. The SJ devices are consistently snappier than the CB devices, in all scenarios and temperatures tested. At room temperature, tB/tA for the SJ device is between 0.23x-0.56x of the CB device, as is expected since the SJ pillars must fully deplete before they can support significant voltage. This constraint on the SJ also leads to an increase in JPR with the SJ devices demonstrating a JPR of 1.8x-2.8x compared to the CB devices. With the exception of the anomalous behavior of the SJ at 77K, the weak dependence of QRR,sp on the ramp rate indicates the RR for both the SJ and CB devices is junction-capacitance dominated as it is for the conv. SiC integral diode. [3] The combination of the significantly improved snappiness of the CB device, the reduced JPR, and the increasing QRR,sp and JPR with temperature favor the usage of a CB integral diode over an SJ integral diode in circuit applications. Although CB diodes exhibit worse forward recovery characteristics than conv. diodes [6], the CB integral diode demonstrates similar RR performance [4].

ABSTRACT. Bias-temperature instability (BTI) is one of the primary sources of parameter drift in silicon and SiC MOSFETs and consequently largely determines device lifetime. Most studies of BTI in SiC MOSFETs characterize the threshold voltage (VT) but not the interface trap density (Nit), leaving uncertainty about the relative contributions of carrier capture and trap creation to the VT shift. In this study, to lend insight into the physical mechanisms responsible for BTI in SiC MOSFETs, we characterize the evolution of Nit during bias-temperature stress (BTS) using the charge pumping (CP) technique. We also characterize the shift in VT and hysteresis using the triple-sense method [1] for comparison with the Nit changes, demonstrating the utility of this technique for reliable characterization of VT and hysteresis. The devices studied are lateral, 4H-SiC MOSFETs fabricated on 4° off-axis 4H-SiC epitaxial wafers, with an implanted acceptor concentration of 2×1017 cm-3 in the channel, a thermal gate oxide formed on the Si face followed by NO annealing, and a channel length and width of 2 μm and 200 μm, respectively. The bias and measurement sequence during positive BTS is shown in Fig. 1(a). After each BTS interval, three ID-VGS sweeps are performed, from which three sense measurements of VT are obtained. For positive BTS, sweep #1 is a down-sweep from inversion to retain the electrons trapped at fast interface traps, sweep #2 is an up-sweep starting in accumulation to rapidly eliminate the trapped electrons by recombination, and sweep #3 is a down-sweep from inversion again. Thus, sweep #1 captures the maximum VT shift due to temporarily charged acceptor interface traps, sweep #2 minimizes the effect of acceptor interface traps by conditioning the interface with an accumulation bias, and sweep #3 allows measurement of the quasi-permanent hysteresis by comparing it with sweep #2. Fig. 1(b) shows representative ID-VGS curves resulting from the triple sense method in this study. The triple-sense measurement after each BTS interval is followed by CP, using a gate pulse amplitude of 15 V, a rise/fall time of 1 µs, and a high/low time of 10 µs. Fig. 2(a) shows the ID-VGS curves for sweep #3 after each positive BTS interval for a cumulative stress time (tstress) ranging from 0 s to 1000 s, for a bias stress field of 7.3 MV/cm in the oxide and a temperature of 175°C. This stress condition is highly accelerated while maintaining normal BTI degradation physics. The ID-VGS curve shifts in the positive direction monotonically with increasing tstress. As shown in Fig. 2(b), the VT shift is accompanied by an increase in hysteresis between sweeps #2 and #3, suggesting an increase in interface and/or border trap density. Fig. 3 shows the change in Nit as a function of tstress measured by CP. The Nit increases with tstress as a power law with an exponent of 0.42, demonstrating that new interface traps are indeed created during positive BTS. Spectroscopic CP (sCP) was also performed following the same procedure in [2] before and after the entire stress duration to evaluate changes in the Dit energy profiles, as shown in Fig. 4. The Dit increases on both sides of the bandgap, but primarily deeper in the bandgap. Fig. 5(a) shows the change in VT from sweep #2 versus tstress, and Fig. 5(b) shows the change in hysteresis (ΔVhyst) between sweeps #2 and #3. Data are shown for VT corresponding to different drain currents. In addition, a quantity ΔVit was calculated using ΔVit = qΔNit/Cox and overlaid in each plot for comparison. This quantity represents the expected change in hysteresis due to newly created interface traps switching charge state when switching between inversion and accumulation. In Fig. 6(a), ΔVT,2 is ~3× greater in magnitude than ΔVit, indicating that most of the VT shift during positive BTS is due to electron capture in border traps, as opposed to interface trap creation. On the other hand, ΔVhyst when measured at low drain current converges with ΔVit, demonstrating that the newly created interface traps during positive BTS are responsible for an increase in hysteresis, which was also measured by the triple sense method.

ABSTRACT. Point defects in semiconductors play a pivotal role in determining the electrical and optical properties of the host material. Understanding the physical fundaments of point defects in semiconductors was a key to arrive at the concept of opto-electronics devices, photovoltaics and energy storage devices, and very recently, state-of-the-art quantum information processing realisations [1] which have been shaped the socio-economical environment at global scale. Point defects may introduce defect levels (DLs) within the host semiconductor's fundamental band gap, thereby influencing its electrical conductivity, i.e., electrically active point defects [2]. Notably, these in-gap DLs and associated states also impact the optical properties of the material by reducing the optical excitation threshold energy compared to the perfect semiconductor's optical gap [3]. As a consequence, a common assumption is that solid-state defect emitters modify the host material's electrical conductivity [4]. We show below that this common assumption is not generally valid. In Fig. 1, we depict the possible optical transition mechanisms within semiconductors. Many point defects introduce multiple deep DLs into the fundamental band gap that could dramatically modify the electrical properties of the host because these deep levels often participate in carrier trapping and recombination events. In these defects, the optical transition could occur between the occupied and unoccupied DLs in the gap (see Fig. 1a). Alternatively, the optical transition can occur between localized DLs and the band edge, either valence band maximum (VBM) or conduction band minimum (CBM) (e.g. Ref. [5]). The respective excited states may be called pseudo-acceptor and pseudo-donor states as they show a Rydberg-series of the excited states converging towards the ionization threshold (see Fig. 1b). We note that the optical excitation threshold energies are lower than the electrical gap between the occupied and unoccupied states participating in the optical transition because of the attracting electron-hole interaction in the excited state. By harnessing this excitonic effect, we suggest a category of point defects that act as emitters and are electrically inactive in the ground state at the same time. A defect may introduce just one occupied DL below VBM without disturbing the bands close to VBM, so the defect is electrically inactive in the ground state and its positive charge state is not stable. This defect can be optically excited where the hole is localized in the resonant DL whereas the electron occupies a state split from CBM that builds up a pseudo-donor excited state. The exciton binding energy in the excited state could shift the excitation energy below the optical band gap of the host semiconductor with establishing a solid state defect emitter (see Fig. 1c). We label these defects as EIDE after the expression of electrically inactive defect emitters in the context. In this study, we demonstrate the principles of EIDE on a tri-carbon interstitial cluster in 4H silicon carbide (SiC) which produces an ultraviolet emission below the gap of 4H-SiC. First-principles calculations were carried out using density functional theory (DFT) with the hybrid HSE06 functional, combined with ΔSCF methods to describe excited states within a 576-atom supercell. Phonon-assisted photoluminescence was simulated using Huang-Rhys theory based on PBE calculations. Excitonic effects were accounted for through GW+BSE calculations. Our results reveal that the given defect has zero-phonon-line (ZPL) emission with characteristic local vibration modes in the photoluminescence (PL) spectrum which agrees well with a previously reported defect emitter, the so-called DII center in 4H-SiC [6,7] (see Figs. 1e,f). The optical excited state is a pseudo-donor type and it does not show electrical activity. The effect is mediated by the attractive electron-hole interaction in the optical excited state of the defect enhanced by the resonant defect states which is strikingly paramount in indirect semiconductors. This example expands our understanding of the interplay between defect-induced optical and electrical effects: we demonstrate the existence of defects that introduce optically active but electrically inactive states. This phenomenon may be observed in rather indirect than direct band gap semiconductors where all the defect levels lie outside to the fundamental band gap but reside very close to the band edges that may alter the minimal optical excitation energy without influencing the electrical conductivity. By exploiting the attractive interaction between electrons and holes in the optical excited state, these defects can show significant optical activity without exerting any discernible impact on the electrical conductivity. This finding might pave the ways to realize new generation opto-electronics devices. Additionally, due to their unique nature of being optically active yet electrically inactive, EIDEs may offer distinct advantages for quantum technologies, enabling photostable single-photon emission when isolated. Compared to well-known quantum emitters, which can undergo temporary or permanent photoionization during quantum optical manipulation, EIDEs remain electrically neutral and cannot be photoionized. This inherent neutrality eliminates charge-state instability, making them particularly suitable for integration with electronic components in quantum chip platforms.

[1] F. A. Zwanenburg, et al. Rev. Mod. Phys. 85, 961 (2013). [2] H. J. Queisser and E. E. Haller, Science 281, 945 (1998). [3] A. Gali, Nanophotonics 12, 359 (2023). [4] J. Weber, et al. Proc. Natl. Acad. Sci. 107, 8513(2010). [5] P. Li, et al. Phys. Rev. B 108, 085201 (2023). [6] S. Sridhara, et al. In Materials Science Forum, vol. 264, 493 (Trans Tech Publ, 1998) [7] W. Sullivan, and J. W. Steeds, In Materials Science Forum, vol. 556, 319 (Trans Tech Publ, 2007)

ABSTRACT. Color centers providing a spin-photon interface such as the silicon vacancy VSi in 4H-SiC bear promising applications for quantum technology devices [1-3]. Many device concepts include color centers close to the surface or close to interfaces [4], e.g. inside of waveguides for integrated photonics. Therefore, the parasitic influence of interfaces, including surface-related photoluminescent emitters, plays a major role in the device performance and complicates the material and device engineering process. The latter requires characterization and a deep understanding of surface emitter distributions, as well as a quantification of the color center generation yield close to the surface. To date, systematic approaches for surface emitter parametrization are missing and the color center generation yield quantification relies on g(2) autocorrelation measurements which is a highly time-consuming technique [5]. Approaches based on machine learning were so far limited to emitters deep in the bulk [6] due to a lack of training data including a sophisticated model of the surface emitter statistics. Real measurement data is naturally missing the corresponding ground truth required for supervised deep learning approaches and is usually not available to the extent required for network training. In this work, we first present a novel approach based on brute-force fitting for systematic parametrization of surface emitter photoluminescence (PL) mappings. We apply this approach on ion-irradiated (see example shown in figure 1a) as well as pristine 4H-SiC epilayers and show that we can achieve a statistical insight into emitter distributions with only the photoluminescence mapping information required. We find distributions for the measured emitter point spread function width (figure 1b), as well as for the emitter brightness (figure 1c) and residual background (figure 1d). The brightness distributions for both samples reveal contributions from irradiation-independent surface emitters, from a class (bright emitters) assigned to VSi(h) color centers, as well as an unexpected additional, not yet identified emitter class of reduced brightness. Subsequently, we demonstrate how to use the extracted statistical information to generate accurate synthetic training data for deep learning approaches, including a synthetic ground truth for supervised deep learning techniques. Finally, we present the performance of our machine learning approach to color center yield quantification for the shallow implanted VSi(h) color centers close to the sample surface, which is many times faster than the state-of-the-art g(2) autocorrelation technique: From the original PL mapping (figure 2a), the network infers the position and brightness of the single emitters (figure 2b). Given the characteristic brightnesses of specific emitter classes, as shown in figure 1c, we can deduce the number of VSi(h) emitters from the network output.

[1] S. Castelletto, C. T.-K. Lew, W.-X. Lin and J.-S. Xu, Rep. Prog. Phys. 87(1), 014501 (2024). [2] M. Ruf, N. H. Wan, H. Choi, D. Englund and R. Hanson, J. Appl. Phys. 130, 070901 (2021). [3] S. Pezzagna and J. Meijer, Appl. Phys. Rev. 8, 011308 (2021). [4] J. Tribollet, D. Muller, S. Roques, J. Bartringer and T. Fix, Nanoscale 13, 13827-13834 (2021). [5] F. Fuchs, B. Stender, M. Trupke et al., Nat. Commun 6, 7578 (2015). [6] D. Kim, S. Paik, J. Park, S.-J. Hwang, S. Onoda, T. Ohshima, D.-H. Kim and S.-Y. Lee, Adv. Quantum Technol. 7 (11), 2400173 (2024).

ABSTRACT. Color centers/defects in semiconductors are promising single photon sources for realization of quantum information processing. It is known that SPSs exist at a SiO2/SiC interface, which exhibit bright emission and can be formed simply through thermal oxidation. However, the emission spectra of these interface SPSs are inhomogeneous, making it difficult to identify their origin and to find a way for practical use. We recently reported that such interface bright SPSs are almost eliminated by oxidation at high temperature. Even with that sample, weak background emission is detected from the interface. Similar phenomena have also been reported by other groups. In this study, we investigated the origin of the background emission using confocal microscopy. We identify that the background emission originates from a distinct class of interface SPSs emitting in the near-infrared (NIR). Remarkably, these SPSs exhibit highly uniform spectral characteristics across different locations and samples, which is totally different from the interface bright SPSs previously reported. Furthermore, we show that their density can be controlled via the NO annealing process.

ABSTRACT. In quantum applications including cryptography, computing, and sensing, spin defects in semiconductors are regarded as attractive candidates as a qubit. As a host for spin defects, silicon carbide (SiC) is appealing owing to its well-established crystal growth, availability of n- and p-type doping, and micro-scale processing technologies. As examples of spin defects, a coherent control of single spins for the silicon vacancy (V_Si) and the nitrogen-vacancy center (N_CV_Si) has been demonstrated. The oxygen-vacancy center (O_CV_Si) has been theoretically predicted to have a high-spin ground state of S = 1 and near-infrared photoemission. Although several other candidates in SiC have been studied, many possible defects remain to be explored. In the present study, we systematically investigated the impurity-vacancy centers (i.e., XV centers) in 4H-SiC based on ab initio calculations.

ABSTRACT. Achieving high-fidelity control of large quantum registers is a central challenge in solid-state quantum information processing. Recent advances in quantum optimal control have enabled the entanglement of multiple weakly interacting nuclear spins, pushing the frontier of scalable quantum logic in systems such as diamond NV centers. Building on this progress, we present a framework that combines robust optimal control techniques with Hamiltonian learning strategies to enable precise characterisation and manipulation of complex nuclear spin environments. In this talk, we highlight recent developments covered by the work of Steidl et al. [1] demonstrating the integration of high quality defect in semiconductor junction combined with sophisticated quantum coherent control. Extending these techniques, we now report fresh experimental results on the characterisation of nuclear spin clusters comprising 20 spins. We achieve reconstruction of interaction topologies and coherence-preserving addressing of individual spins within dense registers. Our results suggest a path toward quantum registers with tens of reliably controlled nuclear spins with high fidelity readout [2], marking a step toward fault-tolerant quantum network node operation in semiconductor solid-state platform. We conclude with an outlook on integrating these techniques with error correction protocols and quantum memory architectures.

References: [1] Steidl, T., Kuna, P., Hesselmeier-Hüttmann, E. et al. Single V2 defect in 4H silicon carbide Schottky diode at low temperature. Nat Commun 16, 4669 (2025). [2] Hesselmeier, Erik, et al. "High-fidelity optical readout of a nuclear-spin qubit in silicon carbide." Physical Review Letters 132.18 (2024): 180804.

ABSTRACT. Abstract

In Electric Vehicle (EV) operation, a three-phase inverter of PWM switching method generates the power dissipation of conduction and switching losses in SiC semiconductor. The power loss, depending on the magnitude of phase current, DC-Link voltage and modulation index, causes an increase of junction temperature that is an important feature for the performance and reliability of the inverter. In this paper, a thermal model is developed to estimate the junction temperature irrespective of various driving conditions such as high-speed driving, regenerative braking, and hill-holding. In addition, the model is effectively used to estimate the reliability of SiC power modules under thermal stress conditions over the EV lifetime. The lifetime calculation is implemented through the vehicle mission profile with the thermal model and a thermal stress counting algorithm.

Synopsis Introduction

Based on EV driving conditions, the inverter performs three different operation modes: motoring for acceleration, regenerative braking for deceleration, and hill-holding for withstanding force on a hill. In these driving conditions, the current passing through the SiC semiconductor produces power loss that is transformed into heat, raising the junction temperature. As the power is applied to the switching devices leading to a rise and fall of temperature, the wire bonds and solder layers are subjected to thermal stress that causes the SiC to fail over time. Therefore, the junction temperature of the SiC can be used as an indicator of secured performance and reliability of the power module [1].

The Thermal Model

The block diagram in Fig. 1 explains how the thermal model is developed to estimate the junction temperature.

First, the Current Map defines an appropriate peak current according to the motor torque and RPM.

Then, the defined current goes into the Power Loss model with two other parameters, battery voltage and switching frequency, to attain total power consumption in the power device.

The second part is the RC model, which reflects the Power Loss model to estimate the delta junction temperature (ΔTj) in transient cases, considering both heat capacity and thermal resistance.

Once the final ΔTj is derived, the water temperature is added to estimate the maximum junction temperature.

Fig. 1. The thermal model to estimate the junction temperature

Lifetime Estimation of Power Module

To ensure reliability, the load profiles must first be qualified and adjusted through field studies with test vehicles. The load profile of the inverter power module originates from a mission profile, which specifies the velocity of the EV for a certain period. To define a mission profile, Hyundai EVs were driven by test drivers on various road conditions such as highway, local road, unpaved road, and city driving. As shown in Fig. 2, the standardized mission profile is constructed from a combination of road conditions with a fixed ratio. The mission profile is then converted into the load profile of the power module, which mainly depends on the driving strategy that controls torque and motor speed [2].

Fig. 2. Vehicle mission profile Fig. 3. Temperature profile

To convert the vehicle mission profile into a temperature profile, parameters such as motor speeds, torque, and DC-link voltages are recorded. The thermal model represents the fluctuating junction temperature cycles (Fig. 3) caused by transient power flow through the SiC power module.

In Fig. 4, rainflow cycles are extracted from the temperature profile and histograms of temperature variations are shown. The dotted line represents the actual junction temperature from the thermal model. To estimate the thermal stress of the SiC power module subjected to a variable load history, the rainflow algorithm—a standard method in fatigue and failure analysis—is used to extract full and half cycles of the generated temperature cycles [3].

With MATLAB tools, the cycles and amplitudes are counted, and subroutines are used to create histograms of the temperature values. This allows for counting accumulated cycles for each occurrence of ΔTj from the temperature profile. For each occurrence, ΔTj is evaluated for lifetime consumption based on the module supplier’s power cycling capability test data. The lifetime consumption from each ΔTj is then summed to evaluate the total lifetime consumption [4].

Fig. 4. Rainflow cycles extracted from temperature profile & histograms of temperature variations

Fig. 5. Power cycling testing method Fig. 6. Power module power cycling curve

For general reliability investigations of power modules, power cycling tests are usually performed with square-wave current, as shown in Fig. 5 [5]. The results are plotted in a power cycling curve (Fig. 6) that represents the number of temperature cycles a module can withstand before failure. Modules commonly fail due to wire bonding fatigue or cracks in solder layers between dies and substrates [6]. The reliability data are plotted in a logarithmic diagram, where the horizontal axis shows ΔTj and the vertical axis shows the number of cycles.

Additionally, passive temperature cycles caused by coolant heating (from ambient to operation temperature) must be included after analyzing yearly ambient temperature distributions in extreme cold regions [4]. Combining active and passive cycles provides the overall power cycling lifetime of the module. The sufficiency of reliability can then be confirmed for a given mission profile [5].

According to our simulation results, the applied power module will operate reliably for the vehicle lifetime as long as all limiting conditions are not exceeded. In terms of reliability, operating within the guaranteed temperature range is essential to prevent accumulated fatigue damage from thermal stress cycles.

Conclusion

The junction temperature is of crucial importance in designing reliable EV power electronics since component reliability strongly depends on device junction temperature. This paper introduced a thermal model that converts a vehicle mission profile into a temperature profile, enabling lifetime estimation of power modules through a thermal stress counting algorithm. Using this method, we ensured that the power module performance can meet a 15-year lifetime target for EV applications.

References

[1] T. K. Gachovska, A real time thermal model for monitoring of power semiconductor devices, Univ. of Nebraska, USA. [2] M. Denk, Efficient online-algorithm for the temperature cycle recording of an IGBT power module in a hybrid car during inverter operation, CIPS 2014. [3] L. GopiReddy, Lifetime prediction of IGBT in a STATCOM using modified graphical rainflow counting algorithm, Univ. of Tennessee, USA. [4] M. Thoben, From vehicle drive cycle to reliability testing of Power Modules for hybrid vehicle inverter, Infineon Technologies AG. [5] A. Hensler, Power cycling test at high temperature with IGBT power modules for hybrid electrical vehicle applications, Chemnitz Univ. of Technology, Germany. [6] T. Hunger, Extended reliability of substrate solder joints in power modules, Infineon.

ABSTRACT. Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have become preferred components for electric vehicle (EV) traction inverters due to their exceptional electrical and thermal properties [1]. Conventional operation employs negative gate-source voltage (VGS < 0 V) to mitigate parasitic turn-on phenomena in half-bridge configurations during switching transitions. Some modern electric vehicle security systems, however, mandate continuous power supply to high-voltage subsystems (including gate drivers and DC-link capacitors) during stationary conditions which are called Sentry Mode. This operational requirement subjects SiC MOSFETs to concurrent negative VGS (-3 to -5 V typically) and elevated drain-source voltage (VDS ≈ 400-900 V) throughout not only operational but also prolonged stationary periods of vehicle. Such persistent dual-bias stress introduces critical reliability concerns that current accelerated lifetime testing methodologies (typically assessing single stress factors) fail to adequately address [2,3], creating a significant knowledge gap in degradation modeling under combined electrical stress conditions. To clarify these concerns, dual-bias time-dependent dielectric breakdown (DB-TDDB) test was proposed and implemented. The experimental configuration employed in this study is illustrated in Fig.1. During testing, a negative gate-source voltage (VGS=-40.5V) was applied to the device under test (DUT) while maintaining a VDS of 880V. Complementary TDDB characterization was conducted under negative gate bias conditions (VGS=-40.5 V, Tj = 175℃). To determine the acceleration factor, constant-voltage TDDB testing (VGS=40.5V) was performed under three junction temperature conditions (Tj=125℃, 150℃, 175℃). Each test group consists of 60 samples, and testing should continue until at least 63% cumulative failure rate (38 pcs failed). The Weibull distributions of time-to-breakdown are shown in Fig.2. To characterize gate oxide (GOX) stress states under various accelerated conditions，Silvaco TCAD simulations were performed to analyze the GOX electric field distribution under varying VGS and VDS. Simulation results revealed two distinct patterns. Under standard reverse bias condition, the maximum GOX electric field (Emax) is localized in the JFET region. In contrast, implementation of the proposed DB-TDDB framework induces a spatial shift of Emax to the source region, as quantitatively compared in Fig.2. This spatial redistribution of Emax indicates that negative gate voltage operation induces a nonlinear coupling effect between gate and drain voltages. To account for this interaction, we developed a dual-acceleration-factor E-model expressed as: TTF=A_0*exp⁡(E_a/kT)*exp⁡(-γ_1 E_ox )*exp⁡(-γ_2 V_DC ) (1) Given the computational complexity of deriving GOX electric fields directly from VDS, an empirical voltage normalization approach was implemented to quantify VDS acceleration factors. In this model, A0 is a constant, while Ea represents the temperature acceleration factor. The parameters γ₁ and γ₂ correspond to the acceleration factors for gate-voltage and Drain-bias, respectively. Notably, the activation energy (Ea = 0.532 eV), derived through the thermochemical linear E-model [4], represents a temperature-dependent parameter governed by the gate oxide's bond dissociation energy under Boltzmann thermal activation theory. Acceleration coefficients were quantified through negative and dual-bias TDDB tests: VGS acceleration factor: γ₁ = 3.9 cm/MV and VDS acceleration factor: γ₂ = 0.5/kV. Weibull analysis (shape parameter β = 2.52) enabled lifetime extrapolation, projecting a 1 ppm cumulative failure rate at 5.11×10¹³ hours under automotive operational profiles (VDS = 880 V, VGS = 18V, Tj = 100℃). This lifetime performance exceeds by orders of magnitude the 20-year service life requirement specified in AEC-Q101 Rev-H qualification standards for automotive power electronics. The complete experimental matrix, including extracted 63% time-to-failure (TTF) distribution parameters and model fitting results, is systematically summarize in Table 1 and visually presented in Fig.4. In conclusion, we have developed an improved E-model lifetime prediction based on proposed DB-TDDB method that comprehensively integrates both negative gate-source and drain-source coupling stress under actual operational conditions. Through several groups of gate oxide lifetime assessment experiments executed according to this framework, key acceleration factors were quantitatively extracted. Subsequent lifetime prediction based on multivariable stress analysis derived an operational lifespan expectation under combined electrical-thermal loading conditions. [1] C.Wu, R.Rout, Yu.Wang, Y.Lin and J. Hu, IEEE Asia Pacific Conference on Circuits and Systems (2024) p.317 [2] G. Rescher, G. Pobegen, T. Aichinger and T. Grasser, IEEE Trans. Electron Devices, 65 (2018) [3] S. Mbarek, F. Fouquet, P. Dherbecourt, M. Masmoudi and O. Latry, Microelectronics Reliability, 64 (2016) [4] K. Matocha, IEEE Transactions on Electron Devices, 55 (2008)

ABSTRACT. The DC Fast charger mission profile requires a high number of daily charging sessions. Each charging session led to a power cycle that induces a fatigue effect on the components where materials are coupled with different expansion coefficient and Young’s modulus. Mechanical fatigue is proportional to the thermal excursion experienced by the material, therefore, depending on the temperature profile, the mechanical fatigue may occur on the wire bonding and/or on the die attach. In this work, several SiC mosfets in base-less modules from different manufacturers have been submitted to power cycle test with several minutes cycle duration. We tested different die size on the same set-up and we confirmed that it does not affect life. We fitted the results with the most popular models. For a specific manufacturer we compared long time cycle test results with a seconds cycle test on the same module. The normalized results have been analyzed and compared with the coefficients proposed in literature. Data seems to be in accordance with the simple power law coefficient indicating that tON does matter in any duration.

ABSTRACT. In this study, a room temperature bonding method using activated Cu atomic layer was proposed, and the effectiveness is experimentally verified. The strong bond strength between SiC and Cu of approximately 52 MPa was demonstrated at room temperature. These results show that the proposed room temperature bonding method has great potential for the efficient heat dissipation of high-power SiC devices

ABSTRACT. Silicon carbide (4H-SiC) devices with blocking voltage rating up to 3.3kV have been successfully commercialized [1]. Two key factors for this are the availability of low cost, high quality SiC substrates, and the availability of low defect epitaxial layers with a thickness of up to 30 m. SiC devices with 6.5 kV and 10 kV blocking voltage ratings have started to become available [2], and their yield and reliability is still influenced by higher density of extended defects [3]. Such devices can be used for median voltage applications such as traction control, motor drives, renewables, etc. However, for grid-scale and defense applications ultra-high voltage devices rated from 15 kV-30 kV are required. To achieve this, SiC epitaxial layers with thickness 125-270 m is required. Several reports have discussed extended defects that are characteristic of 100-200 m thick epilayers such as BPD loops [4], particles related inclusions [5], stacking fault transformations [6] and complex faults [7] resulting in BPD multiplication. These defects are generated due to the thick epitaxial growth and are not replicated BPDs from the substrates. Issues with thick epitaxial layers include combination of higher thermal and lattice strain, growth front morphology, and need for complex growth chemistries. In this work, we report on novel extended defects in SiC epi- layers as thick as 280 m that was grown using CVD technique at Linköping University with modified chlorine-based precursors. A graded doped buffer layer was grown before the drift layer for better strain management. Additionally, novel horizontal appearing half-loop array and its formation was investigated in 125 m thick epi-layers. Ultraviolet photoluminescence (UVPL) imaging was performed using a custom setup with a 355nm laser excitation, and 665 nm long pass filter to image extended defects for such high thickness epitaxial layers. High resolution X-ray topography (XRT) measurements with transmission, reflection as well as cross-sectional XRT was performed using in-lab Rigaku XRTMicron system to investigate defect formation mechanisms. UVPL imaging revealed various extended defects in the wafers. A significant achievement for the 280 m thick epi-layer was that there is not a single BPD that propagated from the substrate into the epi-layer in the entire wafer. The only source of BPDs included particle (down falls), which were ~50 per wafer. In thick epi-layers, BPD loops are typically observed [4], but none were observed in this wafer, which indicates very low thermal stress during growth. The low stress is also evidenced by low glide of BPDs emanating from the inclusions. Detailed strain analysis will be presented including X-ray analysis. In grown stacking faults appearing in an array were observed and their formation was identified as deflection of TSD to form a Frank fault after 240 m growth due to higher step bunching. Details will be presented. Another defect type appearing as horizontal half loop arrays [8] were analyzed in 125 m thick epitaxial layer. These originate from BPD loops nucleated within the thick low doped epi-layer due to high stain during epi- growth. Details of formation mechanism of this defect will also be presented. [1] D. Xing et al., pp 1-6, 2020 WiPDA Asia, doi.org/10.1109/WiPDAAsia49671.2020.9360270 [2] V. Pala et. al., 2014 IEEE Energy Conversion Congress and Exposition (ECCE), 449–454 [3] R. E. Stahlbush, et. al. 2022 IEEE International Reliability Physics Symposium (IRPS) pp. 65–61 [4] H. Tsuchida, et al. physica status solidi (b) 246.7, 1553 (2009) [5] J. Guo et. al., J. Cryst. Growth 480, 119 (2017) [6] Thierry-Jebali et al. AIP Advances 5, 037121 (2015) [7] N. A. Mahadik, et. Al., Scripta Materialia 235, 115598, (2023) [8] N. A. Mahadik, et. Al., J. Appl. Phys. 131, 225702 (2022)

ABSTRACT. Since proton implantation of SiC devises has recently been reported to be effective in suppressing the bipolar degradation phenomenon, we investigated the effect of proton implantation on the expansion of stacking faults of 4H-SiC epilayers by the EVC (Expansion-Visualization-Contraction) method. The experimental results confirmed the suppression of bar-shaped 1SSFs (Shockley-type stacking faults) expansion into the epitaxial layer. However, we have also found the 1SSFs expanded from the proton implanted layer toward the epi/sub interface, implying that crystal structure disorder caused by proton implantation damage can be the starting point of 1SSF expansion.

ABSTRACT. It has been explained that the cause of bipolar degradation of SiC MOSFETs is mainly the bar-shaped 1SSFs (single Shockley stacking faults) expand from the BPDs (basal plane dislocations). However, when in-grown SF (stacking fault) was tested by the EVC (Expansion Visualization Contraction) method [1], a bar-shaped SFs also extended from in-grown SF, when irradiated with UV, but remained mostly bar-shaped SFs without fully contracting compared to 1SSF even when heated. Judging from the results of the EVC method, it is different from pure 1SSF. Therefore, we investigated the spectrum of the extended bar-shaped SFs by mapping measurements using a third harmonic YAG laser beam for SF extension. We report that the in-grown SF was 3C-SiC, and we observed a region of expanded bar-shaped SF in the same PL wavelength range that is thought to be affected by the 3C-SiC in addition to the 1SSF.

ABSTRACT. Stacking faults (SFs), like other structural defects in 4H-silicon carbide (4H-SiC), are propagating from the SiC substrate into the epitaxial layer or generating during the epitaxial layer growth [1]. Some types of SFs in 4H-SiC expand under ultraviolet (UV) illumination or current stress. Bipolar degradations of SiC PiN diodes and MOSFETs resulted from the expansion of triangular SF into the elongated bar-shaped SF and its structure was known as (3,1) single Shockley-type SF [2]. In this study, we investigated the structural transformation within bar-shaped SFs in 4H-SiC epitaxial wafer and substrate. The structural transformation of SFs was systematically investigated based on the photoluminescence (PL) mapping, etch pit formation and evaluation from dislocations, reflection X-ray topography (XRT), and high-angle annular dark-field high-resolution scanning transmission electron microscope (HAADF HR-STEM) observations. In addition, we theorical calculation of stacking fault energy (SFE) by employing ab initio density function theory (DFT). Multiple line features with different PL intensity were found inside the bar-shaped SFs in the PL map image as shown in Fig. 1(a). Some studies showed the PL map images with the similar line features inside the SFs, but it has not been discussed what do the lines mean. Fig. 1(b) shows optical microscope image after molten KOH etching of the same bar-shaped SF in Fig. 1(a). Replica picture for the observed lines in PL map image of Fig. 1(a) was superimposed on the etch pit image of Fig. 1(b). Very surprisingly, we could find oval-shaped etch pits at every inner line ending on the layer surface in addition to oval-shaped etch pits for two partial dislocations at the top and bottom edges of the bar-shaped SF. This strongly meant that the previous lines inside bar-shaped SF in the PL map image indicate partial basal plane dislocations (BPDs) dividing the single bar-shaped SF into many different SF regions. In order to confirm the existing partial BPDs, XRT images were obtained from the same bar-shaped SF region as shown in Fig. 1(c). The previous replica picture for the observed lines in PL map image was superimposed on the XRT image as shown in Fig. 1(d). Some BPDs were observed in the XRT image in Fig. 1(c), which coincides with the locations of the lines in PL map image and etch pits. As mentioned, etch pits were formed at every inner line of the PL map image, however, BPDs were not observed at every etch pit positions. This implied that a net displacement vector relating to the some partial BPDs did not satisfy visible imaging condition i.e., g·r=0 (g: diffraction vector, r: displacement vector of defect), although such BPDs inevitably formed inner lines both PL map and etch pits. To support our investigation, we carried out PL spectrum mapping inside the bar-shaped SF to determine the characteristic PL emission wavelength depending on the SF types across the regions divided by the previous inner lines. Four different characteristic PL emission wavelengths were detected; 425, 427, 428, and 431 nm (in the order of wavelength). This strongly meant again that there are several different types of SFs inside the single bar-shaped SF. In order to confirm the different SF structures inside the single bar-shaped SF, finally, the structures of SFs in the both epitaxial layer and substrate were investigated using HAADF HR-STEM. In the substrate region contacting to the epitaxial layer, bar-shaped SF was confirmed, but the length of it was shorter than that in the epitaxial layer as schematically shown in in Fig. 2(a). Representative observed positions in the epitaxial layer, substrate, and partial dislocation are illustrated in Fig. 2(a). The SF structures at the A' region in the substrate and the A region in the epitaxial layer were determined to the same structure (3,3,3,3) SFs as shown in Fig. 2(b) and (c), respectively. It meant that the bar-shaped SF in the epitaxial layer was replicated from the SF in the substrate. Fig. 2(d) showed the SF structure at the B region in the epitaxial layer, divided by the partial BPD at the C position, and it was determined to a (3,3,2,2,3,3) SF, which is different from the SF in the region A. The continuous structural transformation of the SF structures from the A to the B regions could be confirmed in Fig. 2(e), which was observed at the partial BPD (the position C). Other many numbers of variations and structural transformations of SFs were found at the both epitaxial layer and substrate (not shown here). The representative of such SF structures was (3,2,3,2,2,3,3,2), (3,3,2,2,2,2,2,2,3,2,3,2), and (3,3,2,2,2,2,2,2,2,2,3,2,3,2), all of which showed characteristic PL emission wavelength at 428 nm. We reported that numerous variations of SFs, both Shockley and Frank type, with emission wavelengths in the range of 420–430 nm and miniscule differences in wavelengths were formed in 4H-SiC epitaxial layers [3]. Our investigation and systematic finding in this study meant that the structural transformation of SF was driven by dislocation behaviors, not by external energy like as current stress or UV irradiation. More detail understanding and insight to structural transformation of SF with PL emission wavelengths in the range of 420–430 nm in the epitaxial layer and substrate including theorical calculation of SFE by DFT will be represent at the conference.

This work was supported by the Technology Innovation Program (No. 25A02037, 25A02099) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

[1] T. Yamashita, S. Hayashi, T. Naijo, K. Momose, H. Osawa, J. Senzaki, K. Kojima, T. Kato, H. Okumura, J. Cryst. Growth 490, 89–96 (2018). [2] T. Kimoto, H. Watanabe, Appl. Phys. Express. 13, 120101 (2020). [3] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Appl. Phys. Lett. 124, 152109 (2024).

ABSTRACT. 4H-SiC substrates and epitaxial layers have many different kinds of structural defects like micropipe (MP), threading screw dislocation (TSD), threading edge dislocation (TED), basal plane dislocation (BSF), basal stacking fault (BSF), and prismatic stacking fault (PSF). MP, TSD, TED, and BPD are easily evaluated by simple molten KOH etching by forming the etch pits on the top surface where the defects terminated. Evaluating, recognizing and classifying the origins of etch pits are possible based on shapes and sizes of the etch pits [1,2]. In this study, we report “giant” etch pit formation and its origin formed on 6-inch 4H-SiC epitaxial wafer investigated by KOH etching. PL mapping, FE-SEM, TEM, HRTEM, and HAADF HR-STEM. The giant etch pit is oval-shaped as like the conventional BPD etch pit but it is really bigger than the normal etch pits formed on TSD, TED, and conventional BPD. Fig. 1 shows FE-SEM images of the etch pits and PL mapping images from stacking fault (SF). The oval-shaped BPD etch pits (mentioned to the P-BPD) shown in Fig.1 (a-c) are the etch pits formed from two partial BPDs at the boundary of the SF, in fact. The formation of oval-shaped etch pits from two partial dislocations at the SF can be confirmed by comparing to the corresponding SF PL map images in Fig. 1 (d-f). These results meant that the partial BPDs at the SF can form the oval-shaped etch pits as like those formed on the conventional perfect BPDs. In addition to the oval-shaped etch pits from two partial BPDs, surprisingly, a very big etch pit (mentioned to the giant etch pit) was formed between the two P-BPD etch pits of the typical triangular SF as shown in Fig. 1(c). In order to investigate the origin of giant etch pit, FIB TEM specimen was prepared at the front position of the giant etch pit as mentioned in Fig. 1(c). Fig. 2(a) is low-magnification TEM image showing two basal SFs (BSF-1 and BSF-2), and one PSF. Here, the PSF was not reached to the top surface but terminated inside the epitaxial layer. Fig. 2(b) shows HRTEM image for the two BSFs and one PSF in (a). From the HAADF HR-STEM observations, two BSFs were determined to (5,2) and (4,1) Frank-type BSFs as shown in Fig. 2(c). In addition, the PSF was started at the meeting point of the two Frank BSFs. Fig. 2(d) shows HAADF HR-STEM image at the region of PSF end-pint inside the layer mentioned in Fig. 2(a). The PSF-end was connected to a Frank-type (2,1) SF, therefore, a partial BPD must be existed at the left-end of this Frank-type (2,1) SF. This BPD must reach to the top surface of the epitaxial layer and can form the BPD etch pit. At the right-end of the Frank-type (2,1) SF, there should be a stair-rod dislocation, which connected to the PSF [3], should be reached to the top surface of the epitaxial layer, too. The PSF showed stairs-like feature and there were (2,1) Frank-type BSFs at every step of the stairs. Therefore, we could conclude that the BPD at the (2,1) Frank-type SF formed the giant etch pit but the PSF itself might contributed the formation of the giant etch pit considering the size of pit.

This work was supported by the Technology Innovation Program (25A02037) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

[1] Y. Z. Yao, Y. Ishikawa, Y. Sugawara, H. Saitoh, K. Danno, H. Suzuki, Y. Kawai, and N. Shibata, Jpn. J. Appl. Phys. 50, 075502 (2011). [2] Y. Cui, X. Hu, X. Xie, and X. Xu, Cryst. Eng. Comm. 20, 978 (2018). [3] M. Benamara, X. Zhang, M. Skowronski, P. Ruterana, G. Nouet, J. J. Sumakeris, M. J. Paisley, and M. J. O’Loughlin, Appl. Phys. Lett. 86, 021905 (2002).

ABSTRACT. As the demand for energy-efficient and high-performance power electronics continues to grow, Silicon Carbide (SiC) has emerged as a key material, thanks to its exceptional electrical properties and ability to reduce conduction losses in power devices. A key challenge in SiC device fabrication, such as Junction Barrier Schottky (JBS) diodes, lies in forming low-resistance backside ohmic contacts on mechanically thinned substrates, an essential step for reducing substrate resistance. Traditionally, rapid thermal annealing (RTA) has been used to form these contacts, as shown in Fig. 1(a). However, the wafer thinning by mechanical grinding (Fig. 1(b)), necessary to reduce substrate resistance, introduces mechanical fragility and process limitations that make RTA’s thermal budget incompatible with thin wafers, increasing the risk of wafer breakage and device failure. Laser annealing presents a promising alternative by providing rapid, localized thermal processing with precise control, enabling the reliable formation of ohmic contacts on substrates thinner than 100 µm, as shown in Fig. 1(c).

In this presentation, we present recent advancements in laser annealing techniques for ohmic contact formation on thinned 4H-SiC substrates [1–4]. We investigate how laser parameters interact with grinding-induced crystal damage, focusing on the effects of sub-surface defects and surface roughness on silicide formation during annealing. Electrical characterization, through forward voltage drop, Vf, measurements at the nominal current I₀ is presented in Fig. 2, comparing samples subjected to three different thinning processes on samples laser-annealed at 3.4 J/cm² with three pulses. As a reference, Vf values from diodes annealed using conventional RTA (60 s at 1000 °C in N₂) are also included.

The results show that Vf decreases with increasing defectivity in the sub-surface region induced by the thinning process. Notably, the Vf measured on rough-ground samples is comparable to that of the reference RTA-annealed diodes, indicating effective ohmic contact formation and highlighting the robustness of laser annealing. Further, the talk will cover comprehensive morphological and electrical analyses of laser-annealed contacts using various metallizations, including Nickel (Ni), Nickel Silicide (NiSi), and Titanium (Ti). These insights underscore the potential of laser-based processing to overcome critical thermal and mechanical challenges in SiC power device manufacturing, paving the way for more efficient, reliable, and sustainable power electronic systems that align with the evolving needs of the industry.

[1] S. Rascunà, P. Badalà, C. Tringali, C. Bongiorno, E. Smecca, A. Alberti, S. Di Franco, F. Giannazzo, G. Greco, F. Roccaforte and M. Saggio, Morphological and electrical properties of Nickel based Ohmic contacts formed by laser annealing process on n-type 4H-SiC. Mater. Sci. in Semicond. Process. 97, 62 (2019). [2] P. Badalà, C. Bongiorno, P. Fiorenza, G. Bellocchi, E. Smecca, M. Vivona, M. Zignale, M. Massimino, I. Deretzis, S. Rascunà, M. Frazzica, M. Boscaglia, F. Roccaforte, A. La Magna, A. Alberti, Electrical and Structural Properties of Ohmic Contacts of SiC Diodes Fabricated on Thin Wafers. Solid State Phenomena, 359, 97–103 (2024). [3] P. Badalà, S. Rascunà, B. Cafra, A. Bassi, E. Smecca, M. Zimbone, C. Bongiorno, C. Calabretta, F. La Via, F. Roccaforte, M. Saggio, G. Franco, A. Messina, A. La Magna, A. Alberti, Ni/4H-SiC interaction and silicide formation under excimer laser annealing for ohmic contact, Materialia, 9, 100528 (2020). [4] P. Badalà, C. Bongiorno, P. Fiorenza, G. Bellocchi, E. Smecca, M. Vivona, M. Zignale, M. Massimino, I. Deretzis, S. Rascunà, M. Frazzica, M. Boscaglia, F. Roccaforte, A. La Magna, A. Alberti, Electrical and Structural Properties of Ohmic Contacts of SiC Diodes Fabricated on Thin Wafers. Solid State Phenomena, 359, 97–103 (2023).

ABSTRACT. A body diode (BD) is also widely utilized as a free-wheeling diode instead of the Schottky barrier diode. Utilization of BD can contribute to cost reduction of SiC components and miniaturization of total system application, but there is a disadvantage that switching losses increases due to the reverse recovery current caused by minority carrier accumulation in the case of using a BD. High-temperature activation annealing can potentially introduce carrier lifetime killer without additional processes or equipment, making it cost-effective. However, few studies have reported on the application of the method to SiC-MOSFETs. Therefore, this study focuses on the generation of carbon vacancies through high-temperature activation annealing and investigates the effect of different activation annealing temperatures (1750°C, 1800°C, and 1900°C) on electrical characteristics. We found that at 1900°C, reverse recovery charge is reduced by approximately 70% compared to 1750°C and 1800°C. DLTS analysis confirms that higher annealing temperatures increase the densities of Z1/2 and EH6/7 centers, indicating more carbon vacancies.

ABSTRACT. This paper demonstrates a reliable (tighter than 175°C AEC-Q101 criteria) and manufacturable (enhanced-stress >1400V, yield >92%) SiC 1200V planar MOSFET with leading specific resistance Ron,sp 1.95mΩ·cm². The results of this work are attributed to shrunk cell pitch, retrograde implantation profile, atomic scale planarized surface after high-temperature ion implant activation, reduced carbon cluster during gate-dielectric formation, and thin SiC substrate with eliminated damage layer. SiC devices are key components for high-power and fast-switching energy systems [1]. They have been widely in Electric Vehicles and Energy Storage Systems [2]. However, its high material cost, particularly SiC epitaxial substrate, limits its potential in industrial and consumer markets. While trench MOSFET offers a solution by reducing Ron,sp through alternative crystalline direction [3], its reliability concerns and loss of attractiveness at >1700V applications limit its future outlook [4]. This paper presents a highly reliable planar MOSFET structure with leading performance and high manufacturability through implementing various process innovation and optimization. Fig. 1 shows Ron,sp of the 1200V SiC planar MOSFET, compared leading IDM’s in the world, either planar or trench MOSFET’s, this work has the best result of Ron,sp 1.95mΩ·cm². The high driving current (Fig. 2), combined with suppressed resistance loading, indicates a proper Ni2Si Ohmic source-contact (Fig. 3). At drain-contact (not shown), damage-free layer is achieved by customized backside grinding and polishing. By using an optimized in-house SiC epitaxy process, we achieve stable CP yield >92% (Fig. 4) at enhanced stress >1400V. High efficiency of BPD conversion in buffer layer (Fig. 4 inset) and well-controlled retrograde doping profile (TCAD simulation shown in Fig. 5a) help suppress IDSS drain leakage current. On the other hand, the p-type dopant diffusivity near SiC surface was found to cause significant fluctuation of threshold voltage, Vth. TCAD model after careful calibration was then used to cope with Vth variation issue. Fig. 5b shows the SEM of the innovative structure compared with TCAD Fig. 5a on top. Fig. 6 reveals planarized surface at atomic scale after high-temperature ion implant activation using customized carbonized compound protection. The Ra 3.5Å surface roughness in channel region reduces thermally assisted current scattering at interface during device turning-on while keeping optimized channel electron mobility. Furthermore, interfacial quality between gate-dielectric and SiC is improved by eliminating carbon cluster formation and significantly enhance gate-dielectric lifetime, as shown in Fig. 7. Reduced trap-assisted tunneling further reduces IGSS gate leakage current. With the above-mentioned process knobs, the fully integrated SiC planar MOSFET of this work exhibits not only leading Ron,sp but also exceptionally good reliability. Fig. 8 benchmarks key device parameter shifts and variation after 175oC AEC-Q101 1khrs reliability testing. The key parameter shifts of this work are comparable or better than commercial SiC planar MOSFET products used in power inverters. In this work, reliable and manufacturable 1200V SiC planar MOSFET with leading-performance Ron,sp 1.95mΩ·cm²  is achieved. Device platform offers applications in automotive, various green energy systems, and other applications.

ABSTRACT. Recent studies have shown that the SiO2/SiC interface degrades when SiC power MOSFETs are subjected to positive bias temperature stress (PBTS) [1-4]. The generation of interface trap density (Dit) increases the threshold voltage (VT) and reduces the field-effect mobility (FE), eventually worsening the channel resistance. This work aims to clarify the underlying mechanism by analyzing the PBTS in MOSCAPs, utilizing SiO2 prepared through thermal and LPCVD oxidation, both with and without the nitric oxide post oxide annealing (NOPOA). Fig. 1 summarizes the MOSCAP parameters and the measurement setup of PBTS. Nitrogen areal density, [N], was obtained by XPS analysis where the SiO2 layer was removed using DHF before conducting an XPS spectral scan. The Dit profile and flat band voltage (VFB) are extracted by the “C-s” method [5]. Fig. 2a shows the VFB as a function of increasing oxide electric field (Eox), from which the field acceleration factor () is obtained by power-law fitting. It can be observed that devices with NOPOA exhibit higher  values than those without NO, regardless of the SiO2 growth method. The temperature-dependent time exponent (n) exhibits a similar trend (Fig. 2b), suggesting that the degradation mechanisms differ between MOSCAPs with and without NOPOA. Fig. 3a shows a statistical comparison of the effective oxide traps (Nox) and the integrated interface traps (Nit). Nox is extracted from the VFB before and after PBTS at Eox = 7 MV/cm for 1000 s. The NOPOA process not only reduces Nit but also mitigates the active oxide traps responsible for the VFB shift. Despite the improved Nox and Nit, initial after NOPOA, the interface quality experiences higher trap generation ratio (e.g., Nit/Nit, initial) after PBTS, as evident in Fig. 3b and Fig. 3c. Moreover, the degree of degradation shows a positive correlation with the nitrogen areal density at the SiO2/SiC interface. This reveals that the Nit generation under PBTS may predominantly originate from the NOPOA process. Fig. 3d confirms that Nit exhibits weak temperature dependence, with an activation energy (Ea) of 21 meV extracted from the Arrhenius plot. On the other hand, the degree of Nit shows a strong correlation with Eox for NO-treated MOSCAPs, whereas negligible interface degradation is observed in MOSCAPs without NOPOA (Fig. 4). The  values are extracted by applying power-law fitting to the error bars. The field acceleration factors of VFB (VFB) and Nit (Nit) are summarized in Fig. 5a, demonstrating their correlation with the nitrogen areal density at the SiO2/SiC interface. Fig. 5b shows the initial and stress C-V curves measured after 10 s of UV exposure. A UV light with a wavelength of 375 nm was selected, in which the gate and body were grounded during UV exposure. Electrons in the deep interface traps are emitted by UV, resulting in a larger hysteresis in the subsequent C-V bidirectional sweep [6]. The difference in the area under the curve is used to determine Nit. Nit increases from 1.91×1011 cm-2 to 3.17×1011 cm-2 after PBTS at Eox = 7 MV/cm, confirming the generation of interface traps. Fig 6 depicts the proposed energy band diagrams to explain the origin of interface degradation. It is speculated that a nitrogen-incorporated complex interfacial layer (IL), with a smaller bandgap than SiO2, forms during NOPOA. Under PBTS, the electrons gain sufficient energy to tunnel into the IL, where near-interface defects are generated from the energy released through the potential difference (Fig. 6b). Without NOPOA, and the observed VFB is dominated by electron trapping at near-interface oxide traps (NIOTs) [7, 8]. It should be noted that there is no significant difference in the degradation mechanisms between thermal and LPCVD oxides.

ABSTRACT. We have recently developed a 2-step H2/Ar annealing process that achieves a significant reduction in interface state density (Dit) and improvement in the channel mobility of MOSFETs, without depending on industry-standard nitridation process. In this process, CO2 and 3％-H2/Ar annealing are used as post deposition annealing (PDA), but the impact of each are not fully understood. In this study, MOS capacitors were fabricated by varying the temperature and gas atmosphere conditions for each PDA, and the changes in interface characteristics, insulation properties, and reliability were investigated. As a result, the Dit near the conduction band edge and the hole trap density near the valence band edge were effectively reduced by H2/Ar and CO2 annealing, respectively. In addition, the gate leakage current density of the 2-step H2/Ar sample was low compared to the NO sample at same oxide fields. Furthermore, the 2-step H2/Ar sample showed superior electron and hole injection resistances.

ABSTRACT. 4H - silicon carbide (SiC) stands out as a preeminent wide - bandgap semiconductor material. Its remarkable properties—high breakdown field strength, excellent thermal conductivity, and high carrier mobility—make it highly promising for high - temperature, high - frequency, and high - power electronic devices. The impurity level and defect density are crucial parameters for evaluating silicon carbide substrates. These two research directions respectively correspond to the performance and yield of silicon carbide substrates in industrial production. Since the physical vapor transport (PVT) method is a black-box growth method under high temperature and low pressure, it is difficult to conduct on-line monitoring. Therefore, we have carried out research work combining simulation and experiments, and have determined the distribution of dislocations [1] and impurities [2], as well as the influence of impurities on dislocations [3]. To explain the distribution of 4-fold symmetry BPDs in the grown crystal, 3D modeling of BPDs in 4H-SiC crystals grown by the PVT method has been performed. The results show that the adoption of 4-degree off-axis seed crystals that are widely used in the industry caused the distribution of 4-fold symmetry BPDs. Figure 1 shows the comparison of calculated BPD density and experimental BPD density. To study the evolution of temperature, C/Si ratio and nitrogen incorporation at the growth front as a function of crystal length, 2D global calculation has been performed. We considered gas exchange across the crucible and the crucible etching reaction, and illustrated their effects on the crystal growth rate, temperature, C/Si ratio, and N₂ distribution at the growth front. In figure 3 shows unprecedented agreement with experimental observations. The factors influencing crystal resistivity have been demonstrated. The nitrogen doping efficiency in 4H-SiC crystal growth through the PVT method has been proposed through computed and measured nitrogen concentrations. Based on the thermal stress distribution, the dislocation density distribution has been calculated. To enhance the accuracy of calculating the dislocations in n-type 4H- SiC, we introduced an effective stress of nitrogen and calculated the stress drop due to the nitrogen doping. Through the experimental comparison (Figure 3), we proposed an effective stress of 5 MPa, which is applicable to the calculation of the dislocation density of 4H-SiC at a certain doping concentration. This research lays a foundation for the regulation of impurities and defects in the growth of n-type 4H silicon carbide by the PVT method. In this presentation, a comprehensive study on impurities and dislocations will be presented, and some innovative machine learning methods will also be covered.

ABSTRACT. Silicon carbide (SiC), and notably the 4H polytype, has emerged in the power semiconductor market due to its excellent physical properties, such as wide bandgap and high electrical breakdown field, which make it ideal for high-power, high-frequency and high-temperature applications. Among the different crystallographic orientations of 4H-SiC, the {0001} plane has two distinct polar faces: the Si-face (silicon termination) and the C-face (carbon termination). Although the Si-face is currently the most widely used in industrial production and research, the C-face exhibits structural and chemical features making it of growing interest, especially regarding the epitaxial growth and performance of MOS (metal-oxide-semiconductor) structures [1, 2]. Numerous studies [3, 4] have shown that C-face allows for epitaxial layers with smoother surface morphology than Si-face and reduced propagation of basal plane dislocations (BPDs), with increased conversion to thread-edge dislocations (TEDs). However, the incorporation of impurities, particularly residual nitrogen (N), is less controllable on the C-face, as it is less affected by the C/Si ratio during growth under atmospheric pressure conditions. In addition, the quality of the metal-oxide-semiconductor (MOS) interface on the C-face has been shown to be generally lower than on the Si-face, despite the oxidation rate of the former being about an order of magnitude higher, reflecting greater chemical reactivity. These observations suggest that the C-face of SiC, while presenting critical issues in terms of doping and electronic interfaces, offers non-negligible advantages in terms of structural quality and possibilities for improved electronic mobility in MOS devices. In this context, a thorough understanding of epitaxial growth mechanisms, the physicochemical conditions that influence their morphology, and the interaction between surface and impurities is crucial for the development of new technological strategies to fully exploit the potential of the C-face in SiC-based devices. Homoepitaxial growth of n-type 4H-SiC layers was conducted on 150 mm polished epi-ready Si-face and C-face substrates, both oriented 4° off-axis, using a low-pressure, single-wafer hot-wall chemical vapor deposition (LP-CVD) system. The growth process was performed at a temperature exceeding 1600 °C, a total pressure of 3.0 kPa, and a C/Si ratio fixed at 1.05. The silicon and carbon sources consisted of silane (SiH₄), propane (C₃H₈), and ethylene (C₂H₄), while nitrogen (N₂) was introduced as the dopant to achieve n-type conductivity. Hydrogen (H₂) served as the carrier gas. The introduction of hydrogen chloride (HCl) was essential to suppress the formation of silicon droplets on the growing surface. The target specifications for the epitaxial layers − designed to meet the requirements of medium and high-voltage power devices − included a thickness of approximately 9.5 µm and a doping concentration of ~6 ×10¹⁶ cm⁻³. Under these fixed process conditions, six epitaxial runs were carried out: three on Si-face substrates and three on C-face substrates, enabling a direct comparison of doping behavior, uniformity and defectivity as a function of crystallographic polarity. The uniformity of thickness distribution and doping concentration of epilayers were measured by Fourier transform infrared spectrometry (FT-IR) and mercury-probe CV (Hg-CV). Physical defect characterization analysis was performed by optical inspection tools with and without photoluminescence (Candela and KLA-Altair, respectively) and the surface roughness was tested by atomic force microscopy (AFM). AFM analysis highlights that the Si-face epilayers show greater surface roughness (by about 80 nm) than the C-face epilayer under the same growth conditions. In particular, there is a significant step bunching in the SiC grown on Si-face substrates (Fig. 1). All the characterizations analysis done, will be shown during the conference. Although the epitaxial growth conditions are identical − including precursor fluxes, dopants and C/Si ratio − there is a significant difference in doping concentration between the C-face (carbon terminated) and Si-face (silicon terminated) of 4H-SiC. In particular, the layer grown on the C-face exhibits more than 25 times higher doping than that on the Si-face, exceeding the target concentration. This discrepancy is related to the higher chemical reactivity and different surface structure of the C-face, which makes the incorporation of nitrogen (N) much less controllable. Unlike the Si-face, where the C/Si ratio can effectively modulate dopant incorporation due to “site competition” between carbon and nitrogen, on the C-face this mechanism is poorly effective. Nitrogen incorporates more easily and nonselectively, regardless of the C/Si ratio. As a result, the C-face exhibits lower uniformity in the distribution of normalized doping relative to the target value, as shown on the left in Fig. 2. The profile associated with the C-face shows greater dispersion and irregularity than that of the Si-face, which instead displays a flatter and more controlled distribution. Therefore, although the C-face offers structural advantages such as a smoother surface and reduced defect propagation (data that will be discussed at the conference), the Si-face remains the preferred choice for applications that require high accuracy and uniformity in doping control.

ABSTRACT. The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and/or switching losses both for 150mm and 200mm wafers diameter. Recently proton implantation has revealed its capability to block stacking fault expansion. We have evidenced through material characterization and electrical measurements of 1200 V PIN diodes that bipolar degradation can be mitigated above 1000 A/cm². A strong robustness has been evidenced through UV induced stacking faults. Electrical results are showing no visible bipolar degradation after a 600sec-2250 A/cm² stress test, while the reference material is showing a ~500mV drift at the device rated current of 10A.

ABSTRACT. Silicon carbide (SiC) material has attracted much attention due to its excellent properties including a wide band gap, high thermal conductivity, high electric breakdown voltage, and a large saturated drift velocity for devices capable of operating under extreme conditions [1]. But the dislocations in SiC substrate could degrade the performance of power devices, especially the basal plane dislocations (BPDs) intruduced by the unbefitting growth temperature field distribution. Although most (>90%) BPDs in the substrate are converted to harmless threading edge dislocations (TEDs) within a few micrometers of an initial epitaxial layer without any special treatment. However, a perfect BPD in SiC is dissociated into two partial dislocations, and a single Shockley-type stacking fault is created between the two partials [2]. Because the BPD has an impact on the generation of stacking faults during the epitaxy process, it leads to a drift in the forward voltage drop in bipolar device [3]. In this study, the 8 inches 4° off-axis N-type 4H-SiC crystal with low BPDs density was prepared by the PVT method with the improved design. Compared with the traditional design, the seed holder and guide cylinder both are single poly-crystalline SiC materials coated with thin tantalum carbide film of 10μm [as shown in Fig.1(b)]. After growth, the selective etching to detect BPD defects in SiC crystal was completed by submerging the sample in molten KOH. Images of the etched surface and automated etch feature counting were accomplished by using a FabXLab’s optical microscope with automatic image recognition (As shown in Fig. 2). From Fig. 2, it can be observed that the BPD density in the crystal grown by the traditional design is as high as 1000 ea/cm2. And it shows the characteristics of high BPDs density at the edge of SiC single crystal and low BPDs density in the center. After using the improved design, the overall BPDs density in the crystal is low to 78 ea/cm2, and the density distribution deviation is small. The main reason is that the seed holder and guide cylinder in the traditional design are both made of graphite, and the thermal expansion coefficient of graphite material is quite different from that of SiC crystal. And above 2000℃, due to the large thermal radiation emissivity of graphite (0.7-0.8) and good thermal conductivity, it is easy to form SiC polycrystalline parasitic on the inner wall of the guide cylinder. As a result, the temperature gradient change (∂²T/∂x²) at the edge of the SiC crystal fluctuates too much, so the BPDs density in the SiC crystal shows the characteristics of high at the edge of SiC crystal and low in the center. In the improved design, the SiC single or poly-crystalline seed holder and guide cylinder are used, the thermal expansion coefficient is consistent with that of SiC single crystal, and the TaC coating has a small thermal radiation emissivity (0.3), which is not easy for parasitic SiC polycrystal to nucleate and grow. Therefore, the BPDs density in the overall SiC crystal is low and the distribution uniformity is high.

ABSTRACT. Compared to conventional quartz glass, silicon carbide (SiC) crystals offer superior properties such as a higher refractive index, greater thermal conductivity, higher melting point, and increased hardness. These attributes make SiC a promising candidate for next-generation AR optical glass applications. [1-3]. Low optical loss is a critical performance metric for SiC crystal lenses. Si-rich and C-rich regions in SiC crystals with a non-stoichiometric composition can introduce defects (Si or C vacancies) and additional defect-related energy levels, which enhance optical absorption and increase optical loss [4-5]. Therefore, it is necessary to prepare SiC crystals with a stoichiometric ratio to the greatest extent possible. This paper develops a reaction model for SiC crystal growth via the high-temperature chemical vapor deposition process using the COMSOL commercial software. The reaction model for SiC crystal growth includes both the homogeneous gas-phase reaction and the gas-solid heterogeneous reaction. The main chemical reaction equations used in the model are shown in Tables I, with the reaction equations and thermodynamic data taken from the literature [6-8]. Furthermore, by adjusting the flow ratio of silane (SiH₄) and propane (C₃H₈) precursors in the gas inlet, the C to Si atomic ratio at the edge of the seed crystal is effectively adjusted, thereby regulating the growth ratio of Si(s) and C(s) atoms on the seed crystal surface. To reduce intrinsic defects in the SiC crystal and achieve stoichiometry, the flow of the two precursor gases is carefully adjusted. The results show that at a reaction temperature of 2473 K, a pressure of 4 kPa, a H₂ flow rate of 0.8 m/s, and initial H2 concentration of 1.44 mol/m³, the high temperature pyrolysis of C₃H₈ primarily produces C₂H₂, while SiH₄ primarily produces gaseous Si. The flow field and C2H2 concentration distribution inside the furnace chamber are shown in Figure 1.The intermediate gas adsorbs onto the surface of SiC seed crystal and gradually transform into solid Si(s) and C(s) atoms. The results also show that when the C/Si atomic ratio in the precursor gas is 0.965, the gaseous C/Si ratio near the seed crystal (5 mm away from the seed surface) increases to approximately 0.975, resulting in an almost 1:1 incorporation ratio of Si(s) to C(s) atoms on the seed crystal surface, as shown in Figure 2. This study successfully establishes a SiC crystal growth model for the high-temperature chemical vapor deposition process. It also clarifies the quantitative relationships among the precursor gases, the intermediate species near the seed crystal, and the resulting SiC components. This study also provides directional guidance for subsequent experimental preparation of stoichiometric SiC crystals.

[1] C. Zhe, J. Liang, K. Kawamura, et al. Nat. Commun. 13, 7201 (2022). [2] S. Wang, M. Zhang, G. Wang, et al. Laser & Photonics Rev. 5, 831 (2013). [3] Information on https://www.eetimes.com/from-the-editors-desk-sic-ar-glasses-to-fast-ai-training/. [4] S. A. Tarasenko, A.V. Poshakinskiy, D. Simin, et al. Phys. Status. Solidi. A. 1, 255 (2018). [5] L. Peng, M. Lei, W Ma, et al. Cryst. Growth Des. 7, 5173 (2023). [6] P. M. Lofgren, W. Ji, C. Hallin, et al. J. Electrochem. Soc. 147, 164 (2000). [7] M. D. Allendorf, J. K. Robert. J. Electrochem. Soc. 138, 841 (1991). [8] S. I. Nishizawa, M. Pons. Chem. Vap. Depos. 12, 516 (2006).

ABSTRACT. In PVT growth of SiC crystals, the proper choice of the SiC source material plays an important role because the grain size distribution and the effective packing density have a strong impact on the effective heat conductivity of the SiC source and therefore on the temperature field inside the growth cell [1]. Additionally, the effective surface area and the SiC polytype influence the gas phase composition and C/Si ratio. The latter being related to the different formation energy and surface energies of the various SiC polytypes [2]. Although SiC crystal growers hardly comment on their choice of the SiC powder source, often grain sizes above 500µm are applied exhibiting a comparatively larger heat conductivity and lower effective surface of the SiC powder assembly [3]. Concerning the SiC source polytype, by trend the 6H-SiC polytype from direct Si + C synthesis or from purified Acheson material plays an important role in the global market. In addition, 3C-SiC stemming from a chemical vapor deposition synthesis is also applied in PVT growth. In this work we have studied the application of a new type of fine grain 3C-SiC powder source during PVT growth (aggregates of ca. 150 µm, single particle size of ca. 10 µm, The Yellow SiC Company GmbH). In conjunction with the new patented [4] development of the 3C SiC powder source, small batches of the material have been used in a 75mm PVT system consisting of an in-situ 2D/3D computed tomography X-ray visualization tool. [5]. PVT growth was carried out in a standard PVT configuration for 120 h at the growth temperature ca. 2050°C (crucible top) using nitrogen gas for n-type doping. The average growth rate was 125 µm/h. No special efforts were made to adapt the growth process to the special properties of the newly applied SiC source. Interestingly, although the SiC source deviates in its morphologic properties from “unofficial” specks of many crystal growers in the SiC PVT field, a very high 4H-SiC polytype stability was observed during PVT growth. The optical transmission image in figure 1 (orange color) and the Raman spectrum in figure 3 underline this finding quantitatively. The post growth analysis of the growth step structure at the crystal cap (figure 2) indicate ideal conditions for 4H-SiC growth stability as they have been documented in literature for a high C/S ratio in the gas phase and nitrogen doping (see e.g. [6]). The smooth growth interface exhibits macro-steps with a varying distance of 50 to 500 µm (macro-step height of ca. 3 – 10 (± 0.5) µm). Because of the asymmetric motion kinetics of the steps due to nitrogen doping [7, 8] the probability of unintentional polytype changes is reduced and 4H-SiC growth is stabilized. The charge carrier concentration determined by Raman spectroscopy lies at 1.9 (± 0.1) *1018 cm-3 which could be easily increased during growth by a higher nitrogen gas stream. Noteworthy, despite the cracking observed in the crystal rim area (see wafer pieces in figure 1), the residual stress determined by Raman spectroscopy lies in the low range of ca. 25 (+/- 10) MPa. The latter is reasonably low value for a 75 mm SiC crystal grown in a kind of squeezed growth cell. Concerning the source material purity: Transition metal impurities lie well below ppm-level. The shallow acceptors aluminum and boron lie in the low ppm range. The nitrogen content of the applied batch was in the 100-ppm range. Please note: The Yellow SiC Company GmbH already demonstrated Al, B and N levels below 1 ppm (GDMS data are available on request) for the anticipated crystal growth demonstration of n-type 4H-SiC, the elevated nitrogen concentration was no drawback. The packing density of the SiC source material inside the growth cell was ca. 45 %, which is currently further increased to the widely desired value between 50 and 60%. In summary we have demonstrated the stable growth of 4H-SiC in a standard PVT system using a new 3C-SiC source material which deviates in its morphologic properties significantly from more standard SiC source materials. For state-of-the-art SiC bulk growth technology this implies that a much broader variety of SiC source materials can be used to foster the envisioned market growth of SiC power electronics.

[1] M. Arzig, M. Salamon, N. Uhlmann, B. A. Johansen, P. J. Wellmann, Mat.Sci.For. 924, 245 (2018) [2] Y. M. TairovV. F. Tsvetkov, Progress in Crystal Growth Charact., 7, 111 (1983) [3] P. J. Wellmann, Semicond. Sci. Technol., 33, 103001 (21pp) (2018) [4] S. Greulich-Weber, "The Yellow SiC Holding GmbH, Device and Method for the production of silicon carbide," 2023. [5] P. Wellmann, G. Neubauer, L. Fahlbusch, M. Salamon, N. Uhlmann, Crystal Research and Technology, 50, 1, 2 (2015) [6] M. Arzig, U. Künecke, M. Salamon, N. Uhlmann, P. J. Wellmann, Journal of Crystal Growth, 576, 126361 (2021) [7] N. Ohtani, M. Katsuno, T. Aigo, T. Fujimoto, H. Tsuge, H. Yashiro, M. Kanaya, Journal of Crystal Growth, 210, 4, 613 (2000) [8] N. Ohtani, M. Katsuno, T. Aigo, H. Yashiro, M. Kanaya, Mat.Sci.For. 338, 379 (2000)

ABSTRACT. Simulations of SiC crystal growth on an atomistic scale were in the past most commonly done with Monte Carlo (MC) based methods, such as kinetic lattice MC or kinetic super lattice MC. These however suffer from the fact that they have to use predefined deposition sites and reaction rates, making it difficult to realistically simulate defects, such as dislocations or stacking faults. With the rise of accurate interatomic potentials, also MD simulations of SiC crystal growth have been conducted. These however have the shortcoming of too small simulation times, therefore needing to use growth rates which are ~10^8 times larger than real life SiC growth rates. A recently developed method, called the Minimal energy atomic deposition (MEAD) [1], combines both MD and MC and tries to seamlessly overcome both of these simulation hurdles. The MEAD algorithm works by first scanning the surface of the substrate for deposition sites with low potential energy (Fig.1a). Then these deposition sites are populated by either Si or C atoms. After this deposition step temperature is applied to the system by using time stamped force biased MC (tfMC). This allows the system to get into equilibrium and for the deposited atoms to reach their minimum energy position at the required temperature. This three-step process of scanning the surface for potential depositions sites, then populating the lowest ones and applying temperature to the system is then repeated until the sufficient growth has been simulated.

In this talk, we will present our effort of applying the MEAD simulation method on the SiC system. We apply different temperatures ranging from 2300 to 2500 K and identify the polytypes grown (Fig.1b) using this method on both the C-terminated and Si-terminated 4H SiC surface. In addition, defects, vacancies and add-atoms occurring during growth will be investigated, as well as growth on stepped surfaces. We also compare different interatomic potentials in terms of their predicted SiC growth structure. In this way we hope to gain new insights in the atomistic mechanisms governing the growth process of SiC.

Acknowledgement The authors gratefully acknowledge the financial support provided by the Christian Doppler Forschungsgesellschaft (CDG) and the company partner EEMCO GmbH.

References [1] Shivraj Karewar, Germain Clavier, Marc G.D. Geers , Olaf van der Sluis and Johan P.M. Hoefnagels, Surface & Coatings Technology, 494, 2, 131462 (2024).

ABSTRACT. Silicon Carbide (4H-SiC) has outstanding properties for applications in energy efficient power electronics and has been maturing with regards to material quality and device processing technology. Now, the SiC processing costs need to be reduced and the efficiency with regards to energy and resource consumption needs to be improved. For these reasons, we are testing alternative precursors such as methane (CH4) and tetrachlorosilane (SiCl4). These alternatives may enable higher growth rates, better material quality and lower processing costs. Additionally, methane can act as an isotopically enriched precursor for growth of epilayers with a controlled 12C isotope concentration different from the isotope ratio found in the natural isotope mixture, which could be an enabler for SiC-based quantum technology due to the control of the nuclear spin bath concentration. SiC is a very promising candidate for quantum applications due to its silicon vacancy (VSi), which acts as a color center [1] and its mature processing technology. Depending on the desired quantum application, specific isotope concentrations are required, such as a total concentration of 1.0 to 1.5 % of 13C and 29Si for nuclear spin qubits addressable as quantum memories [2,3]. Hence, the 13C and 29Si concentrations need to be reduced by using isotopically enriched precursors during epitaxial growth. In the carbon case, methane (CH4) can be purchased with a nominal 12C concentration of 99.99 %. This paper investigates the epitaxial growth using methane as a precursor and the characterization of the grown epilayers. For this study, conventional n-type 4H-SiC substrates with a diameter of 150 mm from international vendors have been used for epitaxial growth studies in AIXTRON planetary reactors, which are operated in our joint development lab. The standard growth process was adapted to utilize methane as carbon precursor, while trichlorosilane (TCS) was further used as (standard) silicon precursor. Once a suitable epitaxial growth process was developed, isotopically purified methane with 99.99 % 12C and ultra-low nitrogen concentration (< 3 ppm) was employed. The epilayers produced from this epigrowth study have been characterized with regards to epilayer thickness, doping concentrations and defects by FTIR, capacitance-voltage (CV) and UV excited photoluminescence imaging (UVPL). The resulting isotope concentration was determined by secondary ion mass spectroscopy (SIMS). We have grown epilayers with 12 µm thickness up to 26.8 µm thickness with a thickness uniformity of 1.5 % and 2.3 % /mean, respectively. A growth rate up to 25 µm/h was realized with methane precursor, which is quite comparable to the conventional ethene precursor. Nominally undoped as well as intentionally nitrogen doped epitaxial growth runs were performed and showed a fair and low background doping concentration and an intentional n-type doping of 7.3x1015 cm-3 with 2.6 % /mean uniformity. Defect types and densities were quite comparable for methane and ethene based processes with a killer defect density below 1 cm-2 as shown in Figure 1. After process development for methane precursor, first experiments have been done with isotopically purified methane. SIMS measurements confirmed a 12C concentration of 99.96 % in the epilayer grown with the isotopically enriched precursor of 99.99 % 12C, i.e. the 12C concentration in the epilayer is almost as high as the 12C concentration in the precursor. Hence, there is almost no carbon exchange between the growth atmosphere and the parasitic SiC deposition on the reactor components. As a result, the 12C concentration in the epilayer can be precisely controlled by adjusting the 12C concentration of the precursor (mixing) as shown in Figure 2. We will discuss the results of the methane based epitaxial growth study in detail and show recent results using tetrachlorosilane as an alternative silicon precursor.

ABSTRACT. Silicon carbide (SiC) has attracted considerable interest as a next-generation power-semiconductor substrate because of its exceptional chemical inertness, high hardness, and superior thermal conductivity. However, in conventional chemical–mechanical polishing (CMP), the extreme hardness and chemical stability of SiC inevitably result in low material removal rates and prolonged processing times [1]. Mechanical abrasion by slurry and polishing pads struggles to eliminate micro-defects on the surface completely, necessitating multi-stage, extended-duration treatments. To overcome these limitations, this study investigates a two-step electrochemical–mechanical polishing (ECMP) process that decouples the oxidation and mechanical-polishing stages, allowing each to be independently optimized [2]. In the first stage, nonreactive regions of 15 ㎜ × 15 ㎜, epi-ready SiC wafers were masked with polyimide (PI) film, and anodic oxidation was performed in 0.1 M NaCl at pH 2.02, 4.10, 6.19, and 9.20. In the second stage, the oxidized surfaces were polished using a ceria slurry in a standard CMP tool, enabling precise, separate analysis of oxide-film growth and surface-planarization performance. In all experiments, SiC wafers were used as the anode and graphite as the cathode. Phosphoric acid, citric acid, and sodium hydroxide were employed to adjust the electrolyte pH. Oxidation times of 20, 30, and 40 seconds were applied to characterize the time dependence of oxide-film formation, and CMP was conducted until the oxidized layer was fully removed. Oxide-film thickness and any remaining oxide were measured by α-step surface profilometry, and arithmetic average surface roughness (Ra) was evaluated via optical profilometry. After anodization, the average oxide-film thicknesses were 475.9 ㎚ at pH 2.02, 456.6 ㎚ at pH 4.10, 486.2 ㎚ at pH 6.19, and 466.6 ㎚ at pH 9.20. The greatest film thickness under near-neutral pH 6.19 indicates that electrochemical oxidation is most active under conditions close to neutral rather than in strongly acidic or alkaline enviro㎚ents. Surface-roughness measurements of the as-oxidized films revealed the highest Ra at pH 4.10 (177.1 ㎚) and lower values at pH 2.02 (162.3 ㎚), pH 6.19 (133.5 ㎚), and pH 9.20 (133.9 ㎚). This suggests that the smoother oxide films formed at pH 6.19 and pH 9.20 facilitate more efficient mechanical polishing in the subsequent CMP step. During CMP, net material removal (excluding the oxide film) averaged 262.9 ㎚ at pH 2.02, 262.6 ㎚ at pH 4.10, 235.8 ㎚ at pH 6.19, and 237.5 ㎚ at pH 9.20. When normalized by polishing time, the highest removal rate was observed at pH 4.10 (79.8 ㎚/min), whereas the lowest was at pH 9.20 (44.7 ㎚/min), reflecting the influence of oxide-film roughness on mechanical-abrasion efficiency. Final surface roughness after CMP was lowest at pH 9.20 (Ra = 28.7 ㎚), but this was accompanied by a marked decrease in removal rate. In contrast, pH 6.19 achieved a balanced performance, reducing Ra from 133.5 ㎚ to 36.6 ㎚ while maintaining a removal rate of 64.9 ㎚/min. The conditions at pH 2.02 and pH 4.10 yielded higher final roughness values (48.6 ㎚ and 53.1 ㎚, respectively), consistent with their rougher oxide films and suboptimal polishing regimes. Although pH 4.10 offers the fastest removal rate and pH 9.20 delivers the smoothest surface, the pH 6.19 condition provides the optimal compromise among oxide-film thickness, removal efficiency, and surface planarity. The two-step ECMP process thus overcomes the throughput and control limitations of conventional, simultaneous ECMP. Future work will refine electrochemical parameters such as electrolyte concentration and current density and will scale the process to SiC wafers larger than 6 inches to assess its industrial applicability.

ABSTRACT. Today, the semiconductor industry demands continuous enhancement of electronic device performance, not only at the level of individual components but across the entire system — from the substrate to the metallization, frame, and final module. Metallization have always played a critical role as current collectors, and their structure must be constantly optimized and tailored to meet the requirements of specific applications. With the advent of silicon carbide (SiC) devices, this need becomes even more pressing due to the high current densities these devices are subjected to. Furthermore, in certain applications — such as those requiring transparent yet highly efficient current collectors — it is essential to rethink metallization strategies. This necessitates the development of nanoscale solutions that minimize physical dimensions without compromising electrical or thermal performance. In this context, the use of nanomaterials represents a promising path toward meeting these advanced requirements. We have conducted systematic studies on interface engineering aimed at enhancing device performance, utilizing molybdenum-based metallization directly deposited on 4H-SiC substrates. The thermal stability of these interfaces has been further improved through the development of tailored interfaces, combining CVD-grown graphene with the controlled formation of molybdenum silicide. The study began with the investigation of molybdenum layer growth on both planar films and nanostructured surfaces, through a systematic analysis of spatially confined contacts defined via electron beam lithography. This approach enabled a comparative understanding of the mechanisms occurring at different dimensional scales, particularly highlighting the processes involved in graphene formation and molybdenum silicide development on ultra-thin layers. These engineered interfaces have shown strong potential for application in advanced metallic contacts, including for large-area SiC-based radiation sensors designed to eliminate dead zones. The substrate material used in this study was 4H-SiC. Molybdenum was deposited via sputtering, with thicknesses ranging from a few nanometers to several tens of nanometers. Graphene growth was achieved using a CVD process performed in an AIXTRON Black Magic system, with CH₄ used as the carbon precursor. Figure 1 shows the EELS analysis of the complete system, comprising the 4H-SiC substrate, the molybdenum layer, and the graphene overlayer. The spectra display the characteristic M, L, and K edges associated with Molybdenum, Silicon, and Carbon, respectively. Figure 2 presents cross-sectional TEM images of the material stack, ranging from an overview of the full system to a detailed view of the surface graphene layers

ABSTRACT. The present contribution deals with the optimization of homoepitaxial growth through Chemica Vapour Deposition (CVD) on on-axis alpha-SiC substrates and the influence of vanadium doping on the optimized process.

ABSTRACT. Controlling defect formation during SiC crystal growth remains one of the central challenges in enabling high-yield, high-performance power electronic devices [1]. The interplay between substrate off-cut orientation, surface step morphology, and high-temperature conditions in Physical Vapor Transport (PVT) growth significantly affects the structural integrity of 4H-SiC boules [2]. While bulk growth technologies are advanced, an atomistic understanding of how these factors collectively affect nucleation and growth, and defect generation remains limited [3] because of very high PVT temperatures (~1500 – 2300°C) and lack of in situ atomic imaging [4]. Addressing this gap requires, physics-based simulations capable of resolving atomic-scale processes under extreme thermal conditions. This study first evaluates the thermodynamic stability of surface step configurations using ab initio calculations, followed by atomistic simulations of SiC deposition on 4H-SiC (0001) substrates with a 4° off-axis orientation. The substrate is modeled by tilting the [0001] plane toward the [112 ̅0] axis, to introduce periodic step structures. The study aims to uncover the fundamental processes governing crystal nucleation and growth, defect evolution, and the impact of temperature and substrate geometry on PVT growth. Results indicate that smooth step edges are thermally more stable than sharp step edges near the PVT growth temperature of ~2400 K. During initial deposition, sharp step edges reconstruct into smoother forms, while smooth steps retain their geometry. Depositing silicon and carbon atoms leads predominantly to a 2H-SiC polytype with localized 4H-SiC [Fig. 1(a)]. Notably, nucleation at the smooth step edges initiates the 4H-SiC polytype, suggesting that a threading edge dislocation (TED) and an existing step structure are essential to promote stable, continuous 4H-SiC crystal growth. Dislocation analysis in Fig. 1(b) reveal the presence of basal plane dislocations (BPD) at the surface which evolve into TEDs as the growth proceeds. Subsequent simulations with C:Si molecular precursors at a 1:1 ratio were focused on the smooth step geometry given its high thermal stability. As shown in Fig. 2, these deposition conditions result in a mixture of SiC polytypes including 2H, 4H, 6H, and 3C polytypes, while an excess of carbon promotes the formation of amorphous surface layers [Fig. 2(a)]. The corresponding dislocation analysis [Fig. 2(b)] qualitatively indicates a higher density of BPDs and TSDs compared to Fig. 1(b). The current study suggests that the step morphology and precursor composition critically influence polytype selection, defect formation, and structural order during early-stage SiC crystal growth. These findings underscore the importance of engineering surface steps and stoichiometry to promote stable 4H-SiC formation and minimize dislocation-driven degradation in the PVT growth process. Ongoing model development efforts aim to extend the current framework to support sustained 4H-SiC crystal growth under realistic PVT conditions.

[1] A.A. Lebedev, and V. E. Chelnokov, Semiconductors 33, 999–1001 (1999). [2] H. Tsuchida, I. Kamata, T. Miyazawa, M. Ito, X. Zhang, and M. Nagano, Mater. Sci. Semicond. Process. 78, 2-12 (2018). [3] B. Raghothamachar and M. Dudley, in Wide Bandgap Semiconductors for Power Electronics: Materials, Devices, Applications (P. Wellmann, N. Ohtani, R. Rupp, eds.) pp 169-197, 2022. [4] K. Wu, Q. Mei, H. Liu, S. Zhou, B. Gao, C. Li, S. Liu, L. Wan, Crystals. 13, 715 2023.

ABSTRACT. Presence of porous graphite elements (graphite crucible and felt insulation) in the PVT furnace is crucial for numerous physical chemical processes essential for SiC crystal growth. Permeability of these elements under certain rates of mass production/consumption in the hot zone controls one of the most important parameters of the PVT process - the pressure inside the crucible. Moreover, Si-C vapor transport through the graphite elements is not limited to Darcy diffusion of gaseous species through the porous medium. This process is entangled with the chemical reactions on the surface of graphite grains and fibers, which can result in graphite etching and SiC deposition. At the same time, the permeability of the porous elements is instrumental for the nitrogen delivery to the hot zone where it is incorporated into the growing crystal. The most common approach to the modeling of PVT systems includes the simulations of temperature distribution in the entire growth chamber and the heating elements, however, modeling of the mass transport and chemical processes is confined to the interior of the crucible. Here we present an alternative approach, namely, a direct modeling of the heat and mass transport in the entire growth chamber including the crucible itself and thermal insulations. It enables a direct simulation of the pressure that would establish inside the crucible as the balance between the release of the gas species in the powder charge and at the reactive surfaces of the crucible, their consumption, and losses through the porous graphite crucible and felt insulation. Fig. 1 shows the schematic view of the furnace with specification of the growth setup materials and the flow pattern in the reactor chamber, crucible interior, and porous graphite elements. The results obtained with VR PVT SiC software [1] include percolation of the gas species through the porous elements, chemical processes inside the porous media, and the crystal growth itself. Along with the modeling of the active species transport (Si Si2C, and SiC2), we also study the transport of nitrogen, which is supplied with the argon through the ring-shaped inlet located at the furnace bottom. The results demonstrate nitrogen infiltration from the reactor chamber through the graphite porous elements into the crucible and its distribution inside the crucible cavity. Nitrogen concentration in the growing SiC crystal is calculated using the model of dopant incorporation implemented into the software, which is based on local parameters of the vapor phase and local temperature. Fig. 2 presents distributions of the partial pressures of SiC2 and N2 at the beginning of the long-term SiC growth. In the areas with the highest intensity of the source evaporation, which are also the hottest areas, concentrations of the active species Si Si2C, and SiC2 are high, and nitrogen is diluted with the released active species Si, Si2C, and SiC2. Resulting profile of concentration of nitrogen atoms in the growing crystal as a function of radius is presented in Fig. 3. The proposed approach enables investigation of sensitivity of different growth aspects to the properties of the porous elements of the furnace. It also unlocks potential for investigation of the evolution of the porous elements during the long-term growth and the effect these changes might have on the crystal quality and lifetime of the hot zone parts.

ABSTRACT. The next generation of wireless infrastructure will depend on wide bandgap semiconductors such as SiC and GaN due to their superior properties: large bandgap, high thermal conductivity, and high breakdown field. [1,2] In device industry using SiC wafers, the enlargement of SiC wafer diameter is critically required to improve economic viability and production efficiency. [3,4] Accordingly, intensive research efforts are currently focused on developing high-quality 8-inch SiC crystal ingots, with particular emphasis on eliminating internal polycrystalline inclusions. In particular, the stability of the seed crystal during the initial growth stage is a crucial prerequisite for achieving effective and consistent crystal growth In this study, we investigated the effect of the heating ramp rates and porosity of source powder on the growth of 8-inch 4H-SiC crystals. These factors can influence could damage to the seed crystal at the initial growth stage and even the crystal quality of the final crystal. Prolonged thermal exposure at low ramp rate give rise to surface degradation and detachment of the seed crystal at initial growth stage. In contrast, fast ramp rate can induce steep thermal gradients which increased thermal stress differences between the seed and the seed holder, resulting in frequent crack and detachment of seed crystal.[5,6] To solve these problems, the different porosity of the SiC powder was employed to find improved transport channels of source gas species under proper heating ramp rates, thereby trying to stabilize the flow of sublimated gas species during the initial growth stage. Fig. 1 (a) and (b) respectively exhibited the schematic diagram of the experimental setup and the relationship between seed loss-induced damage width (mm) and heating ramp rate (°C/min) during the initial stage of crystal growth. It is clear that ramp rates of 3~5C/min can effectively decrease the damage width of seed crystal. Fig. 2(a) and (b) present the schematic diagram of the channel distributions for gas flow at low/ high porosity of SiC source powder part and a plot of the damage width (mm) as a function of the gas flow channel of the SiC source powder, respectively. The damage width of seed crystal was obviously suppressed at high gas supply channels (high porosity) of SiC source powder. Based on the simulation result, actual crystal growth employing two type of configurations (different ramp rates and porosity of SiC powder) was conducted using PVT (physical vapor transport) method. Fig. 3 exhibits optical images (left half-plane) and UVF images (right half-plane) of SiC ingots obtained by low gas flow (a) and high gas flow (b) in SiC source powder, respectively. Due to minimized seed crystal loss, SiC ingot grown under high gas flow channels indicates the high quality of the edge region and no polycrystalline compared with that of grown under low gas flow channels. Defect density at the top (near facet region) and bottom (near seed) of the SiC crystal grown under high gas flow after KOH etching was investigated and shown in Table 1. Since densities of TSD and BPD are both below 500 cm-2 and 1,000 cm-2, indicating a high crystalline quality. The distribution of defects such as micropipe, inclusion, and stacking fault from the bottom/top of the SiC ingot was analyzed (Candela, KLA Corporation).

ABSTRACT. Physical vapor transport (PVT) is the dominant method for silicon carbide (SiC) single crystals growth, and its mastery is key for producing large (diameter 200 mm and beyond) high-quality ingots. Despite its widespread use, challenges remain, notably with the optimization of the temperature distribution affecting the growth rate and crystal quality. A non-ideal design of the temperature field and temperature evolution can cause thermal stress and dislocation formation. Direct observation is not possible since the process operates at extreme temperatures in a semi-closed system. Therefore, numerical modeling is essential for understanding and optimizing SiC bulk crystal growth. The thermal field is controlled by several factors that need to be incorporated precisely in the simulation to obtain a high-fidelity thermal field. In our previous work [1], a machine learning algorithm is used to calibrate the thermal material properties of the PVT simulation on experimental data. However, the crystal growth rate and shape depend not only on the temperature distribution but also on mass transport and chemical reactions [2]. In our previous work [3], we utilized the Hertz-Knudsen model at the source and seed surfaces without allowing for deposition or etching on the other surfaces. It has been observed that the graphite crucible wall plays a crucial role in SiC crystal growth as it can act as a carbon source [4]. It is also found that the SiC powder source and growing crystal participate in the carbon (C) exchange with the provision of various species of gas molecules [5]. Numerical modeling results concerning the heterogeneous reaction at the graphite wall have been presented in [2]. However, the SiC deposition reaction was not considered. Recently, L. Xuan [6] numerically predicted the effect of crucible etching on the growth rate while neglecting the deposition of SiC on the graphite walls. To the author's knowledge, none of the previous studies conducted so far have allowed deposition and etching to occur simultaneously. In this contribution, COMSOL multi-physics simulations are presented, coupling heat transfer and mass transport equations. To demonstrate the growth process, we employ a physical growth model and considerations for chemical reactions, vapor species transport, and the kinetics of etching and deposition. Fig.1 shows the partial pressure of 〖SiC〗_2, P_(〖SiC〗_2 ) along the guide wall together with the limiting pressure levels for deposition P_dep or etching P_etch, the difference indicating the driving force for the respective reaction. The plot reveals that SiC deposition is most favorable in the central parts of the guide while etching becomes increasingly more favorable in the upper parts. We analyze how both processes occur simultaneously, discussing the respective molecular fluxes, gas-surface reactions, SiC crystal growth and graphite consumption everywhere inside the growth chamber. We extend this investigation by consideration of different temperature fields and crucible geometries to illustrate how different boule shapes and growth rates can be realized. We also compare thermodynamic databases and different levels of complexity of molecular species. Our approach provides improved insight into SiC crystal growth and generates computational data that can be closely compared to experimental characterization of the crucible and boule after the growth process. Finally, the implications of our results for targeted improvements of the crystal growth process will be discussed.

ABSTRACT. Silicon carbide (SiC) is regarded as one of the most promising semiconductor material for high-power and high-frequency electronic devices due to its outstanding physical and electrical properties, including a wide bandgap, high breakdown voltage, excellent thermal conductivity, and high electron mobility. In particular, 4H-SiC substrates are now commonly used as core materials for power semiconductor devices, with a steadily increasing demand in high-power applications such as high-speed computing and electric vehicles. [1-2] However, the manufacturing process for large-area SiC substrates remains complex and costly, this has led to the development of strategies aimed at improving the process by reducing polycrystalline formation, improving crystal quality, minimizing kerf loss during wafering, and increasing the evaporation efficiency of SiC source material [3-4]. In the growth of large-diameter n-type 4H-SiC single crystals, the thermal stability of the seed crystal and the achievement of stable thermal environment in the growth reactor are crucial for ensuring the final quality of the crystal [5]. In this study, we investigated how the diameter of the inner guide tube near the seed crystal and heating ramp rates affect the growth of 8-inch SiC single crystals using the physical vapor transport (PVT) method. We focus on the impact of these factors on both crystal quality and potential damage of the seed crystal. Structural and thermal environment optimization at the initial growth stage was throughly investigated to minimize damage of seed crystal and reduce the generation of initial defects. Fig. 1 (a) illustrates the schematic diagram of the experimental setup configuration related to the hot-zone. Additonally, Fig. 1 (b) presents a plot of the damage width (DW, in mm) of the seed crystal as a function of the distance (D, in mm) between the inner guide tube and the seed crystal. The results indicate that the damage to the seed crystal can be reduced when the distance (D) is approximately 8 mm. When the diameter of the inner guide tube was too close to the outer part of the seed crystal, it can cause stagnation source gas flow and creat a non-uniform thermal environment in the region surrounding the seed crystal. This results in localized thermal stress and mechanical damage to the growing crystal. In contrast, the diameter of the inner guide tube was excessively large measuring over 8mm, this led to deteoration of thermal stability near the seed crystal region during the initial growth stage, which in turn increased the generation of defects. Fig. 2 (a) denots a schematic diagram of the experimental setup for hot-zone, along with the distribution of the thermal field based on various heating ramp rates. Fig. 2 (b) displays a plot of the damage width (DW) of the seed crystal as a function of the ramp rate (S, °C/min), which varies with the distance between the inner guide tube and the seed crystal. The curvature of the polynomial fitting curve (R2) indicates that for large distance (R2 = 0.86) between the inner guide tube and the seed crystal, the curve is less steep compared to short distances (R2 = 0.94). This suggests that the ramp rate of 3 to 6 °C/min is crucial in minimizaing the damage width of the seed crystal during the initial growth stage. Consequently, a relatively fast ramp rate leads to quicker stablization of the thermal gradient between the seed crystal and the source powder. This improvement enhances the seed adhesion at the initial growth stage and effectively reduces both seed detachment and the formation of microcracks. Fig. 3 (a) and (b) displays optical images of 8-inch SiC ingot grown under optimized growth conditions and an 8-inch SiC wafer after the wafering process, respectively. The defect density (Fig. 3(c)) in five selected regions as shown in Fig. 3 (b), was evaluated after KOH etching. The micropipe density (MPD), threading screw dislocation (TSD), and basal plane dislocation (BPD) densities were evaluated to be less than 1/cm², 500/cm², and 1,000/cm², respectively. These result indicate that the precise adjustment of the inner guide tube diameter is critical for minimaizing the mechanical damage to the seed crystal and relatively fast heating ramp rates significantly enhances seed stability and quality during the initial growth stage.

ABSTRACT. Wafer warpage can cause severe problems during device manufacturing. Therefore, tight specifications for bow and warp for wafer material are well established. However, differences in warpage during processing can still be observed for wafers with nominally identical geometry specifications. In this contribution we demonstrate the impact of residual stress on the mechanical behavior of 4H-SiC substrates and show its critical importance on the wafer bow during subsequent processing. Further, we present a fast method to evaluate this stress and identify the relevant parameters to be specified in order to anticipate the resulting warpage during processing. We investigated the distribution of the residual stress of a set of wafers from different manufacturers obtained by stress-induced birefringence and compared the results to the wafer geometry measured using an optical profilometer. In an earlier contribution, we observed a clear correlation between the mean residual stress and the gravity induced deflection (GID) in SiC substrates with a diameter of 150mm [1]. A broader screening of Ø200mm wafers now shows that some wafers do not follow this trend, indicating that the simple averaging of the stress is not a sufficient measure to predict the warpage behavior. An in-depth analysis also taking into account the direction of the stress reveals that only the tangential stress component has a relevant impact on the GID. As an example, Fig. 1 shows the stress map and GID of a wafer with mainly tangential tensile stress as well as a wafer with a ring of tangential compressive stress. While wafers like wafer 1 follow the observed trend of increasing GID with higher residual stress, wafers with a significant tangential compressive component like wafer 2 experience much lower GID than expected from the mean stress. By replacing the absolute mean stress by the mean value of the tangential tensile component, the correlation again becomes valid also for these different types of stress distribution. The observed differences in GID already provide a clear indication that the residual stress will influence also the wafer warpage during wafer processing steps. We confirmed this assumption by measuring the change in wafer bow after application of an epitaxial layer. For this investigation standard low-doped n-type epilayers with a thickness between 12.25 and 14.5 µm were grown on substrates of different suppliers. The mean residual stress in the substrates laid in the range of 5 to 25 MPa. After epitaxy, we observed a large spread in the change of the wafer bow between 5 and 35 µm, which can be very clearly correlated to the residual stress in a similar way as the GID (Fig.2). We compared these results to the expected wafer curvature following epitaxy applying the models of Jacobson [2] and Stoney [3]. In these models, no influence of residual stress in the substrate is taken into account, resulting in a smaller deflection than measured in all wafers (Fig. 2). However, we observe that the wafer bow approximates the theoretical values in the limit of low residual stress, giving clear evidence that the deviation from the theoretical models is at least mostly caused by the residual stress, which underlines the crucial role of this parameter for the mechanical wafers during processing.

ABSTRACT. Silicon carbide (SiC) is a key material in power electronics under high-temperature and high-voltage conditions due to its thermal conductivity (3.7–4.9 W/cm·K), wide bandgap (~3.26 eV), and high breakdown voltage (>10 kV) [1,2]. However, prolonged operation under electric stress leads to degradation linked to stacking faults (SFs) [3,4]. Among these, rotational stacking faults (RSFs) caused by the relative in-plane rotation of atomic layers are less understood but may significantly affect charge localization and electronic transport. First-principle studies on SFs in 4H–SiC indicate the formation of defect levels ~0.2–0.3 eV below the conduction band minimum (CBM) [4,5]. While these defect-induced traps can hinder device performance, how the electronic structure evolves is largely unexplored under real-time operational conditions. We examine how RSFs influence the time evolution of the band structure using density functional theory-based molecular dynamics (DFT-MD) under constant electric field stress. A rotated 4H–SiC structure with stacking faults was modeled using a 128-atom supercell in the Atomic Simulation Environment (ASE), with DFT calculations performed via the projector augmented-wave (PAW) method in grid-based projector-augmented waves (GPAW). A 0.2 V/Å electric field was applied along the x-direction (Figure 1). Structural relaxation used the Perdew–Burke–Ernzerhof (PBE) functional within the Generalized Gradient Approximation (GGA) framework. DFT-MD simulations ran for 300 steps with a 1 fs timestep, Verlet integration, and a 500 eV plane-wave cutoff under the microcanonical (NVE) ensemble, conserving energy without a thermostat. The initial band structure of the RSF-containing 4H–SiC supercell (Figure 2a) exhibits near-degenerate conduction band minimum (CBM) and valence band maximum (VBM) states at the S and Y points. The calculated direct and indirect band gaps are 3.049 eV and 2.763 eV, respectively. The direct gap closely matches the accepted value (~3.0 eV) for pristine 4H–SiC [2,4]. By step 16, the gap reduced to 0.536 eV (direct) and 0.422 eV (indirect). Transient midgap states emerged alongside local distortions near the fault, temporarily introducing shallow traps. At later steps (75 and 257), band flattening and splitting were observed, indicating localization and lattice distortion. This evolution from dispersive to flat bands suggests increased carrier effective mass and field-induced disorder [6]. The PDOS at steps 215–217 shows an accumulation of Si-3p and C-2p states near the Fermi level, indicating a semiconductor-to-metal transition (Figure 3). This is consistent with previous findings that these orbitals dominate impurity bands near the Fermi level [7]. Rather than decreasing monotonically, the band gap evolves through fluctuating midgap states and a progressive buildup of conduction-band states near the Fermi level, suggesting a reversible partial closure. Initial localized RSF states became increasingly delocalized over time, as the field promotes orbital hybridization and spatial spread, particularly among conduction states. The observed electronic evolution is driven by intrinsic symmetry-breaking at the stacking fault, acting as a dynamic center for band tailing and field-induced metallization. These findings demonstrate how the effects of rotational stacking faults impact the electronic properties of 4H-SiC under electric field stress.

[1] X. She, A.Q. Huang, O. Lucia, B. Ozpineci, IEEE Trans. Ind. Electron. 64 (2017) 8193. [2] W.-W. Xu, F. Xia, L. Chen, M. Wu, T. Gang, and Y. Huang, J. Alloys Compd. 768, 722 (2018). [3] L. Lai, Y. Cui, Y. Zhong, K.Y. Cheong, H. Linewih, X. Xu, J. Han, J. Appl. Phys. 137 (2025) 060701. [4] U. Lindefelt, H. Iwata, S. Öberg, P.R. Briddon, Phys. Rev.. B 67 (2003) 155204. [5] M. S. Miao, S. Limpijumnong, and W. R. L. Lambrecht, Appl. Phys. Lett. 79, 4360 (2001). [6] S. Das, Y. Zheng, A. Ahyi, M. A. Kuroda and S. Dhar, Materials 15, 6736 (2022) [7] J. Xi, B. Liu, Y. Zhang, W.J. Weber, Comput. Mater. Sci. 123 (2016) 131.

ABSTRACT. Deep level defects are important factors affecting the performance of 4H-SiC devices, significantly reducing carrier lifetime, mobility, and device reliability. Therefore, accurate characterization of these defects is crucial for optimizing the epitaxial growth process and enhancing device performance. Deep Level Transient Spectroscopy (DLTS) is a powerful technique widely used for studying electronic properties of deep level defects[1-2], but the accuracy and resolution of DLTS measurements are highly dependent on the optimized settings of the test parameters. This paper aims to systematically analyze the effects of key DLTS test parameters, including the time window (tW), pulse time (tP), reverse voltage (UR), pulse voltage (UP), on the characterization results of deep level defects of 4H-SiC. DLTS measurement reveals three deep level defects in the 4H-SiC Schottky barrier diode (SBD). Among them, T1 and T2 are identified as majority-carrier traps. The activation energy of T1 is located approximately 0.66 eV below the bottom of the conduction band (EC - 0.66 eV), which is attributed to carbon vacancies (VC)[3]. T2 is located around EC - 1.0 eV, and is assigned to extended defects or vacancy pair[4-5]. In addition, a minority carrier trap T3 is observed with an energy level of about 1.10 eV above the top of the valence band (EV + 1.1 eV). The origin of T3 may be related to defects introduced during annealing or associated with the P+ region[6]. Figure 1(a) shows the DLTS spectra of the 4H-SiC SBD measured under different time windows (tW). As the tW increases, all the defect peaks shift towards lower temperatures. While the amplitude of T1 peak remains essentially unchanged, the amplitudes of T2 and T3 peaks decrease. This phenomenon originates from the exponential dependence of carrier emission on temperature. Figure 1(b) demonstrates the effect of pulse width on the DLTS spectrum. As tP increases, the position and shape of T1 peaks remain unchanged. However, the amplitudes of T2 and T3 peaks increase significantly. This increase occurs because the defect state is not saturated and filled under the short tP, resulting in the underestimation of the signal amplitude. Figure 2(a) shows the DLTS spectra under different reverse voltages (UR). As the absolute value of UR decreases, the amplitude of T1 peak decreases due to the narrowing of depletion region, and the T2 peak broadens but its amplitude fluctuates irregularly, indicating inhomogeneously distributed defects. Figure 2(b) shows the DLTS spectra at different pulse voltages (UP). The enhancement of the DLTS signal with increasing UP is due to the filling of more deep levels and interface defects in the expanded depletion region. Table 1 shows the information about the defects obtained by Arrhenius fitting for various conditions. In conclusion, DLTS parameters significantly and systematically affect the position, amplitude, and spreading of defect peaks by modulating the depletion region and the filling and emission kinetics of defect carriers. An in-depth understanding of these parameter effects and their physical mechanisms provides a crucial experimental foundation and theoretical basis for the precise analysis of deep energy-level defects and optimization of the DLTS test scheme.

ABSTRACT. The growing demand of wide-bandgap (WBG) materials in the microelectronics world has led to invest on medium- and high-voltage power products based on SiC technology. SiC present an excellent compromise between high voltage blocking capability, high temperature operation and high switching frequencies [1]. One of key steps in the preparation of high-performance devices is improving the growth process of SiC single-crystal material. Crystal growth occurs through chemical vapor deposition (CVD) method that is reported to generate macrodefects and micropipes (MPs). These defects are defined killer because severely affect the performance of SiC-based devices [2]. The MP are generated during the ingot growth and, usually, they are propagated as they are in the epitaxial layer [3]. They are located at the center of a large spiral on the surface and the diameters of the pinholes range from 0.5μm to several micrometers [3]. Defects having sizes lower than the spatial resolution, nowadays it is close to 1 um with high volume manufacturing tool, can strongly impact the device processing and badly compromise the electrical performances. In this study we propose to evaluate two devices by means of KOH etch molten technique in order to determine the connection between crystal quality and electrical failures. KOH method represents a destructive approach that exhibits selective etching for areas with defects [5]. After the etching, it is possible to detect several pits with different topography and correlate them with different types of defects. In Figure 1 we report sample 1 in which the burn-in was generated by a MP. In figure 2 we report sample 2 in which the burn-in was generated by combination of two MPs. In detail, a combination of etching in molten KOH, optical analysis and SEM analysis were used to investigate the structure of pits and their relationship with the failure of the device. Fig. 1.a) shows the optical analysis of a failed die subjected to electrical stress. To evaluate the nature of the defect, the die was etched in molten KOH at a temperature of 540 °C at different times. The optical analysis (Fig. 1.b) shows clearly that the origin of the burn-in is a MP (large hexagonal etched pit) surrounded by threading screw dislocations (TSD that are medium-sized pits). The image on the top of Fig. 1. c) shows a SEM image of a micropipe on an epilayer surface that has a characteristic morphology around a hole. The image at the center of Fig. 1. c) shows the optical analysis of the MP after etching and the image at the bottom of Fig. 1. c) shows the overlapping between MP revealed at SEM post epitaxy with that revealed with optical inspection after KOH. In Fig. 2. a) is reported another burned sample in which the failure seems to involve multiple defects. In fact, focusing on the area circled in red reveals two defects, one circled in green and the other one in blue. According to different observations [4], micropipes in SiC are often grouped together and coalesce during growth. In this regard, the first step involved scanning electron microscopy (SEM) analysis with FIB cuts to investigate the sample surface (Fig. 1. b)). SEM analysis showed that the burning generated from the pit marked with the name “FIB3 in Fig. 2. b” evolves vertically in the structure. It was not possible to make any evaluations from the other two fib cuts (FIB1 and FIB2, Fig. 2. b). However, since it was not possible to identify the type of surface defects, molten KOH was used to visualize surface defects under optical microscopy (Fig. 2. c). Optical inspection of the sample shows two MPs that branching out from the substrate and are replicated in the epitaxial layer. As reported in literature [3], depending on growth speed and C/Si ratio, the MPs can be dissociated into closed-core screw dislocations (Fig. 3). In according with such observation at the bottom of Fig. 2. c) two MPs, whose traces are highlighted in green and yellow, are propagated from the substrate during the epitaxial growth. In this case the behavior of MPs during epitaxial growth is much more complicated because are dissociated into several closed-core screw dislocations during CVD growth. This leads to the generation of pits on the surface which contribute synergistically to the failure of the device. To improve the understanding of the evolution of MPs the failed sample will be analyzed by micro-Raman spectroscopy (not showed here). These results will help to understand MPs formation/propagation, stress field involved and the evolution mechanisms. The aim is to control micropipe density at the epitaxial layer in order to obtain a high SiC crystal quality.

ABSTRACT. We report a study about digital defect traceability at the early stages of the SiC processing chain, in a SiC puck down to the epi-ready wafers after slicing and polishing. Currently full control of SiC defects takes place downstream, typically at post-wafering stage, when substantial resources have been spent for processing (Fig. 1). However, the internal crystal defects that are discovered in wafers [1] - such as micropipes, dislocations, inclusions - are formed during the crystallization stage, at the very beginning of the production line. We aim at shifting the quality control earlier, to the bulk level. This has an obvious benefit of saving the processing cost of defective material, and also providing quick feedback for optimizing crystal growth. Therefore, we have developed an easy-operating crystal scanner visualizing XYZ defect positions in the puck volume. Such early-stage inspection systems shall ensure that most of defective material is recognized straight after crystallization, and that only quality SiC material goes to costly processing stages.

In this study, we purposely selected a 40.7 mm thick 6-inch 4H-SiC puck for the variety of its defects (polytypes, micropipes, high dislocation density, inclusions…) to assure their traceability in subsequent processing steps. We have inspected the defects within the puck in 3D with the proprietary SiC Puck Scanner and we have built a model presenting the 3D mapping of all defects detected using Yield ProTM software (Fig.2) [2].

Subsequently, 16 sister-wafers were sliced out of the most defective half of this puck and polished. These wafers were first assessed under UV illumination to detect and visualize polytypes. In addition, defect mappings by optical and photoluminescence techniques were carried out on Visiontec Nuvis Systems [3]. Raman measurements and a calibration towards selective etching on one wafer completed this extensive study.

The presentation is devoted to correlation between defect maps observed by the puck scanner and the wafers inspection systems (Fig. 3). While varying between defects types, the substantial overall correlation shows that most of the SiC internal defects can now be detected at the bulk stage, making it possible to a) grade pucks non-destructively, and b) predict wafers quality before wafering. As the fabrication costs of high quality SiC wafers represent one of the biggest challenges in the SiC industry [4], these results hold the promise of large savings on future processing time and consumables. It also secures a higher margin for crystal growers, who could use the 3D defect maps as a time-dependent feedback loop in order to improve their crystal growth process at lower ecological and commercial costs. The puck scanner is now being actively developed and a commercial version will be launched in 2025.

ABSTRACT. Non-destructive wafer-level inspection of SiC substrates prior to device fabrication is necessary in mass production since certain classes of defects in SiC substrates could propagate to the epitaxial layer, which is the active region of SiC power devices, and cause device failures [1]. Defects in SiC substrates can be detected and classified based on the visual contrast attributed to defect features appearing in inspection images acquired based on certain inspection principles, one of which is the photoluminescence (PL) imaging method. It has been reported that non-uniformity in impurity concentration in SiC substrates leads to wafer-to-wafer variations in donor-acceptor pair (DAP) emission intensity [2], and such uncertainties reduce the accuracy of detection and classification of defects using the PL imaging method. To improve the accuracy of defect inspection using the PL imaging method, it is necessary to fully evaluate the PL characteristics of the SiC substrate itself as well as the defects. In this study, we investigated the PL characteristics of commercially available SiC substrates through PL spectrum analysis and verified their influence on defect inspection. In addition, we focused on PL analysis of micropipes (MPs), one of the device killer defects in a SiC substrate, and explored universal inspection conditions for the PL imaging technique that is applicable for SiC substrates with different impurity types and its concentrations. Five commercially available n-type 4H-SiC (0001) substrates (samples A to E) from different vendors were prepared as test samples. For the PL spectral measurements, we used a He-Cd laser (λ = 325 nm) as the excitation light source. For PL imaging, we used a Hg-Xe lamp with a filter (λ = 313 nm) as the excitation source and a CCD camera was used to measure PL images through following optical filters: a band-pass filter with a center wavelength of λ = 450 nm (VIS filter) and a high-pass filter of λ > 650 nm (NIR filter). Surface morphology was observed by a confocal differential interference contrast (C-DIC) optics with excitation light of λ = 546 nm. We also measured X-ray topography (XRT) [3] with a diffraction vector of g = [0008], and combined with the PL and C-DIC measurement results to verify the detection conditions for the MPs. All measurements were conducted at room temperature. Figure 1 shows five PL spectra measured near the center of each SiC substrate. The PL spectra were normalized with the band edge emission peak of 4H-SiC at approximately 390 nm. A broad PL spectrum observed in the wavelength range of 450 nm to 750 nm can be decomposed into two PL components around 550 and 680 nm. These PL components correspond to DAP emissions involving nitrogen (N), boron (B), and aluminum (Al), reported by previous studies [4]. The difference in the intensity ratio between these two components clearly shows the difference in impurity concentrations for each substrate. Figures 2, 3 and 4 show the inspection results for MPs in Samples B, C and E, respectively. In (a) of each figure, the dashed lines show PL spectra observed on the MPs, and the solid lines are the PL spectra of the substrates obtained near the MP but not including the MPs and other defects (Background). The C-DIC and XRT images ((b) and (c) of Figs. 2-4) were used to determine the positions of the MP and Background PL spectra measurements. According to the PL images with the NIR filter ((d) of Figs. 2-4), MPs can be detected as dark contrast by using near IR emission regardless of the wafer-to-wafer variation in the impurity concentration. On the other hand, when the PL images were measured with the VIS filter ((e) of Figs. 2-4), some MPs were detected with bright contrast compared with the Background PL, while the others were detected with dark contrast. The comparison of Figs. 3 and 4 examplifies the opposite PL contrast of the MPs, despite the quite similar Background PL spectral profile. This indicates that the impurity concentration on and around the MP can differ from MP to MP. This variation in PL contrast complicates the identification of MPs, but from a different perspective, the PL imaging combined with VIS and NIR filters possibily identifies not just the MP location but also additional physical information around MPs, such as impurity distribution. To improve detection ability of defects including MPs, the quantitative correlation between PL spectral profile and local impurity distribution for various defects is now under investigation.

ABSTRACT. With the rapid growth of the SiC power device and optoelectronics markets [1], there is increasing demand for larger-diameter SiC substrates and more efficient manufacturing processes. However, the current SiC manufacturing process presents significant challenges; intrinsic stresses, both inherent to crystal growth and introduced during mechanical processing, can lead to non-ideal wafer geometries such as bow, warp, and thickness variations. While lithography compensation techniques can partially mitigate these geometry effects, distortions at the die level and intrinsic stresses can still affect patterning and device performance. Removing high-stress material from the surfaces of wafers using grinding and chemical mechanical polishing (CMP) is effective, but adds to the already high material kerf loss due to wire sawing. In contrast, Halo Industries uses a proprietary laser-based method to create wafers without the use of a wire saw, which greatly reduces both kerf loss and surface stresses.

There are several established methods for measuring wafer geometry and total thickness variation (TTV). Techniques such as chromatic white light (CWL) profilometry enable direct thickness measurements by independently measuring a wafer’s top and bottom surfaces. These methods are limited by the tradeoff between resolution (i.e., spatial sampling frequency) and wafer throughput due to the scanning nature of the technique. On the other hand, interferometric systems such as the Corning Tropel FlatMaster MSP can rapidly capture high-resolution interferograms across an entire wafer surface, drastically improving both measurement time and sampling density as compared to scanning methods [2, 3]. Nonetheless, optical methods require a priori knowledge of the refractive index of the substrate and may be susceptible to artifacts arising from spatial index variations, potentially impacting calculated substrate thickness accuracy. Literature on the effects of SiC doping on index dispersion is sparse, with one found example focusing only on a single wavelength [4].

We demonstrate the repeatability of FlatMaster MSP optical TTV measurements across 4H-SiC wafers manufactured with Halo Industries’ proprietary process. These are compared to physical thickness data obtained using a dual-source CWL system to quantify the impact of spatial index variation on TTV. We further investigate wafer thickness effects on the sensitivity of interferometric methods to refractive index variation. Finally, we explore the role of dopant concentration in driving refractive index variation. This includes both (1) intentional doping differences ranging from semi-insulating to heavily doped and (2) unintentional dopant inhomogeneities such as those arising from preferential dopant incorporation within the basal facet region. This work provides key insights for refining SiC metrology, supporting improved salability in substrate manufacturing.

[1] “Silicon Carbide Semiconductor Device Market Size, Share and Trends 2025 to 2034.” Precedence Research. https://www.precedenceresearch.com/silicon-carbide-semiconductor- devices-market (accessed Apr. 16, 2025). [2] J. Wang et al., “Optical Characterization of High Refractive Index Glass Wafers for Augmented Reality Wearables,” Optical Interference Coatings Conference (2019). [3] T. Dunn, C. Lee, M. Tronolone, and A. Shorey, “Characterization of Wafer Thickness Uniformity During 3D-IC Processing,” IEEE 62nd Electronic Components and Technology Conference (2012). [4] G. Lim, T. Manzur, and A. Kar, “Improved optical properties and defectivity of an uncooled silicon carbide mid-wave infrared optical detector with increased dopant concentration,” J. Opt. 14, 105601 (2012). [5] “FlatMaster MSP for Augmented Reality Waveguides,” Corning Tropel Applications (2019).

ABSTRACT. Spectroscopic ellipsometry is a well-established fast, non-contact and non-destructive characterization technique [1]. It is widely used for the optical characterization of materials in semiconductor production (particularly silicon [2-5]). However, extending its application to silicon carbide (SiC) introduces several challenges due to the more complex optical properties of this material. These challenges include SiC’s transparency across a visible spectral range, the need to account for incoherent contributions from reflections at the back surface of the wafer, and the intrinsic anisotropy with a tilted optical axis. In this study, we employ spectroscopic ellipsometry across a broad spectral range from the far-infrared (Bruker Vertex 70v polarizing FTIR spectrometer with spectral range 0.0124 eV – 0.9537 eV) through near-infrared, visible and ultraviolet (Woollam RC2-DI Mueller matrix ellipsometer with spectral range 0.73 eV – 6.42 eV), and extending into the terahertz region (in-house developed complete THz time-domain spectroscopic ellipsometer [6] with spectral range 0.1 THz – 3 THz) to characterize 4H polytype SiC wafers. This wide spectral range enable us to obtain information about bandgap, transparency windows, absorption and phonon peaks and free carriers contributions as listed in Table I. Our main objective is the development of advanced optical models capable of accurately describe the anisotropic optical properties of SiC, accounting for back-side incoherent reflections, and determining physically meaningful optical constants. Examples of modeled and measured data of 4H-SiC are shown in Fig. 1 and Fig. 2. Oscillations in transparent spectral region in Fig. 1 originate from interferences of polarization states after secondary reflections from substrate back side as shown on the schematic drawing in Fig. 1. The optical models we have developed offer a promising framework for further characterization of thin films and/or epitaxial layers deposited on SiC substrates. These models are particularly relevant for analyzing thin films with various doping concentrations and for studying films designed for ohmic contacts. Our approach contributes to the broader applicability of ellipsometry in advanced semiconductor device development where SiC plays a key role.

Acknowledgements: We acknowledge financial support from GACR (25-15775S); Ministry of Education, Youth and Sports of the Czech Republic (SP2025/090); project "Materials and Technologies for Sustainable Development" (CZ.02.01.01/00/22\_008/0004631); project REFRESH (CZ.10.03.01/00/22\_003/0000048), and OP JAC, reg.NO. CZ.02.01.01/00/23_021/0008592 Advanced Materials for Energy and Environmental Technologies.

[1] H. Fujiwara, Spectroscopic ellipsometry: principles and applications, John Wiley & Sons (2007). [2] C. M. Herzinger, et al., J. Appl. Phys. 83, 6 (1998). [3] G. E. Jellison, F. A. Modine, J. Appl. Phys. 76, 6 (1994). [4] M. Foldyna, et al., The European Physical Journal Applied Physics 42, 3 (2008). [5] Z. Mrazkova, et al., Progress in Photovoltaics: Research and Applications 26, 6 (2018). [6] P. Koleják, et al., IEEE Transactions on Terahertz Science and Technology (2025).

ABSTRACT. In this work, a high repeatability mercury probe [1,2] was used to characterize CVD epitaxially grown 4H-SiC MOSFET structures. Critical material and device performance parameters such as carrier density profiles, specific on-state resistance (RON) and breakdown voltage (VBD) are measured with capacitance-voltage (MCV) and current-voltage (MIV) measurements. Additionally, surface defects, such as triangular defects, are detected with Schottky IV ideality factor, barrier height and reverse leakage current measurements. For determination of drift layer epi thickness, buffer layer thickness and substrate doping level, model-based infrared reflectometry (MBIR) is used [3]. A description of the key forward/reverse biased Schottky IV (FBSIV/RBSIV) parameters is shown in Fig. 1. The ideality factor has been determined to be highly sensitive to surface triangular defects [4]. Reverse biased leakage current is sensitive to all defects within the space charge region as well as those generated in the bulk and drift to the space charge edge. Four (4) 4H-SiC Power MOSFET structures were provided by Veeco and evaluated. The wafers were grown on an EpiStride™ SiC CVD system. The drift layer target dopant densities were 5E15 cm-3, 8E15 cm-3, 1E16 cm-3 and 2E16 cm-3. The drift layer thickness was targeted to be 12.2 µm and the buffer layer was targeted to be 1.4 µm thick with a dopant density of 5E17 cm-3. Schottky CV carrier density profiles obtained on the four MOSFET structures are shown in Fig. 2. The RON values were determined from forward Schottky IV series resistance (RS) as depicted in Fig. 1. A performance plot of measured RON versus calculated VBD is shown in Fig. 3 along with previously reported values [4]. Surface level electrical defect density can be determined from the forward biased Schottky IV ideality factor (n) and reverse leakage current. Fig. 4 shows the cumulative probability plot for ideality factor. Also shown in the inset is a map of ideality Factor for the 5E15 cm-3 wafer. All four MOSFET structures measured exhibited average ideality factors of less than 1.040. Finally, an example map of drift layer thickness for the 5E15 cm-3 wafer is shown in Fig.5. The average drift layer thickness of this 49-site map was 12.24 µm. An MBIR map of the buffer layer thickness is also shown in Fig. 6. The mean buffer layer thickness is 1.39 µm.

[1] T. Boles et al., CSW Japan (2015) [2] Semilab MCV Brochure (2024) [3] R. Duru et al., Adv. Semi Manuf. Conf. (2013) [4] M.G. Coco et al., CS ManTech Conf. (2025)

ABSTRACT. The buffer layer is a key structural element in 4H-SiC epitaxy, facilitating the transition from the heavily doped substrate to the lightly doped drift region and thereby influencing the initiation and propagation of crystallographic defects. The design of the buffer layer significantly affects the appearance of basal plane dislocations (BPD) stacking faults (including triangular defects) and surface flaws that can lessen device reliability [1-2]. Although thicker or more heavily doped buffer layers are commonly employed to suppress substrate defects, recent studies indicate that surface preparation, doping gradients, and interface quality can be equally significant [2]. To investigate the impact of buffer parameters, we conducted a systematic epitaxial growth study using a horizontal batch CVD reactor. The thickness of the drift layer remained constant at ~10 µm with a nitrogen doping concentration of 1×1016 cm-3 across all wafers. The buffer layer thickness, expressed in arbitrary units (a.u.), was varied from 0.1 to 6 by adjusting the deposition time. Three doping regimes (low, target, and high) were established by adjusting the N2 flow during buffer layer growth, with high and low doping levels approximately 25% above and 40% below the target value, respectively. Although wafers were not exclusively sourced from a single 4H-SiC boule, each DOE point incorporated sibling wafers from the same boule to estimate the impact of substrate-related variations. Comparative results between boule resolved and cumulative data sets will be discussed to evaluate substrate influence on defect formation. All wafers experienced identical in-situ H2 surface conditioning prior to the epi growth to ensure uniform starting surface quality. Post-growth defect detection and classification were performed using a SICA88 inspection system equipped with photoluminescence (PL) imaging, enabling automated detection of extended defect types across the wafer surface. Polytype inclusions, critical crystal defects in 4H-SiC, were found to strongly depend on buffer layer thickness and doping. At target buffer doping, inclusion density dropped sharply as buffer thickness increased (Fig. 1a), indicating that ultra-thin buffers fail to stabilize the stacking sequence. At higher thicknesses (≥4.0 a.u.), inclusion counts increased slightly, suggesting new defect formation during extended buffer growth. Boule specific data (Fig. 1b) confirmed this trend across substrates, though absolute levels varied. Additional datasets at low and high buffer doping (Fig. 2) showed distinct behavior: highest inclusion densities occurred at intermediate thicknesses, with lower counts at both extremes. These results suggest that both inadequate structural decoupling and excessive thermal exposure can trigger inclusion formation. The findings support prior reports linking polytype inclusions to local step instabilities, interface stress, and polytype nucleation during early homoepitaxy [1-3]. PL detected stacking faults showed a distinct trend compared to polytype inclusions. At target buffer doping, SF density increased steadily with buffer thickness, from ~32 at thinnest to ~66 in average at thickest buffer with this trend consistent across boules (Fig. 3). In contrast to inclusions, which were minimized at intermediate buffer thicknesses, the increase in stacking faults with buffer thickness appears to be driven by BPDs that are not fully converted or terminated during buffer growth. As the buffer becomes thicker, the longer thermal exposure and stress accumulation may promote BPD glide and expansion into stacking faults in the drift layer [5]. At other doping levels, trends were weaker or reversed, suggesting that doping modulates BPD conversion efficiency and stacking fault suppression. While inclusions are sensitive to early nucleation instability [4], SFs reflect longer-range dislocation propagation and are more sensitive to thermal budget [5,6]. These results underscore that polytype inclusions and SFs arise from distinct mechanisms. Polytype inclusions are highly sensitive to local stacking sequence stability and interface preparation during early epitaxial stages, whereas PL-detected stacking faults are more closely associated with BPD conversion, dislocation dynamics, and thermal budget across the full epitaxial stack. Consequently, optimizing buffer design requires defect-specific strategies: thin, well-conditioned buffers may suppress nucleation driven inclusions, while tailored doping profiles and thermal control are essential to mitigate dislocation-mediated SF propagation. A unified buffer engineering approach that balances these requirements is key to achieving low-defect, device-grade 4H-SiC epitaxial layers for power electronics.

ABSTRACT. Silicon Carbide (SiC) is at the heart of the next generation of high efficiency because of its desirable physical properties. SiC has excellent thermal conductivity, wide bandgap and high breakdown voltage for high-voltage applications and reduced volume and weight, compared to conventional Si devices [1]. Preparation of SiC devices depends on epitaxial growth, which in turn depends on high-quality substrate wafer preparation. Surface, to be epi ready, requires several steps, including mechanical and chemical mechanical polishing (CMP) to achieve surface roughness <1nm and low sub-surface defect densities, some of which may remain after CMP. Such defects propagate into the epitaxial layer, affecting power device performance and reliability, decreasing production yield. Characterisation of sub-surface damage and defects on the substrate has advantages over classic KOH defects reveal, which is a destructive method, carried out after the epitaxy. Therefore, various methods of analysing sub-surface of the SiC, both optical and non-optical [2, 3] have been studied. In this work we’ve attempted EBSD (Electron Backscatter Diffraction) characterisation of the effects of plasma treatment on post CMP SiC surface. EBSD is a scanning electron microscopy (SEM) technique used to study the crystallographic structure of materials. Backscattered electrons from the beam interact with the crystal's periodic atomic lattice planes and diffract according to Bragg's law at various scattering angles before reaching a phosphor screen forming the detector. Analysis of SiC properties, using electron backscattered diffraction (EBSD) with a submicron spatial resolution on the exposed cross-sectional plane, has been reported as a viable of way of spotting sub-surface damage [4]. The goodness of the diffraction pattern can be quantified and related to the near-surface crystal quality, especially the orientation and polytype. With this method we’ve characterised CMP SiC samples, treated in several different plasma processes. The results were compared with AFM measurements, which, due to the smooth CMP surface, show insignificant differences, indicating that roughness alone is not a measure of surface or near-surface quality. This requires more sensitive characterisation methods (Fig. 1 and 2). Figure 1 shows the improvement in the EBSD measurement for different processes compared to an unprocessed CMP surface. This shows a range of difference from the worst process 6, which is c. 25% worse, to process 2, about 25% better. Figure 2 shows comparisons of the surface roughness with the EBSD measurements of plasma improved, plasma degraded and untreated CMP SiC surfaces. The roughness measurements show similar values for all surfaces, however the EBSD Pattetrn Quality strongly differs between the samples, confirming the need of usage of advance methods in analysing sub-surface damages of SiC. Further work will correlate these measurements with the defects identified after EPI growth, using PL measurement and KOH defect reveal etching. This will elucidate both an improvement in the CMP SiC surface and the benefits of EBSD analysis as non-destructive control method of sub-surface damage in SiC.

[1] X. Guo, et al. Micromachines 10(6), 406 (2019). [2] P-C. Chen, et al. Nanoscale Research Letters vol.17, no. 30 (2022). [3] M. E. Bathen, et al. J. Appl. Phys. 131, 140903 (2022). [4] K. Ashida, et al. MRS Advances 1, 3697–3702 (2016).

ABSTRACT. The knowledge of electrically active defects in semiconductors is of primary importance for bulk crystalline material growth as it aids feedback information in the process of growth parameters optimization. It also plays a key role in the design of power devices since, if a defect cannot be eliminated it can still be engineered and its thermal properties – including activation free energy and capture cross section – can be readily incorporated in technology computer-aided design (TCAD) models for electrical simulations. The unavoidable presence of boron impurities in n-type epitaxial 4H-SiC has been shown to have significant effects on the lifetime of minority carriers [1-2] – which is one of the main factors controlling the switching properties of SiC-based bipolar devices – through the action of boron-related electrically active point defects. Deep level transient spectroscopy (DLTS) has provided a straightforward means to access this information and almost unambiguous identification of the main boron-related traps is now available thanks to a combination of experimental DLTS data and density functional theory (DFT) calculations [3], with the main traps known as the deep boron (D) center and the shallow boron (B). A peculiar feature of DLTS is the ability to measure the concentration profiles of deep states, which is highly useful when the associated defects are introduced by ion implantation as it enables the study their microscopic properties like lattice diffusion, conversion mechanisms and their dependence on temperature and external forces. There are several DLTS-related techniques suited for depth profiling of trap states that can be adapted to different situations [4], but all of them share a major restriction: quantitatively they only work well for majority traps. These limits are connected to the intrinsic nature of the DLTS experiment, which relies on the control of the depletion region where filling of the traps of interest is forced by an external source – a voltage pulse or light irradiation (for minority traps). In the case of majority traps, the filling region is usually well-defined by the difference between a filling voltage pulse and a fixed reverse bias that determines the maximum depletion depth, when the depletion approximation holds, and the depth profile is achieved by only playing on the filling pulse [4]. On the other hand, it is undesirable to measure a trap profile by changing the reverse bias, because of further inherent dependencies of the DLTS signal upon the applied bias [4]. However, for the case of minority traps this second approach is intriguing, since minority carriers are introduced by light excitation in optical DLTS experiments and forward bias injection in the case of junction DLTS. These techniques do not give full control on the spatial extent of the filling volume, which basically extends from the surface (or the junction) to the depletion edge defined by the reverse bias. In this work we use junction DLTS to explore capabilities and limitations of a DLTS depth profiling experiment that utilizes reverse bias modulation to control the depletion depth and a fixed forward bias pulse to inject minority carriers into the depletion region, with the aim of measuring the depth distribution of boron-related minority traps in epitaxial n-type 4H-SiC embedded in a PiN device, and their change in concentration after implantation of medium energy protons. An example of high-resolution junction DLTS spectrum of the analyzed device is shown in Fig. 1. The spectrum evidences the presence of two main families of minority traps: the D-center and the shallow B, which is made up of two contributions here named B1 and B2. A first attempt of DLTS profiling of these minority traps is reported in Fig. 2. The graph shows depth profiles of a sample implanted with 1 MeV protons (solid curves) in comparison with a reference (not implanted) sample, where the depth distribution of the traps is assumed to be uniform throughout the material. The main goal of this study is to expand the use of the DLTS profiling method to minority traps and highlight the potential of this technique in pushing the limits of defect metrology, which is a pivotal tool for ion implantation studies on semiconductor materials.

The Research Council of Norway is acknowledged for the support to the Norwegian Micro- and Nano Fabrication Facility, NorFab, project number 295864.

[1] M. Ghezellou et al., The role of boron related defects in limiting charge carrier lifetime in 4H–SiC epitaxial layers, APL Mater. 11, 031107 (2023). [2] P.B. Klein et al., Lifetime-limiting defects in n− 4H-SiC epilayers, Appl. Phys. Lett. 88, 052110 (2006). [3] V. J. B. Torres et al., Theory of shallow and deep boron defects in 4H-SiC, Phys. Rev. B 106, 224112 (2022). [4] P. Blood and J. W Orton, The Electrical Characterization of Semiconductors: Majority Carriers and Electron States, Academic Press, London, 1992.

ABSTRACT. The 4H-SiC exhibits a variety of dimensional defects, including the deep-level point defect SE2 (=E3, Ec - 0.25 eV), reported to have a trap concentration of approximately 1.4×1014 cm-3 and attributed to crystal defects, specifically Single Plain Stacking Faults (SFs) [1,2]. In this paper, we investigated the impact of stacking fault defects on carrier lifetime and electrical performance of SiC devices by integrating experimental measurements with TCAD simulations. Fig. 1(a) and (b) shows the Time-Resolved Photoluminescence (TRPL) analysis illustrating the spatial defect distribution across two different 4H-SiC wafers. Fig. 1(c) specifically maps the locations of defects characterized by distinct PL wavelengths. Utilizing UV-vis spectroscopy-based bandgap calculations, we confirmed that the PL wavelength of 424 nm, corresponding to the single Shockley-type stacking fault (1SSF) defect, precisely matches the previously reported SE2 energy level (Ec - 0.25 eV) [1,3]. Fig. 1(d) highlights the carrier lifetime associated with the largest identified 1SSF defect, quantitatively confirmed minimum lifetime values of 35 ns and 50 ns. In this study, explicitly demonstrated that the presence of the 1SSF defect significantly decreased carrier lifetime, primarily through enhanced Shockley-Read-Hall (SRH) recombination rates [4]. To quantitatively evaluate the impact of defects on device performance, experimentally derived lifetimes (35-40 ns, 50-78 for defective regions and 3 us for defect-free regions) were implemented into Sentaurus TCAD simulation. Fig. 2 demonstrates the influence of carrier lifetime on the static characteristics of SiC IGBTs using TCAD simulations. Fig. 2(a) shows a notable decrease in breakdown voltage (BV) from 4682 V to 4401 V as lifetime increases from 30 ns to 3.0 μs, due to enhanced minority carrier injection and improved conductivity, narrowing the essential space-charge region. Fig. 2(b) indicates stable threshold voltage (Vth) but increased collector current at longer lifetimes, resulting from reduced drift resistance. Fig. 2(c) confirms improved on-state conduction with increased lifetime at higher gate biases (VGE = 5 V and 10 V). Fig. 2(d) summarizes these electrical parameter trends, highlighting the trade-off between conduction efficiency and voltage-blocking capability. Fig. 3 shows the SRH recombination distribution at the turn-off point (3.15 μs) for carrier lifetimes of 30 ns and 3.0 μs. The 30 ns structure exhibits significantly higher SRH recombination activity near the drift region compared to the 3.0 μs case, confirming that shorter lifetime leads to faster carrier removal through enhanced recombination. This behavior corresponds to the observed difference in current tail duration shown in Fig. 4. Fig. 4(a) and 4(b) show the dynamic switching behavior and hole conduction characteristics of SiC IGBT devices with carrier lifetimes τe = 30 ns and 3.0 μs, evaluated using the illustrated switching test circuit and corresponding switching waveforms. At time = 3.15 μs, the 30 ns device has fully turned off, while the 3.0 μs device exhibits a pronounced current tail. Fig. 4(c) presents the hole density (hDensity) distribution at this turn-off point, clearly showing a significantly higher hole concentration in the drift region for the 3.0 μs device. This elevated hole density supports a larger hole current density of 88 A/cm2 compared to 43 A/cm2 in the 30 ns device. Fig. 4(d) further illustrates the vertical hDensity profile, confirming that the extended current tail observed in the 3.0 μs case results primarily from sustained hole conduction. These findings highlight the critical trade-off between conduction efficiency and switching performance, underscoring the importance of carrier lifetime optimization in SiC IGBT design.

ABSTRACT. Silicon carbide (SiC) has attracted considerable attention as a key material for next-generation power semiconductor devices due to its outstanding physical properties [1]. In line with this, the demand for high-quality SiC wafers continues to grow, and accurate defect characterization is becoming increasingly critical for ensuring stable device performance and reliability. Among various crystallographic defects, threading dislocations (TDs) are the most frequently observed and widely studied. Notably, some TDs extend to the wafer surface, forming surface pits that have been reported to contribute to leakage current and electrical non-uniformity in devices such as Schottky barrier diodes (SBDs) [2,3]. To effectively manage these defects, non-destructive characterization techniques are receiving growing attention. Previous studies have proposed a combined approach using X-ray topography (XRT) and birefringence imaging with polarized light microscopy (PLM), enabling the crystallographic distinction between threading screw dislocations (TSDs) and threading mixed dislocations (TMDs) which are difficult to differentiate using a single method [4-6]. Moreover, by simulating the in-plane stress field responsible for birefringence contrast in PLM, it is possible to quantitatively estimate the orientation of the edge component and the inclination of the dislocation line within TMDs [7-9], which supports detailed non-destructive characterization of dislocation. Based on this framework, we investigated how the magnitude and direction of the Burgers vector of individual TDs influence the morphology and electrical properties of associated surface pits, aiming to clarify the formation mechanisms. We first crystallographically identified the Burgers vectors of TDs in 4H-SiC epitaxial wafers using XRT and birefringence imaging with a PLM [4-9]. As shown in Fig. 1, two TDs (#1 and #2) were observed in the same area by XRT (Fig. 1(a)). In the birefringence image (Fig. 1(b)), #1 showed negligible contrast, consistent with a pure TSD having only a c-axis component, whereas #2 exhibited distinct contrast indicative of a TMD with an edge component. Comparison with birefringence in-plane stress field simulations (Fig. 1(c)) revealed that the edge component of #2 aligns with the m-axis along the [1-100] direction, as confirmed by automated birefringence simulation software [8]. This demonstrates the feasibility of refining dislocation classification based on Burgers vector composition. The surface pits formed by these dislocations were then analyzed using conductive atomic force microscopy (C-AFM). As shown in Fig. 2, the surface pit associated with #2 appeared larger and deeper than that of #1. In addition, their I–V characteristics differed significantly, highlighting the influence of the Burgers vector on both pit morphology and local electrical properties. These results provide quantitative evidence that the morphology and electrical properties of surface pits can be influenced by the magnitude and direction of the Burgers vector of each individual TD. Differences in pit morphology may be attributed to a combination of factors, including the anisotropic strain fields surrounding dislocations with different Burgers vector orientations and the interaction between step-flow and spiral growth modes during epitaxial processing. Although the detailed formation mechanism remains to be further investigated, the demonstrated correlation underscores the practical utility of integrated, non-destructive characterization methods. Ultimately, these insights may support more precise defect management strategies, aiding the optimization of SiC epitaxial growth processes and contributing to improved reliability in SiC-based semiconductor devices.

ABSTRACT. Basal plane dislocations (BPDs) in 4H-SiC epilayers are known to lead to bipolar degradation of 4H-SiC devices. The BPDs include not only those in the epilayers before device fabrication but also those formed during high temperature processes such as activation annealing after ion implantation. In-depth physical understanding on the origins and structures of BPDs has been achieved through years of detailed investigations and analyses. One category of BPDs remains to be less intensively studied or clearly understood, which are formed during activation annealing after ion implantation. Although significant strains would be introduced by high dose implantation, no evidence has been found that the onset of BPD formation should be decided by the implantation-induced strain only. This report presents our study on strain evolution and formation of interfacial dislocations (IDs) in ion-implanted 4H-SiC epilayers. There are two types of IDs that have been observed in 4H-SiC. The IDs at the epilayer/substrate interface will be referred to as type-I and those at the bottom of an implanted layer will be referred to as type-II. Results show that if considering the formation of both types of IDs in a typical 4H-SiC device structure, the misfit strain in the epilayer or the implantation-induced strain itself appears not enough to drive BPD glide and multiplication. It happens with the aid of thermal stress. For the consequences of IDs, type-I is considered to be benign for bipolar degradation since both partials are of C-core for most type-I IDs. However type-II will enlarge the area affected by stacking fault expansion since both partials are of Si-core.

ABSTRACT. This study aims to develop sensitive identification and classification of defects in 4H-SiC using RC-XRDI techniques. Measurements were conducted at the B16 Test Beamline at DLS on a 4° off-axis 4H-SiC n-type substrate with a 10 µm-thick epitaxial layer. A high-resolution detector with a 35 µm-thick Ce:YAG scintillator, optical lenses, and CCD camera captured the diffracted X-rays. Two crystal planes were examined in reflection mode: symmetric (0008) at 8.04 keV (Figure 1a) to assess tilt, and asymmetric (2 2 4 ̅ 16) (Figure 1b) at 17.48 keV for twist sensitivity. Imaging the same sample region with both reflections enabled distinction of dislocation types based on differences in peak positions and full width at any fraction of maximum intensity, labelled as, (FWxM). Local rocking curves were extracted pixel-by-pixel using the cumulative integrated intensity (CII) method, [3] yielding three key parameters: area under the curve (AUC) as a measurement of the diffracted intensity, peak position for local Bragg angle shift, indicating lattice distortion or interplanar spacing (d), and FWxM to quantify the extent of local strain, as a measure of material quality [3, 4, 6]. The most frequent values of these parameters, as determined from the histograms across all identified defects, are summarized in Table I.

ABSTRACT. Silicon carbide (4H-SiC), due to its wide bandgap, superior thermal conductivity, and exceptional critical electric field strength, has become indispensable in power device technologies [1]. For planar field-effect transistors (FETs) and superjunction (SJ) devices designed to operate in the 6.5 to 10 kV range, thick epitaxial layers (≥60 µm) are critical to provide sufficient depletion regions and uniform electric field distribution, thereby preventing premature electrical breakdown [2]. Lowering the densities of crystallographic defects, including dislocations, inclusions, and micropipes, is highly desirable for these devices due to severe degradation in device electrical parameters caused by them. Selection of low defect density substrates for epilayer growth followed by comprehensive defect characterization is, therefore, necessary to achieve desired epilayer quality and reduce defect density. In the present study, Coherent team grew epitaxial layers on 6-inch diameter Coherent 4H-SiC substrates using multi-wafer warm-wall epi reactor. Defects in the epitaxial layers of thicknesses 60 µm and 110 µm, being developed for 6.5kV and 10kV devices, respectively, were systematically characterized through synchrotron X-ray topography (XRT), employing both high energy grazing-incidence (22-416) and transmission (11-20) geometries (Fig. 1). Analysis reveals exceptionally high crystal quality of the investigated wafers. Substrate defect content revealed on transmission topography indicate dislocation densities on lower end typically observed for 6-inch wafers (Fig. 2(a), (c)). Grazing incidence topography (22-4 16) with high penetration depth (>40um) reveals that notably, basal plane dislocations (BPDs) originating from the substrates did not propagate into the epitaxial layers, representing significant improvement in epitaxial growth conditions (Fig.2(b), (d)). Moreover, the density of observed 3C inclusions was approximately 30 per 6-inch wafer for 60um epi layer, and 60 for 110 um epi layer respectively, which are markedly lower compared to typical densities exceeding 200 inclusions per wafer (3-inch) in published thick (183um) epitaxial layer studies [3]. Micropipes, recognized as particularly detrimental defects, were rarely observed in this investigation, a stark improvement over literature-reported micropipe densities frequently reaching several tens per wafer [4]. Additionally, threading dislocation densities (including threading screw, edge, and mixed dislocations) were measured between approximately 1000–2000 cm⁻², substantially below commonly cited values that frequently exceed 4000 cm⁻² in other published studies on thick epitaxial layers [5]. Detailed analysis of whole-wafer defect statistics as well as microstructure will be presented. The synchrotron X-ray topography results thus confirm the superior defect characteristics and crystalline quality of the thick epitaxial 4H-SiC wafers examined in this investigation. The exceptionally low defect densities observed provide significant advantages for the development of high-performance, high-reliability power electronic devices. Furthermore, these findings contribute critical insights into effective defect-control strategies and epitaxial growth optimization methods for the SiC industry.

ABSTRACT. 4H polytype of silicon carbide (4H-SiC) is a semiconductor material finding increased use in power devices due to its wide bandgap, high breakdown voltage and high thermal conductivity. 4H-SiC epitaxial layers grown on 4H-SiC substrates inherit defects from the surface of substrate. Since epitaxial defects from substrates adversely affect device performance, the accurate classification of the device killer defects is critical. In general, most epitaxial defects are inspected and classified by confocal digital interference contrast (DIC) microscopy technology. DIC scan images, combined with photoluminescence (PL) intensity, are classified into different defect bins. This study utilizes PL spectrum and carrier lifetime based on band edge emission by Time Resolved PL (TRPL, 355nm laser with 30kHZ 600ps pulse) to identify device killer defects in detail. X-ray topography technology is used to study the defect propagation from substrate to epi 4H-SiC substrates have been scanned first by Lasertec SICA88 for crystal defects and surface defects. Epitaxial films were grown on these substrates and were scanned using Lasertec SICA88 again to identify epitaxial defects. The epitaxial wafers have also been scanned and analyzed using EtaMax MiPLATO-SiC for PL spectrum and carrier lifetime features of epitaxial defects. First, substrate defects and epitaxial defects were compared to correlate and detect propagation of defects from the substrate surface to epitaxial layers. However, it was found that SF defects (stacking fault) were not easy to trace down to substrate related defects. Epi defects classified as stacking faults based on PL intensity are not typically considered as killer defects. Analysis of Epi PL SF with a peak lambda of 540nm in the PL spectrum can reveal additional 3C poly type inclusions. Polytype and some SF defects show a peak at 540nm. The ratio of polytype inclusion from DIC detection to 3C defect using the 540nm peak lambda ranges from 95/109 to 90/122. This implies that DIC based defects may miss some 3C poly type defects. Thus, defect classification based on peak lambda can result in improved killer defects identification for correlation with device performance. Most poly type inclusions are relatively well matched between SICA and MiPLATO-SiC as shown in Figure 1. Individual defects were analyzed using 5um resolution for TRPL carrier lifetime and PL spectrum as shown in Figure 2. The area surrounding the defects has abrupt changes in spectrum and carrier lifetime. The carrier lifetime of normal epi area is longer than 70 ns and the carrier lifetime of most SF defect areas is about 20-60 ns. 3C related defect spots have the shortest lifetime as 20-40 ns. The carrier lifetime of substrates is shorter than 15 ns. These different carrier lifetimes of defects and materials enable dynamic PL to be more efficient in filtering out crystal defects than static PL imaging. Figure 3 shows the different carrier lifetimes of peak lambda-based defects. Depending on epi structure and growth mechanism, band-edge carrier lifetime is different. Thicker structure has usually longer lifetime. The cross-section of defects has been analyzed using Rigaku XRTmicron. We have used the transmission mode of XRT in (1 1 -2 0) diffraction to identify defect propagation. XRT slicing mode shows the top surface to inner substrate. Figure 4 shows an example of defect propagation in a substrate. The top surface of the wafer has only one dark spot as a defect center. Once slicing goes down deeper, it shows BPD (Basal Plane Dislocation) defects in the SiC substrate. The scan depth gets deeper, BPD nature is diluted after the origin of the defect source. We have demonstrated new metrology technology to analyze crystal defects as a function of depth for epitaxial layers and substrates. These technologies will correlate epi and substrate defects.

This project is partially supported by CHIPS Act through the Commercial Leap Ahead for Wide-Bandgap Semiconductors (CLAWS) Hub based in North Carolina and led by NC State University.

[1] T. Kimoto, J. J. Appl. Phys. 54, 040103 (2015). [2] C. Kawahara et. al., J. J. Appl. Phys. 53, 020304 (2014). [3] M. Na et. al., Materials Science in Semiconductor Processing 175,108247 (2024).

ABSTRACT. This paper presents process integration of atomic layer deposition (ALD) SiO2 as gate dielectric in the 1.7 kV SiC trench UMOSFET. This integration provides a solution for embedding complementary metal oxide semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. 4H-SiC power MOSFETs have gained increased attention in medium to high power applications recently due to their wide bandgap, high breakdown electric field, and excellent thermal conductivity. The electric vehicle (EV) is one example of an application where the Tesla Model 3 utilizes SiC 650V VDMOSFETs as driving components in its inverter design. Trench MOSFETs are key to achieving these requirements to further scale down power devices while decreasing the specific on-state resistance (Ron,sp). This is challenging with thermal gate oxide on SiC trench MOSFETs due to the anisotropic thermal oxide growth rate on the sidewalls and the bottom of trench or mesa region. Therefore, we propose a novel fabrication process by integrating ALD SiO2 gate oxide into trench UMOSFET. The Ron,sp of the fabricated device can be reduced to 2.3mΩ-cm2, accompanied by a very low density of interface states (Dit) of approximately 5.36x1010 eV-1cm-2. Another feature of this ALD SiO₂ solution for gate oxide is the monolithic integration of the CMOS circuit with the UMOSFET, enabling the realization of smart power IC management.

ABSTRACT. Silicon Carbide (SiC), a wide band gap semiconductor material, exhibits higher thermal conductivity and higher breakdown electric field as compared to Silicon (Si). With a growing demand for power device applications under conditions of high temperature and high voltage, SiC-based power devices and in particular SiC MOSFETs have attracted much attention as an alternative to Si-based power devices due to the superior material properties of SiC [1,2]. However, reliability issues of SiC MOSFETs related to gate oxide with the poor SiO2/SiC interface quality still remain a significant concern. Threshold voltage (VTH) instability under gate bias stress is known to be caused primarily by near interface traps, also called border traps, that cannot be removed through nitridation annealing of the gate oxide [3-5]. Re-oxidation in a low temperature range of 850-1050℃ following gate oxidation is effective in improving the interface quality by reducing the near interface traps [6-8]. During the re-oxidation, carbon clusters at and near the interface react with oxygen atoms and diffuse out as CO2 gas with almost no further oxidation of the SiC surface [9]. It is noticeable that in addition to the removal of carbon clusters near the interface, the slight additional oxidation induced by the re-oxidation can change the near interface trap density, since the near interface traps are mainly present within 2-3 nm from the interface [10]. In this study, we investigated the impact of the re-oxidation on the SiO2/SiC interface quality. MOS capacitors and N-channel MOSFETs were fabricated on 4H-SiC wafers with or without the re-oxidation (950℃, 1000℃). The flatband voltage (VFB) and the interface state density (Dit) were extracted from C-V curves of the MOS capacitors and from transfer curves of the MOSFETs by the subthreshold slope method, respectively. The SiO2/SiC interface region was examined using scanning transmission electron microscopy (STEM) as well. Furthermore, positive and negative high-temperature gate bias (HTGB) tests for the MOSFETs were performed to evaluate the influence of the re-oxidation on threshold voltage shift. As shown in Table I, it was found that the re-oxidation, regardless of the temperature, results in a reduction of the interface state density and a negative shift of the flatband voltage. Moreover, the transition region at the SiO2/SiC interface was also reduced with the re-oxidation (see Fig.1). In the HTGB tests, the samples with re-oxidation showed a reduction of the threshold voltage shift as compared to the samples without re-oxidation, especially under the positive bias condition.

ABSTRACT. Silicon carbide (SiC) is a ideal material for high-voltage power devices due to its exceptional critical electric field, electron saturation velocity, and thermal conductivity [1]. A key advantage of SiC is the its ability to thermally grow a SiO₂ dielectric layer, which currently provides the lowest interface defect density compared to other dielectrics on SiC. However, the trap density is still higher than Si/SiO2 interface [2, 3]. To further improve device reliability, high-k dielectrics like aluminum oxide (Al2O3) are advantageous, as their higher dielectric constant (k ≈ 9) reduces electric field in the dielectric stack, enhancing the breakdown strength [2, 4]. However, high-k/SiC interfaces typically exhibit higher trap densities than SiO₂/SiC interfaces, leading to charge trapping and instability in parameters such as threshold voltage [3]. Hybrid dielectric stacks combining a thin SiO₂ layer with a thicker high-k film deposited via atomic layer deposition (ALD) have emerged as a promising solution [4]. However, introducing an additional interface between the high-k dielectric and the SiO2 layer (as shown in Fig. 1A) can introduce new interface defects into the system. Since deposition kinetics influence defect formation, this work investigates how Al2O3 ALD parameters—including oxidant chemistry (A, B, C) and deposition temperature (150°C–350°C)—affect the interfacial quality and overall dielectric robustness. Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated by depositing a 20 nm Al2O3 via ALD on an n-type 4H-SiC substrate covered with a 2 nm SiO2 layer. A 10 nm TiN top electrode was sputtered under an ultra-high vacuum and annealed at 480°C in argon for one minute. Finally, Ti (10 nm)/Pt (30 nm) metal dots were evaporated as contact electrodes, with isolation achieved via dry etching (see Fig. 1B). The electrical characterization involved subsequent capacitance-voltage (C-V) dual sweeps. The involved small-signal modulation had a fixed frequency of 100 kHz. Finally, the leakage current of the entire stack was measured over a wide voltage range towards accumulation until dielectric breakdown. In all combinations of oxidants and deposition temperatures, C–V measurements consistently showed a shift in the flat band voltage (ΔVfb), a phenomenon also observed at the SiC/SiO2 interface (Figs. 2, 3, and 4C). Notably, this voltage shift appears quasi-permanent, as subsequent C–V sweeps—both forward and reverse—reproduce the initial reverse sweep (see Fig. 1). Such a behavior can be caused by electron traps with high emission activation energies and correspondingly long recovery time constants. Furthermore, the variations in flat band voltage during the initial upsweep (Fig. 3) likely stem from fixed charges at the SiO2/SiC, Al2O3/SiC interface or from the bulk of Al2O3. In contrast, the measured leakage current predominantly arises from bulk defects in the dielectric stack that facilitate trap-assisted tunneling. Interestingly, altering the oxidant did not yield an ideal stack that simultaneously exhibits low leakage current (Fig. 4) and minimal ΔVfb (Fig. 3), thereby highlighting a trade-off between the density of interface states and the quality of the bulk high-k dielectric. As shown in Fig. 5, this finding could be confirmed for various deposition temperatures. Finally, although variations in deposition temperature did not significantly affect the leakage current and dielectric strength for oxidants B and C, oxidant A demonstrated lower leakage currents and higher breakdown fields within the 200–250°C range—a regime that does not align with the minimal ΔVfb observed around 300°C. Adjusting process parameters, such as the oxidant used in the ALD deposition for the high-k dielectric and the deposition temperature, revealed a trade-off between dielectric leakage current and breakdown strength versus charge trapping characteristics (ΔVfb). Acknowledgment: This work was co-financed by the European Union and from tax revenues on the basis of the budget adopted by the Saxon State Parliament, Project Nr. 100687609. References: [1] M. Ostling et al., ISPSD, 2011. [2] A. Siddiqui et al., J. Mater. Chem. C, 2021. [3] M. Avice et al., Appl. Phys. Lett., 2006. [4] A. Marcuzzi et al., Materials Science in Semiconductor Processing, Jul. 2024.

ABSTRACT. In a previous study, we demonstrated that low-resistivity bonded substrate (SiCkrest) not only reduced the on-resistance of MOSFET but also provided a low-resistance backside contact without the need for contact annealing; it also showed reduced temperature dependence. In this study, we prepared bonded substrates with average resistivities ranging from 2.4 to 31.5 mΩ·cm and focused on the relationship between the resistivity of the bonded substrate and the contact resistance at the grinded backside where metal Ti/Ni was applied. The resistivity of the bonded substrates was evaluated using eddy current measurements, whereas the nitrogen concentration in the polycrystalline layer was analyzed by SIMS, and the carrier concentration was determined through Hall measurements. The circular TLM method was employed to accurately measure the backside contact resistance. As result, it is indicating the existence of a threshold resistivity at which low specific contact resistance (ρC) can be achieved without contact annealing, and eliminating the temperature dependence of ρC between 17.4 and 34.4 mΩ·cm. This phenomenon is expected to occur because ρC is dominated by tunneling current below the threshold resistivity, driven by high nitrogen concentration and sufficient carrier activation in the polycrystalline layer of bonded-SiC.

ABSTRACT. This study investigates the effects of different gate oxide fabrication processes on the electrical performance of 4H-SiC planar MOSFETs. While thermal oxidation followed by nitric oxide (NO) annealing remains the industry standard for SiC gate oxide formation [1], alternative approaches such as atomic layer deposition (ALD) and composite dielectric stacks are actively being explored to further improve interface quality. Gate oxide integrity directly impacts key device metrics such as threshold voltage stability, leakage behavior, and long-term reliability. As device scaling and high-temperature operation become increasingly important in power electronics, improving the SiC/oxide interface remains a primary challenge in MOSFET design. In this work, three experimental conditions were implemented, each varying only the gate oxide process while maintaining a consistent baseline process flow. All devices examined in this study are lateral n-channel 4H-SiC planar MOSFETs. The baseline fabrication flow, shown in Figure 1, remained identical across all conditions, with the gate oxide formation step being the sole variable: • Condition 1: 50 nm thermal oxidation + NO annealing at 1350°C for 1 hr. • Condition 2: HF surface clean + 50 nm thermal ALD + NO annealing at 1250°C for 1 hr. • Condition 3: 20 nm thermal oxidation + 30 nm thermal ALD + NO annealing at 1250°C for 1 hr. Wafer-level CP testing was employed for electrical characterization, focusing on threshold voltage (Vth), leakage currents (IDSS) and body diode forward voltage (VSD) with statistical distributions summarized in Tables 1 and 2. Good die rate was defined as the percentage of dies falling within the range of median ± 3 standard deviations for each measured parameter. In addition, representative IdVg curves were used to confirm device functionality under all three conditions as shown in Figure 2. Condition 1 demonstrated the highest Vth (2.49 V), lowest leakage (6.1E-5 A), and excellent uniformity, suggesting effective interface passivation by high temperature NO annealing. Condition 2 and Condition 3 also produced functional devices, with comparable VSD and complete IdVg switching characteristics. However, slightly increased leakage currents and standard deviation in these two ALD-involved processes indicate that oxide/interface optimization remains necessary. Previous studies have shown that, unlike the carbon-related defects typically observed in thermally grown oxides, the interfacial issues in ALD-based stacks may originate from different mechanisms, which could limit the effectiveness of conventional NO passivation [2]. In particular, the stacked structure in Condition 3 may suffer from additional challenges due to insufficient interface cleaning between the thermal and ALD layers, potentially introducing interfacial contamination during oxide formation [3]. Figure 3 further supports this interpretation by comparing IgEOX characteristics across all three conditions, revealing more frequent oxide breakdown events in the ALD-involved processes, likely due to interface-related weaknesses. These results show that while newer gate oxide schemes offer flexibility in process integration, careful interface engineering remains a key determinant for achieving stable and reliable performance in SiC MOSFETs.

[1] Dhar, S., et al. Applied physics letters 84.9 (2004): 1498-1500. [2] Renz, A. B., et al. Materials Science in Semiconductor Processing 122 (2021): 105527. [3] Li, Shuai, Jun Luo, and Tianchun Ye. ECS Journal of Solid State Science and Technology 12.5 (2023): 053006.

ABSTRACT. Wide-bandgap (WBG) semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO₃) are attracting increasing attention for high-temperature, high-power, and high-frequency applications [1]. Among these materials, aluminum nitride (AlN)-based 4H-SiC heterojunction diodes are considered promising candidates for high-temperature power devices due to their high thermal conductivity and breakdown voltage (BV) [2]. However, precise control of the interface remains a critical requirement. To address this challenge, post-deposition annealing (PDA) has been widely employed to improve film crystallinity and reduce defect density. While previous studies have reported improvements in AlN crystallinity due to PDA [3, 4], the influence of PDA on temperature-dependent electrical behavior and high-temperature stability has not been thoroughly investigated. In this study, AlN thin films were deposited by radio-frequency sputtering on an n-epitaxial 4H-SiC wafer (net doping concentration of 1×10¹⁶ cm−3). PDA was carried out under three different conditions: without annealing, and with annealing at 600 °C and 1200 °C, respectively. The structural and electrical properties of AlN/4H-SiC diodes were systematically investigated. Capacitance–Voltage measurements confirmed that the net doping concentration of the AlN layers ranged from 7.89×10¹⁴ to 1.67×10¹⁵ cm−3. X-ray diffraction and X-ray photoelectron spectroscopy analyses revealed that high-temperature PDA significantly improved the crystallinity of the AlN films and effectively suppressed oxygen-related defects. To analyze the temperature dependence of the Schottky barrier height (SBH) and the existence of SBH inhomogeneities at the interface, the thermionic emission model was applied to extract the ideality factor and SBH. The ideality factor ranged from approximately 1.19 to 4.67, and the SBH ranged from 0.66 to 1.09 eV, depending on the temperature. These results show a clear temperature dependence, reflecting changes in the interface barrier properties. In particular, the observation of an ideality factor exceeding 2 at room temperature is consistent with previous studies [5] reporting that wide-bandgap heterojunction diodes typically exhibit large ideality factors. These trends are attributed to changes in the dominant charge transport mechanism and the degree of interface inhomogeneity. Furthermore, the BV exceeded 2000 V. Compared to the BV of 850 V for conventional n-type 4H-SiC Schottky barrier diodes, the incorporation of the AlN layer significantly enhanced the BV characteristics. This result suggests the potential for designing high-breakdown-voltage power devices by utilizing AlN. This study shows that PDA conditions significantly affect both thermal stability and electrical performance of AlN/SiC heterojunctions, offering a detailed analysis of temperature-dependent behavior beyond film quality improvements. Further optimization of PDA processes and evaluation of long-term reliability are expected to accelerate the practical application of AlN-based power devices.

Acknowledgment This work was supported by the Korea Institute for Advancement of Technology (KIAT) - Human Resource Development Program for Industrial Innovation(Global) (RS-2024-00421235) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea), the Technology Innovation Development Program - Development of 8-inch SiC Wafer-based Multi-Sensor SoC Platform (RS-2023-00266246) funded by the National Research Foundation (NRF, Korea), and also funded by Kwangwoon University in 2025.

References [1] T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology, IEEE Wiley, (2014). [2] M. Hu, P. Wang, D. Wang, Y. Wu, S. Mondal, D. Wang, E. Ahmadi, T. Ma, and Z. Mi, APL Mater. 11, 121111 (2023) [3] Kumar, A., Arafin, S., Amann, M. C., Singh, R. Nanoscale research letters 8, 1-7 (2013) [4] Z. Shen, F. Zhang, J. Chen, Z. Fu, X. Liu, G. Yan, B. Lv, Y. Wang, L. Wang, W. Zhao, G. Sun, and Y. Zeng, Appl. Phys. Lett. 117, 102105 (2020) [5] M. Brötzmann, U. Vetter, H. Hofsäss, J. Appl. Phys. 106, 063704 (2009)

ABSTRACT. Lowering backside contact resistivity is a prerequisite for the widespread deployment of high-performance silicon carbide (SiC) vertical power devices. In this framework, numerous industrial and academic research efforts are currently focused on the development of rapid, cost-effective and reliable test vehicles but also process solutions to support the fabrication of advanced contact modules. The present study is organized into two primary axes: (i) improving the metrological precision of contact resistivity (ρc) measurements by implementing a pattern-last approach for c-TLM structure formation and also by incorporating an n–p–n trilayer stack on the n-type SiC substrate, and (ii) reducing the absolute value of ρc through process optimization, involving dopant incorporation below the silicide/SiC interface followed by activation via laser annealing, as well as optimization of Ohmic Contact Formation by tuning laser annealing parameters.

ABSTRACT. Since SiC is hard and brittle, dicing by normal grinding process not only requires a long time for processing, but also reduces chip strength due to microcracks. The use of highly efficient and damage-free etching with high-pressure plasma as a chemical processing method for dicing rather than mechanical processing was investigated. Using a durable electroplated metal mask, high-power plasma processing was applied to SiC samples, achieving an etching depth of 100 µm. However, the vertical etching rate was found to decrease as the processing progressed. The results of electrostatic field calculations suggest that this is due to a decrease in plasma intensity caused by electric field decreasing.

ABSTRACT. In this research, surface microstructures of Ni-based ohmic contacts on 4H-SiC bulk substrates were investigated. After fabrication process, the Ni/Nb/4H-SiC sample showed a lower contact resistivity compared to that of Ni/4H-SiC sample. The results obtained from the conductive atomic force microscope (C-AFM) showed that a smaller variation in the peak current was observed in the Ni/Nb/4H-SiC sample. These results suggested that the chemical compounds formed at the interface of the Ni/Nb/4H-SiC were uniform. Whereas a lower surface roughness could be achieved for the Ni/4H-SiC sample. The results obtained in this research indicated that the introduction of Nb not only plays an important role in improving ohmic contact for 4H-SiC but also influence the surface roughness as well as current roughness.

ABSTRACT. In evaluating the performances of any emerging semiconductor, Schottky barrier diodes (SBDs) stand out as the frontrunners in technical advancements, holding significant importance from both commercial and scientific perspectives [1]. The Schottky metal, in particular, confers these devices desirable properties, depending on the target application, for example in terms of switching characteristics, operable temperature range or sensing performances. In UV photodetection, an emerging solution is employing Indium–tin-oxide (ITO) [2]. Using this transparent conductor in SiC-SBDs was investigated in our previous paper [3]. The present work focuses on characterizing and identifying critical parameters for ITO/4H-SiC SBD operation as UV photodetector. Mainly, the Schottky Barrier Height (SBH) distribution was evaluated from forward characteristics over a wide temperature domain using various models [4], [5]. The test structures were fabricated starting from an n-type SiC wafer with an epitaxial layer having a doping concentration around 1016 cm-3 and highly doped substrate (1018 cm-3). Firstly, the backside contact (ohmic) was obtained by a sputtering deposition of Ni (100 nm), followed by a high temperature annealing at 1050°C, for 3 min, in Ar atmosphere. Four different batches of Schottky diodes were fabricated, with circular, 600µm-diameter, active areas. Accordingly, the Schottky contact (front side) was fabricated with 200 nm of ITO, deposited by sputtering, followed by three distinct thermal treatments – 400°C (ITO400), 600°C (ITO600) and 800°C (ITO800) – for 30 minutes in an Ar environment. A control sample (ITO), whose Schottky contact was not annealed, was also analyzed. To ascertain the contact inhomogeneity, the test structures were diced, encapsulated in TO39 packages using wire-bonding technology and measured at different temperatures using a Keithley 4200 semiconductor characterization system coupled with a Janis closed cycle refrigerator system. Previously [3], we showed that annealing increases the transparency of the ITO film across the whole wavelength range (200–700 nm). While SiC is applicable for the UV domain, we found that optimal responsivity for our fabricated structures is at 330 nm. In addition, the film crystallinity was considerably improved after thermal treatments. Fig. 1 shows forward bias I-V characteristics of fabricated samples in the temperature range of 40 – 500K. The activation energy method was used on forward curves in the 400-500K domain. The dominant parasitic region was identified for each ITO sample, with effective SBH (ΦBn_eff) and non-uniformity parameter (peff) values given in Table I. It is evinced that, although all diodes exhibit exponential current-voltage dependence, the I-V characteristics of ITO and ITO400 samples have more uniform profiles and their exponential behavior is over more orders of magnitude. Instead, the ITO600 and ITO800 samples show visible irregularities on the forward characteristics, also confirmed by their higher p¬eff. Saturation currents are at least three order of magnitude higher than their ITO and ITO400 counterparts, because of the much lower barrier height (Table I). The apparent SBH was also extracted from forward characteristics, showing an approximately linear increase with temperature. This behavior is exemplary of contact inhomogeneity, indicating that the metal-semiconductor interface contains parasitic low-barrier regions which interfere with current conduction [5]. The performances as UV photodetector for the fabricated SiC Schottky diodes were evaluated using current-time characteristics obtained at three different reverse voltages: 0, –5 and –10V. As seen in Fig. 2, the devices may operate even as self-powered photodetectors (bias at 0V), with best results exhibited by ITO400. The highest photocurrent was obtained for the ITO400 sample, on the entire range of bias voltage, due to the increase in space charge region width. The response and recovery times for each sample were determined and are given in Table II. All annealed samples exhibited both τresponse and τrecovery in the range of few ms. Comprehensive forward curve analysis, modeling and SBH contact surface-distribution, alongside correlations with photocurrent will be discussed at the conference. Acknowledgement. This work was supported by a grant of the Ministry of Research, Innovation and Digitization, CNCS - UEFISCDI, project number PN-IV-P2-2.1-TE-2023-1740, within PNCDI IV and PN-IV-P7-7.1-PED-2024-2521.

ABSTRACT. Silicon Carbide (SiC) is increasingly used in high-power and high-temperature applications due to its wide bandgap, high thermal conductivity, and strong breakdown field. However, its extreme hardness and brittleness present significant challenges during wafer fabrication, particularly in edge grinding processes. Conventional horizontal edge grinding methods often lead to edge chipping, which negatively impacts yield, alignment, and device reliability. This study evaluates a novel edge grinding approach, known as contour edge grinding, and compares it with the conventional method in terms of edge chipping performance. A total of 400 SiC wafers were processed and analyzed using an automated inspection system. Results show that the contour method reduced large edge chipping (≥200 μm) from 6.5% to 1.0%, while also significantly decreasing surface roughness and subsurface damage. These improvements contribute to enhanced process stability, reduced particle contamination, and higher device reliability, making contour edge grinding a promising technology for next-generation SiC power device manufacturing.

ABSTRACT. Silicon Carbide (SiC), as a representative of next-generation wide-bandgap semiconductors, exhibits great potential for applications in new energy vehicles, aerospace, and photovoltaic power generation. Conventional slicing methods based on diamond wire sawing lead to high material loss and are prone to fracture. In contrast, laser slicing emerges as a kerf-free processing technique capable of achieving high-quality wafers with minimized material removal. This study investigates systematically the effects of the processing pass count on crack propagation and delamination strength in SiC laser slicing. Experimental results reveal that under optimized parameters, an appropriate number of processing passes enables successful wafer separation while maintaining surface integrity, achieving a reduction in material loss and a reduced delamination strength. The established processing window provides practical guidelines for enhancing SiC cutting quality, which significantly promotes innovative wafer manufacturing technologies for power electronics applications.

ABSTRACT. Recently, devices that can operate stably under extreme conditions such as high temperature, high voltage, radiation, and corrosive gas environments are required for new applications such as space exploration, nuclear power, and advanced transportation systems [1]. Silicon-based CMOS (complementary metal-oxide-semiconductor) technology has long dominated the mainstream of integrated circuits. Despite its widespread use, the limitations of Si CMOS in terms of blocking voltage, thermal capability, operating frequency, and power efficiency have highlighted the need for new material-based integrated circuit technologies. As a result, wide band-gap (WBG) semiconductor materials have inevitably emerged as next-generation candidates capable of overcoming extreme environmental challenges [1]. Among the candidates, silicon carbide (SiC) is the only next-generation material capable of implementing CMOS technology. While several progress has been made in SiC-based CMOS research in Korea, the field remains largely focused on in terms of simulation and process development [2]. In this study, 6-inch 4H-SiC CMOS inverters were fabricated at Korea’s only 6-inch public SiC fabrication facility, the National Institute for Nanomaterials Technology (NINT) of POSTECH, and their electrical characteristics were evaluated. Figure 1 shows the schematic figure of SiC CMOS inverter fabricated in this study. A total of three inverters were produced by varying the gate lengths (L) and widths of the PMOS (WP) and NMOS (WN) devices, as shown in Table 1. The gate metal was formed using heavily doped poly-Si, exhibiting a sheet resistance of 13.1 Ω/sq. For ohmic contacts, NiAl alloy was used for N-type ohmic contacts, achieving a specific contact resistance (ρsc) of 9.88 × 10⁻⁶ Ω·cm², while a Ti/Al metal scheme was applied for P-type ohmic contacts, resulting in a ρsc of 4.61 × 10⁻³ Ω·cm². The first metal layer was formed using a Ti/Al/Ti metal stack, providing a sheet resistance of 79 mΩ/sq. Before evaluating the SiC inverter, the threshold voltages (Vth) of PMOS and NMOS devices were measured. The results revealed a significantly negative Vth characteristic for both PMOS and NMOS. This phenomenon is likely attributed to the trapping of holes at the SiO₂/SiC interface, which can induce a negative shift in the Vth [3]. This effect also influenced the switching point of the inverter. Figure 2 shows the voltage transfer characteristic (VTC) of a SiC CMOS inverter at VDD = 9V. Ideally, the switching point of the inverter should be at half of VDD (= 4.5V). However, due to the significant Vth difference between the NMOS and PMOS characteristics, switching occurred at a lower VIN than expected. Despite the Vth issue, the device exhibited high uniformity, achieving a switching point variation within 0.2 V across a 6-inch wafer. Additionally, fundamental inverter characteristics were confirmed, including the negative behavior of the switching point as a function of L. These results suggest the potential for fabricating high-performance SiC CMOS devices in Korea.

Acknowledgement This work was supported by the National Research Foundation of Korea(NRF) funded by the Ministry of Science and ICT(RS-2023-00266246).

ABSTRACT. Silicon carbide (SiC) wafers are increasingly utilized in next-generation power devices due to their superior power handling and efficiency characteristics. However, their extreme hardness and brittleness make them susceptible to defects, particularly Basal Plane Dislocations (BPDs), during conventional dicing processes, which negatively impact device reliability and manufacturing yield. This study investigates a Water jet Guided Laser (WGL) processing technique for BPD-free dicing of epitaxial SiC wafers. WGL uses a high-pressure, micron-scale water jet as an optical waveguide for a pulsed laser beam, facilitating precise material ablation and cooling. While previous studies have shown that WGL does not generate BPDs in bulk SiC, its application for dicing epitaxial layers has not yet been fully explored. In this study, WGL-based dicing is applied to epitaxial SiC wafers, and the resulting crystal quality is evaluated using X-ray topography (XRT). The results confirm that WGL processing enables defect-free dicing, offering a promising solution for high-quality SiC wafer dicing suitable for power devices.

ABSTRACT. The formation of high-quality ohmic contacts on the backside of thinned SiC wafers is critical for vertical power devices to minimize R(on,sp) and enhance energy efficiency[1]. Conventional green laser (532 nm) annealing for Ni-based backside metallization faces challenges such as severe carbon out-diffusion, interfacial voids, and high contact resistivity. This work introduces a Ni/Ti composite metallization scheme combined with 355 nm ultraviolet laser annealing (UV-LA) to address these limitations. By replacing the Ni single-layer with a Ni/Ti stack layer, the reflectivity at 355 nm UV laser annealing is reduced, enabling efficient energy absorption and localized alloying. Ti acts as a diffusion barrier, suppressing Kirkendall void formation and immobilizing carbon through in-situ TiC formation[2], as confirmed by XRD and EDS analyses. Additionally, UV-LA at 4.2J/cm2 with Ni/Ti Composite metallization optimizes reaction kinetics, achieving a 69% reduction in void density and a 65% improvement in alloy layer flatness compared to Ni alloy layer as in Fig.1. Implemented in 150 μm thinned wafers, this technology reduces R(on,sp) by 0.15mΩ in 1.2kV SiC MOSFET, aligning with international benchmarks. The results validate Ni/Ti-UV-LA as a scalable solution for high-reliability SiC backside metallization, paving the way for next-generation power devices[3].

To overcome limitations and strengthen advantages, we introduce a Ni/Ti composite metallization. • Barrier & getter: Ti acts as a barrier that suppresses carbon out-diffusion and, as an intermediate reactant, combines with C and Si to form TiC/Ti₃SiC₂ in Fig.2, permanently immobilising free carbon and mitigating adhesion-loss risks at the alloy/SiC interface. • Morphology control: The composite design reduces Kirkendall void density and flattens the alloy layer, preserving backside structural integrity and minimising interfacial degradation. • Band-alignment benefit: TiC’s electron affinity (~3.9 eV) is close to that of SiC (~4.2 eV), delivering an energetically matched interface that enhances carrier injection and intrinsically lowers the ohmic-contact barrier. Ni/Ti composite metallization leads several Optimizations as below. • Structure: Void ratio decrease 69 % and overlap-zone roughness decrease 65 % versus pure-Ni baseline; XRD shows dominant Ni₂Si plus TiC/Ti₃SiC₂ with negligible graphite. • Reliability: No drift after 30k pulsed-current-second stress, confirming interfacial stability. 355 nm UV laser annealing of a Ni/Ti composite stack simultaneously suppresses graphite precipitation, eliminates most Kirkendall voids, flattens the alloy layer and leverages TiC-mediated band alignment, yielding tangible reductions in device R(on,sp). The method removes the bottlenecks of single-layer Ni and provides a manufacturable pathway toward SiC power devices[4].

ABSTRACT. Semi-insulating (SI) SiC substrates, which exhibit high resistivity due to carrier compensation by point defects, are promising for fabrication of SiC IC operational at high temperature. High-purity SI SiC substrates, where intrinsic point defects work as compensation centers, have been proposed for IC fabrication. Nevertheless, difficulty in the quantitative characterization of these defects in high-purity SI SiC poses a significant obstacle for precise doping control. The authors focused on vanadium(V)-doped semi-insulating SiC substrates, in which V atoms work as compensation defects. Although control of conduction type and conductivity through ion implantation in V-doped SI substrates are crucial for IC fabrication, formation and electrical characterization of the implanted layers in V-doped SI SiC substrates remain unexplored. This study demonstrates the formation of Al+ implanted layers in V-doped SI SiC substrates and characterizes the compensation defect density by Hall-effect measurements.

ABSTRACT. While in the past, ALD processes have required very slow deposition rates, new technology advances could enable the adoption of high throughput ALD systems in a production environment. In this investigation, the authors present a systematic study of ALD-SiO2 deposition using Oxford Instrument Plasma Technology (OIPT) PlasmaPro ASP, a high-rate atomic layer deposition (ALD), which was first developed for and adopted by gallium nitride (GaN)-based devices.

ABSTRACT. Silicon carbide has attracted increasing attention in recent years for power electronics applications, thanks to its excellent physical properties, which allow for obtaining higher breakdown voltage, higher switching frequency, lower resistance, and smaller devices [1]. In this context, laser annealing is considered an enabling process for a new generation of SiC power devices, since it allows the formation of ohmic contacts on very thin wafers, therefore significantly reducing their total ON resistance [2]. Ni silicide and Ti silicide ohmic contacts have been widely investigated and reported in literature, exploring in detail the role of laser features, metal thickness and thinning process [3-6]. Nevertheless, adding a small amount of Si to the contact layer could represent an opportunity to increase process options. In this work, a NiSi alloy has been used as a contact metal to study the role of the addition of Si to Ni in the reaction process under laser irradiation. Morphological and structural properties of the reacted layers have been investigated by means of Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD) analyses. The electrical characterization of reacted contacts has been performed by measuring their Sheet Resistance (Rs) by Four Point Probe (FPP) method and, at device level, by measuring the forward voltage drop (Vf) of Schottky Barrier Diodes (SBDs) fabricated on 150 mm-diameter 4H-SiC wafers. Furthermore, a comparison has been made between Ni and NiSi alloy under the same irradiation conditions. It has been reported [3] that the typical Rs curve, as a function of laser fluence, shows an increase of Rs values for low laser fluences, due to the initial intermixing between metal layer and Si, and then a rapid drop of Rs to a final plateau, above a threshold fluence. In particular, the value of threshold fluence depends on contact material and its thickness, number of laser pulses, and SiC roughness. As shown in Fig. 1a, the threshold fluence at which the Rs drop is observed decreases with the increasing number of laser pulses, both for Ni and NiSi alloy, but the threshold fluence of NiSi alloy is lower than that of Ni, at the same number of laser pulses. This could mean that, fixed the laser annealing conditions, the addition of Si to Ni moves the reaction forward. This hypothesis is confirmed by the measurement of Vf of SB diodes. As reported in Fig. 1b, in fact, NiSi sample annealed at 3.8 J/cm2 with two pulses shows a Vf significantly lower than the Ni sample annealed at the same conditions, and even lower than that of a Ni sample treated by Rapid Thermal Annealing (RTA), reported as a reference. XRD analyses (Fig. 2) of Ni and NiSi alloy samples annealed at 3.8 J/cm2, two pulses show the presence of Si-rich phases in NiSi alloy sample, confirming that adding Si to Ni moves the reaction ahead. Cross-sectional TEM analysis of a NiSi alloy sample annealed at 3.8 J/cm2, two pulses, shows a Ni-Si network region with inclusions of C-clusters and NiSi2 regions, according to XRD evidence. In conclusion, adding Si to Ni in the contact metal layer moves the reaction forward, driving the strong relationship found between structural, morphological and electrical properties of the reacted contacts.

ABSTRACT. Ultra-high-voltage (UHV) bipolar silicon carbide (SiC) power devices—such as Insulated-Gate Bipolar Transistors (IGBTs) rated up to 15 kV [1–3] and thyristors exceeding 20 kV [4]—hold the potential to revolutionize future grid and pulsed power applications. However, progress in this area has been hampered by the lack of commercially available P⁺ SiC substrates. As a result, many research groups have resorted to fabricating bipolar devices entirely through epitaxial growth on N⁺ substrates, which are subsequently ground away. Variants of this approach include growing the epitaxial stack "upside-down" (starting with the collector layer, in the case of IGBTs) [1] or "right-side-up" (starting with the emitter) [2,3], and choosing whether to remove the N⁺ substrate before or after front-side processing. Recently, however, P⁺ SiC substrates have begun entering trial production at 150 mm and 200 mm wafer sizes, offering a potential breakthrough. This development could transform UHV SiC device fabrication by enabling a more conventional process flow: epitaxial growth on a P⁺ substrate, followed by front-side device fabrication, wafer thinning, and backside processing. Nevertheless, challenges remain. Since only around 3% of aluminium acceptors are ionised at room temperature, device designers may need to form highly doped surface P⁺⁺ regions—via implantation or epitaxy—to enable effective charge injection and achieve low-resistance ohmic contacts. In this work, we explore these trade-offs by fabricating and characterizing simple N–i–P diodes on a 150 mm P⁺ SiC substrate, focusing on carrier injection efficiency and device resistance.

ABSTRACT. Amorphous silicon nitride is widely used in SiC-based power devices due to its high thermal conductivity, excellent dielectric properties, and mechanical robustness. As these devices are increasingly exposed to harsh conditions such as radiation and extreme temperatures, understanding material behavior under such environments is becoming essential. To evaluate the impact of radiation on its structural and mechanical behavior, primary knock-on atom simulations and subsequent tensile tests were performed on an amorphous Si₃N₄ model generated via the melt-quench method. Structural analysis revealed that irradiation led to the breaking of Si–N bonds and an increase in under-coordinated Si atoms. Stress–strain analysis indicated that increasing temperature reduced ultimate tensile strength and fracture strength, while increasing fracture strain. Similarly, higher radiation doses resulted in decreased mechanical strength due to thermal degradation. However, when compared at the same temperature as non-irradiated specimens, irradiated specimens exhibited a slight increase in elastic modulus, suggesting localized stiffening and embrittlement caused by radiation-induced defects. These findings offer fundamental insights into the mechanical behavior of amorphous Si₃N₄ for diverse applications in radiation-exposed environments

ABSTRACT. A comparative study of state-of-the-art commercial 1200V trench- and planar-gate silicon carbide (SiC) MOSFETs is presented. The experimental study mainly focuses on disclosing the static and robustness characteristics of distinct SiC technologies targeting automotive applications under room and high temperatures. The benchmark study of static characteristics covers specific on-resistance (Rds,on × Active Area), gate leakage (IGSS), drain leakage (IDSS), breakdown voltage (BVDSS), and drain-induced barrier lowering (DIBL) effects. The avalanche robustness is investigated by the unclamping inductive switching (UIS) setup under 25 °C and 175 °C while the single-pulse and repetitive short-circuit capability is revealed by using hard switching short-circuit testing bench under 25 °C.

ABSTRACT. In commercial silicon carbide (SiC) MOSFETs, the channel resistance contributes up to a third of the total device resistance, predominantly due to a defective silicon dioxide (SiO2)/SiC interface. This is a consequence of the thermal oxidation process, raising the density of interface states (DIT) due to residual carbon clusters, silicon suboxide phases, and unpassivated dangling bonds [1]. A novel approach can be the deposition of oxides by means of chemical vapour deposition (CVD) and atomic layer deposition (ALD), chemistry-based processes in which none of the underlying substrate is removed. The authors have previously demonstrated a promising post-deposition anneal process of ALD-deposited SiO2/SiC devices in forming gas at 1100°C, achieving density of interface trap levels of 2 x 1011 cm-2.eV-1 at EC-ET = 0.2 eV [1]. For a deeper understanding of the revealed passivation mechanism, it is essential to have an accurate characterization of the distribution of species, e.g., hydrogen (H), oxygen (O2), within the interfacial region as well as the bulk of the oxide. The role of H is of wider scientific interest, as its role is of paramount importance in passivating silicon (Si) solar cells. Conventional methods to characterize MOS interfaces include, but are not limited to, secondary ion mass spectrometry (SIMS) and atom probe tomography (APT). In SIMS, H profiles have blurring and are spread out from measurement artefacts. Also, H resolution limits are present due to the presence of H2 gas. In APT, H resolution and quantification limits exist due to mass spectra overlapping with background H2 gas [2]. Here, we present a characterization of SiO2/SiC systems by means of time-of-flight elastic recoil detection analysis (ToF-ERD), which were formed by both thermal oxidation as well as ALD deposition. Samples were characterized at the Surrey Ion Beam Centre at the University of Surrey, UK, using the measurement rig depicted in figure 1. Here, primary ion beams enter the sample at a near glancing angle (69.5°C), so atoms are knocked or recoiled from within the sample. Next, the recoiled atoms are measured in two ways. First, their time-of-flight (ToF) between two timing foils is measured to describe the velocity of the recoiled atoms. Next, the atoms enter a gas ionization chamber (GIC) through a silicon nitride window, where the energy is measured. In this way, a histogram of detection events is recorded with the atoms’ ToF and measured energy, which shows elements grouping along different energy-vs-ToF curves [3]. The depth profiles for elements are calculated from the relationship of energy and velocity of recoiled atoms to the depth they escape from, with the highest energy and lowest ToF, for each element, relating to the surface [3]. In our investigation, the 127iodine (I)8+ ion species were used. Figure 2 illustrates the histograms of detected true coincidences measured from ToF-ERD, displaying the energy measured by the detector and the ToF between the timing foils. The results from the coincidence histogram can be seen in Fig. 2 (a) for a thermally grown SiO2 layer and (b) a HfO2/SiO2/SiC gate stack. Due to the different atomic masses, the detection events for different elements follow separated parabolic energy-vs-ToF curves. Fig. (3) shows the ToF-ERD depth profiles for the gate stack in Fig. 2(b), with elements constructed from the representative histogram. Some C and O impurities can be seen within the first 5-7 nm, as expected from handling contamination. All gate stack layers, e.g., HfO2 and SiO2, are clearly visible then, with broad interfaces due to experimental artefacts. An attempt to sharpen the interfaces using Monte-Carlo ERD (MCERD) simulations was then carried out, which helps to deconvolute layers, resulting in a more accurate depth profile of the investigated sample. This is done by assigning separate densities for each layer individually. This can be seen in Fig. 3 (b), exemplary for the HfO2 layer. This demonstrates that ToF-ERD is a powerful technique for characterizing dielectric structures including multiple layers. It is capable of self-calibrating compositional depth profiles, with enhanced mass separation. It also allows for the simulation and accounts for experimental effects that can broaden layer interfaces. In the final submission, we will present an overview of different oxidation mechanisms and their atomic distribution within the MOS systems. [1] Renz et al., Materials Science in Semiconductor Processing, vol. 122, pp. 105527, 2021. [2] Shi et al, Applied Physics Letters, 123, 261106, 2023. [3] Pan et al., Nature Communications, vol. 15, pp. 3354, 2024.

ABSTRACT. Highly integrated electronic systems, necessitating the needs for compact, efficient, and high-performance power electronic converters, particularly for applications interfacing with power grids and motor drives, inherently require switching devices capable of bidirectional voltage blocking and current conduction, referring as bidirectional switches [1]. In addition, driven by advancements in superconducting power grids and quantum computing centers, the demand for devices that reliably operate at cryogenic temperatures has become increasingly crucial. In high-voltage (HV) and ultra-high-voltage (UHV) applications, bidirectional (BD) 4H-SiC power DMOSFETs are especially advantageous, due to lower conduction and switching losses, extended operating temperature capabilities, and substantial potential reductions in overall system size and weight. As the continuation of prior work [2], we have implemented hybridly bonded, 3.3kV 4H-SiC BD, conventional (Conv.) (commercial) DMOSFET dies in single-chip packages and evaluated its static and switching performance at room temperature (RT) and cryogenic temperature (77K) for the first time. The single-packaged 3.3 kV 4H-SiC bidirectional DMOSFET is implemented in a common-drain (CD) configuration using two commercially available Wolfspeed CPM3-3300-R050A SiC Gen3 MOSFET dies, as schematically shown in Fig. 1(a). The custom-packaged BD DMOSFET is depicted in Fig. 1(b). This BD die is fabricated by joining the drain metal contacts of the two dies using a commercially available nanoparticle silver paste, followed by a 200 °C sintering process. The custom package is constructed by sandwiching the BD die between two through-hole G10 substrates, sealed with silicone for mechanical and environmental protection. A 30 μm Parylene layer is deposited to passivate the exposed die surfaces and bonding wires. The static characterizations are performed at room temperature (RT) and 77K, showing bidirectional conduction and blocking (Fig. 2). Measured RON,sp of the BD at RT is 27mΩcm2, showing doubling of the RON,sp of the unidirectional device. It increased by 40% at 77K with the channel component increased from 13% to 47% of the total on-resistance. The increased channel component at 77K can be attributed to channel mobility degradation from increased coulombic scattering with interface states. Threshold voltage and subthreshold slope extracted at VDS of 0.1V increased from 4.2V to 7.4V and 860mV/dec to 1100mV/dec at RT and 77K respectively, due to increased interface trapping at 77K. Over 3.4kV and 3.8kV bidirectional blocking is achieved at RT and 77K. This anamously increase in BVDSS at 77K could be due to better insulation from liquid nitrogen. Fig.3 shows the static performance trade-off comparison with prior BD devices from our group [4,5]. RT Inductive load (12mH) double pulse switching is conducted at 200V and 5A with 100Ω gate drive resistance. Fig. 4 shows the turn-on and turn-off waveforms. The extracted specific switching energies, EON,sp and EOFF,sp, at RT are 0.46mJ/cm2 and 0.69mJ/cm2 respectively, approximately twice those measured in the unidirectional device. This is attribute to the doubling of on-resistance in CD configuration. We will show the comparison in switching energy at RT vs. 77 K at conference. We have demonstrated experimentally the electrical performance of our single packaged 3.3kV 4H-SiC Bidirectional Conv DMOSFETs at RT and 77K for the first time, showing bidirectional conduction and over 3kV bidirectional voltage blocking capability at 77K. Our results show that the specific on-resistance is only 2X higher, in conjunction with 4X in component count and >3X reduction in package area.

ABSTRACT. Silicon carbide (SiC) power devices are increasingly considered for their superior material properties, including wide energy bandgap, large critical electric field, and high thermal conductivity, which make them suitable for high-power operations. One of the challenges facing high power devices resided on their exposure to harsh environmental conditions, including humidity, temperature, and corrosive elements. These conditions are critical considerations in the design of power electronics [1,2]. In particular, the design of edge termination is crucial to manage the electric field distribution at the periphery of the active region of the device, achieving high breakdown voltage (BV) and reliability, but without sacrificing the active area of the device and hence increasing the chip cost [3]. However, the presence of contaminants, material defects and/or charging effects during device operation might contribute to electrical instability of performances, such as higher current leakage, BV degradation and bring to premature failure [4,5]. In this work, we focus our interest on the effect of charge accumulation at the material interface of SiC edge MOSFET. Through technical computer-aided-design (TCAD) simulations we analyzed the effect of localized negative and positive charge been placed at various dielectric passivation interfaces. As shown in figure 1, we find that a charge density superior to ±1e12cm-2 has an effect in perturbing the potential field distribution and moving the impact ionization point at the edge ring termination. The overall effect is a lower BV value compared to reference charge-free device. Moreover, the distance of the localized charge from SiC interface and type of charge have also an effect, since negative charge closer to the SiC interface have the higher impact on BV. To prove such an effect in real device operation, commercially derived SiC MOSFETs were fabricated by artificially introducing a density of defect charge on the edge passivation interface layers. Figure 2-a shows the IDSS curve of a reference charge-free and charged SiC MOSFET. A charge-free device shows an IDSS curve with a well-defined BV onset. Emission Microscopy (EMMI) analysis shows that at BV, the localization of impact ionization maximum spot lies at the margin of the active area (figure 2-b), consistent with TCAD design. When a charge is introduced, an anomalous bump of the IDSS curve appears. Such behavior is consistent with a shift of the BV at the device edge. Moreover, EMMI analysis shows that the BV localization moves to the external side of the device edge, in correspondence to the ring termination (figure 2-c). This behavior is consistent with the presence of a high density of negative charge and can be explained as the effect of charge unbalance of the ring termination played by charge contamination. Such results will be discussed in detail, taking into consideration innovative edge design concepts to improve the robustness of SiC power devices against charge contamination.

ABSTRACT. Silicon carbide (SiC) is widely adopted for high-voltage power device applications due to its superior material properties, including a wide bandgap and high critical electric field. These advantages are particularly significant in high-voltage applications, such as 10 kV and above, where Si-based devices are no longer viable. In such high-voltage SiC power devices, minimizing reverse leakage current and ensuring robust blocking characteristics are essential. Among the key design factors that influence reverse behavior, epitaxial layer engineering, edge termination design, and active cell geometry play critical roles [1-2]. This study investigates the impact of active cell geometry—specifically hexagonal and stripe designs—on the forward and reverse characteristics of 10 kV-class SiC Junction Barrier Schottky (JBS) diodes. Experimental results are complemented by 3D TCAD simulations to analyze the underlying physical mechanisms contributing to leakage current behavior. To investigate the influence of active cell geometry on reverse leakage behavior, two types of 10 kV-class SiC JBS diodes were fabricated: one with a hexagonal cell and the other with a stripe cell. Both designs shared identical P+ and Schottky widths, with Lpp = 2.0 µm and Lsch = 3.0 µm. Fig. 1 presents the top and cross-sectional views of both designs extracted from the GDS. As shown in Fig. 2, the forward conduction performance between the two designs was not significantly different. Under a reverse bias of 8 kV, however, the measured leakage current for the hexagonal cell was 4.0 × 10-8 A, while the stripe cell exhibited 1.0 × 10-5 A, indicating a difference of more than two orders of magnitude, as shown in Fig. 3. To understand the physical mechanisms underlying the observed leakage difference, 3D TCAD simulations were conducted for both hexagonal and stripe active cell designs. Fig. 4 shows the simulated top and cross-sectional views of both structures. Fig. 5 presents the electric field distributions extracted from the 3D simulation: the top row shows isometric views under reverse bias, the middle row illustrates electric field surface plots at the bottom of the P+ junction (ABCD plane), and the bottom row shows field distributions at the surface center of the Schottky region (A′B′C′D′ plane). Fig. 6 further compares the 1D electric field profiles along the drift depth. The stripe structure exhibits strong field concentration at the P+ junction corners, whereas the hexagonal design maintains a more uniform distribution. The peak electric field at the P+ junction bottom corner is 2.02 MV/cm for the hexagonal and 2.25 MV/cm for the stripe. At the Schottky region surface center, the local electric field is 1.13 MV/cm for the hexagonal and 1.43 MV/cm for the stripe. These results suggest that the concentrated electric field in the stripe cell lowers the Schottky barrier and enhances electron injection, leading to higher leakage. 10 kV-class SiC JBS diodes with hexagonal and stripe active cell designs were fabricated and evaluated. While both designs exhibited comparable forward conduction characteristics, a significant difference was observed in their reverse leakage behavior: the stripe cell design showed over two orders of magnitude higher leakage current than the hexagonal counterpart. 3D TCAD simulations revealed that the excessive leakage in the stripe structure originates from strong electric field crowding at the bottom corners of the P+ junctions, which lowers the Schottky barrier and induces enhanced electron injection. In contrast, the hexagonal cell design effectively mitigated such peak electric field and exhibited a more uniform electric field distribution across adjacent P+ regions. These findings highlight the critical role of active cell geometry in controlling reverse leakage and ensuring reliable blocking performance in high-voltage SiC JBS diodes. Adopting a hexagonal structure is thus a promising approach to suppress leakage current and enhance device robustness.

[1] A. Mihaila, R. A. Minamisawa, L. Knoll, V. K. Sundaramoorthy, E. Bianda, H. Bartolf, G. Alfieri, M. Rahimo, Mater. Sci. Forum, vols. 897, pp. 471–474, May 2017. [2] L. Liu, J. Wu, H. Xu, Z. Zhu, N. Ren, J. Zhang, K. Sheng, IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1226–1232, Mar 2022.

ABSTRACT. In recent years, SiC power devices have been widely used in a variety of applications, including trains, electric vehicles, industrial equipment, and information and communications. These applications require stable operation of SiC power devices, but the high defect density of the SiC wafers used to manufacture the devices significantly reduces device yields and reliability, preventing the widespread adoption of SiC power semiconductors in society. Therefore, we are promoting the construction of an evaluation and analysis platform for SiC power semiconductor materials and devices that will contribute to the realization of a stable supply system for high-quality SiC wafers and the high-yield production of highly reliable SiC power devices. We have established a multi-channel analysis technique for SiC wafer quality using several types of wafer inspection data acquired using different test principles and have achieved high-precision detection of defects in SiC epitaxial wafers. Furthermore, we have reported on the factors that lead to yield loss based on the correlation between wafer quality and SiC power device characteristics. In this study, we developed a multi-modal analysis technique that can easily perform correlation analysis between SiC epitaxial wafer quality and SiC power device characteristics, and report on the development of a device yield prediction method using this technique.

ABSTRACT. The application areas of imege sonsors are expanding to extreme environments such as high temperature and under high radiation. However, conventional silicon-based devices have operating limitations based on characteristic physical property value. In this research, active pixel sensors (APS) were fabricated on 4H-SiC substrates and its high-temperature operation characteristics were investigated. The temperature dependence of quantum efficiency (QE) and the output voltage was also evaluated with the fabricated PDs and APSs respectively. At high temperature, the increase of the band edge wavelength was observed, and the output voltage increase of the APSs was observed.

ABSTRACT. The development of “go anywhere” extreme-environment durable SiC Junction Field Effect Transistor – Resistor (JFET-R) integrated circuits (ICs) has been reported by NASA Glenn Research Center at previous ICSCRM meetings [1-3]. While prior generations of these prototype ICs have demonstrated unmatched T > 400 °C electronic stability in long-term operational tests, further maturation of this technology is necessary for practical manufacture and deployment of SiC JFET-R into harsh-environment application. This ICSCRM 2025 submission will report DC electrical characterization of the first wafer of JFETs from the IC Generation 12 prototype run that just completed fabrication (at GE Aerospace [4] and NASA Glenn). Since these measurements reveal significant differences compared to previously estimated/published IC Gen. 12 JFET circuit models, these results have triggered new/updated JFET models for use in circuit design and simulation. Fig. 1 shows the designed device cross-section and optical microscope image of a standard “M=6” JFET geometry [5] with gate width WG = 39 µm and gate length LG = 3 µm that was repeated across the 100 mm diameter IC Gen. 12 wafer. Fig. 2 compares examples of drain current vs voltage (I-V) characteristics measured from typical JFETs located near the wafer center vs. near the wafer edge during 25 °C on-wafer probe testing. Both characteristics show evidence of slight contact rectification near the I-V origin. Fig. 3 shows the measured threshold voltage VT0 as a function of die/device location on the wafer. The observed trend in which VT0 becomes more negative with increasing radial distance from the wafer center is qualitatively consistent with behavior (including parabolic shape evident in left plot of Fig. 3) of prior NASA IC prototype generations [6]. The left side of Fig. 3 also plots 25 °C threshold voltages employed for IC Gen. 12 circuit design/simulation [7] that are substantially different from measured VT0 values. As such discrepancy in VT0 can significantly impact circuit designs, updated IC Gen. 12 JFET SPICE models better approximating the measured devices will be presented at the conference. Since VT0 of the long-channel JFET structure is solely determined by the as-grown epilayer profile [6], the discrepancy reinforces the important need to improve JFET epilayer structure reproducibility and uniformity in order to accurately design, simulate, and mass-manufacture SiC JFET-R extreme-environment ICs. This first IC Gen. 12 wafer has now been diced with chips presently undergoing bonding into high temperature ceramic packages. Electrical characterization of packaged JFETs as a function of temperature will be presented at the conference along with corresponding updates to high temperature JFET SPICE models.

Acknowledgements: This work was conducted by The NASA John H. Glenn Research Center in Cleveland, OH USA with funding from the NASA Science Mission Directorate under the High Operating Temperature Technology (HOTTech), NASA Aeronautics Research Mission Directorate under the Transformational Tools and Technologies (TTT) project, and Defense Advanced Research Projects Agency (DARPA) High Operating Temperature Sensors (HOTS) project.     [1]   D. Spry et al., Mat. Sci. Forum, vol. 924, pp. 949-952 (2018) [2]   P. Neudeck et al., Mat. Sci. Forum, vol. 963, pp. 813-817 (2019) [3]   P. Neudeck and D. Spry, Mat. Sci. Forum, vol. 1004, pp. 1057-1065 (2020) [4]   GE Aerospace, Niskayuna, NY, https://www.geaerospace.com [5]   P. Neudeck and D. Spry, https://ntrs.nasa.gov/citations/20190025716 [6]   P. Neudeck, D. Spry, L. Chen, Mat. Sci. Forum, vol. 828, pp. 903-907 (2016) [7]        P. Neudeck, https://ntrs.nasa.gov/citations/20190026451

ABSTRACT. This abstract presents a detailed comparison of the electrical characteristics of several Bi-Directional MOSFET (BiD-MOS) design approaches. It was found that the monolithic integration approach exhibited negligible differences in conduction, blocking, and switching characteristics when compared to its 2-Chip counterpart. However, during short-circuit withstand time testing, severe gate oscillations were observed in the 2-Chip design—an issue not present in the monolithic configurations. Therefore, due to its robust electrical performance, monolithic integration is established as a promising design approach for creating an efficient and reliable Bi-Directional Switch.

ABSTRACT. Silicon carbide (SiC) semiconductor devices provide significant advantages over conventional silicon-based semiconductors, such as higher operating temperatures, greater power density, and superior thermal conductivity. However, the limited development of SiC logic devices has forced SiC-based systems to integrate with silicon CMOS circuits, complicating the fabrication of SiC integrated circuits (ICs). Therefore, the development of next-generation SiC CMOS logic devices is critical for realizing System-on-Chip (SoC) technologies based entirely on SiC. In this study, SiC CMOS FinFETs were designed and optimized through Technology Computer-Aided Design (TCAD) simulations (Sentaurus Synopsys). The FinFET structure was selected due to its superior gate controllability and higher integration density compared to planar structures. To ensure simulation accuracy, material and device parameters were calibrated against measurement data from fabricated SiC planar MOSFETs. Optimization focused on achieving CMOS-compatible threshold voltage (Vth) and subthreshold swing (SS). The dependence of Vth and SS on fin width (WFin) and fin height (HFin) was analyzed. Reducing WFin below 60 nm improved Vth and SS, with performance saturation observed below 30 nm, suggesting a practical scaling limit. Increasing HFin enhanced gate control, and 100 nm was determined to be the optimal height, balancing Vth and SS characteristics. To address the mobility asymmetry between n-type and p-type devices in SiC, a multi-fin structure was adopted for p-type FinFETs. As a result, both n-type and p-type devices achieved Vth and SS values suitable for standard CMOS operation. Furthermore, the fabricated CMOS inverter operated at a low supply voltage (Vdd) of 3.3 V—significantly lower than previous reports—while maintaining compatibility with conventional CMOS technology. The resulting FinFET-based binary inverter achieved a maximum voltage gain of 8.2 and a noise margin of 0.92 V, maintaining robust operation up to 500 K, and demonstrating superior thermal stability compared to Si-based CMOS devices. These results suggest that optimized SiC CMOS FinFETs are promising candidates for high-temperature and low-power integrated systems.

ABSTRACT. Reliability of gate oxides in silicon carbide power MOSFETs has significantly improved in recent years; however, it might take further effort to reach the same reliability level as that offered by silicon power devices. A significant roadblock comes from limited set of available efficient tools. Reliability-related device development techniques are often based on statistical analysis of failures post lengthy stress tests with inspection of failure locations, if such inspection is possible. An option for direct imaging the gate leakage could simplify development of reliable MOSFETs. In this presentation we demonstrate a prospective approach based on imaging visible light emission from the gate-oxide interface to SiC under negative-bias gate stress conditions. Light emission from the interface of gate oxide to SiC was first reported for lateral SiC MOSFETs by Macfarlane and Stahlbush from the NRL [1], who employed pulsed gate biasing to form an inversion channel with subsequent release of the interface-trapped electron charge. This excitation technique is similar to well-known charge pumping. Depending on the voltages of high and low gate-bias levels, visible-light emission spectra correspond to either bulk recombination in SiC or to recombination at the oxide interface states. A recent series of spectral and imaging studies applied the Macfarlane-Stahlbush technique to SiC power MOSFETs; which summary can be found in S. Naureen1 [2]. In this study we applied high negative DC bias to the gate of a planar power MOSFET in SiC to force relatively high current of around 100 µA through the gate oxide. Because of the rapid increase of the oxide current density with electric field, the current flow pattern becomes very sensitive to even minor field non-uniformity which provides efficient means of troubleshooting. Backside contact metal was polished away from SiC, and emission images were captured from the crystal backside using a microscope with a cooled CCD camera. Low-magnification emission image of a power MOSFET shown in Fig. 1a shows fairly uniform gate current density. No emission comes from the gate pad or the gate runner. High-magnification image in Fig. 1b reveals the active device structure. In order to locate the regions of peak light emission, reflected-light micrograph was taken through the wafer backside (Fig. 2a) and complemented by two aligned insets, showing the gate outline and the gate emission. Peak light intensity originates from the regions corresponding to the interface of the gate oxide to the p-well. Those regions are shown on a schematic cross-section in Fig. 2b. The origin of microscopic-scale emission non-uniformity is yet unclear; it might come from step bunching of the SiC surface or from process-related fluctuations of the p-well width. Shown in Fig. 3a is the band structure of the MOSFET active channel under the conditions of negative-bias gate stress. High-field conductance of silicon dioxide is governed by conduction-band electrons, which are driven by electric field from the gate to towards interface to SiC. The holes of the SiC valence band are driven to the same interface, at which interface they recombine with the electrons. An example image of a problematic MOSFET design is shown in Fig. 3b, for which the imaging technique reveals highly non-uniform gate current flow under negative-bias gate stress.

ABSTRACT. In this study, 4H-SiC neutron sensors were designed with three transistor-active pixel sensor (3T-APS) structure and a parasitic n-p-n structure in the detection area. Their performance is investigated by using LT spice simulation. Because of high absorption thermal neutron cross-section of 3835 barns, 10B can be potential candidate to neutron conversion layer. By changing the thickness of aluminum layer under neutron converter with 10B, it is possible to control the energy enters the detection area and thereby change the number of electron-hole pairs generated during the ionization process. As the simulation results, with the thicker Al layer of 2.2 μm, the output potential changed slightly of 45 mV compared to without neutron irradiation. On the other hand, a thinner Al layer of 0.3 μm, a larger number of electrons were generated in the detector region, thereby the output voltage signal changed clearly of 175 mV compared to without neutron irradiation. The simulation results show the neutron detection ability of SiC neutron sensors based on 3T-APS structure and a parasitic n-p-n structure in the detection area. These results laid the foundation for the fabricating SiC neutron sensors for BNCT and testing of thermal neutron irradiation.

ABSTRACT. Silicon Carbide (SiC) MOSFETs have attracted significant interest in high-power applications due to their superior material properties, such as wide bandgap, high critical electric field, and excellent thermal conductivity. These attributes enable lower conduction and switching losses, making SiC devices well-suited for next-generation power electronics [1]. In the development of SiC MOSFETs, device layout optimization plays a critical role in enhancing both static and dynamic performance. This study investigates newly designed 1.2 kV/17 mΩ SiC planar MOSFET topologies, with an emphasis on their impact on key electrical characteristics. Specifically, we evaluate how different cell geometries affect specific on-resistance (Ron,sp) and switching behavior. In addition, we examine the influence of gate runner design on internal gate resistance (Rg) and switching losses [2]. The results presented in this work underscore the importance of layout-level engineering in improving the efficiency and reliability of high-voltage SiC MOSFETs and offer valuable design insights for future device optimization. Fig. 1 presents cross-sectional views of three topologies: (a) Stripe, (b) Wavy, and (c) Octagonal. The Wavy and Octagonal structures are derived from the conventional Stripe layout, each exhibiting distinct electrical behavior. Among them, the Octagonal design achieves the lowest specific on-resistance (Ron,sp), demonstrating a 13% improvement over the Stripe topology, as shown in Fig. 2(a). The box plot in Fig. 2(b) further supports this result by indicating a lower mean RDS(on) and reduced variability for the Octagonal structure compared to the Stripe and Wavy designs. While the Octagonal design exhibits superior static performance, dynamic behavior is equally critical for achieving high-efficiency operation. To this end, we further investigated the influence of gate runner configuration on switching performance. As shown in Fig. 3, both single-gate and dual-gate runner layouts are evaluated. Gate runner design is a key factor affecting internal gate resistance and switching behavior, particularly in high-speed operation. Optimizing the gate runner structure enables reduced switch losses, shorter transition times, and improved overall device efficiency. The impact of gate runner configuration was assessed using double-pulse testing. The results, shown in Fig. 4 and Fig. 5, reveal that the dual-gate runner design significantly reduces both turn-on and turn-off losses compared to the single-gate runner configuration. Specifically, the dual-gate runner exhibited an approximately 25% reduction in total switching loss at 800 V and 50 A, primarily due to decreased internal gate resistance. This confirms that gate runner optimization directly enhances the dynamic performance of high-voltage SiC MOSFETs. In conclusion, the Octagonal SiC planar MOSFET topology offers superior static performance, achieving a 13% reduction in Ron,sp over the conventional Stripe design. Additionally, implementing a dual-gate runner layout effectively reduces switching losses by approximately 25%. These results highlight the effectiveness of layout-level optimization in improving both conduction and switching performance in high-voltage SiC MOSFETs.

ABSTRACT. SiC diodes are well-established in power applications due to their high voltage endurance, but they suffer from high VF, leading to increased conduction losses. This study introduces a novel design, the Lateral Pinched Barrier Rectifier (LPBR), which modifies the traditional Trenched Junction-Pinched Barrier Rectifier (TBR) by rotating its vertical channel to a lateral orientation. LPBR simplifies the fabrication process by controlling key factors such as channel width and length through implantation and lithography. Simulation results demonstrate that LPBR achieves a favorable balance between low VF and high on/off ratio, making it a promising solution for reducing conduction losses in various applications. The device structure, process flow, and performance comparisons with SBD and JBS diodes are discussed, highlighting LPBR's potential despite challenges in channel width and doping concentration control.

ABSTRACT. SiC MOSFET are widely used in tuyere industries industries such as new energy vehicles, transportation railways, and photovoltaics, thanks to their advantages of high temperature and high voltage resistance, high frequency operation, low power loss, and high switching speed. Compared with planar MOSFET devices, SiC trench MOSFET have advantages such as lower on-resistance and higher power density. However, they also face a stronger electric field aggregation effect and have the risk of easy breakdown of the gate oxide layer. This paper is based on the 8-inch SiC process platform of the laboratory and independently develops a SiC trench MOSFET with a deep P-region protection. Structurally, an Inverted T-shaped deep P-injection region is formed through a self-aligned secondary injection process. Combined with the JFET injection, while reducing the on-resistance and increasing the current density, the protection ability of the trench gate oxide is not reduced. In terms of the process, the SiC etching process is optimized, the etching morphology of the trench corner is improved, the roughness of the trench sidewall after annealing is optimized, and the gate oxide is deposited in the LPTEOS method and passivated with NO to solve the problem of the inhomogeneity of the sidewall and bottom gate oxide in the thermal oxidation process. Finally, an Al ion injection with a P-region junction depth greater than 1.7μm and a doping concentration greater than 1E18cm⁻³ is achieved; the trench width is 0.5-0.8μm, the depth is greater than 0.9μm, the radius of the bottom fillet after sacrificial oxidation is greater than 90nm, and the sidewall roughness is less than 1.0nm; the gate oxide on the trench sidewall and bottom is uniform and controllable, and the hard breakdown field strength of the gate oxide is greater than 6MV/cm; in addition, according to the simulation results of Sentaurus TCAD, the doping concentration of the drift region in the device design is 1E16cm⁻³, and the thickness is 12μm; the doping concentration of the P-type base region is 2E17cm⁻³, and the depth is 0.7μm; the doping concentration of the current spreading layer is 1E16cm⁻³, and the depth is 1μm; the doping concentration of the P⁺ shielding layer is 1E19cm⁻³, and the depth is 1.7μm. Based on the above parameters, the device finally achieves a breakdown voltage of 1500V, an on-resistance specific value of 1.9mΩ·cm⁻², and a threshold voltage of 3V. The feasibility of the simulation parameters and the superiority of the laboratory trench SiC MOSFET process platform are verified.

ABSTRACT. SiC power semiconductors have gained increased prominence in applications such as electric vehicles and industrial motor drives, where high-voltage operation and elevated temperatures place demanding requirements on device robustness. Among the most critical metrics in these contexts are the short-circuit safe operating area (SCSOA) and the short-circuit withstand time (SCWT) (Fig. 1), which together reflect a device’s ability to endure large currents and associated thermal stress without failure [1]. This work has researched an embedded Schottky barrier diode (SBD) architecture in a 4H-SiC MOSFET, with Schottky characteristics differ depending on nickel silicide formation temperature (Fig. 2). The results confirm that carefully engineered NiSi formation in the SBD region promotes more even heat distribution during short-circuit events, thereby preventing the localized overheating that typically limits SCWT. By dispersing current flow away from the gate region, this results approach enhances device reliability under harsh electrical and thermal conditions (Fig. 3). Overall, these results provide a pathway for improving short-circuit capabilities in high-power SiC MOSFETs, offering a valuable tool for developers of next-generation automotive inverters and industrial power converters. Fine-tuning the silicide process parameters such as RTP temperature could significantly elevate the SBH in the SBD region, enabling effective heat management and improved short-circuit performance. Consequently, incorporating embedded-SBD structures with optimized Ni silicide processing stands out as a promising solution to the challenges of compact, efficient, and robust power electronics [2].

ABSTRACT. SiC nanostructures have garnered significant research attention owing to their unique high-voltage and high-current characteristics [1]. SiC nanostructures are crucial in high-temperature and high-power electronic device applications [2]. Most SiC nanostructures are typically in the 3C-SiC form, and synthesizing 4H-SiC and 6H-SiC nanostructures remains a challenging task. 4H-SiC and 6H-SiC nanostructures have potential applications in high-temperature and high-power electronic devices owing to their high thermal stability, high breakdown voltage, and excellent thermal conductivity [3]. SiC nanostructures are stable without raw material loss even in high-temperature and extreme environments. Thus, they have applications in power semiconductors, optoelectronic devices, and secondary batteries. In this study, SiC nanostructures were grown via the mixed-source hydride vapor-phase epitaxy method with Si and graphite sources, and the growth mechanism was elucidated. The mixed-source HVPE equipment comprises a furnace with three high-temperature zones (T ≈ 1200 °C) and a specially designed graphite boat placed within a quartz reactor tube. The sources—20 g of Ga, 20 g of Al, 20 g of graphite, and 30 g of Si—were mixed and placed in the graphite boat. Cylindrical graphite with an average diameter of 2 mm and a length of 8 mm was used as the graphite source. Small pieces of n-type Si substrates were used as the Si source. The high-purity Ga (7N) removed oxides and nitride films from the surface of Al and thereby, promoted the reaction between Al and HCl. The 4N metallic Al induced the formation of AlN nanostructures, and the grown AlN nanostructures adsorbed Si and C elements, resulting in the growth of SiC nanostructures. HCl and NH3 were used as reaction gases, and N2 was used as the carrier gas. HCl, NH3, and N2 were flown into the quartz reactor tube through the inner quartz tube at flow rates of 200, 1000, and 5000 sccm, respectively. The SiC nanostructures were grown at a growth temperature of 1200 °C and a growth duration of 60 min. The SiC nanostructures primarily grew between the SiC substrate and the graphite source, whereas carbon nanostructures grew on the surface of the graphite source. The properties of the SiC nanostructures grown in this study were characterized using field-emission scanning electron microscopy, energy dispersive spectroscopy, Raman spectroscopy, X-ray diffraction, and high-resolution transmission electron microscopy. The d-spacing between two adjacent lattice fringes was 0.25 nm, which is in good agreement with the interplanar spacing in the (111) or (102) plane directions of SiC. Thus, the growth of SiC nanostructures via the HVPE method is feasible. SiC nanostructures grown via the mixed-source HVPE method are expected to be an innovative example in the field of semiconductor growth.

This work was supported by the Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Korea government (MOTIE) (RS-2022-00154720, Technology Innovation Program Development of next-generation power semiconductor based on Si-on-SiC structure).

[1] C. Vatankhah and H.A. Badehian, Solid State Commun. 344, 114672 (2022). [2] X. She, A.Q. Huang, Ó. Lucía, and B. Ozpineci, IEEE Trans. Ind. Electron. 64, 8193 (2017). [3] G. Wei, W. Qin, G. Wang, J. Sun, J. Lin, R. Kim, D. Zhang, and K. Zheng, J. Phys. D: Appl. Phys. 41, 235102 (2008).

ABSTRACT. Currently, Si is a crucial material in major industrial sectors, exhibiting various structural forms under external conditions such as pressure and temperature. Si-based semiconductors have an indirect energy band in the natural cubic phase, whereas 2H-Si has a direct energy band [1]. In addition, unlike bulk materials, nanoscale materials exhibit unique electrical, magnetic, optical, and mechanical properties, enabling the development of innovative technologies in various industrial fields [2]. 2H–Si single crystals with a direct energy band are used in various applications related to the silicon industry, such as solar cells, secondary batteries, power semiconductors, optical devices, and monolithic silicon photonics optoelectronic integrated circuits, in which optical and electronic devices are integrated simultaneously. These crystals can revitalize the industrial and technological applications of integrated circuits. The difference between direct and indirect bandgaps is one of the important characteristics that determine the efficiency of solar cells. Notably, the predicted bandgap of 2H–Si microneedle crystals is 1.65 eV, which is different from the indirect bandgap of conventional cubic Si (~1.1 eV). This difference in bandgap indicates that the 2H–Si microneedles can be used as materials in light-emitting devices. We employed the mixed-source HVPE method and designed a graphite boat structure with inclined blocks to grow straight Si microneedles with a longitudinal growth rate of 6.7 × 104 Å ·s−1, which could not be explained by conventional crystal growth mechanisms. The growth mechanism was identified by FE-SEM electron microscopy. AlN nanowires were formed at 1250 °C by the supplied NH3, and Al membranes were formed by controlling the timing of NH3 supply cessation. The Al membranes were then separated into elliptical Al membranes owing to PRI, and SiCln generated by HCl was absorbed into the membrane, forming Si droplets. Each Si droplet simultaneously progressed into a Si microneedle, leading to the formation of straight microscale 2H-Si microneedles with an ultrahigh growth rate. The average spacing of the Al membranes was 4 μm, implying that approximately 10,000 elliptical Al membranes absorbed the SiCln molecules, almost simultaneously, to grow 40-mm 2H-Si microneedles within 100 min. The PRI principle facilitated separation of the Al membranes, which appeared to have been generated simultaneously, within 0.166 s [3]. The HRTEM measurements showed that the grown 2H-Si microneedles exhibited a dumbbell structure and an ABAB stacking arrangement in the [112 ̅0] direction, a characteristic of 2H–Si. This result was consistent with the crystallographically symmetric structure of P63/mmc (D46h) [2]. In addition, the Raman spectroscopic results revealed the characteristics of Si allotropy. Therefore, the mixed-source HVPE growth method was used to elucidate the mechanism by which nanoscale phenomena contribute to the growth of microscale crystals. In addition, a method was proposed for growing 2H–Si microneedles at a remarkably high crystal growth rate that cannot be realized using conventional growth methods.

This work was supported by the Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Korea government (MOTIE) (RS-2022-00154720, Technology Innovation Program Development of next-generation power semiconductor based on Si-on-SiC structure).

[1] J. S. Kasper and R. H. Wentorf, Jr., Science 197 599 (1977). [2] W Lu, CM Lieber, Nat. Mater. 6 841 (2007). [3] Y Zheng, H Bai, Z Huang, X Tian, FQ Nie, Y Zhao, J Zhai, L Jiang, Nature 463, 640-643 (2010).

ABSTRACT. Over the past several decades, silicon has maintained its position as a major focus of the semiconductor industry [1-2]. However, in recent years, wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) offer superior performance compared to silicon-based semiconductors, owing to their high breakdown field and electron saturation velocity, making them ideal for operation in high-frequency and high-power conditions [3]. SiC substrates are frequently employed in AlGaN/GaN high-electron-mobility transistors (HEMTs). The lattice constant and thermal expansion coefficient of SiC closely match those of GaN, minimizing stress during the growth process and improving the device's performance and reliability [4]. Despite these advantages offered by SiC, the power industry still demands high-frequency performance and operational reliability in high-power applications, which is why the introduction of a field plate in AlGaN/GaN HEMTs aims to enhance the device's operational reliability in these conditions. However, the addition of a field plate inevitably increases the device capacitance, which directly degrades RF performance. Fig 1. shows the cut-off frequency (fT), and parasitic gate-to-source capacitance (Cgs) with and without field plate structure. Results indicate that the introduction of the field plate leads to an increase in parasitic capacitance, which results in a reduction of fT by 23.26 %. Therefore, it is crucial to optimize the field plate configuration to improve RF performance while minimizing the reduction in the device’s breakdown voltage (VBD). In this study, we systematically investigate the impact of top field plate length (LTFP) on both electrical characteristics and transient responses of AlGaN/GaN HEMTs using technology computer-aided design (TCAD) simulation. Fig. 2 illustrates the field plate configurations in AlGaN/GaN HEMT device. To assess the effect of LTFP, we first compare the fT and Cgs and analyze how these variations affect the RF characteristics. Then, simulations are conducted to investigate the VBD and transient responses. Finally, we propose the optimal top field plate configuration considering Johnson’s figure-of-merit (JFOM), which can be expressed as JFOM = VBD × fT, and the transient responses. As a result, we propose valuable insights for optimizing top field plate design to balance electrical performance and reliability, thus contributing to the advancement of AlGaN/GaN HEMTs for high-frequency and power electronic systems.

ABSTRACT. The single negatively charged silicon vacancy at hexagonal lattice site gives rise to the V1 spectral line in SiC and is viewed as a promising spin-qubit candidate for future applications in quantum cryptography, communication and sensing. We perform TCAD simulations for a variety of electronic devices to examine which type of structure is best suited for charge-state stabilization and emission-line tuning of silicon vacancies in c-plane oriented 4H silicon carbide (4H-SiC). For this purpose, the electronic structure needs to (i) achieve local field strengths aligned with the crystal c-axis of 5 to 20 MV/m, (ii) stabilize the charge state of the silicon vacancy by controlling the local Fermi level, (iii) be thin enough to allow for an integrated single-mode waveguide and (iv) minimize the absorption of the evanescent wave due to metal contacts. These criteria are investigated for various devices using the latest version (W-2024.09) of the Sentaurus device simulation tool from Synopsys. First results show that specially designed vertical pin diodes are able to achieve the requirements on electric field strength and orientation, while commonly used signal-ground-modulators do not achieve the required field strengths.

ABSTRACT. In recent years, the utilization of diamond-based hybrid spin defect systems, which in-volve the nitrogen-vacancy (NV) color center and various nuclear spin species, has garnered significant attention. These systems hold promise as platforms for atomic-scale magnetic field sensors and serve as building blocks for quantum information processors. This is attributed to their robust nature and the ability to achieve high-precision spin control even at ambient tempera-tures. At KIST (Korea Institute of Science and Technology), we are actively involved in the de-velopment of a comprehensive framework for utilizing hybrid electron-nuclear spin defect regis-ters. Our approach encompasses the entire spectrum of activities, ranging from the develop-ment of optimal control tools to device engineering, with the aim of realizing an ensemble spin cluster quantum node for diverse quantum applications. In this work, I will present our recent works focused on the coherent manipulation of a spin cluster system in diamond for quantum information applications. Additionally, I will discuss our latest research efforts involving the application of nano-fabrication techniques to engineer a qubit cluster system. Finally, I will present an example that demonstrates the utilization of an electron-nuclear spin hybrid system for simulating topological phase transitions in solid-state systems.

ABSTRACT. Gallium nitride (GaN) is a promising material for high-power semiconductor devices due to its wide bandgap and high electron mobility. While AlGaN/GaN high-electron-mobility transistors (HEMTs) typically operate in a normally-on mode, incorporating a p-GaN layer on top of the AlGaN/GaN heterostructure enables normally-off operation by depleting electrons at the interface. There are two main types of p-GaN gate HEMTs: Schottky and Ohmic. The latter, also known as gate injection transistors (GITs) [1], offer higher drain current due to conductivity modulation through hole injection. Moreover, Ohmic p-GaN gate contacts help mitigate threshold voltage (Vₜₕ) instability by injecting holes into the AlGaN/GaN interface [1, 2]. However, these devices often suffer from high gate leakage current even at low gate voltages [3]. In this study, we propose a novel Ohmic p-GaN gate structure featuring dual Al₂O₃/SiO₂ dielectric layers in a T-gate configuration to suppress gate leakage current. Fig. 1 shows cross-sections of the simulated devices. The epitaxial structure consists of an 80 nm p-GaN layer, a 15 nm Al0.15Ga0.85N barrier, a 105 nm GaN channel, and a high-resistivity buffer layer on a Si (111) substrate. Device dimensions include a gate length (LG) of 3 µm, gate-to-source spacing (LGS) of 1 µm, and gate-to-drain spacing (LGD) of 6 µm. The proposed device uses a T-gate structure with dual Al₂O₃/SiO₂ insulator layers positioned only at the gate edge, maintaining Ohmic contact at the gate center. The gate foot length, where the metal directly contacts the p-GaN, is 1 µm. The gate metal work function is set at 6.2 eV. As shown in Fig. 2, the proposed gate structure significantly reduces gate leakage current. The dual Al₂O₃/SiO₂ insulator stack increases the effective potential barrier at the insulator/p-GaN and p-GaN/AlGaN interfaces, limiting both hole and electron injection. Consequently, the device exhibits a higher gate forward breakdown voltage compared to both the reference device and a device using only SiO₂ (see Fig. 3). The band alignment between the two dielectric layers helps reduce the peak electric field under the gate, improving breakdown performance. Additionally, Fig. 4 demonstrates that the proposed structure achieves higher off-state breakdown voltage and significantly lower off-state leakage current. The reduction in peak electric field under the p-GaN layer and suppressed gate leakage contribute to enhanced off-state reliability. This study presents a novel T-gate structure with dual Al₂O₃/SiO₂ insulator layers that effectively suppresses gate leakage current in Ohmic p-GaN gate HEMTs while preserving hole injection. The design offers improved gate and off-state breakdown characteristics, demonstrating its potential for robust high-power applications. This research was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government (Ministry of Science and ICT) (RS-2024-00431359) and (2022M3I8A1077243).

[1] Y. Uemoto et al, IEEE Trans Electron Devices, 54, pp. 3393-3399, (2007) [2] L. Ghizzo et al., Solid-State Electronics, 214, pp.108868 (2024). [3] W. Lu et al., 2022 19th China International Forum on Solid State Lighting & 2022 8th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS), pp. 527–531 (2005).

ABSTRACT. Electric fields of pin-diodes (E||c) allow functionalization of silicon vacancies (VSi) for quantum sensing, communication and computing applications [1]. Using lateral pin-diodes on 4H-SiC a-plane wafers enable convenient resonant excitation across the wafer surface (a⊥c). Since these pin-diodes can be manufactured in a CMOS-compatible process on the 4H-SiC platform [2, 3], co-integration of advanced integrated electronics and photonics is enabled which is a key step towards quantum photonic integrated circuits (QPICs) [1]. In this work we demonstrate the compatibility of the CMOS process on c-plane and a-plane wafers exemplarily using a pMOS field effect transistor, thus allowing transfer of state-of-the-art devices and circuits to a-plane wafers. Furthermore, a tunneling diode is proposed as possible on-chip light source for initial off-resonant excitation of VSi. The electronic devices were fabricated using a CMOS-compatible process [2] on 35 mm on-axis 4H-SiC a-plane substrates [3]. As reference, the same devices were also manufactured on 150 mm c-plane wafers. On both substrate types 10 μm thick n-type epitaxial layers were grown (see Table I – top row). The pMOS transistors consist of aluminum implanted p-type source and drain areas with a n-type epitaxial channel region. The tunneling diodes were designed as overlapping nitrogen and aluminum implanted profiles. Dry thermal oxidation with subsequent NO annealing [3] and a LPCVD n-type poly-Si serve as gate stack of the transistors. NiAl ohmic contacts were formed by 2 min 980 °C rapid thermal annealing step. Platinum with a Titanium adhesive layer was used as metallization. The transfer and output characteristics of exemplary pMOS transistors are shown in Fig. 1. The transistors show an excellent IOn to IOff ratio. The threshold voltage of the transistors on a-plane wafers is clearly shifted to higher negative voltages compared to those on c-plane wafers. The increased interface state density (Dit) and the higher channel doping contribute to this shift. In saturation region (Fig. 1b) an almost constant current for a-plane transistors in contrast to the c-plane samples can be observed. This reduced short channel effect is explained by the higher epitaxial layer doping. In the linear region (Fig. 1b – Inset) a completely ohmic behavior nonetheless the higher on-resistance for a-plane is observed. The mobilities as a function of the VTh corrected gate voltage (Fig. 2) show very similar characteristics with peak mobility voltages |VG – VTh| of 2.3 V (a-plane) and 1.4 V (c-plane). The reduced maximum mobility on a-plane wafers can be explained by the increased channel doping as well as Dit [4]. Key parameters of all manufactured devices are summarized in Table I. Transistors manufactured in a similar process flow are also already shown to remain functional down to 14 K [5]. The tunneling diodes exhibit electroluminescence in forward bias (LED) as well as reverse biasing (TD). The recorded spectra at room temperature are shown in Fig. 3a. The forward spectrum peaks at 392 nm and 479 nm can be attributed to N donor to valence band and N donor to D1 defect transitions, respectively [6]. In reverse bias tunneling enhanced light emission with a broad spectrum takes place. This is due to recombination processes between donor and acceptor states in the co-implanted region. Since acceptor and donor state cannot be at the exact same position in the crystal, electric field driven tunneling processes must enable the recombination. Thus, the distance between donor and acceptor combined with the band-bending determines the emission wavelength, leading to a broad emission spectrum. This broad spectrum with emission of up to 44% (a-plane) or 33% (c-plane) of peak intensity being in the region of 730 nm to 785 nm can be used for off-resonant excitation of VSi. The deviations in fine structure of the spectrum are explained by different interference of the emission with overlaying passivation layers, having slightly different thicknesses for c-plane and a-plane samples. Cryogenic measurements (Fig. 3b) show functionality of the tunneling diodes even at 4 K. At cryogenic temperatures the observed currents rise slower for both forward as well as reverse biasing, but still light emission is observed. The jump of the current in forward biasing is explained by the need to re-ionize frozen-out charge carriers at low temperatures using the internal electric field of the tunneling-diode [7]. In conclusion, the compatibility of CMOS processing on a-plane and c-plane wafers is demonstrated exemplarily using a pMOS transistor, thus enabling transfer of advanced electronics to a-plane wafers. In addition, a reverse biased tunneling diode is shown to be a possible light source with up to 44% of the peak intensity at wavelengths relevant for off-resonant excitation of VSi.

ABSTRACT. Micro- and nanomechanical resonators are important elements for future quantum technology applications, e.g. for the entanglement of quantum states of color centers via mechanical oscillations. For the fabrication of the required structures, such as cantilevers, disk resonators or freestanding membranes, high-quality 3D shaping techniques for SiC are key. We build upon our previously published work on monolithic electrochemical etching (ECE). This 3D etching technique relies on doping contrast (p-type SiC vs. n-type SiC), which introduces an etching contrast in ECE, allowing for selective etching of p-type SiC while preserving n-type SiC. Here, we demonstrate the fabrication of large-scale ultrathin freestanding 4H-SiC layers and investigate the dependence of the etching process on the aluminum doping concentration.

ABSTRACT. Owing to its remarkable properties, such as highly transparent conductive oxide, high breakdown electric field, and wide energy bandgap, β-Ga2O3 is a potential material for power devices [1]. However, achieving high crystal quality and smooth surface β-Ga2O3 hetero-epilayers with single-rotational domains (RDs) or minimizing RDs is still challenging because of different structures and the large misfit between films and substrates. β-Ga2O3 (-201) epilayers have grown widely on the affordable C-plane sapphire substrates. However, growth of the (-201) β-Ga2O3 epilayer on (0001) C-axis oriented sapphire substrates resulted in in-plane RDs with six-fold symmetry because of the hexagonal symmetry structure of the C-axis oriented sapphire substrate [2]. To overcome the stated challenge and achieve high-crystal-quality epilayers, many researchers have shown the effect of vicinal surface epitaxy (VSE) on the growth of hetero- and homoepitaxial layers [3-4]. However, there are no detailed studies on the effects of steps and terraces on the growth behaviors in VSE. Quality of the films is strongly determined by the terrace uniformity and kink density on the growing surface in VSE. Therefore, a detailed understanding of surface diffusion length and terrace width is in VSE is the key to obtain the desired β-Ga2O3 heteroepitaxial films. Thereby, in-situ monitoring and characterization of step-terrace array structure (or/and surface morphology) on film/VSE would be advantageous for understanding the mechanism of growth films on VSE compared to the growth film on the non-miscut substrate surface. In this study, the step arrays of miscut sapphire substrates from ∆a=00 to ∆a=140, and growth of β-Ga2O3 epilayers on them during plasma-assisted molecular beam epitaxy (PAMBE) have been assessed by reflection high-energy electron diffraction (RHEED). As shown in Fig. 1. split streaky RHEED was observed due to the coherent interaction of the incident electron beam (E-beam) with periodic step arrays on VSE. It is confirmed that the inclination of the RHEED pattern is due to surface steps and terraces. Azimuths are maintained and illustrated on the RHEED images. Additionally, the space between the split RHEED streaks increases proportionally with the miscut angle and inversely correlates with terrace width. indicating dimensional parameters relevant to terrace width and in-plane lattice spacing. Moreover, RHEED and atomic force microscopy (AFM) observations showed a growth transition mechanism from 3D growth to step-edge-guided nucleation growth mode, resulting in improved smooth surface morphology and crystallinity of the β-Ga2O3 epilayers due to suppressing RDs. The best crystallinity of the (-201) β-Ga2O3 epilayers was obtained from the grown films on ∆a=120 and ∆a=140 miscut substrates, in which phi-scan measurements indicated a single-domain (SD) and two domains separated by 1800, respectively, as shown in Fig. 2(a). The growing of single domain, i.e., single crystalline epitaxial layers on the high miscut substrates implied that the adatom diffusion length could be engineered to align with step-edge height. High-resolution X-ray diffraction (HRXRD) measurements for the omega rocking curves showed decreased full width at half maximum values with increasing substrate miscut angles, which meant the improved crystal quality as shown in Fig. (b). Also it was observed that d-spacing of the (-201) plane increased for the single crystalline film on ∆a=140 miscut substrate. Our findings give us a detailed understanding of the PAMBE step-edge-guided nucleation growth of oxide thin films on VSE and can open a pathway to achieving high-quality crystalline oxide thin films by controlling the orientation of the growing films in VSE.

This research was supported by National Research Foundation of Korea (NRF) (grant No. 2020R1I1A3073787).

[1] M. Higashiwaki, K. Sasaki, H. Murakami, Y. Kumagai, A. Koukitu, A. Kuramata, T. Masui, and S. Yamakoshi, Semicond Sci Technol 31, (2016). [2] S. Nakagomi and Y. Kokubun, J Cryst Growth 349, 12 (2012). [3] Y. Oshima, E.G. Víllora, and K. Shimamura, J Cryst Growth 410, 53 (2015). [4] T.S. Chou, J. Rehm, S. Bin Anooz, O. Ernst, A. Akhtar, Z. Galazka, W. Miller, M. Albrecht, P. Seyidov, A. Fiedler, and A. Popp, J Appl Phys 134, (2023).

ABSTRACT. Beta-phase gallium oxide (β-Ga2O3), which has a monoclinic structure, has emerged as a next-generation power semiconductor material with a wide band gap of 4.7 to 5.2 eV [1]. Among various methods for growing β-Ga2O3 single crystals, Edge-defined Film-fed Growth (EFG) has the advantages of a fast growth rate and easy crystal plane control compared to other growth methods [2]. However, despite these advantages, various challenges still need to be addressed in the EFG method, such as doping uniformity, polycrystalline contamination, and defect control. Twin defects are a common problem in a crystal grown by the EFG method, which limits the production of large single crystal substrates [3]. In contrast, other growth methods for β-Ga2O3 crystals have not reported any occurrence of twinning yet. In the EFG method, twin defects are commonly formed in the early stages of the process, and the density of twin boundaries (TBs) is greatly affected by the temperature gradient during the ‘shouldering’ process [4]. Since twin boundaries formed at the shoulder part of a β-Ga2O3 ingot in the initial stage of the EFG method, and propagate throughout the entire ingot, their control is essential for achieving high-quality single crystals [5]. Accordingly, optimization of growth conditions requires a thorough understanding of the structural characteristics and formation mechanisms of twins at the atomic scale. However, the origin of the generation and propagation mechanism of twin defects during the EFG method, especially during the shouldering process, has not been studied intensively. Therefore, in this study, we conducted a detailed atomic-level analysis of the crystallographic structure of twin defects, focusing particularly on the shoulder region of β-Ga₂O₃ ingots, to clarify their formation mechanisms and gain insight into their evolution during crystal growth. As-grown β-Ga₂O₃ ingot by the EFG method was first investigated through polarization analysis for checking the internal grain boundaries in our ingot, as shown in Figure 1(a). The typical β-Ga₂O₃ crystal structure(matrix) and regions of twining structure can be distinguished by the contrast in light diffraction by the naked eye. As shown in Figure 1(b), we observed the originating point of the twin boundary with inclined step structures at the shoulder part of the ingot by distinct polarization contrast. Moreover, the twining structure shows the different Raman behavior that an increase in intensity and a peak shift observed in the Ag(4), Ag(5), and Bg(5) active modes, as shown in Figure 1(c). Figure 2(a) is a schematic diagram of the shoulder region including the twin area. Twin boundary sites were extracted using FIB-SEM at TB 1 and TB 2, and transmission electron microscopy (TEM) was performed to analyze crystallographic differences between the boundaries. Finally, it is confirmed that the twin boundary has initiated the atomic disorder along (200). To form the (200) plane of the twin boundary, two Gaocta–O bonds per unit cell must be broken, followed by the formation of Gaocta–O and Gaocta–O bonds. During this process, the unit cell must be displaced by –¼[001]C along the [001] direction, as illustrated in Figure 2(b). In addition, scanning transmission electron microscopy (STEM) was employed to investigate atomic-scale distortions between the twin and the matrix regions. These findings are expected to provide insights for optimizing EFG growth parameters and reducing twin-related defects in β-Ga₂O₃ crystals.

ABSTRACT. Recent advancements in the miniaturization of electronic devices have significantly increased thermal accumulation, which adversely affects the efficiency, reliability, and lifespan of devices, and has become a primary cause of failure. Diamond has attracted attention as a promising material to alleviate these thermal issues and improve device performance under extreme operating conditions due to its ultra-wide bandgap (~5.5 eV) and excellent thermal conductivity (~2000 W/m K at 300 K) properties [1]. However, homoepitaxial diamond growth faces challenges such as high cost and difficulty in large-scale wafer production. Therefore, research on diamond heteroepitaxial growth is actively conducted to overcome these limitations and obtain large diamond substrates. Among various substrate materials, silicon carbide (SiC) is widely used in diamond heteroepitaxial growth research because it has a lower lattice mismatch with diamond (~18.2%) and a wide bandgap (~3.4 eV) compared to Al₂O₃ (~25.4%) or Si (~34.3%) [2], [3]. Since 4H-SiC contains carbon atoms in its crystal structure, it can readily form strong C–C bonds, which is advantageous for achieving high interfacial adhesion. However, the details of the diamond growth mechanism related to the unique polar properties of 4H-SiC materials are still lacking and require further investigation. Therefore, in this study, we focused on the heteroepitaxial diamond growth behavior on 4H-SiC substrates depending on the surface characteristics. For the experiments, 0 ° and 4° off-cut 4H-SiC substrates with a size of 10x10 mm were prepared through ultrasonic processing using a solution containing diamond powder (170–250μm) with 200 mL of ethanol solution, as in our previous experimental conditions [4]. Subsequently, diamond growth was carried out for 1 hour using the microwave plasma chemical vapor deposition (MPCVD) method at 2.45 GHz, 5 kW of power, 6% CH4/H2 gas mixture with the pressure of 120 Torr. The temperature of 4H-SiC substrate during MPCVD process was approximately 1150°C. As shown in Figure 1, the C-face exhibited a rougher surface morphology after the roughening process compared to the Si-face, which correlates with the difference in activation energy between the two polarities [5]. Diamond growth on the C-face was more continuous and uniform, exhibiting higher nucleation density and improved surface coverage. A thin amorphous layer was observed at the diamond/SiC interface on the Si-face, but it was absent in regions without diamond coverage. This layer is presumed to be diamond-like carbon (DLC). The formation of this layer is believed to result from either faster carbon adsorption than silicon desorption or carbon atom accumulation at the interface during diamond growth. In contrast, the C-face exhibited diamond growth directly on the SiC surface. A bright contrast layer was locally detected at the interface, which is likely associated with silicon accumulation caused by lattice disorder during growth. This study highlights the critical role of the physical and chemical properties of the substrate surface in determining diamond heteroepitaxial growth behavior. At the conference, additional results will be presented regarding the effects of various surface roughening techniques—including grinding, mechanical polishing, and chemical mechanical polishing (CMP)—on diamond growth behavior on 4H-SiC substrates.

ABSTRACT. Diamond is recognized as an ideal material for next-generation power and quantum devices, owing to its outstanding physical and electronic properties. These include an ultra-wide bandgap of 5.47 eV, a high breakdown electric field exceeding 10 MV/cm, superior thermal conductivity (~2200 W/(m·K)), and high carrier mobility [1]. These characteristics enable diamond-based devices to operate under extreme conditions, including high power, high voltage, high frequency, and elevated temperatures, with superior efficiency and thermal management. In addition to its classical electronic applications, diamond also serves as a leading platform for solid-state quantum technologies. Color centers such as nitrogen-vacancy (NV) or silicon-vacancy (SiV) defects exhibit long spin coherence times and stable photoluminescence even at room temperature, enabling applications in quantum sensing, communication, and computation. The realization of such quantum devices, however, requires highly pure and structurally controlled diamond films with minimal background defects and interfaces. However, the widespread adoption of diamond in electronic and quantum applications remains limited due to the challenges associated with large-area single-crystal growth and its integration onto foreign substrates [2]. To overcome these limitations, heteroepitaxial growth techniques have been actively investigated, enabling diamond deposition on non-diamond platforms such as Si, SiC, and metal substrates [2]. Nevertheless, heteroepitaxial growth is inherently accompanied by significant challenges, such as high dislocation densities and polycrystalline morphologies, primarily resulting from severe lattice and thermal expansion mismatches between diamond and the underlying substrate. One promising solution to alleviate these issues involves the insertion of an intermediate oxide buffer layer between the diamond film and the substrate. The oxide layer can serve multiple purposes. First, it can be used as a sacrificial layer, enabling mechanical or chemical lift-off of the diamond film for substrate reuse or heterogeneous integration. Second, it can function as an electrical barrier, effectively suppressing leakage currents that commonly occur at the diamond–substrate interface during device operation. Al2O3 has attracted attention for this role due to its chemical stability, thermal endurance, and insulating nature. In this study, we investigate the influence of Al2O3 buffer layer thickness on diamond film growth behavior and quality, using microwave plasma chemical vapor deposition (MPCVD) under high-power conditions. By analyzing crystallinity, surface morphology, and Raman spectral features across various oxide thicknesses, we aim to clarify the role of the oxide layer in enabling high-quality heteroepitaxial diamond growth.

ABSTRACT. The precise placement of individual dopant atoms into solid-state structures is a fundamental requirement in the development of scalable quantum technologies. Among the available approaches, deterministic single-ion implantation has emerged as a promising method to meet this challenge, allowing control over both the number and spatial distribution of implanted ions. This technique plays an important role in realizing qubit arrays and other quantum components across various material platforms [1,2]. Scanning-probe-based lithography offers excellent spatial precision. However, its limited scalability and compatibility with different dopant species restrict its potential for industrial integration [3]. The most industrially promising approach relies on controlled in-situ ion implantation platforms equipped with reliable single-ion detection systems. However, common detection strategies, such as secondary electron emission, charge collection in PiN diodes or drain current modulation in FETs, require integrated detection setups and are limited by device architecture and by implanted species [4, 5]. To address these limitations, we outlined a novel detection strategy based on an independent, ultra-thin silicon carbide (SiC) membrane sensor capable of real-time single-ion detection. This system allows ion transmission with minimal energy loss (ΔE) and negligible deviation in their trajectory, preserving the implantation profile. The detector consists of a free-standing SiC membrane obtained via doping-selective electrochemical etching (ECE) of the highly doped SiC substrate. This configuration allows the formation of a sub-micrometric Schottky diode in parallel-plate geometry. Ion detection occurs through the generation of electron–hole pairs in the membrane and collection of these charge carriers through the electrodes. The resulting charge is then amplified, producing distinct electrical pulses for each ion event. The sensor’s performance was assessed at the 6 MV Tandem Van de Graaff accelerator of the Ruđer Bošković Institute using a 4 MeV O3+ ion microbeam. The SiC detector and a reference Passivated Implanted Planar Silicon (PIPS) detector were simultaneously employed to monitor incoming and transmitted ions respectively. The signals acquired from both detectors were used to quantify detection efficiency and evaluate any ion beam alterations due to membrane interaction. Energy deposition analysis, supported by SRIM simulations, confirmed a membrane thickness of approximately 730 ± 60 nm. The relatively high uncertainty was attributed to surface roughness introduced during the electrochemical etching process [6,7]. To investigate spatial resolution and signal uniformity, Ion Beam Induced Charge (IBIC) measurements were performed in mapping mode, generating two-dimensional charge collection efficiency maps for both the SiC sensor (Figure 1a) and the PIPS detector (Figure 1b). The signal variation between the bulk and membrane regions of the SiC sensor (Regions A and B in Figure 1a) was initially attributed to bulk-related effects, such as diffusion of bulk-generated charge pairs or funneling. However, recent Synopsys Sentaurus TCAD simulations revealed only a 37% signal difference, suggesting that more complex phenomena, likely related to defects introduced by the ECE process, are involved. By comparing the number of events detected in the active region of the SiC sensor to those observed on the reference PIPS detector, a single-ion detection efficiency of 96.5 ± 0.9% was established, indicating excellent reliability for real-time ion counting. However, as the ions interact with the SiC membrane, beam straggling is induced. This effect can introduce significant uncertainty in the final position of the dopant atom within the target lattice, thereby compromising the deterministic nature of the implantation process. To quantify this effect, the spatial distribution of the ion beam was measured before and after traversing the SiC membrane using Scanning Transmission Ion Microscopy (STIM). A 10 MeV C4+ beam was employed in combination with a 25.4 μm pitch electroformed metal grid positioned between the SiC membrane and the PIPS detector. STIM profiles were extracted using a knife-edge analysis method near the grid shadow edge, and the transition regions were modeled using Boltzmann sigmoid functions (Figure 2). Without the membrane, the beam spot size was measured as 3.4 ± 0.5 μm, increasing to 8.2 ± 0.7 μm after passage through the SiC membrane. This ~4.8 μm broadening was consistent with simulation data. However, this lateral spread exceeds the tolerance required for deterministic single-ion implantation. This limitation is primarily attributed to the relatively large distance between the sensor and the downstream grid, which amplifies the effect of angular scattering.While the presented results confirm the feasibility of the SiC membrane for single-ion detection, there remains significant room for performance optimization. Reducing the membrane thickness to 100 nm would substantially minimize both the energy loss and angular straggling of the transmitted ions, thereby enhancing spatial resolution. Simultaneously, decreasing the sensor-to-substrate distance to a few micrometers and improving the ion beam focus at the membrane entrance would contribute to greater implantation accuracy. As an illustrative example, simulations indicate that a 250 keV phosphorus ion traversing a 100 nm-thick membrane would deposit approximately 190 keV within the sensor, continuing into the silicon target with a residual energy of 60 keV. These improvements enable the use of an ultra-thin silicon carbide membrane as a sensor for high-fidelity and high-spatial-resolution single-ion implantation, supporting the development of scalable quantum devices.

Fig. 1. (a) IBIC map acquired by the SiC sensor, (b) IBIC map acquired by the PIPS detector.

Fig. 2. Count event profile close to the grid shadow edges measured by the PIPS detector without and with the SiC membrane sensor (black dotted line). The dashed red curves represent the Boltzmann sigmoidal function fitted to the experimental data.

Device fabrication was made possible thanks to the technological support and materials provided by STLab srl.

[1] Kalra, R. et al., Phys. Rev. X 4, 021044, 2014. [2] Pla, J.J. et al., Nature 496, 334–338, 2013. [3] Stock, T.J.Z. et al., ACS Nano 14, 3316–3327, 2020. [4] Shinada, T. et al., Nature 437, 1128–1131, 2005. [5] Johnson, B.C. et al., ECS Trans. 33, 179–189, 2010. [6] Nida, S. et al., J. Synchrotron Radiat. 26, 28–35, 2019. [7] Mokhtarzadeh, M. et al., Micro Nano Eng. 16, 100155, 2022.

ABSTRACT. β-Gallium oxide (β-Ga2O3) has garnered significant attention as a next-generation material for high-voltage power electronics due to its ultra-wide bandgap of 4.8 eV and high theoretical breakdown electric field of 8 MV/cm [1]. However, realizing p-type conductivity in β-Ga2O3 remains a major challenge. As a promising approach to overcome this limitation, the development of PN diodes incorporating nickel oxide (NiO), which inherently exhibits p-type conductivity, has been proposed [2]. Holes in NiO thin films are generated from defects such as oxygen interstitials or nickel vacancies, and the electrical properties of NiO/β-Ga2O3 PN diodes can be improved by tuning the hole concentration through the control of various processing parameters [3]. This study evaluates the effects of annealing on the defect characteristics and electrical performance of NiO/β-Ga2O3 PN diodes. The NiO/β-Ga2O3 PN diodes were fabricated by depositing NiO thin films onto a β-Ga2O3 epi-layer grown via Halide Vapor Phase Epitaxy (HVPE). The NiO films were deposited using radio frequency (RF) sputtering in an Ar/O₂ (3:1) ambient with a flow rate of 4 sccm, followed by PDA at 400°C for 5 minutes in an oxygen atmosphere. After fabrication, current density–voltage (J–V) characteristics of the devices were measured before and after annealing, as shown in Fig. 1. Although the on-resistance increased after annealing, the ideality factor (η) and leakage current were significantly reduced, resulting in a substantial improvement in the on/off ratio from 4.58×10^5 to 1.62×10^8. In both devices, η exceeded 2 in both the pre-turn-on and post-turn-on regimes, indicating that non-ideal transport mechanisms—such as interface recombination and trap-assisted tunneling—dominate charge transport. The suppression of these mechanisms following annealing is attributed to a reduction in recombination centers at the NiO/β-Ga2O3 interface, which will be further discussed in conjunction with the trap characteristics. For the reverse characteristics, the breakdown voltage improved from 880 V to 1550 V after annealing. The deep-level trap characteristics were analyzed using Deep Level Transient Spectroscopy (DLTS). Figures 5(a) and (b) show the DLTS spectra of the non-annealed and annealed diodes, measured under a reverse bias of VR = –4 V, a pulse voltage of VP = +1 V, and a temperature range of 80–700 K. While both diodes exhibited similar trap energy levels, the post-annealing spectra revealed a noticeable reduction in peak intensity and a thermal shift toward higher temperatures. Based on the spectra, the trap activation energy, density, and capture cross section were extracted, revealing a reduction in both energy level and trap concentration after annealing, as shown in Fig. 5(c). In particular, the E2* trap detected in the 350–400 K range has been previously identified as a primary contributor to interfacial recombination in the forward subthreshold regime of β-Ga2O3-based PN diodes [4]. This finding is consistent with the reduction in ideality factor observed in Fig. 2(a), suggesting that post-annealing effectively improves interfacial quality and suppresses recombination activity. In conclusion, this study presents the impact of controlling the hole concentration in NiO thin films through annealing on the electrical properties and defect characteristics of NiO/β-Ga2O3 PN diodes. The results demonstrate that optimized processing conditions can enhance device performance.

ABSTRACT. The possibility of hosting color centers and the technological advancements in mass production in the power electronics industry have attracted attention to the use of Silicon Carbide (SiC) as a quantum technology platform. Due to its spin coherence, bright, stable emission, and the possibility to control its charge state, the Silicon Vacancy (VSi) is a highly studied color center. The VSi can be created by several methods such as heavy-ion irradiation, laser irradiation, thermal oxidation, or during epitaxial growth. Nevertheless, to realize quantum operations, the color center needs to be localized. One path toward localized quantum defects is heavy-ion irradiation, especially with microbeam irradiation.

The present work aims to understand the correlations between the heavy-ion properties (penetration range and linear energy transfer (LET)) and the SiC properties (undoped and doped wafers). Undoped and doped wafers with Nitrogen (N), Phosphorous (P), and Aluminum (Al) were used to study the influence of the pre-processing on the creation of color centers. This work shows that Al implanted samples have the highest VSi concentration in comparison to N or P implanted samples. For the final contributibution the mechanism related to the doping dependent color center creation will be discussed and the Zero Phonon Line (ZPL) measurements will be presented.

ABSTRACT. A single-photon emitter (SPE) is a key element in various quantum technologies, such as quantum computing, communication, and sensing. Color centers located at the SiO2/SiC interface have been reported to function as highly bright SPEs. Although previous studies have successfully controlled the density of color centers, their microscopic origin has remained elusive. In the present study, we controlled the color center density at the SiO2/SiC interface by varying the oxidation conditions, and investigated their correlation with electrically active defects. Furthermore, based on the analysis of the defect energy levels, we explore their potential origins.

ABSTRACT. To qualify and characterize the lifetime of semiconductor power packages, the ECPE Guideline AQG 324 [1] outlines and details the necessary tests. One such test is active power cycle testing (PCT), which requires the accurate transient measurement of the virtual junction temperature Tvj. For SiC MOSFETs, the voltage drop of the body diode VSD(T) is used as a temperature-sensitive electrical parameter (TSEP). Recent research on advanced SiC MOSFETs from different manufacturers has shown that the widely used static temperature calibration method can lead to a considerable error in estimating Tvj [2]. This is attributed to a newly observed transient behavior of VSD following a gate bias switch with a constant measurement current Imeas and temperature, resulting in a Tvj calculation error of approximately 10 K [2]. This study continues and deepens the investigation of the effect in [2–4] on 1200 V SiC MOSFETs from four different suppliers, extending the temperature range down to -196 °C (LN2). The objective is to use the cryogenic temperatures to slow down trapping/detrapping [5], as trapping at the SiC/SiO2 interface is one of the suspected reasons for the dynamic effect, thereby allowing insight into the semiconductor effects at play. The electrical circuit used for this investigation as well as the pattern of Drain-Source current IDS, and the Gate-Source voltage VGS is covered in [2–4]. For tempering the setup described in [6] is used. As in [2–4] the transient shift of VSD after switching VGS from the maximum positive to negative values according is designated as ΔVSD, representing the disparity between VSD right after the gate bias switch including device and circuit charging effects, and the end of the cooling cycle. Furthermore, the influence of VGS,off (0, -4 V, -8 V, -12 V) and the temperature (-100 °C- -196 °C) were analyzed in a measurement series. For temperatures above -150 °C the transient effect gets reduced greatly by decreasing negative gate voltage. For the devices from suppliers A, B and D the effect vanishes completely at -12 V. For supplier C the dynamic effect does not vanish at -12 V and inverts for -150 °C. Review of the transient curves after switching the gate to VGS,off. For temperatures below -175 °C all devices show a differently pronounced transient behavior after switching the gate to a negative value. Furthermore, at -196 °C the devices show unusual shapes. The similarity over several devices of the same manufacturer, indicates a design specific behavior. Further research of the authors will increase the number of measurements and investigate the semiconductor effects leading to the behavior of the samples under cryogenic temperatures. [1] ECPE Guideline AQG 324: Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles, 03.1/2021, ECPE European Center for Power Electronics e.V., May. 2021. [2] J. Breuer et al., "Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling – a Dynamic Approach," in CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems, Düsseldorf, 2024, pp. 239–245. [3] J. Breuer, F. Dresel, A. Schletz, J. Klier, J. Leib, and B. Eckardt, "Transient junction temperature measurement error of SiC MOSFETs in power cycling – Influence of gate voltage," in 35th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Parma, 2024. [4] J. Breuer, F. Dresel, A. Schletz, J. Leib, B. Eckardt, and M. März, "Dynamic Calibration of Junction Temeperature of SiC MOSFETs for Power Cycling," in 2024 IEEE 10th Electronics System-Integration Technology Conference (ESTC), Berlin, Germany, 2024, pp. 1–6. [5] M. Bhattacharya et al., "The Effect of Cryogenic Temperature on Subthreshold Hysteresis of Commercial SiC Power MOSFETs," in 2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), Charlotte, NC, USA, 2023, pp. 1–4. [6] S. Büttner, J. Windisch, and M. März, "Design and Operation of a Cost-Effective Cooling Chamber for Testing Power Electronics at Cryogenic Temperatures," IEEE Instrum. Meas. Mag., vol. 26, no. 3, pp. 46–51, 2023, doi: 10.1109/MIM.2023.10121411.

ABSTRACT. The ECPE Guideline AQG 324 standardized procedures and methodologies for the lifetime characterization of power electronic converters for automotive applications [1]. These procedures include thermal impedance measurement (Zth) and active power cycling tests (PCT). During PCT, the virtual junction temperature (Tvj) of the device under test (DUT) is estimated using temperature-sensitive electrical parameters (TSEP). For SiC MOSFETs, the temperature-dependent built-in voltage drop across the intrinsic body diode (VSD) is employed to determine Tvj by applying a sense current (Isense) [1]. However, this method faces several challenges - specifically, when the MOSFET channel is still partially-on at certain negative gate-source voltage. In general, a more pronounced body effect for SiC MOSFETs intensifies this effect. However, it can be mitigated by applying a sufficiently negative gate voltage [2]. Although in some cases, this mitigation exceeds the lower limit of the gate voltage specified in the datasheet. Additionally, interface traps at the SiC/SiO2 interface can influence the transient VSD behavior [2]. Experimental measurements have shown that the VSD transient often exhibits a slow decay lasting up to seconds before reaching steady-state voltage values, especially in the absence of load current [3]. However, this anomalous VSD behavior remains unexplained in the existing literature. In this work, a pulse pattern similar to the PCT cool-down measurement routine was applied by switching the gate source voltage (VGS) without applying a load current. The time-dependent dynamic behaviour of the body diode’s forward voltage drop (VSD), was investigated by using only a small Isense (like the measurement current in a PCT) in the range of milliampere. Commercially available trench-gate SiC MOSFETs with an 80 mΩ on-resistance and 1200 V blocking capability were utilized. In this study, the influence of various parameters such as negative gate-source voltages (VGS,off), gate inductance (Lg) and gate resistance (RG,off) on dynamic VSD behaviour is systematically analyzed.

ABSTRACT. Paralleling SiC MOSFETs in power modules often causes overvoltage and oscillation due to parasitic inductance [1]. This study compares trench and planar 1200V SiC MOSFETs modules in 200 kW EV inverter application to assess their impact on resonance damping. The finding enabled planar SiC MOSFET device for 6 in 1 power module AEPR25B12C1STJN being optimized at 2mohm Rdson level. The performance of the optimized module was benchmarked against a commercial 200 kW product, the FS03MR12A6MA1B.

Two devices modules were tested: 15 mΩ industrial trench and custom planar SiC MOSFETs devices (Fig.1), parallel connected 6 in 1 modules. At 800 V switching, planar modules maintained Vgs within ±15 V, while trench modules showed severe Vgs overshoot (+24.9 V) and undershoot (–11.7 V), leading to severe ringing and burnout (Fig. 2, Table 1).

DOE sensitivity analysis, done at 800V 600A test condition, showed Cgd had minimal effect, while internal Rg and Vth significantly influenced ringing (Fig. 3, Table 2) [2]. Vt sensitivity is more than that from internal Rg in the planar module. DOE condition C, Vt =3V and Rg=10 ohm, showed better performance in the planar SiC MOSFET devices. Further optimization for high temperature operation is required due to this test was done at room temperature.

Key damping enhancements for 1200V planar SiC MOSFET devices include: T-CAD-based implant/drain engineering to limit gate oxide stress (2.8 MV/cm) (Fig. 4), hexagonal cells for 10% Rg control (Fig. 5, 6), silicide gate, multi- gate finger, wider and thick metal routine for gate runner to reduce gate delay, retrograded P-well for high breakdown voltage and high current density, optimized body diode for reverse bias durability

Packaging and layout were optimized using current balancing methodology (CBM) with six planar devices in symmetric layout which was compatible with HDP module (Fig. 7, Table 3) [6]. ATC planar modules showed superior temperature performance, with improved Rdson, Eon/Eoff, output current (Fig. 8, Table 3). Dyno tests confirmed 200 kW AC output at 98% efficiency, matching benchmarks product which using eight trench devices (Table 3)

ABSTRACT. Silicon Carbide (SiC) MOSFETs offer various electrical advantages, such as high breakdown voltage, low on-resistance, and fast switching speed, due to their wide bandgap material properties [1]. These characteristics make them widely applicable in high-reliability fields such as aerospace, electric vehicles, and industrial power systems. In particular, many studies have attempted to implement SiC MOSFETs in space power systems. However, few investigations exist that provide a direct comparison of static and dynamic characteristics before and after radiation exposure, based on the package type. This study investigates 1200V-SiC MOSFETs packaged in the widely used TO-247 type and in a hermetic type designed for harsh space environments. The comparison focuses on static characteristics, such as on-resistance and threshold voltage, and dynamic characteristics, such as turn-on/off time and switching losses, evaluated before and after radiation exposure. Radiation exposure can lead to Total Ionizing Dose (TID) effects, where charge trapping occurs in the gate oxide. This results in electrical degradation, including threshold voltage shifts and increased leakage current. Additionally, phenomena such as Single-Event Effects (SEE) and Single-Event Burnout (SEB) can further impact the reliability of SiC MOSFETs [2]-[3]. To mitigate such radiation-induced degradation, the choice of package type becomes critical. A hermetic package, composed of sealing materials such as metal or ceramic, is designed to protect the internal semiconductor from environmental stressors like moisture, gases, and radiation [4]. The hermetic package was fabricated following the process flow shown in Fig. 1, and its internal structure and materials are detailed in the design layout illustrated in Fig. 2. These figures provide the basis for evaluating the contribution of packaging design to radiation hardness. Compared to TO-247, the hermetic package offers superior sealing, enhanced thermal dissipation, and improved protection against radiation. This study aims to analyze the impact of package type differences on the performance and reliability of SiC MOSFETs in radiation environments and to provide technical insights that support the selection of high-reliability packaging for future space power systems.

ABSTRACT. In standard environmental reliability tests, Silicon Carbide (SiC) MOSFETs show a superior performance in comparison to their Silicon counterparts. This raises the question if the SiC modules are robust and reliable under all circumstances in the field and against all failure mechanisms or only in the standard laboratory tests. The HV-H³TRB (High Voltage – High Humidity High Temperature Reverse Bias) test is the standard test for humidity reliability and SiC modules survive this test for several thousand hours, easily surpassing the 1000 h qualification requirement. The next step is to investigate the influence of steep voltage slopes (high dv/dt) during a usual HV-H³TRB procedure instead of a DC voltage stress. In this work, a dynamic HV-H³TRB test was performed on 3.3 kV SiC MOSFET modules for 2000 h with switched voltages. The test has been continued.

ABSTRACT. 10 kV SiC-MOSFET power modules are developing for medium-voltage applications, but their thermal characteristics have not yet been fully verified. This study demonstrated the wire bond layout design on 10 kV SiC-MOSFET power modules for improved thermo-mechanical performance based on the 3D temperature simulation. The 10 kV SiC-MOSFET used in this research is 8.1 mm square in size, with a current rating of 20 A per die. Then, the wire bonds are placed on the edge of each source pad to reduce the wire heating ∆T(wire) by 6.2% compared to the central wire bond placement. These differences were verified in the power cycle test (PCT) on ∆T(diemax) = 105 oC, T(diemax) = 175 oC. As a result, the lower ∆T(wire) samples increased the PC lifetime by changing the failure mode from wire lift-off to solder failure. This might suggest that minimizing ∆Twire causes the shift of failure mode from the wire bonds, with its lifetime increasing. This demonstration highlighted the potential of utilizing a digital design approach based on thermal simulation, utilizing a limited number of samples as an initial structural optimization.

ABSTRACT. This study investigates the effect of negative high-temperature gate bias (HTGB) stress on 1200 V 4H-SiC planar MOSFETs. In this work, Fowler–Nordheim (FN) tunneling and hole injection occur simultaneously but with unequal impact. MOSFETs were stressed at −20 V and 150 °C for 1008 h. In the first 504 h, Vth increased by 2.17% and Crss decreased by 13.69%, both attributed to electron tunneling into the oxide. In the next 504 h, Vth decreased by 1.16% and Crss increased by 6.71%, both linked to hole injection from the p-body. The Crss behavior under stress results from these competing charge dynamics. A positive shift in the Cg–Vg curve confirms electron trapping in the oxide. These results highlight the combined roles of electron and hole processes in device degradation under negative HTGB stress.

ABSTRACT. Bipolar degradation (BD) in Silicon Carbide (SiC) power devices arises from charge carrier recombination at certain crystal defects such as basal plane dislocations (BPDs) and stacking faults (SFs), leading to defect conversion or expansion and severe device performance deterioration [1], [2]. The BD performance evaluation of such devices is challenging due to the interplay of several multiple group factors such as (i) defect type, size, density and location; (ii) epi-layer and buffer-layer thickness and doping profiles; (iii) device design architecture and packaging; (iv) in-field application conditions and other concurrent degradation mechanisms. A previous work [3] shed light on their impacts in SiC Merged-PiN-Schottky (MPS) Diodes (650V/10A), which compared devices with classified intentionally pre-existing BPDs and SFs defects against good dies. Using a moderately different approach, in this work, we employed an in-house setup for an accelerated Bipolar Degradation Robustness (aBDR) performance evaluation of 1200V SiC MOSFETs. TO247 packaged devices from trial production runs, without prior photoluminescence defect screening (PL) but passed final electrical testing (FT) were randomly selected and tested. Devices underwent static and body diode sweep characterization (forward i.e., 3rd quadrant and reverse) before and after BDR testing. BDR stress was applied using repetitive square current pulses (IFRM) with 1ms/100ms (on/off) cycle time at 20A, 30A, and 50A across different sample batches, inducing bipolar conduction through the body diode. Figure. 1 presents pre- and post-stress I–V characteristics of a representative device stressed at 20A for a cumulative 100 seconds. Figure 1b shows a hard short failure linked to BD, confirmed by PL imaging after decapsulation (Figure 1c), which reveals localized bar-shaped and triangular defect structures. While some devices exhibited hard failures, some others showed partial degradation, including increased leakage current and voltage shifts. Their implications along with corrective measures will be discussed in detail at the conference. In summary, we successfully developed and demonstrated an effective and accelerated method for rapid BDR performance evaluation of SiC MOSFETs, also applicable to SiC diodes. This approach offers valuable insights for device design optimization, process improvement, and reliability assurances, significantly supporting real-time feedback and corrective actions during early-stage technology development and application-specific qualification processes.

References: [1] J. P. Bergman, H. Lendenmann, P. Å. Nilsson, U. Lindefelt, and P. Skytt, “Crystal defects as source of anomalous forward voltage increase of 4H-SiC diodes,” Mater. Sci. Forum, vol. 353–356, pp. 299–302, 2001. [2] T. Kimoto and H. Watanabe, “Defect engineering in SiC technology for high-voltage power devices,” Appl. Phys. Express, vol. 13, no. 12, pp. 1–44, 2020. [3] S. Laha, J. Leib, D. Zhao, A. Schletz, M. März, C. Liguda, F. Faisal, D. Momeni., “Milliseconds Power Cycling (PCmsec) driving bipolar degradation in Silicon Carbide Power Devices),” in ICSCRM24, Raleigh, USA, 2024.

ABSTRACT. When characterising 1200 V Silicon Carbide (SiC) power MOSFETs, the choice between testing at the bare die level versus in a packaged format such as TO-247 has substantial implications for the extracted electrical parameters. Bare die characterisation, often performed using a probe station with thermally conductive fixtures and Kelvin sensing, isolates the intrinsic electrical behaviour of the semiconductor structure without the influence of packaging-induced parasitic elements. In contrast, the TO-247 package introduces parasitic inductances, resistances, and thermal resistance and that can significantly alter the apparent characteristics of the device. These packaging parasitics are particularly consequential in wide-bandgap devices like SiC MOSFETs, which operate at high frequencies and fast switching speeds, where even small parasitic values can lead to substantial voltage overshoots, delayed switching, and degraded performance.