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| 09:45 | (Invited) 200 mm 4H-SiC Substrate Status and 300 mm 4H-SiC Substrate Development PRESENTER: Gao Chao ABSTRACT. SiC substrate is accelerating 200 mm (8 inch) application transfer from 150 mm (6 inch) in the industry. The underlying driving force for this conversion is to further decrease the cost from material to device fabrication. However, with the substrate diameter become larger, more technical and quality challenges arise, with respect to the crystal stress and substrate warpage stability, defect reduction and conversion, quality consistency in volume production and application, etc. In this report, we would like to show the status of 200 mm SiC substrate in both research and production level. Evolution mechanism and reduction trend of various defects in SiC crystal are discussed, dislocation and stress characterization method is developed, quality performance in volume production is elaborated for conductive n-type SiC substrate produced with physical vapor transportation (PVT) technology. Besides, top-seeded solution technology (TSSG) is developed to fabricate conductive p-type SiC substrate with resistivity lower than 200 mΩ·cm, which is important to support n-channel insulate gate bipolar transistor (IGBT) with even higher operation voltage. As 200 mm SiC substrate step into volume production, 300 mm SiC substrate is put on agenda in research. Here we report the 4H-SiC crystal diameter expansion process from 200 mm to 300 mm, which is based on thermal field simulation and thermal field design, as shown in Fig. 1. The first 300 mm SiC substrate is reported in 2024, which is nitrogen doped conductive n-type. And then, 300 mm conductive p-type SiC substrate and high purity SiC substrate are subsequently fabricated, as shown in Fig.2. To make 300 mm SiC into practical application in the future, research work on crystal quality improvement and boule thickness increase are simultaneously carried out. Now, boule thickness over 30 mm is achieved which show possibility of lower cost 300 mm SiC substrate fabrication. However, challenges regarding crystal stress and defect control, especially substrate thickness and warpage in SiC substrate with such large diameter should be further considered in device application regarding the yield and cost. |
| 10:15 | Quality Improvement in 200mm Silicon Carbide Substrate PRESENTER: Rajan Rengarajan ABSTRACT. Silicon carbide (SiC) substrates are increasingly used in power electronics due to their high thermal conductivity, wide bandgap, and high breakdown field. High-quality, large-diameter substrates are essential for improving performance and reducing manufacturing costs of SiC-based electronic devices. Coherent Corporation has commercialized n-type 150mm and 200mm SiC substrates in recent years [1]. Typical crystal defects in SiC substrates include micropipes, dislocations, stacking faults, and inclusions. In this paper, we report on our method and progress in achieving high-quality 200mm 4H n-type substrates. SiC crystals with diameters larger than 200mm are grown using a patented physical vapor transport process [1-2]. SiC source material and single crystal seed are loaded into a crucible and heated in excess of 2000°C. The temperature gradient is controlled by precise arrangement of the heating element, insulation, and the location of the source material and seed. During crystal growth, the silicon carbide source vaporizes non-congruently, and the vapor is deposited on the seed, forming a single crystal. Crystal defects typically originate from two sources: inherited from seed crystals and formed during the crystal growth process. By using Design-of-Experiment approaches, we optimized the crystal growth process to achieve minimal inclusions and stacking faults. With the optimized growth process, the dislocation density typically reduces naturally over time during crystal growth due to the annihilation of dislocation pairs with opposite Burgers vectors. Figure 1 shows total dislocation density (DD), threading screw dislocation density (TSD), and basal plane dislocation density (BPD) as a function of distance from the seed for a 4H n-type boule grown under optimized conditions. The boule was sliced into wafers, and the distance from the seed was determined from wafer thickness and kerf loss. Dislocation densities (DD, TSD, BPD) were determined by polishing the silicon face of the wafers, etching the wafers in a potassium hydroxide molten flux, and counting the etch pits of various sizes and shapes [3-4]. The dislocation density decreased dramatically in the earlier stage of growth when the initial dislocation density was high. The rate of dislocation density reduction decreased in the later stage of growth. The measured dislocation density data can be fitted nicely with the distance from the seed in a log-log fashion. Figure 2 shows the DD, TSD, and BPD as a function of distance from the seed for another crystal. The initial defect densities were lower, and the reduction of defect densities from seed to tail of the growth was also decreased; however, they still fit nicely with the distance from the seed in a log-log fashion. Another factor that impacts the quality of the grown crystal is the quality of the seed crystal. Threading screw dislocations and micropipes typically propagate from the seed to the crystal. The density of these defects will continuously decrease during growth under optimized conditions, although the rate of reduction decreases when the density is low. We have developed a manufacturing process to continuously improve 200mm 4H n-type wafer crystal quality by feeding the line with the best quality seed crystals and growing boules under optimized conditions. Figure 3 shows defect maps of recent 200mm 4H n-type wafers, indicating TSD of 78 cm-2, BPD of 88 cm-2, and MPD of 0.00 cm-2. Typical wafer shape parameters are TTV ≤5µm, bow ±5µm, warp ≤10µm, SFQR ≤ 1um for 10mmx10mm. Figure 4 shows SICA map for a recent wafer with TUA >99.5%. |
| 10:30 | Mechanisms and Modeling of Degradation of Graphite Crucible and Thermal Insulation During PVT Growth of SiC Crystals PRESENTER: Andrey Smirnov ABSTRACT. Physical vapor transport (PVT) is currently the primary method used for the production of bulk SiC crystals. To grow the crystals that would satisfy current industry requirements in terms of size and quality, it is crucial to design optimal thermal fields. Since PVT is an essentially long-term process, thermal design should cover the whole duration of the growth. However, over time, inherent changes to the crystal, source, and furnace elements can have significant cumulative effect on thermal profiles. Thus, for high accuracy of thermal design, these changes should be understood and accommodated into respective design tools. Among these inherent changes, evolution of the powder charge and crystal shape have been studied previously both experimentally and with simulations. However, other notable effects such as erosion of the graphite crucible and degradation of the graphite felt insulation received much less attention. Moreover, chemical processes inside the porous walls of the crucible and felt insulation as well as associated changes of the material properties, to our knowledge, have not been simulated directly. In this work, we use modeling to get an insight into the processes experimentally observed as changes of the crucible and felt insulation. Graphite structural elements of the hot zone exposed to the high temperature of 2000-2300°C and chemically aggressive environment can undergo noticeable physical and chemical changes. For instance, it is generally acknowledged that the internal walls of the graphite crucible serve as a supplementary source of carbon, which can be beneficial for the growing crystal [1]. At the same time, accumulated material loss can cause significant damage to the crucible. Degradation of the felt insulation, in turn, can have a pronounced effect on the temperature field in the hot zone. The latter is particularly important since deviation from the optimal thermal gradients can have detrimental effect on the crystal shape, stress, and related defects. To perform conjugated simulations of the chemical reactions, heat, and mass transport inside the porous media of the insulation and the crucible walls, computational domain for the mass transport and chemical reactions was extended to include the flow in the entire reactor chamber, chemical reactions inside the graphite felt insulation and the crucible walls. In the porous media, the approach implemented in VR-PVT SiC software [2] for modeling of the powder evolution was used: solution of the heat and mass transfer problems inside the porous media was coupled with the prediction of the local phase composition, surface chemical reactions, and automatic adjustment of local porous medium properties (porosity, heat conductivity, specific interfacial surface, etc.). Simulations show that the crucible degradation is predicted to be mostly contained within thin superficial layer facing the crucible interior, see Fig. 1. In the outer felt insulation, the areas of material evaporation and SiC deposition are expected over entire insulation thickness, Fig. 2. Experimental demonstration was performed by a 200 hrs growth run in a conventional PVT furnace. The hot zone differs from the model case, but all the phenomena predicted by the simulation are observed. The internal graphite wall is etched to a certain depth, the inner surface of the outer soft felt insulation is degraded, and the region containing a solid deposit exists inside the felt (Fig. 2b). Very good qualitative agreement was demonstrated, and further experiments are planned to evaluate the level of quantitative prediction. The etching of the graphite walls of the growth chamber may alter the growth chemistry and the geometry of the crystal surroundings. The densification and erosion of the thermal insulation can have significant effect on the global thermal field through variation of insulating properties of the felt. Hence, accounting for these processes can increase the modeling accuracy, enhance the level of process control, provide valuable insight into details of the PVT process, and stimulate new directions of SiC crystal growth development. [1] J. Liu et al., Diamond & Related Materials 15 (2006), pp. 117–120 [2] VR PVT SiC, https://str-soft.com/crystal-growth/pvt-sic/ |
| 10:45 | Efficient Thermal Field Optimization of Physical Vapor Transport Simulations for Silicon Carbide Single Crystal Growth PRESENTER: Lorenz Taucher ABSTRACT. Key aspects of physical vapor transport (PVT) growth of silicon carbide (SiC) bulk crystals are the influence of process parameters on defect formation (such as polytypes, dislocations, voids, or parasitic secondary phases), the growth rate, the C/Si ratio, and the evolution of the boule and the powder, as well as their interdependencies. Based on these fundamentals, favorable process conditions for the growth of SiC have been identified, with a particular focus on the thermal field, as it mainly determines the crystal growth and defect evolution dynamics. While PVT simulations have been successfully employed to evaluate the suitability of new reactor designs for the growth of crystals of large size and low defect density, a key challenge remains: optimizing reactor designs and the PVT process itself. The optimization goal is to determine the optimal process parameters (e.g., power, crucible position) and reactor geometry (e.g., insulation or crucible thickness) that best meet the thermal objectives and constraints derived from the fundamentals. In this context, machine learning (ML) enables the creation of efficient surrogates that approximate simulations at a targeted accuracy while being computationally cheap. These advantages of ML-based methods allow for the exploration of a wide range of process settings and geometric configurations to identify the most suitable one. We present an approach for reactor optimization where we build an ML surrogate trained on COMSOL Multiphysics finite element method (FEM) PVT simulations for SiC single-crystal growth. Unlike PVT optimization strategies in the literature, our work demonstrates an improved scheme to optimize temperature profiles by employing a ML model capable of generating higher-dimensional output [1-3]. This model utilizes Singular Value Decomposition (SVD) to reduce the dimensionality of the thermal profiles and fields. Specifically, SVD extracts principal component (PC) basis functions from the training dataset, and a ML model learns the dependence of each basis function’s weight on the process parameters and the reactor geometry (Fig. 1). Given the critical role of the thermal field in the optimization, the objectives include (i) the radial temperature profile/gradient along the seed, (ii) the axial temperature profile/gradient between the source and the seed, and (iii) uniform temperature distribution within the source. The optimized temperature profiles along the seed and from the source to seed for a given PVT reactor design (see Fig. 2 (c)) are shown in Fig. 2 (a) and (b), respectively. Our framework enables efficient multi-objective optimization of the PVT reactor using a surrogate model combined with optimization algorithms such as NSGA-II. This approach is expected to accelerate the discovery of optimal reactor designs and process settings by facilitating the optimization of growth reactors regardless of the PVT furnace operation principle (resistive or inductive) or seed crystal diameter (6-inch, 8-inch, etc.). Acknowledgement The authors gratefully acknowledge the financial support provided by the Christian Doppler Forschungsgesellschaft (CDG). The project is supported by funding from the Important Project of Common European Interest on Microelectronics (IPCEI ME) grant agreement No FO999917424bbg. The project is also supported by the Chips Joint Undertaking (JU) via the European Union’s Horizon Europe research and innovation programme and its members, including top-up funding by Austria, France, Germany, Romania, and Slovakia, under grant agreement No 101139788. |
| 11:00 | Reactive Infiltration SiC Crucibles Unlock Macrodefect Mitigation in 2-Inch SiC Solution Growth PRESENTER: Sakiko Kawanishi ABSTRACT. In the silicon carbide (SiC) solution growth method, a graphite crucible is typically employed to contain the silicon-based solution and simultaneously serve as a carbon source [1]. However, the use of graphite crucibles inevitably reduces the Si concentration in the solution. Additionally, the imbalance between the carbon supplied by the crucible dissolution and the carbon consumed during SiC growth can easily lead to the formation of SiC microcrystals in the solution. This in turn causes macrodefects in the grown crystals, specifically SiC inclusions. To eliminate this issue, we proposed the use of SiC liner crucibles fabricated through physical vapor transport (PVT) for SiC solution growth, successfully achieving complete suppression of SiC inclusions [2]. In addition, we introduced liquid Si infiltration (LSI) using a SiC/carbon mixed powder with fine carbon as a cost-effective method for fabricating SiC polycrystals for liners, thereby enabling the production of dense SiC [3]. In this study, we conducted the solution growth of 2-inch SiC using a SiC liner crucible fabricated by LSI. The efficacy of the LSI-SiC liner crucible as a SiC source was evaluated by comparing the results of the SiC solution growth with those obtained using alternative SiC sources. SiC powder with an average grain size of 2.3 µm and carbon black with an average grain size of 0.1 µm were mixed to obtain a carbon mole fraction of 0.67. This mixture was then formed in a crucible with an outer diameter of 120 mm through uniaxial pressing. The preform was placed in a graphite crucible filled with Si and maintained at 1450 °C for 30 min under vacuum to promote reactive Si infiltration. A Si-Cr based solvent alloy was retained in the LSI-SiC liner crucible. Solution growth of SiC was conducted using a 2-inch-diameter on-axis 4H-SiC (000-1) seed crystal at 1940 °C for 3 h in a He atmosphere. Fig. 1 presents the cross-sections of the SiC crystals obtained using a PVT-SiC liner crucible [2], a commercially available sintered SiC crucible, and an LSI-SiC liner crucible. Although the PVT-SiC liner is not optimal for mass production, it is composed of high-purity dense SiC, which results in high-quality SiC crystals devoid of macrodefects [2]. Conversely, the use of a commercial SiC crucible resulted in numerous voids attributed to oxide sintering aids. These voids proved to be challenging to eliminate when the crucible served as the SiC source, rendering it unsuitable for solution growth. In contrast, the LSI-SiC liner crucible exhibited no voids. However, SiC inclusions were detected, originating from the detachment of a portion of the LSI-SiC liner rather than from SiC microcrystals formed in the solution when graphite crucibles were employed. Consequently, although improvements in the LSI process are necessary to mitigate SiC detachment, the LSI-SiC liner is anticipated to be an effective and relatively cost-efficient SiC source. |
| 11:15 | Reconstruction of PVT-SiC Growth Setup to Simultaneously Achieve High Material Yield, High Growth Rate, and Large Crystal Height PRESENTER: Daisuke Nakamura ABSTRACT. Bulk SiC crystals are typically grown using the physical vapor transport (PVT) technique to produce SiC wafers. Conventional PVT-SiC reactors employ a single-coil radiofrequency (RF) heating system combined with a quartz-glass-tube chamber. These RF-heated systems are favored in industry due to their simplicity, low cost, and high energy efficiency, making them suitable for mass production. However, achieving large crystal heights in a single growth run, along with high growth rates and high material yield, remains challenging due to limited control over the temperature profile in the simple single-coil setups. In this study, we demonstrate a significantly improved crystal height—achieved through both high growth rate and high material yield—using a reconstructed yet still simple PVT growth setup. The reconstruction involved modifying the graphite crucible components and thermal insulation materials, guided and optimized via two-dimensional finite element method (2D-FEM) simulations of the growth process. The goal of this reconstruction, illustrated in Fig. 1, was to alleviate the sharp temperature gradients within the SiC source powder caused by localized hotspots at the graphite source container, an inherent feature of RF heating. These steep gradients lead to polycrystalline formation in cooler regions, which reduces material yield and consequently lowers the overall growth rate and final crystal height. By redesigning the crucible geometry and incorporating advanced materials for crucible and insulation, we successfully moderated the temperature gradients within the source. Figure 2 presents the growth result using the reconstructed setup over a growth duration of 168 hours. The resulting crystal achieved a height of approximately 70 mm, corresponding to a time-averaged growth rate of 417 μm/h—both values, to our knowledge, represent record highs for bulk PVT-SiC growth. These achievements are attributed to an exceptionally high material yield of ~87%, calculated as the product of the source-powder consumption ratio and the source-gas recovery ratio. Specifically, the residual polycrystalline mass in the used source powder was only 442 g out of an initial 4794 g, corresponding to a consumption ratio of ~91%. This confirms that nearly all the source powder was effectively sublimated and the resulting vapor was efficiently converted into single-crystalline SiC. Furthermore, 2D-FEM simulations of the reconstructed setup revealed that reduced temperature variation within the source powder correlates directly with improved material yield and growth rate. The successful integration of thermal design and simulation in the reactor reconstruction points toward the scalability of this method for growing even larger SiC ingots and reducing wafer production costs. |
| 09:45 | (Invited) TCAD-Driven Design and Analysis of Advanced 3D SiC MOSFET Structures ABSTRACT. The use of Technology Computer-Aided Design (TCAD) simulators is a fundamental pillar of the power semiconductor industry, as they enable a significant reduction in both development time and cost. This work presents two application examples of TCAD simulations for the development of SiC MOSFET devices with strongly three-dimensional designs. Simulating such devices requires the development of strategies to obtain accurate results within reasonable computational times—such as geometric simplification of the design, mesh optimization, and reduction of circuital complexity for mixed-mode simulations—as well as a careful selection of suitable physical models to accurately describe the device behavior. The first case study focuses on the development of a 3.3 kV Quasi-Planar Trench (QPT) SiC MOSFET design. The concept behind this design is introduced in [1]-[3]. Its operating principle is based on the idea of bypassing the JFET region of a planar SiC MOSFET by means of trenches, orthogonal to the JFET region, operating in accumulation mode (see Fig. 1). The accumulation layer formed along the vertical trench sidewalls, also connected to the gate terminal, provides electrons with an alternative, lower-resistance path toward the drift region. In the absence of such a solution—i.e., in a purely planar design—one way to reduce the specific ON-resistance (Ron) is to decrease the cell pitch. However, accurate 3D TCAD simulations reveal that beyond a certain point, Ron actually increases with further reduction in pitch (see Fig. 2). The use of 3D TCAD simulations allowed for a detailed analysis of the trench's impact in the JFET region, as illustrated in Fig. 3. Alongside the output characteristics (Fig. 3a), which clearly highlight the benefits of the QPT design, current density maps are shown for both the planar (Fig. 3b) and QPT (Fig. 3c) structures [4]. In the QPT device, the current flow along the vertical trench walls is clearly visible. Fig. 4 shows the effect of increasing the oxide thickness along the vertical trench sidewalls relative to the planar region. As observed, the thicker oxide reduces carrier flow along the trench, thereby increasing Ron. The second example in this work concerns the design and analysis of a 1.2 kV Gate-All-Around (GAA) SiC MOSFET structure, whose geometrical features are shown in Fig. 5a. The second example in this work addresses the design and analysis of a 1.2 kV Gate-All-Around (GAA) SiC MOSFET, whose geometric characteristics are shown in Fig. 5a. Assuming a pillar array layout as in Fig. 5b, an appropriate area factor can be defined to scale the current flowing through the unit cell, modeled in TCAD as shown in Fig. 5c. The structure is inherently 3D, lacks a termination region, and requires a simulation approach that leverages structural symmetries and specific modeling techniques. Due to the cylindrical nature of the pillar, cylindrical coordinates were employed to simplify simulations, along with the MLDA model to account for electron density modeling in the channel based on quantum mechanical equations [XX]. This strategy was used to simulate the structure in Fig. 5c, with output characteristics versus pillar radius reported in Fig. 6. One notable effect of small-radius pillars (radius < 50 nm) is the occurrence of a second derivative of the output characteristic greater than zero—an effect not observed in standard MOSFET technologies, which typically show a downward-concave behavior. Finally, Fig. 7 shows how the output characteristics, and thus the breakdown voltage (BV), vary as a function of the pillar angle inside the oxide. This type of analysis is motivated by the actual non-ideal pillar shape that results from the complex fabrication process of such a design. TCAD simulations play a crucial role in the development of highly complex and innovative device architectures, especially those that would otherwise require extensive and costly experimental validation. In the context of 3D SiC MOSFETs, where each prototype iteration involves intricate fabrication steps, TCAD offers an invaluable virtual platform for design optimization, failure analysis, and process sensitivity studies. By enabling comprehensive pre-fabrication insight, TCAD significantly reduces the need for multiple test batches, shortening development cycles and accelerating the innovation pipeline while minimizing resource consumption. [1] Rahimo, M.T., et al. "Singular Point Source MOS Cell Concept (S-MOS) Implemented on a Narrow Mesa Trench IGBT", 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), IEEE, Nagoya, Japan, 27–30 (2021). [2] Rahimo, M.T., et al., "Advanced 1200V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology". MSF 1062, 539–543 (2022). [3] Rahimo, M.T., et al., "Suppression of Short Channel Effects for a SiC MOSFET Based on the S-MOS Cell Concept". KEM 945, 83–89 [4] Scognamillo, C., et al. "TCAD-Based Investigation of a 3.3 kV Planar SiC MOSFET: BV-R ON Trade-Off Optimization." 2024 IEEE 18th International Conference on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG). IEEE, (2024). [5] Maresca, Luca, et al. "SiC GAA MOSFET concept for high power electronics performance evaluation through advanced TCAD simulations." Solid State Phenomena 360 (2024): 75-80. |
| 10:15 | Origin of high mobility in 4H-SiC FinFETs through theoretical analysis of electron scattering mechanism PRESENTER: Shion Toshimitsu ABSTRACT. For physical understanding of mobility enhancement in SiC FinFETs, the electron scattering mechanism in 4H-SiC FinFETs with different fin widths was theoretically analyzed, taking account of the self-consistently calculated electronic states. High mobility in SiC FinFETs is mainly attributed to reduction of Coulomb scattering, resulting from the lowering of potential energy across the fin due to the merger of depletion layers extending from both the sidewalls. Although the influence of trapped charges on channel mobility is negligibly small in SiC FinFETs owing to the reduction, the Coulomb scattering due to fixed charges at the SiO2/SiC interface remains as the dominant limiting factor for channel mobility. |
| 10:30 | FinFET Effect of Vertical-channel Fin-SiC MOSFET PRESENTER: Tomoka Suematsu ABSTRACT. This study focuses on a novel vertical-channel (VC) Fin-SiC structure for power devices, showing superior performance with an ultra-narrow fin channel. The 1.2-kV-class VC Fin-SiC achieves reduced threshold voltage and improved mobility, enhancing efficiency in electric vehicles and power systems. These findings pave the way for developing high-efficiency power devices. |
| 10:45 | Study of interface traps and scattering mechanisms in 4H-SiC MOS channel using gated Hall measurements PRESENTER: Suman Das ABSTRACT. The high density of traps at the oxide semiconductor interface (4H-SiC/SiO2) and various scattering centers [1, 2] at the channel are believed to be responsible for limited channel performance in silicon carbide MOSFETs. Studying the behavior of these traps and the corresponding scattering mechanisms influenced by physical parameters such as doping concentration, oxidation method, and post-oxidation treatment, among others, is crucial. In this work, gated Hall measurements are used to investigate the impact of doping concentration on interface traps and then Hall mobilities are modeled using different scattering mechanisms present at the channel to study universalities in SiC MOSFETs. Figure 1(a) shows a cross section and (b) top-view of the fabricated MOS gated Hall bar. The Hall bar is fabricated on a Si-face 4° off-axis 4H-SiC (0001) wafer, on uniform Al-doped implanted p-well layers ranging from 2×1017 to 3×1018 cm-3. This device is a long channel (Lch=1 mm, Wch=200 um) lateral MOSFET with Hall voltage contacts, fabricated with a thermal oxide passivated with a NO anneal. Figure 2 (a) shows the measured field effect 〖(μ〗_FE) and (b) Hall mobility (μ_Hall) for different p-well concentrations at room temperature. The difference between μ_FE and μ_Hall occurs due to the high density of interface traps. The total charge density at the interface is calculated using a split CV measurement between G to SD keeping the B contact grounded. The typical split CV measurement is shown in Fig 3. The total charge (n_total) measured is consistent with the value calculated from the measured Cox. The free carrier concentration (n_free) is obtained from the gated Hall measurements and then subtracted from n_total to extract occupied trapped charge density (n_trap). These are plotted in Fig 4 (a) and (b), the measured value of n_free is decreasing with the increasing p-well concentrations, and therefore the value of n_trap increases as a result. These traps could be either very shallow traps near the conduction band edge or border traps. To observe the effect of these traps on scattering mechanisms at the channel, the Hall mobility is modeled using different types of mobility components arising due to scattering such as bulk mobility (μ_Bulk), Coulomb limited mobility (μ_C), phonon limited mobility (μ_Ph), and surface roughness limited mobility (μ_SR). Figure 5 shows Hall mobility versus effective field at the channel. The field dependence of μ_Bulk,μ_Ph,and μ_SR is taken from earlier observation from literature [1,3]. The Coulomb limited mobility is then calculated from the measured Hall mobility using Mattheisen’s rule 1/μ_Hall =1/μ_Bulk +1/μ_C+1/μ_Ph +1/μ_SR . The red dotted line is the fit line to the data by considering all the scattering components. Fig. 6 shows the effect on these scattering mechanisms on different doping concentrations. The values of μ_Ph and μ_SR remain constant; however, the values of μ_Bulk and μ_C change. Due to increased remote coulomb scattering centers, μ_C drops with increasing p-well concentration. The increase in total occupied trap density with increasing p-well doping concentration occurs as the threshold voltage moves closer to the conduction band edge and therefore accessing more traps. These traps do not seem to affect phonon or surface roughness scattering properties. These results from Hall measurements and the analysis regarding scattering mechanisms reveal intricate details that are useful in modelling mobilities and improving 4H-SiC/SiO2 channel characteristics. [1] M. Noguchi et al., IEEE Trans. Elec. Dev., 68, 12, (2021). [2] S. Das et al., MDPI Materials, 15, 19 (2022). [3] S. Takagi et. al., IEEE Trans. Elec. Dev. 41, 12 (1994). |
| 11:00 | Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its relation with Transconductance PRESENTER: Ilaria Matacena ABSTRACT. SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/ SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage(I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we investigate the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum. |
| 11:15 | Comparison of Ramp- and ac-based C-V Methods for Characterization of SiC Power MOSFETs PRESENTER: Michel Nagel ABSTRACT. The aim of this paper is to compare ramp- and ac-based C-V methods to explore the footprint of these traps within the capacitance-voltage (C-V) characteristics of SiC power MOSFETs, which potentially affect the dynamic performance of SiC power MOSFETs in actual applications. For understanding the fast and slow switching capabilities of SiC power MOSFETs, it becomes crucial to investigate frequency (f)-dependent C-V MOSFET characteristics captured by the ramp- and the ac- C-V measurement methods. Such an analysis is performed in this work by means of TCAD simulations, which allows for distinguishing physical effects contributing to the f-dependent behavior of SiC power MOSFET’s C-V characteristics that is rather challenging to comprehend from the measurements solely. This work contributes to a deeper understanding of the differences between C-V characteristics obtained from ramp- and ac-C-V measurements, and points out that detailed C-V characterization of SiC power MOSFETs is relevant for specific applications. |
| 13:00 | (Invited) Smart Cut™ for Wide Bandgap Semiconductors: Enhancing SiC’s Potential PRESENTER: Julie Widiez ABSTRACT. Whereas materials were traditionally valued for structural properties, the 20th century saw the emergence of functional materials, capable of storing or transmitting information. In such systems, the substrate, often overlooked, plays a critical role, both structurally and functionally. Modern device requirements impose contradictory demands: high electrical conductivity and insulation (e.g., for an electrical cable), mechanical flexibility and rigidity, thermal dissipation and low permittivity etc. These challenges require new material architectures. Conventional micro/nanofabrication techniques enable either the deposition of amorphous layers onto crystalline substrates or the epitaxial growth of crystalline films on lattice-matched crystalline hosts. However, the reverse - placing a crystalline material onto an amorphous or lattice- incompatible substrate - remains unachievable using standard deposition or etching methods. To address this limitation, Smart Cut™ technology (Fig. 1) enables the transfer of thin crystalline layers onto virtually any handle substrate, including monocrystalline, polycrystalline or even amorphous materials. The choice of host substrate can be driven by functional requirements - such as thermal, electrical, or insulating properties - or by broader considerations such as environmental impact and cost-effectiveness. Originally developed at CEA Leti in the early 1990s for the fabrication of silicon-on-insulator (SOI) substrates [1], Smart Cut™ was industrialized by SOITEC in the 2000s [2] and has since enabled a wide range of engineered substrates including strained SOI (sSOI) [3], germanium- [4-5] and III-V-on insulator [6] (GeOI and III-V-OI). More recently, SmartSiC™ has been developed [7-8], consisting of a thin monocrystalline 4H-SiC layer transferred onto a polycrystalline 3C-SiC handle substrate. For wide bandgap semiconductors such as SiC, GaN, or diamond - materials whose bulk synthesis is extremely energy-intensive (e.g. monocrystalline SiC growth requires temperatures around 2400 °C) - the fabrication of such hybrid substrates offers a promising route to both reduce energy consumption and enable enhanced performance and integration. This work focuses on two such directions: SmartSiC™ substrates for high-voltage power devices and SiC- on-insulator (SiCOI) for photonic applications, enabling the realization of optical waveguides. As shown in Figure 1, the transfer process relies on ion implantation within the WBG material, which leads to the electrical deactivation of dopants and partial lattice disorder. We investigated the healing and dopant reactivation mechanisms in the transferred 4H-SiC layer over a broad temperature range, relevant to both power [9–10] and photonic [11] applications. A combination of advanced characterization techniques – including TEM, XRD, SSRM and Raman spectroscopy - was employed to monitor the structural and electrical recovery of the material. Full restoration of the crystalline quality was observed after annealing at 1300 °C, with no further structural improvement at higher temperatures. At this stage, n-type dopants remained inactive. Reactivation occurred above 1500 °C, consistent with the thermal budget typically required for dopant activation in ion-implanted bulk SiC. Photonic demonstrators on SiCOI are ongoing, but 1200 V power diodes (Schottky, JBS, hexagonal and stripe-cell) have already been fabricated on SmartSiC™ and compared to monoSiC. Static and dynamic electrical characterizations showed i) no significant impact of substrate on OFF-state performance (indicating the absence of additional defects in SmartSiC™ substrate) and (ii) improved ON-state resistance with SmartSiC™ substrate (Figure 3) [12]. |
| 13:30 | Characterization of Al-Gate MOS Capacitor on Thermally-Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method PRESENTER: Masao Sakuraba ABSTRACT. We fabricated aluminum-gate metal-silicon oxide-semiconductor (MOS) diodes in the 4H-SiC and 3C-SiC regions on the surface of a single 4H-SiC wafer by the simultaneous lateral epitaxy (SLE) method and evaluated their high-frequency differential capacitance-voltage (C-V) characteristics. It is confirmed that the formation of accumulation and depletion layers and the clear difference in flat-band voltage. Moreover, inversion layer carrier transport at high-frequency signals was observed only on the 3C-SiC, suggesting the possibility of 2-dimensional hole accumulation at the 3C-SiC/4H-SiC heterointerface due to spontaneous polrization. |
| 13:45 | Key Mechanisms of Laser-Based Splitting and Dicing of 4H-SiC Wafers PRESENTER: Hanan Mir ABSTRACT. Lasers have become indispensable for machining 4H-SiC, offering precision, wear-free operation, and scalability driven by increasing laser power [1]. This is especially valuable in wafer splitting and dicing, where lasers improve material efficiency and reduce costs as substrate sizes grow [2-3]. However, hardness, wide bandgap, and complex absorption mechanisms—including nonlinear, free-carrier, and defect-induced absorption—make laser-SiC interactions highly complex. Doping variations [4] and intrinsic stress introduce spatial inhomogeneities, causing incubation effects and variability that challenge robustness, especially for larger (200 mm) wafers. To address these issues, our research spans three interconnected stages: 1. Fundamental Understanding of Laser Modifications: To quantify spatial inhomogeneities and laser response variability in n-type 4H-SiC, we performed z-scan, absorption, and Raman measurements across full wafers. These revealed ±20% variations in absorption (α) and LO-phonon shifts correlated with doping levels ranging from 5–20 × 10¹⁷ cm⁻³, pointing to inhomogeneous free-carrier absorption as a key influence. We calculated single-pulse damage thresholds with a tunable femtosecond–picosecond source (185 fs to 2.5 ps, w₀ = 8–13 µm), obtaining fluence values from 1.2 to 1.9 J/cm² that increased with pulse duration. Normalized Ablation Efficiency was then evaluated as a function of pulse number, revealing rapid saturation for femtosecond pulses and slower, near-linear accumulation for picosecond pulses over hundreds of shots (Fig. 1a–c). These trends, together with spatial variations in α, indicate that incubation dynamics and local variations in doping could critically affect modification consistency across surface and subsurface machining. 2. Process Development: Based on these physical insights, we investigated processing behaviors in both subsurface and surface regimes. We examined how localized defect generation during subsurface processing triggers amorphization, carbonization, and stress-induced crack initiation, and how these effects can be controlled through tailored hatching patterns (Fig. 2a). Full-wafer splitting was achieved at adjustable depths (Fig. 2b), but residual cleaving forces—linked to laser pattern geometry, crack orientation and extent—promoted vertical crack formation under mechanical loading (Fig. 2e). Surface micromachining experiments demonstrated strong sensitivity of groove depth and uniformity to pulse overlap and energy input. Increased overlap resulted in a clear transition from laser-induced periodic surface structures (LIPSS) to well-defined microgrooves, signifying a critical regime shift driven by cumulative energy input and pulse-to-pulse interactions (Fig. 3a–f). These findings underscore the need for precise spatial control in subsurface splitting to ensure consistent crack propagation and for managing total energy input in surface dicing to increase throughput. 3. Optimized Setups: To overcome these limitations, we developed dedicated experimental setups optimized for each processing regime. For wafer splitting, integrating a nanosecond laser and a high-numerical-aperture objective with in-situ focus control significantly improved spatial stability and minimized Z-position uncertainty, enabling reproducible subsurface cracking. For surface dicing, we employed a high-power ps laser system (τ = 3 ps, 200 W, 1MHz) coupled with a high-speed polygon scanner (w₀≅20μm) achieving scan speeds exceeding 1 km/s. The study examined the impact of normalized fluence (F/Fth, where Fth ≈ 1.82 J/cm²), spatial pulse separation (∆x), and the number of scans (n). As shown in Fig. 3g, ablated depth scaling with total energy input shows that faster deflection speeds maintain micromachining efficiency at high scanning rates, delivering a ten-fold increase in throughput compared to conventional galvo-based dicing. Optimizing laser parameters, understanding incubation phenomena, and enhancing spatial stability collectively enable robust, efficient, and scalable laser-based wafer splitting and high-speed dicing, establishing a pathway to sustainable and high-yield 4H-SiC manufacturing. |
| 14:00 | Comparison of Mo, Mo-carbide and Mo-silicide Schottky contacts on 4H-SiC PRESENTER: Marilena Vivona ABSTRACT. The Schottky-barrier diode (SBD) on 4H-SiC is a well-established technology, which offers undoubted advantages (namely fast switching, low forward voltage drop, high temperature operations) in apllications. However, further enhancements are necessary to fully exploit the potential of 4H-SiC. To this end, various approaches have been explored to improve the properties of the metal/4H-SiC interface, with particular attention to the metal choice and its interaction with 4H-SiC during thermal annealing for the Schottky contact formation. In recent years, molybdenum (Mo) has attracted interest due to its good thermal stability and ability to form contacts with low Schottky barrier height, which is beneficial for minimizing the conduction power losses. As matter of fact, a wide variability in the Schottky barrier height has been observed in Mo/4H-SiC Schottky contacts, depending on factors such as surface passivation treatments, temperature of the metal deposition and metal stack composition, with the barrier heigth varying between 1.0 and 1.5 eV. Based on the ternary phase diagram of the Mo-Si-C system, solid-state reactions can occur between Mo and both silicon (Si) and carbon (C), leading to the formation of carbides and silicides and opens the possibility to further explore and tune the Schottky barrier properties to 4H-SiC, potentially broadening the range of achievable barrier height values. In this study, we investigate the morphological and electrical properties of Mo silicide and carbide-based/4H-SiC contacts. The two contacts show good rectifying properties, with low value of Schottky barrier height. Their properties will be discussed and compared to highlight specific characteristics of the contacts. |
| 13:00 | In-situ measurement of the gain stage of a SiC JFET operational amplifier under gamma ray irradiation PRESENTER: Masayuki Yamamoto ABSTRACT. Research and development of SiC integrated circuits for harsh environments, such as nuclear reactors and space applications, have recently attracted significant attention. Previous studies have investigated the effects of accumulated gamma-ray doses on non-operating (floating) SiC devices and circuits. Although some studies have examined the behavior of SiC circuits under operation during gamma-ray irradiation, the detailed effects of irradiation during active operation remain insufficiently understood. In this study, we conducted in-situ measurements on a SiC JFET operational amplifier operating under gamma-ray irradiation. The results revealed that no abnormal noise appeared in the output signal, and the voltage gain remained consistent with that observed prior to irradiation. However, the output offset voltage decreased by approximately 2 V within a few minutes after the start of irradiation. |
| 13:15 | Improvement of Single-Event Gate Rupture tolerance by terraced gate 4H-SiC DMOSFET PRESENTER: Kana Hiramastu ABSTRACT. The issue with the use of power devices in a space environment is improving tolerance against Single-Event Effects induced by heavy-ion irradiation [1]. Single-Event Gate Rupture (SEGR) is the catastrophic breakdown of a gate oxide caused by an increased electric field in SiO2 [2]. In the case of SiC MOSFET, SEGR is a major concern because the electric field in the gate oxide (Eox) is higher than that of the Si-MOSFET in the off state, owing to the high breakdown electric field of SiC. In this study, we demonstrate the improvement in SEGR tolerance by decreasing Eox in a 4H-SiC planar-gate MOSFET (DMOSFET). |
| 13:30 | Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total Ionizing Dose Radiation and High Drain Voltage Bias PRESENTER: Zhaoxu Song ABSTRACT. Currently, the trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention in power electronic fields owing to their higher channel mobility, higher power density, and low ON-State resistance, and they have the potential to be the candidates that used in aerospace missions [1-2]. However, the total ionizing dose (TID) effect with the high bias conditions, i.e., high drain voltage bias, can heavily degrade the electrical characteristics of the devices and further reduce the operation life [3-4]. As a result, it is of significance to investigate the degradation behaviors and mechanism of the trench SiC MOSFETs under TID radiation with high drain bias conditions comprehensively. Among the electrical characteristics of the SiC MOSFETs, the ON-State resistance has an importance position, which has a strong relation with the current variations and radiation tolerance capability. In fact, the resistance degradation induced by the TID effect makes the current increase, illustrating the ON-State resistance is deeply influenced by the TID effect. In this work, the resistance degradation of the double trench (DT) and the asymmetric trench (AT) SiC MOSFETs are investigated in detailed. The commercial DT (SCT3160KL) and the AT SiC MOSFETs (IMW120R140M1H) with the breakdown voltage over 1200V are selected as the samples and the schematic cross sections of them are shown in Fig. 1. The Cobalt-60 gamma-ray at dose rate of 100 rad(Si)/s is the radiation source in this experiments and the rest of radiation and bias conditions for the samples are listed in Table I. Fig. 2 illustrates the output characteristics of DT and AT SiC MOSFETs, it can be observed that the TID effect makes the drain current (IDS) increase, especially in DT samples. Meanwhile, the drain voltage bias has no impact on the IDS. Notably, when the gate source voltage (VGS) is 12V, the IDS has a drastic increase for the samples A1, B1, and C1, while the IDS has a slight increase for the samples A2, B2, and C2. Actually, the IDS variations results from the channel resistance. Considering that the resistance component under different VGS has changed a lot, the main resistance values are calculated and are depicted in Fig. 3. Here, the RCH1 is the channel resistance when the VGS is 6V, the RCH2 is the channel resistance when the VGS is 12V, and the RD is the drift region resistance, it shows that the channel resistance of the DT samples has obviously decrease compared to the AT samples, which causes the differences of the IDS variations under different VGS. Subsequently, the threshold voltage (VTH), leakage current (IDSS), and the gate leakage current (IGSS) results are shown in Figs. 4-6. Fig. 4 illustrates the TID effect damages the channel region of the devices and the DT samples has more heavily negative shifting than the AT samples, which causes more current increase and the resistance decrease. It also reflects the AT samples have better radiation tolerance capability. Fig. 5 depicts the IDSS increase results, which is resulted from the VTH negative shifting. Apparently, the DT samples have larger IDSS than the AT samples because of the differences in VTH shifting. Fig. 6 shows that the IGSS has no obvious change for both of DT and AT samples, because the IGSS keeps at nA or pA level. It indicates that the IGSS has no sensitive to the TID effect. Finally, the Silvaco TCAD simulations are shown in Figs. 7-8. It is observed that the TID effect causes the oxide trapped charges in oxide, which leading to the channel opened and the current increase than before. The DT structure also exhibits more obvious increase trend than the AT structure under the same radiation and bias conditions, which has good agreements with the tests results. |
| 13:45 | Channel Length Effects on Threshold Voltage Instability in Gamma-Irradiated 4H-SiC PMOSFETs PRESENTER: Chuan-Han Chen ABSTRACT. Silicon carbide (SiC) has emerged as an attractive semiconductor material due to its exceptional physical and electrical properties [1]. In addition to its conventional applications in power electronics—such as electric motors and vehicles—SiC also shows strong potential for use in the aerospace industry [2-3]. Furthermore, continuous advancements in SiC complementary metal-oxide-semiconductor (CMOS) technology over the past years have significantly expanded its range of applications [4-5]. Therefore, the electrical performance and stability of PMOSFETs under harsh environments require thorough investigation. In this study, a channel-length-dependent threshold voltage (Vth) instability in PMOSFETs was identified, and a corresponding mechanism was proposed to explain this behavior. Fig. 1 presents the cross-sectional schematic and simplified process flow of the fabricated PMOSFETs. The devices were subjected to gamma irradiation at a dose rate of 0.515 kGy(Si)/hr for a duration of 2 hours. During irradiation, the gate electrode was biased at –20 V, while the source, drain, and body terminals were grounded. The Vth was defined as the gate voltage at which the normalized drain current, |ID| × (L/W)—where L and W denote the channel length and width, respectively—reached 10 nA. The subthreshold swing (S.S.) was extracted based on the normalized current in the range of 10 to 100 pA. To eliminate the influence of S.S. on Vth, an additional parameter, Vi, was defined as the gate voltage at which the normalized current reached 1 pA. Devices with channel lengths of 0.8 μm and 50 μm were selected to represent the short- and long-channel regimes, respectively. The transfer characteristics of the PMOSFETs before and after irradiation are illustrated in Fig. 2, with the corresponding measured values summarized in Table I. As expected, I-V curves exhibited a leftward shift after 1 kGy gamma exposure due to hole trapping in the gate oxide. The shift observed in short-channel devices was significantly more pronounced than that in their long-channel counterparts. It was estimated that the density of positive charges trapped in the gate oxide of short-channel devices was approximately 2.7 times higher than that in long-channel devices, based on the shift in ΔVi. In order to isolate the effects of gate stress from those of radiation, additional stress tests were conducted on PMOSFETs under gate bias for 2 hours. The results of these tests are shown in Fig. 3. As shown in Table I, the gate-length-dependent effect remained evident; however, it was unexpectedly found that the majority of trapped charges were induced by gate bias stress rather than radiation. Additionally, an improvement in ΔS.S. was observed to reduce the magnitude of |ΔVth|. The limited contribution of radiation to ΔVi can be attributed to the direction of the electric field, which drives positive charges toward the gate electrode. In contrast, radiation primarily contributes to subthreshold swing degradation. The gate oxide contamination is suspected to originate from aluminum (Al) implantation used for the source and drain regions. Fig. 4 presents the secondary ion mass spectrometry (SIMS) analysis of the P+ region after thermal oxidation, confirming that a significant amount of Al dopants remains within the oxide. Despite the low diffusivity of Al in oxide [6], these dopants are still capable of diffusing laterally at elevated temperatures, such as 1200 °C or higher, which are typical gate oxide processing conditions for SiC devices. This suggests that Al atoms diffuse from the edges of the implantation region toward the center of the gate. As the channel length decreases, a larger proportion of the gate oxide becomes contaminated by Al, thereby resulting in degraded performance stability. In summary, a channel-length-dependent Vth instability was observed under gate bias stress and gamma-ray exposure. The majority of positive charge trapping is attributed to hole injection induced by the external bias. SIMS analysis confirmed the presence of aluminum species retained in the gate dielectric after thermal oxidation. Based on the experimental results, it is concluded that dopant contamination in the gate oxide is the primary cause of the channel-length-dependent instability. |
| 14:00 | Isolation of cumulative heavy-ion induced gate degradation effects within a commercial 4H-SiC double trench MOSFET PRESENTER: Peter Gammon ABSTRACT. As 4H-silicon carbide (SiC) double trench MOSFETs gain traction in space applications due to their efficiency and compactness, understanding their resilience to cumulative radiation damage becomes critical. This study investigates the progressive degradation effects in a commercial 4H-SiC double trench MOSFET subjected to continuous heavy-ion irradiation using Xe ions with high linear energy transfer (LET). Experimental results reveal that while the device withstands repeated single-event effects (SEE) below 150 V, degradation emerges above 200 V, manifesting as persistent increases in gate and drain leakage currents and eventual loss of blocking capability. TCAD simulations corroborate the experimental findings, linking gate rupture and source trench damage to the observed leakage behavior. The study identifies source trench vulnerability as a key degradation pathway and highlights that permanent performance loss can occur below catastrophic burnout thresholds. These findings support the need to revise derating strategies for SiC power devices in space environments, taking into account cumulative SEE-induced degradation rather than focusing solely on single-event burnout prevention. |
| 14:45 | (Invited) The mechanisms of Defect Replication, Propagation, Modification, Nucleation and Multiplication in 4H-SiC PVT-grown Substrates and CVD-grown Homo-epitaxial Layers PRESENTER: Michael Dudley ABSTRACT. As silicon carbide, specifically the 4H polytype, based power devices are increasingly being adopted in electric vehicles and chargers, railway, power grid and other high voltage applications, it has become imperative to improve the yield while sustaining reliability and long-term performance. This begins with addressing the basis of 4H-SiC device technology, PVT-grown 4H-SiC wafers and CVD-grown epilayers. The deleterious influence of crystallographic defects in these wafers and epilayers on device yield and performance is well-known [1] and therefore, has led to a heightened awareness of the importance of the minimization of their densities. This requires an intimate understanding of the processes of generation and nucleation of such defects. In this paper, a review is presented of the mechanisms of defect replication, propagation, modification, nucleation and multiplication in 4H-SiC PVT grown substrates and CVD-grown homo-epitaxial layers [2]. The replication of Threading Screw and Mixed Dislocations (TSDs and TMDs), Threading Edge Dislocations (TEDs), Stacking Faults (SFs) and Partial Dislocations (PDs) from seeds during PVT growth (Fig.1) [3] and from substrates during CVD [4] will be discussed. The propagation of Basal Plane Dislocations (BPDs) under thermal gradient induced stress on the basal plane will be described as will the propagation of dislocations belonging to the prismatic slip system under the action of stresses originating from a radial thermal gradient [5]. The modification of TMDs and TSDs by macro-step overgrowth leading to the formation of various types of grown-in SF will be explained [6]. The redirection of Basal Plane Dislocations (BPDs) into TEDs during PVT and CVD growth will be clarified as well as the converse redirection of TEDs into BPDs. The nucleation of dislocations at inclusions during PVT-growth will be elucidated. This will include the nucleation of opposite sign pairs of TMDs, TSDs and TEDs as C inclusions; the prismatic punching of dislocation loops at refractory metal inclusions (Fig.4) [7], the nucleation of half loops of Basal Plane Dislocation (BPD) at 3C inclusions in homo-epitaxial layers, and the nucleation of half loops of BPD at the epilayer surface. Various mechanisms of creation of low angle grain boundaries (LAGBs)will be described. Multiplication of BPDs in substrates via the Frank-Read mechanism will be explained in detail showing the origins of the pinning points (Fig.2,3 [8,9]. Similarly, the multiplication of PDs during thick epilayer growth will be described [10]. The generation of interfacial dislocation during epilayer growth will also be described as well as the mechanism of formation of Half Loop Arrays during such relaxation processes [11]. Strategies for the mitigation and control of these various mechanisms will be discussed. [1 R. Stahlbush, et. al., 2018 IEEE IEDM, IEEE, 2018, pp. 19.4. 1-19.4. 4; J. Sumakeris, et. al., Euro. Phys. J. Appl. Phys. 27(1-3) (2004) 29-35; M. Na, et. al., ECS Transactions 85(7) (2018) 59. [2] B. Raghothamachar, M. Dudley, in Wide Bandgap Semiconductors for Power Electronics: Materials, Devices, Applications (Edited by Peter Wellmann, Noboru Ohtani, Roland Rupp Wiley VCH 2022) [3] T. Ailihumaer, et. al., Materials Science Forum 1004, 44 (2020). [4] H. Wang, et. al., ECS Transactions, 64 (7) 145-152 (2014) [5] J. Guo, et. al., J. Electron. Mater. 46(4), 2040 (2017). [6] S. Byrappa, et. al., Materials Science Forum, 717-720, 347-350, (2012) [7] Q. Cheng, Ph.D. Thesis, Stony Brook University, 2024. [8] H. Wang, et. al., Appl. Phys. Lett. 100, 172105 (2012) [9] Y. Yang, et. al. Materials Science Forum, 924, 172–175 (2018). [10] N.A. Mahadik, et. al., Materials & Design (2024) 113435. [11] N. Zhang, et. al., Appl. Phys. Lett., 94 (12), 122108 (2009). |
| 15:15 | Synchrotron X-ray topography analysis of low angle grain boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals PRESENTER: Jianpei Zhang ABSTRACT. Low angle grain boundaries (LAGB) are aggregation of dislocations, usually threading edge dislocations (TEDs) or edge type basal plane dislocations (BPDs) to accommodate the misorientation of lattice planes[1-2], that lower yield of PVT 4H-SiC substrates and prevent the implementation of large size SiC devices. Therefore, establishing a clear understanding on the dislocation nature of LAGBs and their formation mechanisms is of great significance. Classical formation mechanisms of <1-100> orientation LAGBs are generally associated with threading screw/mixed dislocations (TSDs/TMDs), which act as growth centers by generating spiral steps[3]. TED LAGBs formed as TEDs align along the <1-100> direction to accommodate the c-axis rotation between the TSDs and surrounding regions when growth centers converge. Recently, a step flow based mechanism [4] was proposed which indicates that steps originating from the facet region propagate faster near the boule edges than at the central region of the crystal due to radial temperature difference, forming a horseshoe shaped growth step morphology. Growth fronts encounter each other on the far side of the boule away from the facet forming TED LAGBs to accommodate the misorientation of the two step fronts. In this study, unique distribution patterns of LAGBs observed in physical vapor transport (PVT) grown off-axis 4H-SiC wafers is investigated. Synchrotron X-ray topography (XRT) reveal the presence of LAGBs networks around the facet regions as well as associated with micropipes in two different wafers. For wafer A, LAGBs networks are observed near the facet region (Fig. 1a) consisting of LAGB arrays with white and dark contrast TEDs extending from the facet region. All individual TED arrays in each LAGB set extend along the < 1-100 > directions, with identical 1/3<11-20> Burgers vectors perpendicular to the array direction. Comparison with ray tracing simulated images [4] allows unambiguous identification of the different Burgers vectors and resultant tilt directions. Three spikes are observed on the left edge of facet (Fig. 1b). Based on the horse-shoe shaped mechanism [4], these obesrvations indicate that growth fronts associated with the outer spikes propagate faster than the inner one due to radial temperature gradients. When the growth fronts of the outer spikes encounter each other first, LAGBs are formed along [01-10] & [10-10] directions to accommodate misorientation in this region. Growth front associated with the central spike will keep moving forward and encounter the other two fronts to form the LAGBs along the [1-100] direction. A similar step flow mechanism can explain the formation of LAGBs from a group of micropipes (MPs) observed in the left edge of the wafer A (Fig. 2). Step growth fronts propagates around the MPs and similar to the horse-shoe shaped mechanism, the growth fronts encounter each other to form LAGBs. For wafer B, LAGBs networks are observed in the facet region (Fig. 4) and it consists of LAGB arrays with white and dark contrast TEDs extending from the center of facet to left side of it. Several micropipes (MPs) observed on the right side in the facet region suggest the classical formation mechanism applicable here with MPs acting as growth centers during the growth process and TED LAGBs network formed to accommodate the c-axis rotation between the MPs and the surrounding regions. |
| 15:30 | Revisiting the (4,1) Frank-Type Stacking Fault in 4H-SiC: Extrinsic or Intrinsic Stacking Fault? PRESENTER: Soon-Ku Hong ABSTRACT. Various kinds of stacking faults (SFs) have been reported in 4H-SiC epitaxial wafers, and identification of SFs and structure determination have been investigated by using characteristic photoluminescence (PL) emissions from SFs, high-resolution transmission electron microscope, and high-angle annular dark-field high-resolution scanning transmission electron microscope (HHADF HR-STEM) [1-9]. SFs on close-packed planes like {111} for FCC and {0001} for HCP structures can be classified into Shockley-type SF (SSF) and Frank-type SF (FSF). SSFs are formed by gliding of Shockley partial dislocations, i.e., Shockley gliding of dislocation [6,9,10]. FSFs are formed by removal of layer through the coalescence of vacancies or inserting an additional layer with or without the Shockley gliding. In forming the FSFs Shockley gliding can be engaged additionally [6,9,10]. On the other hand, SFs can be classified into intrinsic and extrinsic SFs [6,9,10]. The key criteria for assigning to intrinsic and extrinsic SFs is whether an extra layer is inserted (extrinsic) or not (intrinsic) [6,10]. In the international standard document that classified typical standard SFs in 4H-SiC with characteristic PL emission wavelengths (C-PLWs), Shockley-type SFs are four kinds of single, double, triple, and quadruple as (3,1), (6,2), (5,3) and (4,4) SFs, respectively. In case of Frank-type SFs, there are three kinds of SFs as intrinsic (5,2) and (4,2), and extrinsic (4,1) SFs. The C-PLWs these 7 kinds of standard SFs in 4H-SiC are well summarized although there are some differences [5,10]. In this study, we investigated commercial 6-inch 4H-SiC epitaxial wafers and substrates by employing PL mapping and spectra analyses, HAADF HR-STEM, and DFT calculations. Based on the investigated results, we claim two critical issues on (4,1) FSF; 1) Is it extrinsic or intrinsic SF? 2) What is the characteristic PL emission wavelength? In the literatures, there are several formation mechanisms for the (4,1) FSF have been proposed, and it was classified to extrinsic FSF [3,8]. Table 1 summarizes the proposed formation mechanisms for the (4,1) FSF. In most cases the (4,1) FSF forms from the intrinsic (5,2) FSF by the ways of the “missing layer” process. If the (4,1) FSF was formed by the “missing layer” processes without the “inserting layer” process, the (4,1) FSF should be the intrinsic FSF not the extrinsic FSF. Fig. 1 shows TEM images for three mechanisms investigated in this study (the SF structures were confirmed by HR-STEM, will be presented at the site) for the (4,1) FSF formations through the “missing layer” process. Fig. 2(a) is HR-STEM image showing the transforming point from the (5,2) FSF to the (4,1) FSF, directly. Our observations are strong evidences for the formation mechanism of the (4,1) FSF from the (5,2) FSF through the “missing layer” process. The other way to form the (4,1) FSF is forming from the (3,2) FSF. The (3,2) FSF is an extrinsic SF without any argument [10,11], which could be formed from the perfect (2,2) 4H-SiC by inserting one layer, simply [6,9]. If the (4,1) FSF was formed in this way it should be extrinsic SF [10]. However, there is no direct TEM imaging result showing the transformation of the (4,1) FSF from the (3,2) FSF. Next issue is the C-PLW for the (4,1) FSF. The C-PLW for the (4,1) FSF was assigned to 424 nm [3,4,8]. However, there are no direct results showing the 424 nm PL emission from the (4,1) FSF by providing both PL and HRTEM (or HR-STEM) picture. Here we can deduce following summary for the C-PLWs from various SFs by surveying investigation in literatures [1-9,11,12 or references therein]; i) the SFs composed with the Zhdanov notation numbers of “3” and “2” like (3,2), (3,3), (3,3,3,2) (3,3,3,3), (3,3,3,3,2), (3,3,3,3,3,2), (3,2,2,3), (3,3,3,2,3,2), and (3,2,3,3,3,2) SFs have the C-PLWs between 420-430 nm. ii) the SFs with the Zhdanov notation number of “4” like (4,4), (4,2), (3,3,3,4), (3,3,2,2,4,2), and (4,3,2,3) SFs have C-PLW between 454-460 nm except the reported 424 nm for the (4,1) SF. iii) the SFs with the Zhdanov notation number of “5”, like (5,2), (5,3), and (5,3,3,2) SFs appeared at the C-PLWs of 482-485 nm. iv) the SF with the Zhdanov notation number “6” like (6,2) SF showed the C-PLW of about 503 nm. The C-PLWs from investigated SFs in the literatures since the late 2000s have shown a robust tendency of the C-PLWs of ~425 nm ~455 nm ~483 nm ~503 nm as the Zhdanov notation changed by (3,#) (4,#) (5,#) (6,#), except the 424 nm of the (4,1) FSF. Therefore, having a question on the C-PLW of 424 nm for the (4,1) SF is reasonable. Fig.2 (b) shows PL map image corresponding to the HR-STEM image of Fig. 2(a). Fig.2(c) shows a spectrum line scan result from the SF and the corresponding C-PLWs are 483 and 459 nm as shown in Fig. 2(d). Fig. 2 clearly showed that the C-PLWs for the (4,1) FSF is 459 nm. This is the first direct evidence for the C-PLW of the (4,1) FSF. The 483 nm C-PLW is from the (5,2) FSF [5,6]. In conclusion, the (4,1) FSF should be the intrinsic SF if formed through the missing process and its C-PLW should be 459 nm not 424 nm. Detailed further results including formation mechanisms, DFT calculations of stacking fault energies and band structures with SFs will be presented, additionally. This work was supported by the Technology Innovation Program (25A02037) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea). [1] T. Kimoto, Jpn. J. Appl. Phys. 54, 040103 (2015). [2] H. Tsuchida, I. Kamata, M. Nagano, J. Cryst. Growth. 310, 757 (2008). [3] I. Kamata, X. Zhang, and H. Tsuchida, Appl. Phys. Lett. 97, 172107 (2010). [4] I. Kamata, X. Zhang, H. Tsuchida, Mater. Sci. Forum.725, 15 (2012). [5] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Mater. Sci. Semicond. Process. 175, 108247 (2024). [6] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Appl. Phys. Lett. 124, 152109 (2024). [7] S. Hayashi, H. Sako, J. Senzaki, J. Cryst. Growth. 648, 127880 (2024). [8] International Electrotechnical Commission (IEC), Semiconductor Devices, Part 3, IEC 63068-3:2020, IEC, 2020. [9] M. Na, S.-K. Hong, W. Bahng, H. Jung, C. Oh, D. Jang, D. Kim, T. Iqbal, J. Park, Y. G. Park, Appl. Surf. Sci. 703, 163425 (2025). [10] D. Hull and D. J. Bacon, Introduction to Dislocations, 5th ed. (Butterworth-Heinemann, 2011). [11] M. Aoki, H. Kawanowa, G. Feng, and T. Kimoto, Jpn. J. Appl. Phys. 52, 061301 (2013). [12] H. Suo, T. Yamashita, K. Eto, A. Miyasaka, H. Osawa, T. Kato, and H. Okumura, Jpn. J. Appl. Phys. 61, 105502 (2022). |
| 15:45 | Polytype analysis of 3C-SiC/4H-SiC stacked epilayers on trenched 4H-SiC substrates by Raman spectroscopy PRESENTER: Masashi Kato ABSTRACT. In this study, we evaluated 3C-SiC/4H-SiC stacked epilayers on trenched 4H-SiC substrates. We discussed the relationship between the substrate trench structures prior to epitaxial growth and the SiC polytype based on the peak intensity ratio of Raman spectra. |
| 16:00 | Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method PRESENTER: Zeyu Chen ABSTRACT. Silicon carbide (SiC) is a semiconductor with a wide bandgap and exceptional electronic and physical properties, including high saturation velocity, high breakdown field, and excellent thermal conductivity [1]. These attributes make SiC a highly promising material for demanding applications involving high voltage, high power, and high temperature environments. The development of large-scale, high-quality single crystal SiC is crucial for enhancing device performance and broadening its application scope. Among the available growth techniques, physical vapor transport (PVT) [2] is the most widely used method, as it allows the production of large SiC substrates with controllable growth rates. However, the presence of various crystallographic defects, such as threading screw/mixed dislocations (TSDs/TMDs) and micropipes (MPs) can significantly impact device performance, limiting the full potential of SiC-based technologies [3,4]. Therefore, the generation and impact of such defects during PVT growth should be thoroughly investigated to improve the growth processing and furnace design. In this study, one 4H-SiC wafer was analyzed by synchrotron white beam X-ray topography (SWBXT)while mappings of TSDs/TMDs density for the sequence of wafers sliced from the same boule were conducted by high resolution X-ray topography (HRXRT) in 0008 reflection. Fig. 1(a) and 1(b) show the SWBXT in 1-100 and 1-101 reflections, where formation of mixed Frank and Shockley type stacking faults due to deflection of the TSDs/TMDs can be observed in the region between the spoke pattern which is highlighted by the dotted lines. Fig. 1(c) to 1(e) show some selected density maps of TSDs/TMDs from the seed side to the dome side, where higher density of TSDs/TMDs were observed in the earlier growth stage near the facet region (Fig.1(c)) and the TSD/TMD density decreases as the wafer is closer to the dome side. Here, the spoke feature near the center of the wafer, highlighted by the dotted box, will be specifically analyzed. Two areas with lower TSDs/TMDs density between the central spoke are highlighted by the white solid line box. The TSD/TMD density decreases due to the deflection process as the growth progresses, where deflections occur in between the central spokes (Fig. 1(d)) then more deflections take place on the central spokes. Generally, TSDs/TMDs will have a faster growth rate than other parts of the crystal and form spiral steps during the growth [5], then when these steps merge, a growth island will be formed on the surface as shown in Fig.2(a). When the growth proceeds, step bunching occurs and deflects TSDs/TMDs toward the step flow direction (Fig.2(b) and (c)). Since the density of TSDs/TMDs are lower between the central spoke, as shown in the white box of Fig.1(c), the growth rate along [000-1] will be slower, leading to ridge formation on the spoke position, as shown in Fig.2(d). Therefore, macrosteps can be accumulated between the spokes that then cause the deflection of TSDs/TMDs in that region, as shown in Fig.2 (e). Finally, as the growth interface becomes convex, all the TSDs/TMDs will be deflected as shown in Fig. 2(f) and (g)). The detailed mechanism of the spoke pattern of stacking faults will be developed with supporting microstructure data and presented. [1] A.A. Lebedev and V.E. Chelnokov, Semiconductors 33, 999–1001 (1999). [2] Y. M. Tairov and V.F. Tsvetkov, Journal of Crystal Growth 43(2), 209-212 (1978) [3] P. Bergmanet al, Mater. Sci. Forum 353-356, 299-302 (2001) [4] P. G.Neudeck et al, Solid-State Electronics 42(12), 2157-2164 (1998). [5] WK Burton, N Cabrera, FC Frank, Philosophical Transactions of the Royal Society of London. Series A, Mathematical and Physical Sciences 243.866, 299-358 (1951). |
| 14:45 | (Invited) Technology Trends of performance improvement in SiC MOSFETs: The Impact of Trench and Super Junction Structure Technology PRESENTER: Hiroshi Kono ABSTRACT. Silicon carbide (SiC) power devices are promising candidates for miniaturization of power devices and achieving lightweight power conversion units. For instance, the on-resistance (Ron) of 1.2 kV-class silicon carbide MOSFETs has decreased significantly over the past 15 years, reaching approximately 2 mΩcm² today. It is expected that 1 mΩcm² will be achievable by around 2030 (Fig. 1) [1]. This presentation will discuss the device technologies supporting this trend. SiC has a poorer quality oxide interface compared to silicon, and its low inversion channel mobility results in high channel resistance. To address this issue, the cell pitch has been miniaturized to increase channel density. In addition to conventional cell pitch miniaturization, trench MOSFET structures can further reduce device losses by utilizing the m-face and a-face of SiC, which have higher mobility compared to the Si-face. Although SiC has high breakdown electric fields, the electric field on the gate oxide on the semiconductor increases. Therefore, design strategies for managing this electric field are necessary to ensure long-term reliability. In fact, trench MOSFETs have pseudo-JFET resistance due to their structure, which relieves the electric field on the gate oxide film at the bottom of the trench. Therefore, they do not have a simple advantage over planar devices with JFET resistance seen in Si devices. Consequently, trench MOSFETs must have a field protection structure that achieves both low Ron and high short-circuit withstand capability. Figure 2 shows the schematics of trench MOSFET with bottom-p structure [2]. This paper discusses the technical challenges and improvement efforts related to trench MOSFETs with bottom field protection structures. SiC is a device that can operate in high temperatures condition [3]. However, the resistance of the drift layer increases significantly at high temperatures. Therefore, in power conversion system designs that require high-temperature operation, loss reduction with SiC devices cannot be expected to achieve the same level as at room temperature. A promising candidate to address this issue is SiC Super Junction. The Super Junction structure uses a higher concentration of drift layer compared to conventional structures. In this case, the decrease in electron mobility is suppressed, resulting in a smaller increase in resistance compared to low-concentration cases. Generally, SJ structures are considered candidates for high-voltage SiC devices, but from the perspective of reducing high-temperature losses, they can demonstrate sufficient advantages even at medium voltages. Figure 3 shows the schematics of a super junction SBD structure and characteristics of fabricated devices [4]. This point will also be discussed. This paper is based on results obtained from a project, JPNP21029, subsidized by the New Energy and Industrial Technology Development Organization (NEDO). [1] H. Kono, R. Ohara, T. Suzuki, S. Asaba and K. Sano, "Performance and Reliability Improvement Trends in Silicon Carbide Power Devices," 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2024, pp. 1-4. [2] K. Tanaka, Y. Kusumoto, H. Hasegawa, H. Kono, K. Sano, “Impact of bottom p-well grounding resistance on unclamped inductive switching ruggedness of SiC trench MOSFETs”, Proc. 2025 37th ISPSD, 2025. [3] H. Kono et al. “14.6 mΩcm2 3.3 kV DIMOSFET on 4H-SiC (000-1).” Materials Science Forum, vol. 778–780, pp. 935–938, (2014). [4] H. Kono, K. Tanaka, T. Kiyosawa, K. Sano, “Investigation of static and dynamic behavior of silicon carbide semi-super-junction structure in Schottky barrier diodes”, Proc. 2025 37th ISPSD, 2025. |
| 15:15 | Effect of Dynamic AGE-ing Process on the Electrical Characteristics of 3.3kV SiC MOSFETs PRESENTER: Kumiko Konishi ABSTRACT. A major challenge for the expansion of the SiC power device market is to improve the quality of the SiC epitaxial wafers. To address this issue, a non-contact process technology (Dynamic AGE-ing (DA) process) that integrates thermal etching and crystal growth is being investigated. By applying the DA process, it is possible to remove the damaged layer of SiC bulk wafers and form a BPD-free buffer layer, which is expected to result in low-defect density SiC epitaxial wafers. The application of the DA process can affect the electrical characteristics of SiC devices, but there are no reports on the characteristics of SiC MOSFETs to which the DA process has been applied. Therefore, in this study, we experimentally verified the effect of the DA process on the device characteristics. We fabricated 3.3 kV SiC MOSFETs by applying the DA process to the buffer layer and experimentally investigated the effect of the DA layer on the electrical characteristics. The results showed that the recovery loss can be reduced by 50% without deteriorating the static characteristics. As a next step, we plan to proceed with the reliability evaluation of SiC MOSFETs with a DA layer. |
| 15:30 | High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd Quadrant Conduction PRESENTER: Shariare Hossain Rabbi ABSTRACT. Junction Barrier Schottky (JBS) Diode integrated MOSFET (JBSFETs) are promising for high-voltage 4H-SiC power applications, offering superior 3rd quadrant performance and unipolar current conduction. This becomes critical for high-voltage devices, where an integrated JBS diode helps mitigate bipolar degradation caused by basal plane dislocations (BPDs) [1]. While JBSFETs may exhibit higher specific on-resistance (Ron,sp) due to increased cell pitch, structural innovations with efficiently integrated JBS diode enhance the forward conduction, achieving performance comparable to that of MOSFET [2]. Although such performance has been demonstrated in low-voltage devices, it has yet to be achieved in high-voltage applications. Building on prior work where Stripe JBSFET showed reduced 3rd quadrant forward voltage drop (VF) compared to nominal MOSFET [1], this study extends the technique to enhance the 3rd quadrant conduction, while offering the same Ron,sp. A comparative analysis of JBSFET structures and MOSFET is presented, focusing on structural evolution, trade-offs in Ron, sp, VF, and the role of Schottky width in reducing leakage current for enhanced high-voltage device reliability. Fig. 1 illustrates the structural differences between the JBSFETs and the MOSFET. These include: (1) Nominal MOSFET with a P+ source is placed in the orthogonal direction, with the linear topology of the MOSFET, (2) the Stripe JBSFET features the widest cell pitch with a linear Schottky region, (3) the Island P+ JBSFET with the Schottky opening placed in the orthogonal direction shielded solely by the P-well in X-direction. Fig. 2 illustrates that, along the X-direction, the Schottky region in the Stripe and Island P+ JBSFET is shielded by a P+ region and the P-well, respectively. The exclusion of the P⁺ region in the X-direction leads to a significant reduction in cell pitch, resulting in the most compact JBSFET design, which is slightly larger than that of the nominal MOSFET [2]. To ensure a fair comparison, all devices were fabricated with the same active area, JFET width, and channel length. Fig. 3 shows the forward conduction, where the Island P+ JBSFET achieves a significantly lower Ron,sp than the Stripe JBSFET due to its reduced cell pitch, and closely matches the MOSFET performance, offering a 7.55% improvement over the Stripe JBSFET. Fig. 4 shows that the Island P+ JBSFET exhibits a lower VF than the Stripe JBSFET and outperforms the MOSFET during the 3rd quadrant operation. Notably, despite the discontinuity of the Schottky region in the Island P+ JBSFET, the aggressive cell pitch design increases Schottky density, resulting in highly efficient unipolar current conduction and a substantial reduction in VF. In Fig. 5, the nominal MOSFET and Island P+ JBSFET showed avalanche breakdown with a high breakdown voltage of 8.3kV, where the Stripe JBSFET showed soft-breakdown due to high leakage current governed by the high electric field beneath its large Schottky region. Although leakage was high in the Island P+ JBSFET, this can be reduced by reducing the Schottky width to 0.8 µm with a cell pitch of 5.2µm, as shown in Fig. 6. However, this also impacts 3rd quadrant conduction and requires further optimization of Schottky width and process conditions. Among these JBSFET variants and MOSFET, the Stripe structure demonstrates improved 3rd quadrant performance but suffers from the highest Ron,sp, and leakage current with the largest cell pitch compared to the nominal MOSFET. In contrast, the Island P+ design achieves the lower Ron,sp than the Stripe structure, which offers almost the same Ron,sp as the nominal MOSFET. The superior 3rd quadrant performance of the Island P+ structure, thanks to the design innovation to achieve a smaller cell pitch, as illustrated in Fig. 7. Despite a slightly larger cell pitch than the MOSFET, the Island P+ JBSFET demonstrates well-balanced performance in forward conduction, 3rd quadrant behavior, and leakage current, underscoring its strong potential as a next-generation high-voltage, reliable power device. |
| 15:45 | Minimizing edge termination footprint in UHV SiC power devices: an area-efficient edge structure for power devices rated over 10 kV PRESENTER: Marco Pocaterra ABSTRACT. Ultra-High-Voltage (UHV) SiC devices are drawing attention as leading candidates for next-generation power systems, enabling performance advantages, topology simplifications and footprint reductions in the expanding market of MV high-power converters [1]. A critical aspect for UHV-SiC devices with blocking ratings exceeding 10 kV, is the design of effective edge-termination structures. Conventional edge structures with UHV blocking capabilities often entail large termination footprints. Such area consumption is particularly critical as UHV capabilities require the use of expensive SiC wafers with drift region thickness exceeding 100 µm [2]. Therefore, minimizing termination footprint while ensuring robust blocking performance is paramount for the commercialization of UHV-SiC devices. In this work, compact UHV terminations are investigated by TCAD simulations and designs achieving >10 kV blocking within a < 350 µm footprint are experimentally demonstrated. Fig. 1 summarizes the concept and parameters of the termination of this work. This is a derivation the RA-JTE concept [3-4] where, differently from conventional design, high dose p-rings are used to enhance blocking capabilities. Table 1 summarizes the parameters of the four investigated designs (D1-D4). Fig. 2 compares the blocking capabilities extracted by TCAD for the investigated designs, comparatively to that of their constituent parts (rings and JTE only terminations), highlighting how the careful addition of p-rings in the JTE implant allows larger blocking voltages without increasing the footprint. The working principle of the terminations is further examined in Fig. 3. Fig. 3 (a) reports the electric field (EF) intensity in SiC as a function of the blocking voltage, showing that up to 10 kV all designs contain the maximum EF below the 2-2.5 MV/cm range. As further highlighted in Fig. 3(b), the EF peak is initially located at the JTE implant edge whereas, during the depletion of the main JTE implant at larger voltages, the p-rings get progressively engaged and the peak EF travels towards the active-transition overlap. Following the TCAD investigation, the terminations have been implemented in SiC-MOSFETs realized on 6-inch 4H-SiC wafers with a 100 µm thick epitaxial layer. A multi-mask approach has been employed to replicate the different termination designs on the same wafer. The implanted JTE dose has been varied across different wafers within a 50% range from the simulation optimal dose, while the p-ring dose has been fixed to a level that minimizes their depletion at increased blocking voltages. Experimental results are reported for the optimal dose only. The blocking capability of the MOSFETs has been characterized up to 10 kV directly at the wafer level. Fig. 4 exemplifies the blocking characteristics of MOSFETs employing D3 terminations. Within the investigated blocking range, the leakage current is mostly contained below 10 nA. Further experimental data is reported in Fig. 5. Fig. 5 (a) shows the cumulative distribution of the blocking voltage reached by the four designs (VBD defined at IDS(VDS)=1µA). While for designs D1, D2 and D3, around 60% of the population exhibit a blocking voltage exceeding 10 kV, samples employing D4 design do not block over 3 kV, highlighting the role of the p-ring distribution in enhancing the blocking voltage and desensitizing the design from JTE dose variations. Fig. 5 (b) reports on the leakage current probability distribution for designs D1, D2 and D3, measured at 9 kV. On average, design D1 exhibits the lowest leakage current, with almost 70% of the population leaking less than 100 nA. Such result highlights the impact of the JTE width on the leakage current, where the reduced depletion area achieved by a smaller JTE allows to limit the average leakage current. Additional details and experimental characterization will be included in the final paper. |
Analysis of Axial Resistivity During SiC Crystal Growth by PVT Method PRESENTER: Lingling Xuan ABSTRACT. Nitrogen doped n-type SiC substrates are extensively employed for high-power devices, where a low and uniform resistivity distribution is essential for minimizing on-resistance fluctuations across the wafer [1]. The resistivity of SiC crystals is strongly influenced by key growth parameters, including growth temperature, C/Si ratio and nitrogen partial pressure. In this study, a comprehensive multi-physical model coupling heat and mass transport have been developed to simulate the growth process of SiC crystals via the physical vapor transport (PVT) method (Fig. 1(a)). This model incorporated gas exchange across the crucible and crucible etching reaction to provide a more accurate explanation of experimental observations. The effects of these factors on temperature, C/Si ratio and nitrogen distribution at the growth front were thoroughly analyzed. The study revealed the evolution of temperature, C/Si ratio and nitrogen incorporation along the crystal length at the growth front (Fig. 1(b), (c)). By comparing numerical simulation results with experimental resistivity distributions (Fig. 1(d)), the key factors influencing crystal resistivity were identified. Furthermore, for the first time, the nitrogen doping efficiency in 4H-SiC crystal growth using the PVT method has been given based on computed and measured nitrogen concentrations [2]. |
Homoepitaxy and defect control of 300-μm ultra-thick 4H-SiC layers PRESENTER: Rong Wang ABSTRACT. Owing to the unique properties including wide bandgap, high breakdown electric field strength, high thermal conductivity, high carrier mobility, and high stability, 4H silicon carbide (4H-SiC) homoepitaxial layers with the thickness lower than 30 μm have gained a great success in midium- and high-voltage power electronics such as electric vehicles, photovoltaics and rail transits [1]. As the application of 4H-SiC is spreading to ultra-high power devices including smart grids, offshore wind powers and radiation detectors, developing 4H-SiC epitaxial layers with ultra-high thickness, ultra-low doping concentration and high-demanding defect control becomes the development trend of 4H-SiC homoepitaxy [2]. In this work, we firstly optimize the configuration of the 4H-SiC epitaxy chamber for the epitaxy of ultra-thick 4H-SiC layers. The dependence of the distribution of doping concentration under different inlet C/Si ratios are investigated by combining SiHCl3-C2H4-H2 CVD and numerical simulations. We find that the net doping concentration decreases and the distribution of net-doping concentration changes from “M” to “∩” shape, and the wafer-scale distribution of N exhibits the invariable “∩” shape [Fig. 1 (a)]. The non-uniform distribution of C/Si ratio contributes to a non-uniformity of net carriers. We propose that reducing the hot wall height and reducing the edge C/Si ratio is promising in improving the uniformity of net carrier distribution in ultra-thick 4H-SiC layers [3]. The dependence of step-flow growth on the growth rate and C/Si ratio of 4H-SiC is then investigated. The growth window of ultra-thick 4H-SiC homoepitaxial layers is established, which ensures stable step-flow growth and lays the foundation of defect control [Fig. 1 (b)]. During the defect control, we find that the downfall disturbs the step-flow growth of 4H-SiC, and causes the formation of triangular defects. The internal stress originating from triangular defects plays a critical role in the nucleation and slip of BPD half-loop and in the formation of the dislocation half-loop array [4] [Fig. 1 (c)]. Therefore, optimizing the maintenance period is critical to reduce the density of triangular defects and dislocation half-loop array, which is beneficial to enhance the yield and reliability of ultra-high power devices based on 4H-SiC. Combining the optimization of thermal and flow field, the improvement of wafer-scale doping uniformity, and the defect control, we finally obtain ultra-thick 4H-SiC layers with the thickness above 300 μm. The wafer-scale doping uniformity is as low as 8.29%, and there does not exist any macroscopic defects [Fig. 1 (d)]. [1] T. Kimoto and J. A. Cooper, Fundamentals of silicon carbide technology: growth, characterization, devices, and applications, John Wiley & Sons (2014). [2] R. Wang, Y. Huang, D. Yang, X. Pi, Appl. Phys. Lett. 122 (2023) 180501. [3] W. Liu, R. Wang, D. Yang, X. Pi, Sci. China. Inf. Sci. In press (2025). [4] W. Liu, X. Wei, X. Zhao, R. Wang, D. Yang, X. Pi, J. Phys. D: Appl. Phys. 58 (2025) 175103. |
Development of high concentration uniformity epitaxial growth on 200 mm 4H-SiC wafers PRESENTER: Weining Qian ABSTRACT. Silicon carbide (SiC), with its exceptional electrical properties such as wide energy band gap, high breakdown electric field strength, and high thermal conductivity, exhibits revolutionary advantages over silicon (Si) in numerous applications [1]. As is well known, larger-diameter SiC wafers enable higher device counts per wafer with driving down per-unit device costs [2]. Therefore, in order to reduce the device cost and improve device performance, SiC wafer diameters have progressively evolved from 100 mm ( 4 inch ) to 150 mm ( 6 inch ), and are now advancing toward 200 mm ( 8 inch ) technology [3]. The performance of power devices depends to a large extent on the quality of 4H-SiC epi-wafers [4], so the homoepitaxial growth of 4H-SiC is critical for the fabrication of 4H-SiC power devices. As the diameter of the 200 mm substrates increases, the difficulty of controlling multiple physical fields significantly multiplies in epitaxial growth process, especially with respect to the thermal field and flow field. The radial temperature gradient increases and the gas flow dynamics within the reaction chamber become more complex, which makes the problem of uneven nitrogen doping even more apparent [5]. Therefore, achieving high doping concentration uniformity(δ/mean) of epitaxial layers on 200 mm substrates is critical factor for minimizing device performance variation across large-diameter substrates. This work presents the most recent results coming from the optimization of homoepitaxially grown n-type 4H-SiC epilayers on 200 mm substrates. Through systematic optimization of critical process parameters including main H2 flow rate, C/Si ratio, dopant source flow, growth temperature and so on, we achieved significant improvement in the concentration uniformity. This optimization successfully enhanced the doping concentration uniformity of the epi-wafer from an initial 3.56% (with 5 mm edge exclusion) to an exceptional 0.67%, as illustrated in Fig.1 (a). Meanwhile, the thickness uniformity of the epi-wafer is 0.81% in Fig.1 (b), and the total number of triangle and downfall defects is only 3 in Fig.1 (c). Furthermore, the statistics data based on recent over 8,000 epi-wafers were analyzed for the optimized process. The doping concentration uniformity of 75% epi-wafers is below 2% in Fig.2 (a). The thickness uniformity of 75% epi-wafers is below 1.57% in Fig.2 (b). And the total usable area (TUA, 5 mm*5 mm) of 75% epi-wafers is above 97.1% in Fig.2 (c). These researches demonstrate successful achievement of excellent growth process for high quality 4H-SiC homoepitaxial layers on 4° off-axis 200 mm substrates. This technological breakthrough represents a milestone in the industrialization of 200 mm SiC epitaxy. |
Ring Coating Thickness Control for High Quality N type 4H-SiC Epilayers Based on Growth and Doping Kinetic Analysis PRESENTER: Jiahui Wang ABSTRACT. The advancement of 4H-SiC epitaxial layers is critical for next-generation power electronics, yet challenges persist in achieving uniform doping and thickness control while minimizing defects[1]. Recent studies emphasize the role of reactor design and process parameters in optimizing epitaxial growth, particularly for high quality N type 4H-SiC thick epilayers under high-temperature chemical vapor deposition (CVD) conditions. However, the doping mechanisms during deposition processes remain poorly understood, resulting in unresolved doping drift phenomena and insufficient guidance for process adjustment strategies. In this work, we present a first-reported three-dimensional (3D) multiphysics simulation modle specifically tailored for the SiHCl3/C2H4/H2 system with N2 as doping precursor, incorporating growth and doping reaction kinetics. Based on this model, the effects of key process parameters and ring coating thickness on growth dynamics and doping behavior were systematically investigated, and the quantitative relationship between coating thickness and nitrogen doping distribution is established, leading to the reliable optimization methodology for doping uniformity, which provides an effective solution to these challenges. Model details The three-dimensional geometry of the horizontal hot-wall CVD reactor was employed to define the geometric boundary conditions for the computational model (Figure 1). The Navier-Stokes equation and convection-diffusion equation were used to describe the flow and transport of the gas species. Regarding the chemical reaction kinetics, the growth-related parameters adopted in this study were derived from our previously validated work [2]. Furthermore, Table 1 summarizes the nitrogen doping corresponding kinetic parameters, which have been systematically characterized in reference [3]. Effect of the ring coating thickness and process parameters on the growth and doping Figure 2 shows the C/Si ratio exerts the most pronounced influence on the epitaxial growth rate, whereas the ring coating thickness and N2 center/side flow ratio predominantly affect doping efficiency. Notably, with the accumulation of growth runs and concomitant increase in ring thickness, precise control of doping concentration solely through adjustments of process parameters becomes increasingly challenging, particularly pronounced in epitaxial layers with lower doping concentrations. Consequently, it is imperative to systematically investigate the correlation between doping behavior and ring thickness variations, thereby enabling precise adjustments of process parameters during epitaxial growth to ensure wafer-to-wafer uniformity in doping concentration. Investigating the mechanism underlying the impact of ring coating thickness on doping behavior To elucidate the underlying mechanism, we further analyzed the gas-phase and surface reaction kinetics governing the growth and doping processes (Figure 3). The epitaxial film deposition was found to be limited by surface SiCl_s species, while the doping efficiency was constrained by N_s species availability, coupled with competitive interactions with carbon surface species. Upon increasing the ring thickness, the concentration of SiCl_s species exhibited minimal variation, whereas a substantial alteration in N_s species distribution was observed, thereby accounting for the significant changes in doping concentration. Calculation results demonstrate that ring coating thicknesses spanning 1-1.5 mm necessitate an increase in the N2 center/side flow ratio to compensate for thickness-dependent doping drift, thereby maintaining wafer-consistent doping concentrations within ±3% specification limits. |
Control of SSF Defects in 8-inch SiC Epitaxial Wafers PRESENTER: Zehua Wang ABSTRACT. Silicon carbide (SiC) has been considered as a promising material for next generation power devices in recent years. While the industry has established strict control over fatal defects such as triangles, downfalls and carrots in the early stages of SiC epitaxy, growing attention has been paid toward Shockley stacking faults (SSFs)[1-2], which can cause test failure during the reliability process of SiC MOSFIT devices [3-4]. This presentation demonstrates a systematic study on defect suppression and process optimization during high-speed epitaxy of 4H-SiC using Naso Tech’s novel 8 inch horizontal hot-wall CVD equipment. It is found (1) the SSF density in epilayers depends strong on the basal plane dislocation (BPD) density in substrates through quantitative analysis via molten KOH etching and photoluminescence (PL) mapping. (2) the SSF density can also be significantly reduced through process optimization. Low epitaxial growth rate (≤12 μm/h) adopted in the buffer layer can efficiently suppress formation of SSFs. The relationships of the SSF density in SiC epilayer with the BPD density of the substrates and the growth rate of buffer layer are listed in Table I and II. Here show the results of recent consecutive growth runs on 8 inch SiC substrates. An average SSF densities of 0.16 cm⁻² has been achieved on 25 grade-D SiC substrates while the nonuniformity of thickness (σ/mean) is about 1% and the nonuniformity of doping concentration (σ/mean) is less than 1%. Naso Tech’s innovations in process and reactor design directly address critical industry challenges in high-quality SiC device manufacturing. The demonstrated reactor systems have been successfully deployed in major Chinese epitaxial foundries, accelerating the transition to 8-inch SiC production while setting new benchmarks for defect control. [1] S. Izumi, H. Tsuchida, I. Kamata, and T. Tawara , APPLIED PHYSICS LETTERS 86, 202108 (2005). [2] H. Tsuchida, I. Kamata, T. Jikimoto, and K. Izumi, J. Cryst. Growth 237, 1206 (2002) . [3] Hull, D. and Bacon, D.J. (2001) Introduction to Dislocations, 4th edn, Butteworth-Heinemann. [4] Skowronski, M. and Ha, S. (2006) Degradation of hexagonal silicon-carbide-based bipolar devices. J. Appl. Phys., 99,011101. |
Heteroepitaxial Growth of CVD SiC on Graphene Buffer Layers Formed on SiC wafers PRESENTER: Jungmin Lee ABSTRACT. Direct growth of graphene on an off-axis Si-face SiC wafer has been identified as a promising technology for producing high-quality graphene [1]. This study demonstrates the growth of highly ordered monolayer graphene (MLG) and a graphene buffer layer (GBL) on a 4H off-axis SiC wafer through thermal decomposition of SiC. Thermal decomposition was conducted at temperatures ranging from 1300°C to 1600°C in an argon atmosphere (1 atm) to achieve well-ordered graphene layers on these SiC substrates. Silicon powder served as a decomposing agent of silicon gas within a graphite crucible adjacent to the SiC wafer to facilitate smoother and controlled formation of MLG and GBL layers. The resulting MLG and GBL were analyzed using electrical resistance measurements, atomic force microscopy (AFM), Raman spectroscopy, X-ray Photo-electron Spectroscopy (XPS), and transmission electron microscopy (TEM). The roughnesses of the GBL and MLG formed on the SiC wafer is 0.45 nm and 1.07 nm, respectively. Electrical conductivity of the graphene, assessed through the van der Pauw method, exhibited values up to 2.52×106 S/cm depending on orientation. Additionally, heteroepitaxial growth of chemical vapor deposition (CVD) SiC utilizing a methyltrichlorosilane (MTS) precursor and hydrogen flow was applied to the MLG and GBL on the off-axis Si face SiC wafer. As the grown thickness increased, a transitional interface appeared in the growth mode, shifting from epitaxial to polycrystalline or amorphous formations. The number of graphene layers on the substrate and the CVD temperature significantly influenced the SiC growth mode. Thin epitaxial SiC films with thicknesses ranging from 20 to 50 nm were successfully fabricated at 1300°C on the GBL. In HR-TEM analysis, the epitaxial SiC layer conformed to the single crystal SiC wafer substrate confirmed by Fast Fourier Transform (FFT) spot alignment with the substrate diffraction pattern dots, indicating the occurrence of epitaxial growth.Remarkably, the deposited layer could be easily detached from the substrate using commercial tape. Importantly, the GBL on the SiC wafer was sequentially reused for CVD SiC deposition, allowing this process to be repeated multiple times for CVD SiC layer production using a single 4H SiC wafer. Detached layers were transfered onto silicon dioxide insulating substrates, and two-probe devices were fabricated for semiconductor applications. This study demonstrates that the formation of GBL and the CVD SiC deposition process can be performed in conventional graphite heating furnaces and CVD chambers, thus presenting a viable method for mass production and offering a groundbreaking approach to fabricating SiC-based devices. |
Improved Particle Removal and Sub-Nanometer Roughness Control in 4H-SiC Wafers Using PVA Brush Conditioning PRESENTER: Yoon-Ji Ra ABSTRACT. Silicon carbide (SiC) has emerged as a key material in next-generation power electronics due to its wide bandgap, high breakdown electric field, and superior thermal conductivity, offering distinct advantages over conventional silicon (Si) substrates. Among its polytypes, 4H-SiC is particularly well-suited for high-voltage and high-frequency applications, including metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes (SBDs) [1]. However, chemical mechanical polishing (CMP), the final step in substrate planarization, often leaves behind particulate contamination and nanoscale surface irregularities that can interfere with epitaxial layer growth [2]. To address these challenges, this study investigates a polyvinyl alcohol (PVA) brush cleaning process aimed at enhancing both particle removal and surface morphology prior to epitaxy. In particular, the process effectiveness for post-CMP cleaning of 4H-SiC wafers is assessed, focusing on simultaneous particle removal and surface roughness improvement. 4H-SiC were first subjected to CMP using a precision polisher (PM5, Logitech, UK) to replicate the surface condition typically observed after CMP processes. These wafers were processed using a pencil-type scrubber (CSY, Korea) equipped with the nodule of PVA brush. The brush cleaning was conducted under systematically varied parameters including chemical solution, brush stiffness, gap distance, brush rotation speed, and cleaning duration. Particle removal efficiency was evaluated by measuring the change in particle count on the SiC wafer surfaces before and after cleaning using an optical microscope in dark field mode (LV-100D, Nikon, Japan), allowing for qualitative and quantitative assessment of residual particulate contamination. Additionally, scanning electron microscopy (S4700, Hitachi, Japan) was employed to investigate the contamination level on the PVA brush surface. In parallel, surface morphology was characterized using atomic force microscopy (NX20, Park Systems, Korea) to evaluate changes in roughness parameters and power spectral density. Among the tested chemical cleaning conditions, the cleaning solution was identified as the most influential process variable affecting particle removal efficiency. According to the zeta potential analysis (ELSZneo, Otsuka, Korea), it was confirmed that the interaction forces among the SiC surface, residual abrasive particles, and the PVA brush varied significantly with the different pHs of the solution. In particular, a solution at pH 11 exhibited the highest particle removal efficiency, attributable to enhanced electrostatic repulsion under strongly alkaline conditions. This repulsion promotes particle detachment and minimizes re-adsorption, resulting in improved surface cleanliness. These findings are summarized in Table 1 and indicate that the PVA brush cleaning process can be effectively optimized under high-pH conditions for post-CMP treatment of 4H-SiC substrates. As shown in Figure 1, brush scrubbing not only contributed to particle removal but also enhanced the uniformity of the surface morphology. This modification in surface roughness can be understood considering the crystallographic nature of 4H-SiC. Owing to the 4° off-axis orientation, the SiC surface inherently forms a nano-terrace structure, which terrace uniformity critically influences epitaxial growth quality [3]. By enabling controlled mechanical interaction with the surface, the PVA brush process selectively polished high asperities while preserving the step structure. This fine-tuning capability led to an average roughness (Ra) reduction of approximately 0.05 nm under optimized conditions. Consequently, the PVA brush process enhances the nano-terrace uniformity, providing a more ideal surface for subsequent epitaxial growth. This study confirms that the PVA brush process serves as an effective post-CMP cleaning method for 4H-SiC wafers, offering dual advantages in decontamination and fine surface conditioning. By leveraging electrostatic repulsion effects, the process minimizes the risk of particle recontamination, while its mechanical action enables precise tuning of surface morphology without the need for additional polishing or alternative surface conditioning steps. Consequently, this method provides a practical solution for achieving epitaxy-ready surface conditions, thereby enhancing the uniformity and reliability of subsequent SiC epitaxial growth processes. |
An In-Situ Study of Al Effects on Step Structures under Diffusion Controlled 4H-SiC Solution Growth PRESENTER: Ryunosuke Hashimoto ABSTRACT. Solution growth has attracted attention for producing high-quality SiC single crystals because the growth interface is close to thermal equilibrium. However, step bunching, which significantly degrades the crystal quality, occurs readily. Therefore, understanding and controlling the step behavior, as well as suppressing bunching, are key challenges. Previous studies have investigated the effects of convection [1] and solvent components [2, 3] on suppressing bunching. It has been demonstrated that the Al addition in Si-Cr solvent suppresses bunching on the post-growth crystal surface and leads the smooth surface [2]. Furthermore, in-situ observations have reported that continuous step-flow growth suppresses bunching when Al is added. However, it is desirable to isolate the effects of solvent components and elucidate the interface phenomena because convection may contribute to these evaluations. This study aims to establish a technique for in-situ observation of the solution growth interface under diffusion-controlled conditions to determine the effect of solvent components and elucidate the effects of Al addition on step structures. Solution growth was performed using the travelling solvent method (TSM). Solvent components were deposited on the C-face of an on-axis 4H-SiC substrate by electron beam evaporation, and two different types of samples, with and without Al addition, were prepared. One of the two samples was prepared with a concentration of 60 at% Si and 40 at% Cr, whereas the other contained an additional 2 at% Al. The seed and source substrates were cut into squares of 4 mm length, and the substrates were placed with the deposited surfaces in a face-to-face configuration. The samples were kept at 1548 °C in a temperature gradient using an infrared-gold-image-furnace controlled with an Ar atmosphere to obtain SiC growth by TSM. By maintaining the thin liquid film at less than 10 μm, convection was expected to be suppressed, allowing crystal growth to proceed under diffusion-controlled conditions. The crystal growth interface was observed through a technique developed using an optical microscope [4]. To clarify whether convection was inhibited, the step advancing velocities of a series of six uniformly elevated steps constituting a hexagonal island observed with Al addition were evaluated. The velocities of each step were approximately constant at 0.06 μm/s. In the presence of convection, the solute supply for each step varies, resulting in non-uniform advance velocities. Consequently, the convection was suppressed in this study. Thus, we established a technique that evaluates the crystal growth interface under diffusion-controlled conditions, which is suitable for elucidating the effects of solvent components. The step structures varied depending on the presence of Al. In the absence of Al, meandering steps were observed, as shown in Fig. 1(a). Conversely, with the addition of Al, the steps maintained a linear shape during the growth, as shown in Fig. 1(b). The step meandering was suppressed, and the stability of the steps was markedly improved by Al addition, both of which coincided with previous studies [2, 3]. In addition, the alteration in the step configuration implies that the step energy was changed by Al incorporation in SiC and Al addition in the solution. [1] Can Zhu, Shunta Harada, Kazuaki Seki, Huayu Zhang, Hiromasa Niinomi, Miho Tagawa, Toru Ujihara, Cryst. Growth Des. 13, 3691 (2013). [2] Takeshi Mitani, Naoyoshi Komatsu, Tetsuo Takahashi, Tomohisa Kato, Toru Ujihara, Yuji Matsumoto, Kazuhisa Kurashige, and Hajime Okumura, Mater. Sci. Forum 821-823, 9 (2015) [3] Sakiko Kawanishi, Tomohiro Yamada, Hironori Daikoku, Hiroyuki Shibata, and Takeshi Yoshikawa, ECS Trans. 114, 3 (2024). [4] Sakiko Kawanishi, Masao Kamiko, Takeshi Yoshikawa, Yoshitaka Mitsuda and Kazuki Morita, Cryst. Growth Des. 16, 4822 (2016). |
Effects of Post-Deposition Annealing on Temperature dependent Electrical Characteristics of SnO₂/4H-SiC Schottky Barrier Diodes PRESENTER: Chang-Jun Park ABSTRACT. Wide-bandgap (WBG) semiconductor materials, particularly silicon carbide (SiC), have attracted considerable attention as key candidates for next-generation power devices due to their wide bandgap, high critical electric field, excellent thermal conductivity, and superior electron mobility. Despite these outstanding material properties, SiC-based Schottky contacts often suffer from surface defects and inhomogeneities in Schottky barrier height (SBH), leading to degradation in device performance and reliability [1]. To address these challenges, the integration of oxide semiconductors has been actively investigated. Several n-type oxide semiconductors, such as ZnO and TiO2, have been investigated to improve the surface and electrical properties of 4H-SiC devices [2,3]. However, challenges such as limited carrier mobility and interface instability remain. Among these candidates, SnO2 has emerged as a promising material owing to its higher electron mobility and superior chemical stability. Previous studies have demonstrated that SnO2 contacts can effectively compensate for oxygen vacancy-related defects and improve the barrier height uniformity in Ga2O3 and diamond-based heterojunctions [4,5]. Building upon these insights, the integration of SnO2 with 4H-SiC is expected to suppress surface related defect states, enhance the uniformity of the Schottky barrier height, and improve the thermal and electrical stability of SiC-based devices. In this study, we investigated the electrical and morphological properties of SnO2/4H-SiC heterojunction diodes and the effect of PDA on their characteristics, as shown in Fig. 1 SnO2 films were deposited by radio-frequency (RF) sputtering, and characterized using atomic force microscopy (AFM) and x-ray photoelectron spectroscopy (XPS). Additionally, current density-voltage (J-V) and capacitance-voltage (C-V) characteristics, as well as temperature-dependent current density-voltage (J-V-T) measurements, were conducted to assess the electrical properties. Fig. 2 shows XPS result of a 2.75% reduction in oxygen vacancies, indicating a decrease in oxygen related defects in the SnO₂ films. Fig. 3 shows that AFM data confirmed PDA significantly enhanced the crystallinity of SnO₂films, reducing the RMS roughness from 40 nm to 32 nm, which improved surface smoothness and uniformity. Fig. 4(a) shows significant improvements in electrical characterization, with the specific on-resistance (Ron,sp) decreasing by 99.9%, from 146.7 Ω·cm² to 0.002 Ω·cm², and the on/off ratio improving by 1.25 × 103 times, from 1.85 × 10⁴ to 2.31 × 10⁷. Fig. 4(b) shows the 1/C²-V characteristics measured at 1 MHz, from which the net doping concentration of the SnO2layer was confirmed to be in the range of 5.48 × 1015 to 8.22 × 1015 cm⁻³. We also investigated the temperature-dependent electrical characteristics of the SnO2/4H-SiC heterojunction Schottky barrier diodes (SBDs) over a temperature range of 298-478 K. To address inhomogeneities in the Schottky barrier height (SBH) and its temperature dependence, we applied the thermionic emission model to calculate the ideality factor and SBH, both of which varied with temperature. The result in Fig. 5 shows that as the temperature increases, the ideality factor approaches unity, while the SBH exhibits an increasing trend. Fig. 6 shows the result of applying Gaussian distribution fitting to both the As-deposited and annealed samples to analyze the spatial distribution of the SBH at the contact interface. The O2-annealed sample exhibited a σs value of 0.21V, slightly lower than the value of 0.42V in the As-deposited sample, indicating improved SBH uniformity in the annealed SBDs. In conclusion, this study presents the electrical characteristics of SnO2/4H-SiC heterojunction diodes and the impact of post-annealing. These findings demonstrate that SnO2 integration can significantly enhance the performance and reliability of 4H-SiC Schottky diodes. Acknowledgement This work was supported by the Korea Evaluation Institute of Industrial Technology (KEIT) - Development of next-generation power semiconductor based on Si-on-SiC structure (RS-202200154720), and the Korea Institute for Advancement of Technology (KIAT) - Human Resource Development Program for Industrial Innovation(Global) (RS-2024-00421235) grant funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea), and also funded by Kwangwoon University in 2025. [1] Kimoto T, Watanabe H, Appl. Phys. Express 13, 120101 (2020). [2] Taube A, Sochacki M, Kwietniewski N, Werbowy A, Gierałtowska S, Wachnicki Ł, Godlewski M, Szmidt J, Appl. Phys. Lett. 110, 143509 (2017). [3] Alialy S, Altındal Ş, Tanrıkulu EE, Yıldız DE, J. Appl. Phys. 116, 083709 (2014). [4] Zhang S, Wang W, Wen F, Lin F, Wang R, Li Q, Chen G, Zhang Z, Wang HX, IEEE Electron Device Lett. 45, 1496 (2024). [5] Du L, Xin Q, Xu M, Liu Y, Mu W, Yan S, Wang X, Xin G, Jia Z, Tao XT, Song A, IEEE Electron Device Lett. 40, 451 (2019). |
Comprehensive Analysis of Carrier Lifetime and Deep-Level Traps in 4H-SiC: Impact of Epitaxial Growth Temperature and Rate PRESENTER: Firas Faisal ABSTRACT. Low-doped 4H-SiC drift layers are essential for achieving energy efficient unipolar and bipolar power devices. In commercially available devices, the drift layer is typically 8-20 µm thick with a background doping level in the range of 1×1016 cm-3. This provides an optimal balance between breakdown voltage and on-resistance for devices in the 1-2 kV class. For defect spectroscopy purposes, however, lower doping levels (~1×1015 cm-3) are often employed to ensure sufficient sensitivity in deep-level transient spectroscopy (DLTS) measurements [1,2]. Such deep level defects impact the minority carrier lifetime, which in turn, directly influences the forward voltage drop and switching behavior of (bipolar) power devices. Thus, we investigate the influence of epitaxial growth rate and temperature on deep level defects and on the carrier lifetime of 4H-SiC drift layers using DLTS and microwave-detected photoconductance decay (µPCD) techniques. A series of wafers was grown in a horizontal planetary CVD reactor. The growth rate was systematically varied by up to ±20% and the temperature adjusted within a 40 °C window, while keeping the buffer layer conditions constant across all samples. All epitaxial layers were deposited to a thickness of approximately 15 µm on commercially available 4H-SiC substrates with a 4° off-axis orientation toward [11¯2 0]. A fixed low n-type doping (~1×1015 cm-3) was used in all samples to ensure high sensitivity for subsequent defect spectroscopy. Carrier lifetime was evaluated using full wafer µPCD mapping with 349 nm laser excitation. The effective lifetimes across the sample set ranged from approximately 140 ns to 270 ns, depending on growth conditions, as depicted in Fig. 1. The highest lifetime (~270 ns) was observed for a sample grown at the highest tested growth rate (1.39 a.u.) and reference temperature. In contrast, wafers grown at elevated temperature (+40 °C) generally showed lower lifetimes across all growth rates, indicating increased incorporation of recombination-active defects under these conditions. [1] The µPCD data also revealed a clear trend with respect to growth rate: while the influence of growth rate alone was not monotonic, the combination of high growth rate and low temperature favored longer lifetimes, as summarized in Fig. 2. Across all wafers, the low doping (~1×1015 cm-3) ensured that µPCD measurements were performed in the low-injection regime, providing a good approximation of the bulk minority carrier lifetime. To further investigate the nature of the recombination-active defects, DLTS measurements are planned on selected samples. These will aim to correlate lifetime variations with the concentration of known deep-level traps such as the Z₁/₂ center, widely reported as the dominant recombination defect in 4H-SiC [3,4]. The interpretation of the observed trends will be extended using carrier recombination models that account for trap kinetics, including the negative-U behavior of Z₁/₂ [5]. This study demonstrates a clear and systematic dependence of carrier lifetime on epitaxial growth temperature and rate in 4H-SiC epi layers. By independently varying these parameters while maintaining all other growth conditions constant, we established consistent trends in the effective carrier lifetime across the wafer series. The results provide a foundation for further defect-level analysis and support the development of process guidelines for controlled tuning of carrier lifetime. |
Thick SiC-4H epitaxy perspectives PRESENTER: Silvio Preti ABSTRACT. Silicon Carbide epitaxy technology is growing up continuously through “hills” and “valleys”, reaching a maturity level to explore higher thickness epitaxy which can offers significant benefits for high-power and high-temperature applications: thick SiC epitaxial layers can withstand ultra-high blocking voltages, making them ideal for power devices that require high voltage operation (for instance, a 100µm thick epitaxial layer can support voltages above 10kV), while it helps in better thermal management by reducing the heat flux density (this leads to a lower junction temperature rise, which is crucial for maintaining device performance and reliability under high current conditions) [1]. Nowadays SiC devices are boosting by automotive market which doesn’t need thick epitaxy (6-12 m epitaxy is enough!), the rest of SiC devices are used for energy market (inverter, converter, storage system, et.), light industrial market (server SMPS, netcom SMPS, et.), heavy industrial market (traction, industrial automation, et.). In recent times the biggest EV world seller reveals is going to install in China more than 4000 fast chargers (2 kilometers in 1 second) using new SiC modules. This is just one example which confirms how day by day more applications are identified for SiC devices and in the future thicker epilayer will be needed to work at higher voltage with higher power density. Currently several research groups are working on 30 microns epitaxy to supply new SiC device which can work at 3kV [2] and surely in the next future higher thickness epitaxy can be useful for other higher voltage applications, such as ultra-high-power devices exceeding 30 kV which need a 200-300 m thick epilayer [1]. Obviously the SiC-4H thick epitaxy introduced new challenges related to the growth process, for example SiC-4H thick epitaxy grows on 4°off SiC-4H substrates, then it has bigger size epi defect which decrease the usable wafer area, as a result it is mandatory to decrease as much as possible the epitaxy defectivity: new process parameters must be set in comparison with standard thickness epitaxy growth recipe. Furthermore the SiC-4H thick epitaxy process, during the epitaxy growth, some defects (BPD, SF etc.) are introduced to relieve the stress inside the epiwafer between substrate and thick epitaxy: a Japanese research group (F. Fujie et al.) observed when the epitaxy thickness is above 50m, two kind of BPD half-loop have been generated due to substrate-epilayer misfit which increase tensile/compressive stress near triangular defect [3]. Another open question in SiC-4H thick epitaxy is the growth rate: thick epilayer need high growth rate process to decrease the process time, but it is not clear what the best solution is. Swedish university (LIU) (G. Misagh et al.) studied thick epitaxy growth using different carbon precursors. They showed promising result by using methane as carbon precursor, because it has a larger process window, even if the best epitaxy results have been reached at a “standard” growth rate of 25m/h [4]. In those years ASM® developed a low doping (<3E13cm-3) high growth rate epitaxy process to grow thick epilayer (100 m), by adjusting the growth parameters such as growth rate, temperature, and precursors gas fluxes. Of course, close to a good epitaxy process, a good substrate surface preparation and prior growth etching are mandatory to obtain a usable thick epilayer. Will show some of the most interesting results in our thick epitaxy activity focalizing on defectivity. Today we present an advanced epi process to obtain thicker epilayer (>100 m) with good thickness - doping uniformity and low defect density (see Fig.1) on 150mm SiC-4H epiwafer. |
The effect of the Si partial pressure depending on SiC powder stacking configurations on the heat treatment of 4H-SiC wafers PRESENTER: Gyeong Jun Song ABSTRACT. Silicon carbide (SiC) has emerged as a next-generation power semiconductor material due to its wide bandgap, high breakdown voltage, and excellent thermal stability. However, in the physical vapor transport (PVT) growth process, precise control of the thermal field is challenging, and a non-optimized thermal environment can induce residual stress in the grown crystal through lattice mismatch and polytype inclusions [1]. Furthermore, the SiC crystal experiences internal stress during the wafering process such as mechanical grinding and polishing. Residual stress in SiC crystal leads to the formation of basal plane dislocations (BPDs) and threading screw dislocations (TSDs), which result in increased leakage current and reduced breakdown voltage in devices [2]. The post-growth heat treatment of 4H-SiC wafers for relieving such internal stress has been limitedly studied. In the previous study, since heat treatment can increase the local partial pressure of silicon species (Psi), silicon desorption on SiC surface could be suppressed by employing a carbon cap. However, under these conditions, BPDs rarely convert to TEDs, which could limit the improvement of electrical performance. The open-surface heat treatment therefore has gained attention as a more effective approach [3]. Besides, heat treatment at high temperatures over 1300C without surface protection leads to the desorption of silicon species, causing surface graphitization and degradation of surface quality [4]. In this study, three different SiC source powder stacking configurations—including one without powder in the crucible—were proposed for the heat treatment of 6-inch 4H-SiC wafers with the Si-face oriented downward to compare their silicon desorption behavior at the surface and stress relaxation on the whole wafer. Each design employed a different powder stacking configurations and STR's Virtual Reactor 9.0 simulation tool was used to calculate the effect of Psi in the crucible during heat treatment. Fig. 1 shows the schematic diagram and distribution of Psi at the different powder stacking configurations near the SiC powder and wafer in the crucible. As shown in Table 1, the Psi at wafer center region for design a, b and c was approximately 24.1, 24.2 and 24.1 mTorr, in contrast, the Psi at wafer edge region was 24.3, 24.1, and 23.7 mTorr, respectively. This indicates that the lower Psi gives rise to prevention of desorption for Si atoms on the wafer surface by stacking the SiC powder in crucible. Here, we focused on results on Si-face of 4H-SiC wafer due to its quality of epi-ready surface. From the analysis XRD rocking curve analysis, the crystal quality at the center region (at the edge region) of Si-face after heat treatment was dramatically improved from 21 arcsec (32 arcsec) to 14 arcsec (14 arcsec) for design B. We compared the shift of FTO phonon band of 4H-SiC at ~777cm-1 (stress-free value) after heat treatment employing design A and B as shown in Fig. 2(a) and (b). The difference in FTO shift () before and after heat treatment of 4H-SiC wafer clearly shows that the residual tensile stress was relaxed in design B (=0.5 cm-1) compared with design A (=0.1 cm-1). It is well known that a shift rate of 3.1 cm⁻¹/GPa is used for stress calibration in hexagonal SiC crystals [5]. Fig. 2(c) shows the plot of FTO band shift as a function of five measurement points within the 4H-SiC wafer in design B. The residual stress (tensile stress) was relaxed to widespread region based on the stress-free value of 777 cm-1 (blue dashed line) after heat treatment. Design C revealed similar results to design B. Additionally, mechanical stress images within the wafer before and after heat treatment was obtained and analyzed using the PSI-3000 tool from Semilab (data not shown). |
Improvement of SiC crystal quality and residual stress by a seed adhesion process employing carbon-based adhesive and buffer-layer PRESENTER: Na Kyeoung Kim ABSTRACT. SiC (silicon carbide), with its wider band gap, superior thermal conductivity, and higher electrical resistivity relative to conventional silicon, exhibits stable device performance in high-temperature and high-voltage environments, along with improved thermal dissipation efficiency. Currently, SiC crystal growth is primarily carried out using the physical vapor transport (PVT) method, which offers several advantages over other techniques, including high growth rates and scalability to larger wafer diameters. However, the PVT growth method presents significant challenges in quality control, as numerous growth parameters can critically impact the resulting crystal quality.[1] The seed adhesion process is the most critical step in SiC crystal growth, and this process involves in attaching the SiC seed crystal to the graphite plate using an adhesive. Since inherent difference in coefficient of thermal expansion (CTE) between the seed crystal (2.3x10-6/K@RT for 4H-SiC) [2] and the graphite plate (4.8x10-6 /C@RT), this difference leads to various defects and residual stress at their interface after seed adhesion process at the initial growth stage. This mismatch becomes more pronounced when a larger seed crystal is used in the adhesion process, compared to relatively smaller seeds. Improper heat treatment of the adhesive at the interface between the seed crystal, adhesive, and graphite plate can lead to bubble or void formation. This issue can cause reverse crystal growth from the seed crystal toward the graphite plate. In the worst- case scenario, the seed may detach from the graphite plate during the initial stage of crystal growth. In this study, we propose a simple configuration for seed adhesion using carbon-based adhesive and buffer-layer. We employed the carbon-based buffer-layer (a graphite foil, the value of CTE has about 60x10-6/K through-plane at 20~1000 °C) to relax the stress between the seed crystal and the graphite plate. Since the significant difference in CTE of graphite foil between the in-plane and through-plane directions, it is required to minimize as much as possible through thermal treatment and pressurizing process. Fig.1 (a) and (b) denote the schematic diagram of seed adhesion configuration employing design A using polymer-based adhesive (adhesive #1) w/o any buffer-layer and design B using carbon- based adhesive (adhesive #2) inserting a carbon-based buffer-layer, respectively. SiC crystal growth was conducted at N atmosphere (20 sccm) of 5 torr in growth temperature ~ 2350 °C for 50 hours by the PVT method. 4° off n-type 4H-SiC crystal was used as a seed crystal. We evaluated their crystal quality and residual stress using cross-polarizing, SEM, XRD, and Raman scattering measurement. Fig.2 (a) and (b) display the optical images of grown SiC ingot and their cross-sectional SEM images using the design A and design B, respectively. Both grown SiC ingots with about 100mm of diameter shows a convex shape. Cross-sectional SEM image of the SiC ingot grown by design B has a well-defined boundary by types of materials, however, that of design A has no clear boundary. The five points of FTO phonon band were measured along the vertical direction on the 4H-SiC wafer and plotted to compare with stress-free value of 4H-SiC at ~777 cm-1 (dashed line) [3]. The average FWHM (full width at half maximum) of five FTO phonon bands at design A (design B) was approximately 5.3 cm-1 (5.6cm-1). Additionally, the center wavenumber of five FTO phonon bands in both crystals was around 777.0 cm-1 as shown in Fig.3. As the result, we confirmed that crystal quality and residual stress observed in both design A and design B were nearly identical. To improve the crystal quality and reduce residual stress in SiC crystals, we propose a new seed adhesion configuration in the near furture. This design will consist of multiple stacked layers with a repeating structure of carbon-based adhesive and buffer layers. |
Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals PRESENTER: Shota Tani ABSTRACT. The Physical Vapor Transport (PVT) method is widely used for bulk SiC single crystal growth. However, excessive temperature gradients in the source powder promote severe recrystallization, reducing both the growth rate and source utilization. In this study, numerical simulations using Virtual Reactor were performed to investigate optimal temperature distributions based on the equilibrium vapor pressure of SiC₂. In the first simulation (Model 1) using conventional RF coil heating, recrystallization occurred in both the lower and upper regions of the source due to insufficient heating and disturbances in gas transport. These phenomena were attributed to significant variations in the second derivative of the equilibrium vapor pressure (d²Psic2/dy²). In contrast, in the second simulation (Model 2), applying a virtual boundary temperature distribution to minimize the temperature gradient effectively suppressed recrystallization. These results confirm that controlling d²Psic2/dy² is essential for suppressing recrystallization and improving material utilization. |
SiC Single Wafer Chemical Mechanical Polishing Process Improvements for Throughput and Surface Finish PRESENTER: Ruijie Li ABSTRACT. Silicon carbide (SiC) power devices have been extensively employed in electric vehicles owning to SiC’s excellent electronic and thermal properties, such as wide bandgap, high thermal conductivity, and and high breakdown field strength. Chemical-mechanical polishing (CMP) is an indispensable process for producing high-quality SiC substrates. However, the material removal rate (MRR) of this process is relatively low due to SiC’s high hardness and chemical inertness. Additionally, the slow polishing required to produce to finest surface finishes further reduces throughput. Therefore, developing promising solutions to improve the throughput of SiC CMP and achieve the lowest surface roughness efficiently have emerged as urgent needs in the SiC substrates industry. We used the Applied Materials™ Mirra™ Durum™ single wafer CMP to explore these improvements. To improve throughput without affecting process quality, we investigated in-situ pad conditioning. Pad conditioning plays a critical role in maintaining MRR and cleaning the pad to reduce defectivity. Current practice is dominantly ex-situ, with polishing and conditioning as separate steps, because conventional disks cannot withstand the highly oxidative permanganate based slurries required for SiC. To overcome this, we present two practical and efficient approaches. First, we use a novel corrosion-resistant disk for in-situ pad conditioning during the main polish step, enabling simultaneous polishing and conditioning (Table 1). Second, we modify the ramp-up conditioning, incorporating pre-cleaning and pad conditioning prior to main polishing (Table 2). Results show these methods improve throughput of SiC CMP by 27.0% to 32.4% without degradation of MRR or defectivity (Fig. 1). There are some demanding SiC wafer specifications that require a smoother surface finish than can typically be achieved with bulk slurries. It is well-documented that a fine slurry can produce the desired finish, but the additional time required by this step has a significant impact throughput. To address this, we conducted a series of experiments aiming to reduce the wafer surface roughness using a final fine step minimizing the impact to throughput. These experiments involved adjusting the pH of the slurry and using a hard pad (Table 3), diluting the slurry on both a hard and soft pad (Table 4), and finally using a unique fine slurry on a soft pad (Table 5). We found that diluting the slurry resulted in a significant loss of removal rate, but not so much as using the unique fine slurry. When the dilutions are used on a fine pad, the surface finish was only marginally better than that produced by the fine slurry, which was the best result (Fig. 2). |
SIMS Profiling of 3D SiC Mesas: Top and Sidewall Analysis ABSTRACT. Secondary ion mass spectrometry (SIMS) is widely employed for high-sensitivity chemical profiling of planar semiconductor structures. However, standard approaches are insufficient for analyzing three-dimensional device architectures such as trench-based SiC MOSFETs. In this work, an extended SIMS protocol is presented for quantitative dopant profiling in non-planar SiC mesas, both vertically (top-down) and laterally (sidewall-to-sidewall). The top-down configuration is realized by orienting the mesa surface parallel to the direction of incoming ions under a high incident angle (typically 75° from normal). A high voltage applied to the sample holder electrostatically suppresses secondary ion emission from recessed trench regions, allowing selective sputtering and analysis of the mesa top only. During the measurement, the bias is dynamically adjusted to compensate for the gradual reduction in mesa height and to maintain lateral separation from the substrate. This setup enables accurate extraction of dopant profiles along the vertical axis of the mesa without background contribution from deeper layers. The method permits position-resolved detection using spatially sensitive detectors, enabling selective reconstruction of p-type and n-type regions within the same structure. For lateral analysis, the sample is rotated by 90°, aligning the mesa sidewall with the ion beam direction. By partially removing adjacent material to prevent shadowing effects, a lateral depth profile can be recorded from one side of the mesa to the other. The combined top-down and lateral SIMS analysis reveals complex dopant redistribution effects not accessible by conventional techniques. In thermally annealed samples, significant lateral broadening of implanted species was observed, exceeding the corresponding vertical diffusion. This capability opens new pathways for characterizing dopant stability, oxidation behavior, and spatial confinement in 3D SiC devices. The method is adaptable to a wide range of non-planar structures, including full device stacks with metal contacts or encapsulation layers. Acknowledgements: This work was supported by the National Centre for Research and Development, project No. LIDER/8/0055/L-12/20/NCBR/2021. |
Improvement of gate-source short failure by suppressing abnormal polySi layer in 1200V SiC MOSFETs PRESENTER: Haeri Kwon ABSTRACT. Silicon carbide (SiC)-based power devices are well-suited for high-temperature operation due to their intrinsic material properties, including high breakdown voltage, low on-resistance, fast switching speed, and superior thermal conductivity. These attributes facilitate efficient heat dissipation without the need for auxiliary cooling systems, thereby supporting device miniaturization and system integration [1]. Despite these advantages, SiC substrates possess a crystalline structure characterized by alternating silicon and carbon atoms on a single surface, which renders them vulnerable to stress accumulation arising from lattice mismatch and differences in thermal expansion coefficients [2]. As a result, fabrication processes involving mechanical or thermal stress, such as plasma-enhanced chemical vapor deposition (PECVD) and ion implantation, can induce wafer warpage. This deformation often leads to misalignment during subsequent photolithography steps, adversely affecting device performance and yield. To address warpage, several stress-relief techniques are commonly employed, including lapping, annealing, and backside grinding [3]. While lapping and backside grinding physically reduce wafer thickness, they may introduce additional complexity in downstream processing. In contrast, annealing offers a straightforward solution, as it can be performed in conventional high-temperature furnaces to relieve internal stress and improve wafer flatness. During annealing, the thermal dissociation of Si–H and C–H bonds within the substrate facilitates stress relaxation and mitigates warpage [4–5]. Typically, annealing at temperatures above 800°C is conducted following stress-inducing steps to recover lattice damage. However, such high thermal budgets can inadvertently alter film properties and promote dopant diffusion. In our previous study, for instance, PECVD-deposited SiO₂ films subjected to annealing at 950°C for 4 hours exhibited abnormal polycrystalline silicon (poly-Si) formation on the oxide surface. Subsequent device analysis revealed that this phenomenon caused gate–source short failures (Fig. 1). To overcome these limitations, we propose a modified annealing strategy that applies thermal treatment directly to the bare SiC substrate prior to film deposition. This approach enhances substrate densification and effectively suppresses warpage without inducing undesirable side effects. Accordingly, the proposed process not only effectively suppressed the intrinsic warpage of the SiC substrate but also prevented the occurrence of defective dies associated with abnormal poly-Si formation, thereby achieving an improvement in yield. [1] T. Anzai, Warpage evaluation of high-temperature sandwich-structured power module for SiC power semiconductor devices, Journal of microelectronics and electronic package, vol.12, no.3, pp. 153-160, (2015). [2] T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology. Hoboken, NJ, USA: IEEE Wiley, pp. 12-13,112, (2014) [3] I.Y. Jung, Evolution of mechanically formed bow due to surface waviness and residual stress difference on sapphire (0001) structure, J. Mater. Process. Technol., vol. 269, p.104, (2019). [4] Ellison, Wafer warpage, crystal bending and interface properties of 4H-SiC epi-wafers, Diamond and Related Materials, pp. 1369–1373, (1997) [5] Y.T. Kim, Annealing effect on the optical properties of a-SiC:H films deposited by PECVD, Materials transactions, vol.43, no.8, pp. 2058-2062, (2002) |
Non-Destructive Optical Detection of Dislocation Defects in N-type SiC Substrate Wafers PRESENTER: Yuzhong Chen ABSTRACT. In the past decades, the detection of Dislocation Defect (DD) in SiC wafers relies on a traditional KOH etching method, which is destructive and thus cause a huge economic loss in the manufacture. Moreover, the KOH etching method tends to underestimate the presence of TSDs, which could affect the yield and reliability of SiC devices. In contrast, X-ray diffraction topography (XRT) serves as a reliable and non-destructive method for DD inspections, provides high accuracy in the detection of TSDs (in the (0008) reflection mode). However, XRT still faces challenges in accurately detecting TEDs. Therefore, developing an alternative non-destructive method for fast DD inspection—capable of accurately detecting TSDs, TEDs, and BPDs simultaneously—has been a long-standing and urgent need in industrial SiC wafer manufacturing. Herein, we report a purely optical technique for the non-destructive detections (mappings) of TED, TSD and BPD defects in N-type SiC substrate wafers. The development of this innovative technique is based on a laser-pump and laser-probe transient imaging method, where the pump laser is to generate photoinduced carriers (minority carriers) by exciting the SiC wafer and the probe laser is to image the density of photoinduced carriers by collecting their photoinduced absorption signal. It is well-known that DDs are killers of the photoinduced carriers in SiC crystals by causing a fast carrier recombination. Therefore, a DD site in a SiC wafer exhibits a lower photoinduced carrier density compared to DD-free area, thus being identified in photoinduced carrier density image. Figure 1 shows an example of carrier density image of a N-type SiC substrate wafer, where the BPDs are identified as dark (lower density) lines and TEDs (TSDs) as dark spots. The TED and TSD are separated based on their shapes and signal contracts. Fig. 1. A typical non-destructive optical image of a N-type SiC substrate wafers. The BPD, TED and TSD sites are identified by exhibiting a lower signal intensity (lower carrier density). For TSD detection, the optical non-destructive method shows strong agreement with XRT results; for TED and BPD detection, it aligns well with those obtained by KOH etching. Figure 2 presents a representative benchmarking result from a 6-inch SiC wafer: the first row shows the TSD detection by XRT and the TED/BPD detection by KOH etching, while the second row displays the corresponding results from the optical non-destructive method. As seen from the comparison, the optical method is capable of accurately detecting TSDs, TEDs, and BPDs simultaneously. Fig. 2. Comparison of TSD (detected by XRT) and TED/BPD (detected by KOH etching) with the results from the optical non-destructive method on the same 6-inch SiC wafer. Further, to comprehensively evaluate the reliability and accuracy of the optical non-destructive technique in detecting dislocation defects in SiC wafers, a large-scale investigation was conducted across a number of wafers. Statistical analysis indicates that the detection results of TSDs obtained using the optical non-destructive method exhibit a strong linear correlation with those acquired via X-ray topography (XRT), with a slope approximately equal to 1 and a coefficient of determination R2=0.97. Likewise, for s TEDs, the optical method shows excellent agreement with the conventional etching technique, yielding a linear slope close to 1 and R2=0.99. These results further validate the accuracy and consistency of the optical non-destructive method in quantifying dislocation-related defects. Fig.3. (a) presents a comparison between the TSD counts obtained by the optical non-destructive technique and those measured by XRT, where each data point represents a substrate wafer. (b) illustrates the corresponding comparison for TEDs, between the optical method and the etching method, where each data point represents a substrate wafer. Notably, this optical non-destructive dislocation defect (DD) detection method typically completes a full inspection of a 6-inch wafer within 15 minutes. This makes it possible to apply non-destructive inspection in SiC substrate production. We believe this optical technique holds great potential to significantly reduce the cost of DD inspection in industrial SiC manufacturing by replacing the conventional KOH etching method |
Advanced defects study and monitoring in new generation 4H-SiC devices PRESENTER: Nicolo Piluso ABSTRACT. The global semiconductor market is expected to grow significantly. Considering the expansion to 8in wafer size and with the strong dedicated investment, the silicon carbide (SiC) power device market will reach $9B by 2028 [1]. This growth is driven by the rising demand for efficient power electronics in electric vehicles (EVs), renewable energy systems (smart grids), IT infrastructures (AI, data centers), and other applications, thanks to the significant benefits over traditional silicon-based semiconductors. To achieve market leadership, semiconductor companies must quickly transition to high-volume manufacturing (HVM) with Zero Defect standards [2], preventing productivity bottlenecks during fab ramp-up. Sensitive inspection, effective review, and reliable AI-based defect classification during R&D and maturity phases are critical solutions for early detection of process flaws and killer defects, determining yield and accelerating the time to result (T2R). In this work, we will demonstrate the benefits of enhancing process control during device development to detect critical defects in non-standard SiC material where new substrate technology and multiple epitaxial steps are considered. The main purpose is to strengthen the automated inspection procedure, identify features potentially critical and follow their evolution during the growth processes. Novel defectivity will also be characterized and presented. Coupling high-quality mono-SiC on robust polySiC substrates is a promising approach to enhance the performance of power electronic devices [3,4,5,6]. Optical microscopy is the most widely used method for detecting defects in this technology. Defects are classified based on size, shape, and intensity, which are crucial for determining the killer ratio during electrical evaluation. Typical polycrystal macroscopic defects (Figure 1a, b), easily detectable due to their size and contrast, are considered killers for devices. More challenging defects smaller than 25 µm (Figure 1c), especially those less than 1 µm (Figure 1d), require advanced characterization techniques such as inline defect detection and AI-based classification (Figure 1e). In figure 2 enhanced detection of sub-1µm defects in SiC material is shown by using 20x high-sensitivity objective. Multiepitaxial growth is a strategy used to improve device performance, particularly in minimizing on-resistance (Ron) [7,8,9] thanks to superjunction-like drift layers. While this approach is common in silicon devices, SiC devices have challenges due to low diffusion coefficients of dopants (e.g. phosphorus and aluminum), and the evolution of crystal defects during the multi-epitaxial process [10,11,12]. Figure 3 shows the evolution of defects from epitaxial layer to thin epitaxial regrowth. To define the killer ratio (KR) of structured defects it is necessary to detect and monitor defects after regrowth. Studies on prismatic defects and complex stacking faults (Figure 3 A,C) reveal understandings how defects propagate and the potential device performance degradation. Additional partial dislocations after regrowth (Figure 3 B,D) must be detected, classified, and monitored to assess their impact on final electrical performance and process flow. Despite the limited size increment after regrowth process, micropipes (Figure 3 E,F) are known to have KR close to 100% and their evolution is fundamental to identify crystallography changes and to quantify the portion of the surface impacted due to the enlargement thereof. |
Investigation of Mechanical Stress and Warpage in 200mm Silicon Carbide Wafers: Implications for Production Scalability PRESENTER: Lin Dong ABSTRACT. Bosch is continuously expanding its semiconductor business in silicon carbide (SiC) chips by significantly increasing manufacturing facilities and transitioning from 150mm to 200mm wafers in production lines. This growth is accompanied by the establishment of a diversified supplier portfolio, following a multi-sourcing and multi-location strategy. From a technical perspective, in addition to a deep understanding of substrate quality and supplier maturity, front-loaded requirements engineering is essential for ensuring the scalability of production. In recent years, Bosch has focused on improving crystal defect characteristics; however, the mechanical behavior of substrates during device manufacturing is now gaining increased attention. The overall shape of a substrate is typically defined by its bow and warp. As the wafer diameter increases from 150mm to 200mm, the influence of gravity on bow and warp values becomes more pronounced. According to SEMI standards for silicon wafers, which typically include diameters of 200mm and 300mm, the effects of gravity on bow and warp values can be estimated through experimental or mathematical methods. However, for SiC wafers, particularly with the industry's initial adoption of 200mm wafers, these topics have not been extensively explored. The warpage of a substrate results from the overall mechanical stress state within the material. Photoelastic measurements can be employed to assess the stress levels in crystalline materials such as SiC and silicon wafers. This paper focuses on Bosch's in-depth investigation of residual mechanical stress in SiC substrates and its impact on wafer warpage. Figure 1 illustrates the comparison of bow and warp results for identical 200mm SiC wafers using different sample holders in wafer metrology tools. The results indicate that bow and warp values for the same wafers can vary significantly depending on the wafer support methods. This variation primarily arises from the deformation of the wafer, which is notably influenced by the gravitational forces acting on it. Photoelastic experiments were conducted using Raphael Optech SV200 on the same group of wafers depicted in Figure 1 to gain insights into the wafer stress levels. Figure 2 presents two typical stress patterns observed in the SiC wafers under investigation. In Figure 2a, a typical ring-like symmetric stress pattern is evident, characterized by low stress levels at the wafer center and a sharp increase towards the edges. Conversely, the wafer in Figure 2b exhibits an asymmetric stress pattern, with one side experiencing significantly higher stress levels than the other. To correlate wafer stress with warpage, Bosch references the “z_gravity” concept described in SEMI standard MF1390-0218 for silicon wafers, introducing the term "sag value" in this paper. The sag value is defined as the average of bow values measured with the wafer oriented with the Si face up and the C face up, respectively. The wafer bow measurements were taken using the FRT metrology tool with a 3-point holder, which effectively highlights the impact of gravitational forces on wafer shape. The correlation between the average wafer stress and the sag value is illustrated in Figure 3, with blue dots representing wafers exhibiting a symmetric ring-like stress pattern and orange dots indicating wafers with an asymmetric stress pattern. A linear relationship between stress values and sag values is evident, characterized by different slopes based on the analysis of the stress patterns discussed in Figure 2. This correlation indicates that: 1) as the wafer stress level increases, the sag value (and consequently, the wafer warpage) also significantly increases; and 2) the relationship between sag and stress values varies depending on the stress distribution across the wafer. The theoretical model underlying these correlations is currently under investigation and will be reported in future work. |
Multi-channel defect inspection for 4H-SiC epitaxial wafer and integrated defect classification PRESENTER: Masaki Hasegawa ABSTRACT. To control the quality of SiC epitaxial wafer, accurate defect inspection is indispensable. This paper reports that performance of the defect classification was found to be remarkably improved by integrating classification results of different inspection methods (the optical inspection, the photoluminescence, and the X-ray topography) based on a predetermined decision table. The result shows that the integration of inspection results based on different physical principles can compensate for the low detection sensitivities depending on inspection methods. Here, to detect and classify defects more accurately for each inspection method, we used a convolutional neural network (Faster-RCNN) trained by defect images of each method. |
Non-contact Micro-scale Imaging Analysis of Electrically Active Defects Causing EOL Failures in Merged PiN Schottky Diodes PRESENTER: Marshall Wilson ABSTRACT. As the SiC epitaxy industry continues its rapid expansion, there is an increasing demand for more advanced defect detection and yield optimization methods. Inline techniques such as optical inspection and ultraviolet photoluminescence (UVPL) mapping are widely used, but they lack the ability to directly determine the electrical activity of detected defects. To overcome this limitation, Semilab SDI introduced the QUAD (Quality, Uniformity, and Defect) mode within their corona noncontact Capacitance-Voltage (CnCV) tools. QUAD enables mapping of depletion voltage on epi layers after being uniformly charged by corona, allowing electrically active defects to be clearly identified. This method serves as a powerful complement to UVPL and optical mapping, which, while capable of identifying defect types, cannot distinguish which are electrically detrimental to device performance [1]. By combining the classification abilities of UVPL with the detection of electrically active defects by QUAD, more accurate predictions of device yield early in the manufacturing process become possible. QUAD has recently been applied with success in the SiC industry to investigate a Merged PiN Schottky (MPS) diode fabrication process [2] and a SiC MOSFET process [3]. In this work we have further extended the application of the QUAD technique to investigate the detailed electrical activity and nature of device killer defectivity on the micro scale (μQUAD) within individual MPS diodes. Surface potential measurements were performed using a 10 μm diameter Kelvin Force Microscopy (KFM) probe, as shown in Fig. 1. μQUAD mapping was applied to both as-grown SiC epitaxial wafers and fully processed metallized MPS device wafers. In the latter case shown in Fig. 2, the metallized surface is equipotential within each individually isolated MPS diode and defects are manifested as a reduced surface voltage across the entire bad die. Removal of the Schottky metal enabled direct observation of localized depletion voltage variations caused by defects such as polytype inclusions and stacking faults. Combining μQUAD results with UVPL allowed spatial correlation and defect classification, providing a powerful tool for failure analysis and process improvement in SiC device fabrication. To demonstrate the capabilities of the μQUAD technique, two case studies of MPS diode failures are presented: one from a process-induced defect and another from an initial epi growth defect. Fig. 3a shows a QUAD failed die bin map (blue squares) including process-induced failures (red squares) and final electrical test failures (open triangles) [2]. A cluster of process-induced failed dies was further examined using μQUAD (Fig. 3b). After corona charging, good dies maintained a depletion voltage of –20 to –30V, while the defective cluster of dies held no voltage. Upon discharging the corona charge using UV illumination and mapping the surface voltage, it is apparent that the isolation between this cluster of failed dies is not present when compared to the rest of area with good dies as seen in Fig. 3c. μQUAD analysis indicates a likely cause of this process-induced failure, ultimately traced back to vibration from a pin lift system. This demonstrates the value of μQUAD as a diagnostic tool for identifying issues in front-end processing. The second example of a device killer defect is downfall triangular defect present from the initial epi growth. Fig. 4 illustrates UVPL, differential interference contrast (DIC), μQUAD and Raman images of the downfall precipitated triangle defect on the final device after stripping the metallization. μQUAD be an important complement to UVPL by adding information about the specific electrical activity of the defect. The work function map of the triangular defect reveals the localized electrical activity of the defect indicating the regions of exposed 3C-SiC. A Raman spectroscopy map of the 796 cm-1 line identifies and confirms the regions of 3C-SiC. The integration of μQUAD mapping with conventional optical and spectroscopic techniques enables a new methodology for identifying and spatially resolving electrically active defectivity at the die level. This approach not only enhances failure analysis capabilities but also provides a predictive framework for improving yield and reliability in advanced SiC device manufacturing. [1] A. Savtchouk, et al., Defect and Diffusion Forum 434 (2024): 129-134. [2] F. Faisal, et al., Scientific Books of Abstracts 8 (2024): 265-266. [3] J. Thörnberg, et al., Defect and Diffusion Forum 434 (2024): 111-115. |
Formation and reduction of surface pits on 4H-SiC epitaxial layer PRESENTER: Weining Qian ABSTRACT. Surface pits of 4H-SiC epitaxial layer are generally regarded as non-killer defect of SiC devices. However, according to some reports[1,2], there may be different influence on SiC devices. When there are pits, the device characteristics may be deteriorated due to the electric field crowding. Therefore studying the formation mechanism of surface pits and suppressing their formation are of great significance. In this work, the origin of surface pits was studied. Molten KOH treatments were carried out on epitaxial layer with surface pits. The surface morphology of the substrate, the epitaxial wafer and the epitaxial wafer after KOH treatment at the same location are shown in Fig.1. The results demonstrate that the surface pits originate from the threading dislocations, especially the threading screw dislocations (TSD). In the epitaxial growth, threading dislocations terminated at the substrate hinder the step propagation resulting in the formation of the surface pits. In addition, the influences of growth temperature, C/Si ratio and epitaxial layer thickness on the surface pits were investigated by SICA88. According to the research findings, as the temperature decreases, the density of the surface pits reduces. Similarly, the density of the surface pits reduces with a decrease in the C/Si ratio. Therefore, under the low temperature or rich Si conditions, the density of pits identified by SICA88 can be effectively reduced. As shown in Fig.2 (a) and Fig.2 (b), with the epitaxial layer thickness increasing, the density of pits increases and the size of pits enlarges. Due to the limitation of the detection precision of SICA88, only the pits that exceed a certain size can be identified by SICA88. Based on the above analysis, it can be inferred that temperature and C/Si ratio have an impact on the size of the pits. Finally, Based on the origin of surface pits and the effect of the growth parameters on surface pits, we propose a model of the formation mechanism of surface pits, given in a schematic illustration in Fig.2 (c). The competitive interaction between step-flow growth and spiral growth affects the size of surface pits, which subsequently results in the variation of pits density detected by SICA88. Under the low temperature or rich Si conditions, the step-flow growth becomes the dominant mode[3,4], the spiral growth originating from TSD is effectively suppressed. This reduces the size of surface pits, especially reducing the dimensions of pits in the perpendicular direction of the step-flow movement. |
Optical localization of passivation discoloration using admittance spectroscopy PRESENTER: Marvin Gloth ABSTRACT. Wide-bandgap semiconductors like silicon carbide (SiC) are essential for power electronics in energy transition and electromobility applications [1]. While SiC offers significant advantages over silicon power devices such as higher thermal conductivity, electric fields strength and consequently higher breakdown voltages [2], its device reliability must be thoroughly evaluated due to the higher density of defect states inherent in the material. The wide band gap of SiC leads to a greater number of accessible energy levels at the semiconductor/oxide and passivation interfaces which act as charge traps and can impact the device behavior [3]. Defects in the termination region are particularly critical, as they can be influenced by charge trapping effects or act as recombination centers under high-voltage stress, such asHVH3TRB, HVHAST or short-circuit tests. These defects may lead to degradation or even device failure [4]. One manifestation of such degradation is low ohmic behavior or total loss of the blocking capability. Visually, this degradation manifests as edge discoloration (Fig. 1), which traditionally requires destructive mechanical preparation. This study demonstrates that admittance spectroscopy offers a non-destructive alternative for detecting termination defects in SiC power devices. A characteristic electrical signature – seen as an inflection point in the susceptance spectrum (B) and a minimum in the conductance spectrum (G) at ~800 Hz depicted in Fig. 2, correlates strongly with defect-induced discoloration. Modeling confirms this behavior originates from recombination centers with dominant thermal hole emission rate (Fig. 3), challenging earlier explanations involving positive charge accumulation [5,6]. Further investigations reveal that these defects are linked to oxygen vacancies in oxidized SiC [7-12], which under high-voltage stress can cause interface delamination. According to the measurement method, the underlying model is a sinusoidal excitation of the occupancy level of the defect states in an n-type semiconductor. The characteristic frequency and the ratio of capture cross section to emission rate are responsible for the fundamental shape of the admittance spectra. Additionally, the ratio between doping and defect concentration plays a crucial role in shaping the spectral characteristics. Unlike the measurement results (Fig. 2), which represent a superposition of all defect states, including those associated with doping, the modelling isolates the response of a single recombination center, characterized by a distinct frequency at approximately f = 800 Hz. The magnitude of capacitance change (ΔC) is directly proportional to defect concentration (NT) and thus to discoloration severity (Fig. 4). Both lock-in thermography and photo emission spectroscopy confirm that breakdown occurs at the termination edge as seen inf Fig. 5, rather than in the active area, with the resulting leakage path exhibiting inductive behavior shown by the negative imaginary part of the susceptance spectrum. These findings demonstrate that admittance spectroscopy as an effective, non-destructive technique for early detection of termination-related defects. It enables more targeted physical failure analysis and enhances the reliability assessment of SiC power devices in high-voltage applications. |
Characterization of 3C-SiC thick epitaxial layers grown on off- and on-axis 4H-SiC substrate PRESENTER: Jun Fujita ABSTRACT. Cubic silicon carbide (3C-SiC) is a promising photoelectrode material for photoelectrochemical water splitting due to its favorable band alignment and chemical stability. To enhance its performance, we investigated the mechanism by which substrate off-axis angles affect crystalline quality, using 3C-SiC thick layers grown on on-axis and off-axis 4H-SiC substrates. |
Thin transition zone measurement in silicon carbide epi structures by Fourier transform infrared reflectometry and point contact current-voltage technique PRESENTER: Eszter Eva Najbauer ABSTRACT. Silicon carbide epitaxy is a critical step in semiconductor fabrication, where a buffer and one or more drift layers are deposited onto a SiC substrate. Tight control of the epitaxial process is essential for ensuring uniformity across the end products, as epitaxial layer thickness has a direct impact on electrical properties such as breakdown voltage and carrier mobility. Fourier transform infrared spectroscopy (FTIR) is commonly used for determining layer thickness in Si epi samples, as well as in two-and three-layer SiC stacks non-destructively. While several studies exist where Si layer thickness as determined by FTIR spectroscopy is validated by destructive methods [1-2], such as secondary ion mass spectrometry (SIMS) and spreading resistance profiling (SRP), barely any such results have been published for SiC samples. Here, we compare thickness results obtained on SiC wafers by FTIR [3] and point contact current-voltage technique (PCIV) [4-5]. PCIV is an advanced adaptation of SRP, specifically optimized for characterizing electrically active dopants in wide-bandgap materials. We show that FTIR is capable of measuring epitaxial and buffer thickness accurately, showing excellent correlation with PCIV results (Figure 1). Moreover, we observe and determine the thickness of the few hundred nm thick transition zone (TZ) both by PCIV and EIR between the buffer and epi layer, stemming from ramping the gas flows during the growth process. A similar transition region is well-known to exist in Si epi samples (although having a different mechanism of formation) [2], however for SiC samples, it is seldom described in literature. Since the TZ’s thickness is comparable to the buffer layer, it is essential in accurately describing SiC epitaxial structure. We also evaluate the use of different profiles for accurately determining the transition zone’s thickness. Depending on the reactor type and the treatment of the wafers, some samples may have a thin region of increased resistivity between the substrate and the buffer layers, as detected by PCIV, which also manifests itself in FTIR spectra as a pronounced beat pattern in the SiC reflectance spectrum’s thickness oscillations. We show that optical modelling is able to accurately determine TZ and buffer layer thicknesses also in these types of samples, matching PCIV results (Figure 2). [1] Y. Kostoulas, G. Kneissl, I. Kohl, Solid State Technol., 43, 289 (2000). [2] E.E. Najbauer, L. Sinkó, S. Biró, Z. Durkó, P. Basa, Applied Research, 3:e202300146 (2024). [3] E.E. Najbauer, Compound Semiconductor, 30, (4), 22-25 (2024). [4] R.J. Hillard, H.L. Berkowitz, J.M. Heddleson, R.G. Mazur, P. Rai-Choudhury, Euro III-V Review, 3, (5), 31-33, (1990). [5] Y. Fukuda, K. Nishikawa, M. Shimizu, H. Iwakuro, Materials Science Fourm, 389-393, 671-674 (2002). |
Insight into the Features and Characteristics of Stacking Faults on 129 4H-SiC Epitaxial Wafers Investigated Using Wafer-Scale Photoluminescence Mapping and Spectra Analysis Combined with HAADF HR-STEM PRESENTER: Hyundon Jung ABSTRACT. In 4H-SiC epitaxial wafers there are several different kinds of structural defects. These are threading dislocations (TDs) like threading screw dislocation (TSD) and threading edge dislocation (TED), basal plane dislocation (BPD), micropipe (MP), carrot defect, and stacking fault (SF) [1]. Among these defects MP and carrot defect are typical killer defects. Simple SFs are not regarded to the killer defect but are negligible because SFs results in significant reduction of breakdown voltages by 20-50% [1]. Recently, SFs have been regarded one of major defects can’t be negligible as thicker epitaxial wafer over 100 um is required for high-voltage power device applications. On the other hand, the so-called complex SFs which surface morphological line (SML) features [2] can result very severe degradation of SiC power devices because the SF complex is colossal defect. In fact, at the bottom of the SML, there is a prismatic stacking fault (PSF) and can be a killer defect [3,4]. Various kinds of SFs have been reported in 4H-SiC epitaxial wafers, and identification of SFs and structure determination have been investigated by using characteristic photoluminescence (PL) emissions from SFs and high-angle annular dark-field high-resolution scanning transmission electron microscope (HAADF HR-STEM) [5-7]. In the international standard document, seven representative SFs, which are four kinds of Shockley-type SF (SSF) and three kinds of Frank-type SF (FFS) with corresponding characteristic PL wavelengths (C-PLWs) are described although some of C-PLWs are arguable. The four representative SSFs are single (3,1), double (6,2), triple (5,3), quadruple (4,4) SFs and the three FSFs are (5,2), (4,2) and (4,1) SFs. In this study, we investigated commercial 129 4H-SiC epitaxial wafers (8-inch: 55 ea, 6-inch: 67 ea, and 4-inch: 7 ea) by using wafer-scale PL mapping with PL spectra analysis. Detailed methods can be found in our recent publications [5,6]. In order to confirm and determine the SF types and structures we have performed HAADF HR-STEM observations from the 142 FIB TEM specimens. Based on these accumulated results in recent 3 years, we address insight into the SFs in 4H-SiC epitaxial wafers. Fig. 1 shows plots of the C-PLWs from all SFs in 4-inch and 6-inch epitaxial wafers from 4 vendors. This plot is named to a “band plot” because the SFs with the same C-PLWs make a band. Regardless of the vendors, 4~6 apparent bands of wavelengths with deviations of <0.5 nm from each band are observed. Six bands of the C-PLWs were observed at 424, 428, 457, 462, 483, and 503 nm with narrow distributions, as indicated in Fig. 1. This plot implies representative C-PLWs for the typical SFs existing in SiC epitaxial wafers, and can give us information on major and minor SFs as current status of epitaxial technology. In addition, we could know the SFs with scattered C-PLWs data point away from the major bands meant variations of SFs from the typical 7 kinds of representative SFs. Fig. 2 is a histogram constructed based on the accumulated data, which was drawn by counting the SFs per wavelength with a step of 0.8 nm for 70149 SFs from the investigated 129 epitaxial wafers. Fig. 2 clearly gave us important information on two major SFs; the (6,2) SSF of 18349 ea (26.2%) and the (5,2) FSF of 14390 ea (20.5%). Therefore, we can get an insight into the current status of epitaxial wafers that the most of SFs are (6,2) and (5,2) SFs and these SFs were easily formed in 4H-SiC epitaxial wafers. It is a very surprising value for the 20.5% of the (5,2) FSF among the 7 representative SFs. Additionally, we could know that SSF (5,3) and FSF (4,1) are really rare, which implied that these types of SFs are difficult to be formed or easy to be transformed to other types after formation. The ratio of “SSFs (4,4) and (6,2)”/FSFs (4,2) and (5,2)” is almost 1. Fig.3 is a histogram to show the percentage of FSFs with the SML feature among the FSFs. The SFs with the SML feature corresponding to the basal SF (BSF) at the carrot defects and the complex SFs, i.e., the FSF with PSF. In Fig. 3, the (3,X) SF corresponds to both SSF and FSF like the (3,1) SSF, the (3,2) FSF and variations of these SFs. In this case, large portion of SFs (64.2%) are FSF with the SML feature and remaining (35.8%) are normal FSF without the SML feature or SSF. In case of the (5,2) FSF, 19.7% of SFs are the SFs with the SML feature and 80.3% is normal SFs. The percentage of the SFs with the SML feature significantly increased to 58.9% in the case of the (4,2) FSF, which meant that more than the half of the (4,2) FSF is harmful FSF with the SML feature. This gives us a very important insight that a significant portion of the FSFs has the SML feature, i.e., PSFs, and therefore can be act as the killer defect. If we apply the percentage of SFs with the SML feature to the total SFs of (3,X), (4,2), and (5,2) SFs, we can expect that about 20% among the total SSF and FSF has the SML feature, therefore can be the killer defect. Followings are key summary of investigations and insight deuced in this study; 1) Most of SFs in current 4H-SiC epitaxial wafers are (6,2) SSF and (5,2) FSF. 2) The ratio of “SSFs (4,4) and (6,2)”/FSFs (4,2) and (5,2)” is almost 1. 3) The (5,3) SSF and the (4,1) FSF are very rare and difficult to be formed or easy to be transformed to other types after formation. 4) About the 20% of the total SFs (SSFs and FSFs) have surface morphological line feature, which will be the killer defect. 5) More than the half of the (4,2) FSF has the surface morphological line feature. This work was supported by the Technology Development Program (No. 22A02098) funded by the Ministry of SMEs and Startups (MSS, Korea) by the Technology Innovation Program (No. 25A02037, 25A02099) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) and by the Korea Electrotechnology Research Institute Primary Research Program (No. 25A01009, 25A01006) through the National Research Council of Science and Technology funded by the Ministry of Science and ICT (Korea). [1] T. Kimoto, Jpn. J. Appl. Phys. 54, 040103 (2015). [2] International Electrotechnical Commission (IEC), Semiconductor Devices, Part 3, IEC 63068-3:2020, IEC, 2020. [3] H. Sako, K. Kobayashi, K. Ohira, T. Isshiki, J. Electon. Mat. 49, 5213 (2020). [4] S. Hayashi, H. Sako, J. Senzaki, J. Cryst. Growth, 648, 127880 (2024). [5] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Mater. Sci. Semicond. Process. 175, 108247 (2024). [6] M. Na, W. Bahng, H. Jung, C. Oh, D. Jang, S.-K. Hong, Appl. Phys. Lett. 124, 152109 (2024). [7] M. Na, S.-K. Hong, W. Bahng, H. Jung, C. Oh, D. Jang, D. Kim, T. Iqbal, J. Park, Y. G. Park, Appl. Surf. Sci. 703, 163425 (2025). |
Challenges in 1SSF detection in 4H-SiC epilayer and related failure PRESENTER: Cristiano Calabretta ABSTRACT. Basal plane dislocations (BPDs) are considered the most harmful defects in SiC epitaxial wafers. They cause forward degradation, which manifests as an increased forward voltage drop, in SiC bipolar devices and body diodes in power FETs when they occur in the active region. During forward bias in a SiC pn junction, BPDs can lead to Shockley-type stacking faults due to the injection of minority carriers. This expansion of stacking faults is driven by the electron-hole recombination enhanced dislocation glide (REDG) process [1-2]. This phenomenon was initially observed as causing degradation in the forward characteristics of high-voltage SiC pin diodes, with its primary source identified as stacking faults expanding within the voltage-blocking region. Shockley stacking fault (SSF) expansion from BPDs occurs during forward bias operation in 4H-SiC, leading to forward voltage drift in minority carrier SiC devices [3]. Additionally, SSF expansion has been linked to reverse bias breakdown voltage degradation [4]. To reduce the impact of these SSFs in the active drift layer, a highly doped buffer layer was developed to convert most BPDs into threading edge dislocations (TEDs). It is seldom observed that nominal current density degradation is generally not impacted. However, at exceptionally high current levels, the increased density of minority charge carriers can penetrate deeper into the buffer region, potentially triggering stacking fault growth at deeply embedded crystal defects within the buffer or even the n+ substrate. Sample analyzed in this work didn’t exhibit any indicators of impending failure, offering no warning of electrical issues at the Electrical Wafer Sorting test (EWS). After assembly process, sample was subjected to Early Life Failure Rate (ELFR) test flow, not exhibiting any anomalous current trend. Following ELFR, some electrical parameters have been additionally tested in order to confirm the goodness of the piece. As shown in Fig. 1, electrical test for this device revealed a slight increase in drain leakage current at high bias (850 nA at 1200V) compared to other pieces subjected to the same test cycle in which IDSS value is lower than 200 nA. Following the Emission Microscopy investigation and spatial detection of the failure, photoluminescence (PL) analysis was conducted using a LabRam Odyssey spectrometer equipped with a =320 nm wavelength and 600 gr/mm grating. Micro-photoluminescence (μ-PL) analysis was carried out to examine stacking faults which were expanded in 4H-SiC epilayers., Based on the SSF shape detected, the Burgers vector for most typical linear BPDs in 4H-SiC epilayers is b=(±1/3)[11-20]. This aligns with the fact that only some BPDs with this Burgers vector replicate from substrates without converting into TEDs. Indeed, Fig. 2 shows the region where only band-to-band emission is visible, along with -PL acquisition within the SF layer, identifying it as a 1SSF emitting at =424 nm. From the μ-PL analysis, it can be inferred that the dislocation direction is [10-10] with a Burgers vector of (1/3)[11-20] [5]. As evidenced by the SSF length that matches the depth of the epitaxial layer, the 1SSF originates from a BPD located just below the BPD-TED conversion point during the early phases of epitaxial growth. According to the PD loop model which describes the evolution of partial dislocations from BPD [6], the right sides of SSF is bordered by C-core PDs, a finding corroborated by the restricted expansion observed following repeated laser exposure. Subsequently, the 1SSF extends through Si-core dislocation until it reaches the surface. The study underscores the challenges posed by BPDs and SSFs in SiC epitaxial wafers, which are hard to detect early despite their significant impact. Although the device shows only a slight increase in drain leakage current after the ELFR test, these kind of faults can lead to forward degradation in SiC bipolar devices and power FETs due to SSF expansion during forward bias operation. Mitigation strategies, such as enhancement of BPDs to TEDs conversion at the interface between substrate and epilayer as well as advanced diagnostic techniques like μ-PL are crucial for analyzing SSF dynamics on wafers. Additional analyses are in progress to characterize the SSF expansion under laser pumping and studies on its rearrangement under thermal conditions are considered as well. The electrical characterization on SSF andin general on SFs, are increasingly playing an essential role to drive the process control, not only at epitaxial growth step, but also involving thermal and oxidation processes in order to define the correct screening procedure and reduction of failures. |
Impact of ICP-RIE Process-Induced Deep-Level Defects on Carrier Lifetime in 4H-SiC Epitaxial layers PRESENTER: Minseok Kim ABSTRACT. 4H-SiC is a wide-bandgap (WBG) semiconductor that exhibits excellent electrical performance under high-voltage and high-temperature conditions, making it highly suitable for power device applications. Inductively coupled plasma reactive ion etching (ICP-RIE) has been widely employed in the fabrication of SiC-based devices. However, it has been reported that the RIE process introduces various deep-level defects in both n-type and p-type SiC, with these defects forming at depths of several micrometers. To date, the surface reactions during RIE in SiC have not been fully clarified, highlighting the need for fundamental research on its etching mechanism. In this study, the effects of ICP-RIE and subsequent annealing on deep-level defects and reverse recovery characteristics of 4H-SiC were systematically investigated. Fig. 1 presents FIB-SEM images of three representative samples used in this study. The first sample is an as-grown Schottky barrier diode (SBD) without any additional processing. The second sample underwent ICP-RIE treatment, while the third sample was subjected to ICP-RIE followed by post-annealing at 1200 ℃. Fig. 2 presents the temperature-dependent behavior of Z1/2 and EH6/7 defects, analyzed using deep level transient spectroscopy (DLTS). The Z1/2 defect appeared prominently around 300 K, while the EH6/7 defect was observed near 450 K. The Z1/2 defect is widely attributed to carbon vacancies, and EH6/7 is commonly associated with carbon vacancy-related complexes acting as deep recombination centers [1]. In particular, the Z1/2 defect was found to reduce carrier lifetime and enhance recombination at elevated temperatures [2]. In the RIE + annealed SBD, the ON1 center was observed near 400 K, likely caused by the high- temperature annealing above 1200 ℃. In contrast, the EH3 center disappeared after annealing, which can be attributed to the removal of single carbon interstitials. EH3 centers are known to be thermally unstable and typically vanish after annealing above 500 ℃. Meanwhile, the Z1/2 center remains thermally stable and is widely associated with carbon vacancies exhibiting multiple charge states. Fig. 3 shows the carrier lifetime calculated based on the Z1/2 trap concentration. The carrier lifetime decreased from approximately 25 μs in the as-grown state to about 13 μs after RIE treatment [3]. Carrier lifetime is a critical parameter that significantly impacts switching behavior, especially in PiN diodes. Accordingly, reverse recovery simulations were performed for PiN diodes incorporating Z1/2 traps in the epitaxial layer. The analysis revealed that Z1/2 defects act as lifetime killers, and the reduction in carrier lifetime led to a shorter reverse recovery time. Specifically, the reverse recovery time decreased from 98 ns to 70 ns, and the peak current dropped from –230 A to –203 A. This clearly indicates a strong correlation between Z1/2 defect concentration and reverse recovery behavior. In conclusion, this study provides a quantitative analysis of deep-level defect formation induced by ICP-RIE and annealing, and their effects on the reverse recovery characteristics and carrier lifetime in 4H-SiC devices. The Z1/2 defect was found to have a significant impact on switching performance and demonstrated thermal stability with negligible change in concentration after annealing. These findings underscore the importance of defect-specific and process-optimized strategies for improving the reliability and high-temperature performance of SiC-based power devices. |
Investigating the temperature dependence of charge carrier lifetime in low-doped n-type 4H-SiC PRESENTER: Anders Hallén ABSTRACT. The charge carrier lifetime is a very important parameter for bipolar semiconductor devices. For ultra-high voltage devices, >10 kV, a long lifetime of several µs is needed in the drift layer to keep the on-state losses at a low level. However, during the turn-off shorter lifetimes are needed to minimize the losses during this phase, which necessitate a balance between on-state and switching losses dictated by the device applications. The carbon vacancy is known to induce a strong recombination center called Z1,2 defect from deep level transient spectroscopy (DLTS), which has been responsible for controlling the lifetime in low n-doped epitaxial 4H-SiC. Over the years, several techniques have demonstrated how to reduce the carbon vacancy concentration [1,2] and, more recently, other defects have shown to be limiting the carrier lifetimes, such as the deep and shallow boron related levels in the lower part of the 4H-SiC bandgap [3]. In this contribution we will show what lifetimes are expected from the boron-related defects and how the lifetime can increase, or decrease, with temperature depending on the relative concentrations of shallow and deep boron traps. The lifetimes are calculated from the Shockley-Read-Hall (SRH) model, following the full thermodynamic treatment with Gibbs free energy instead of the commonly used ionization energy of the traps. To obtain correct thermal dependence, the recombination parameters: capture cross section, Gibbs free energy [4] (i.e. ionization enthalpy and entropy), and defect concentration, are obtained by DLTS measurements from literature. Finally, the calculated results will be compared to IV measurements on 10 kV pin diodes [5], where also carbon vacancies have been introduced by energetic particle bombardment. [1] L. Storasta and H. Tsuchida,” Reduction of traps and improvement of carrier lifetime in 4H-SiC epilayers by ion implantation”, Appl. Phys. Lett 90, 062116 (2007) [2] H. M. Ayedh, Anders Hallén, and B. G. Svensson, “Elimination of carbon vacancies in 4H-SiC epi-layers by near-surface ion implantation: Influence of the ion species”, Journal of Applied Physics, Vol. 118, 175701 (2015) [3] M. Ghezellou, P. Kumar, M.E. Bathen, R. Karsthof, E.Ö. Sveinbjörnsson, U. Grossner, P. Bergman, L. Vines, J. Ul-Hassan, “The role of boron related defects in limiting charge carrier lifetime in 4H-SiC epitaxial layers”, APL Mater. 11, 031107 (2023) [4] O. Engström and A. Alm, "Thermodynamical analysis of optimal recombination centers in thyristors." Solid-State Electronics 21.11-12 (1978): 1571-1576 [5] K. Tian, J. Xia, K. Elgammal, A. Schöner, W. Kaplan, R. Karhu, J. Ul-Hassan, A. Hallén, “Modelling the static on-state current voltage characteristics for a 10 kV 4H-SiC pin diode“, Mat. Sci. Semicon. Porc. 115, 105097 (2020) |
Analysis of Overlapping Capacitance Transients in DLTS and MCTS for Commercial SiC Power Diodes PRESENTER: Natalija Für ABSTRACT. Deep level transient spectroscopy (DLTS) and minority carrier transient spectroscopy (MCTS) are established techniques for characterizing defects in semiconductors. These methods provide essential information about the energy levels, spatial distribution, and capture cross-sections of electrically active defects within the semiconductor bandgap. However, conducting DLTS and MCTS on devices with p-regions remains complex. This study systematically analyzes the capacitance transients of commercial SiC Junction Barrier Schottky (JBS) diodes, rated for blocking voltages of 1.2 kV and 1.7 kV, and forward bias currents of 10 A and 25 A, respectively. Measurements were performed over a temperature range of 20 K to 350 K using a high-energy resolution DLTS setup. The study shows the importance of time window selection to avoid overlap of majority and minority carrier trap emission signals, which can complicate analysis and lead to incorrect conclusions. |
Chelation-Assisted Cleaning for Effective Removal of Al and Mn Contaminants on 4H-SiC Wafer PRESENTER: Yeon-Je Gye ABSTRACT. Research on SiC manufacturing processes is increasingly important for advancing high-performance power semiconductor devices. Among the critical steps, the chemical mechanical polishing (CMP) process is extensively studied for achieving surface planarization. However, the subsequent post-CMP cleaning process is equally vital, as it addresses contamination issues resulting from polishing. Metal contaminants, if not effectively removed, can degrade surface integrity and diffuse into the substrate during high-temperature treatments, where they act as deep-level defect centers [1,2]. In the CMP process of 4H-SiC, a specialized slurry containing abrasive particles (Al₂O₃) and oxidizing agents (KMnO₄) is employed. These components introduce metal ions such as Al³⁺ and Mn⁴⁺, which tend to adhere to the wafer surface post-polishing [3]. Such residual metal contamination presents a significant challenge, as it directly affects the wafer's surface quality and downstream process reliability. While the hydrochloric peroxide mixture (HPM or SC2), commonly used for Si wafer cleaning, is designed to remove metal ions, it exhibits limited effectiveness on SiC surfaces. Furthermore, traditional RCA cleaning methods are inadequate for eliminating these metal residues. Therefore, this study investigates a chelation-assisted cleaning approach aimed at more effectively removing metal contaminants from the SiC surface. In this study, the removal behavior of residual Al and Mn metal ion contaminants on the SiC wafer surface after CMP was investigated by comparison with a Si wafer, and various chemical cleaning formulations were evaluated for their effectiveness in eliminating these contaminants. The SC2 solution supplemented with citric acid demonstrated effective Mn ion removal, as quantitatively confirmed by inductively coupled plasma mass spectrometry (ICP-MS) analysis. As shown in Fig. 1, Mn ion contamination remaining after CMP exhibited different cleaning behaviors between Si and SiC wafers. For Si wafers, both SC1 and SC2 cleanings were sufficient to effectively remove Mn ions. However, for SiC wafers, neither SC1 nor SC2 alone achieved adequate Mn removal. This indicates that Mn ions interact more strongly with the SiC surface, making their removal more difficult using RCA cleaning. Fig. 2 presents a comparative analysis of the residual concentrations of Al and Mn metal contaminants on SiC wafers after CMP using various cleaning solutions. The tested chemicals included standard RCA cleaning solutions (DHF, SC1, SC2), a phosphoric acid-based ceramic etchant for Al removal, and SC2 with citric acid. The results showed that Mn was effectively removed under most conditions, with the citric acid-supplemented SC2 solution showing the best performance. In this case, the residual Mn concentration was reduced to below the detection limit (in the sub-ppt range), which is attributed to the high stability of the Mn–citrate complex and the relatively weak bonding between Mn ions and the SiC surface. These chemical characteristics significantly improve the cleaning performance and demonstrate the strong effectiveness of citric acid-assisted SC2 for Mn removal. In contrast, Al consistently remained on the SiC surface regardless of the cleaning solution used. This suggests that Al forms stronger bonds with the SiC surface compared to Mn, making it harder to remove using standard RCA-based cleaning. This behavior is likely due to stronger chemical bonding between Al ions and the SiC surface [4], emphasizing the need for an improved cleaning method specifically designed to efficiently remove Al contamination. In conclusion, the effective removal of metallic ion contaminants after CMP was experimentally demonstrated, which is expected to be beneficial for maintaining the crystalline quality of SiC epitaxial layers. In particular, the citric acid-assisted SC2 cleaning process, which exhibited outstanding Mn removal performance, is expected to become a key technology for the future fabrication of high-reliability SiC power devices. |
Evaluation of transmission spectra of vanadium-doped 4H-SiC substrates by optical transmittance measurement PRESENTER: Haruhiko Udono ABSTRACT. Silicon carbide (4H-SiC) has garnered significant attention in recent years as a next-generation power device material due to its exceptional properties, including a wide bandgap, high breakdown voltage, and high thermal conductivity [1]. Although high-quality SiC crystals have been grown by the sublimation, PVT, and gas-source methods, the control of polytype generation and the reduction of crystal defects, such as through-going dislocations and micropipes, are still recognized as important issues [2,3]. As for impurities, it is well known that nitrogen (N) produces a high concentration of donors in SiC, and nitrogen addition is used for n-type SiC crystals with low resistivity [4]. Since nitrogen is easily introduced from the ambient during growth, a method to evaluate nitrogen concentration by optical absorption and transmission measurement has been reported extensively [5]. On the other hand, vanadium (V) doping is also investigated to form semi-insulating SiC crystals, photoconductive semiconductor switches, and quantum emitters using SiC [6,7]. In this study, we investigated the transmission spectra in 4H-SiC doped with N and V to evaluate their concentrations in the 4H-SiC crystals by optical transmission measurements. Evaluation samples were prepared by cutting wafers perpendicular to the c-plane from 4H-SiC crystals grown by the sublimation method [2]. V-doping was also conducted to obtain semi-insulating SiC crystals. The surface of wafers was ground mechanically and then polished by chemical mechanical polishing (CMP) process to obtain a smooth surface. Transmission spectra were evaluated using a UV-VIS-NIR spectrophotometer (Hitachi High-Tech UH4150). Impurities in the crystal were also evaluated by electron spin resonance (ESR) measurements. Figure 1 shows the results of transmission measurements. The transmission spectrum of the N-doped n-type sample indicated the presence of an absorption peak at a wavelength of approximately 450 nm. This peak is in close correspondence to the previously reported absorption peak wavelength of 460 nm [5], which was attributed to N impurities in the 4H-SiC crystal. In the V-doped SiC crystal, three peaks and one shoulder were observed between 800 and 1400 nm wavelength range. This characteristic spectrum is attributed to the absorption peaks from the intraband V level in the V-doped 4H-SiC crystals with a sufficiently low N impurity concentration [7]. Consequently, the N impurity concentration in our V-doped sample is considered to be sufficiently low. These findings reveal the potential for semi-quantitative evaluation of V content and N concentration through spectral analysis of optical transmission measurements. |
Characterization of Stress and Defects in 4H Silicon Carbide Wafers by Scanning Infrared Depolarization PRESENTER: Markus Stoehr ABSTRACT. Single-crystalline SiC has been established as the favored material for electronic devices operating at high power, high frequency and high temperature with superior energy efficiency. Hence, the worldwide fabrication of SiC substrates is rapidly growing. Quality control and process monitoring of high wafer quantities requires suitable measurement systems, preferably fully automated, fast and non-destructive. Stress is a relevant property of the substrate material and gives an indicator of the wafer quality and can additionally be used to monitor process steps. The photo-elastic measurement system SIRD (Scanning Infrared Depolarization) has been successfully applied to monitor the industrial production of semiconductor wafers for many years [1, 2]. It offers a fully automated, fast and non-destructive method to measure stress inside substrates with highest sensitivity. Consequently, now the SIRD measurement and analysis strategies have been also adapted to SiC [3]. SIRD is a fully automated transmission dark-field plane polariscope, which scans the wafer with an infrared laser probe. In this way the SIRD visualizes global and defect-related stress states in semiconductor wafers by using the phenomenon of stress-induced optical birefringence. Using the anisotropic stress-optical law, it is possible to calculate quantitatively the stress field based on the measured optical birefringence as shown in Figure 1a. Additionally, it is possible use a high-pass filter to visualize local stress indications of defects as micropipes, sliplines and dislocation cluster as seen in Figure 1b. |
Inhomogeneity of recombination lifetime in 4H-SiC epitaxial layers and surface passivation PRESENTER: Dávid Krisztián ABSTRACT. Accurate carrier lifetime measurement in 4H-SiC epitaxial layers is critical for the development of high-voltage bipolar devices such as PIN diodes and insulated-gate bipolar transistors (IGBTs). We investigated 4H-SiC epitaxial layers of varying thicknesses to differentiate between bulk and surface/interface-related recombination mechanisms. In addition to measuring carrier lifetimes, µ-PCD offers valuable insight into the SiC/SiO₂ interface quality. To explore this, we evaluated the passivation effectiveness of silicon dioxide layers deposited by various methods. |
Effects of Conditioning Disc Designs on the Tribological, Vibrational, Thermal, Kinetic, Pad Micro-Textural and Pad Wear Characteristics of Silicon Carbide CMP Processes PRESENTER: Ara Philipossian ABSTRACT. Three conditioning discs (one with conventional grits and two CVD-deposited) were tested for silicon carbide (both Si-face and C-face) CMP applications. All discs were coated with proprietary films to withstand the corrosive environment of the polishing process, as the Fujimi DSC223 slurry contained potassium permanganate. In particular, we looked at how different sliding speeds and applied wafer pressures affected the tribological, vibrational, thermal, and kinetic attributes at the onset of the polishing process and after a 10-hour marathon run period. We also quantified how the discs affected the final micro-texture of the pad and its wear rate and began to understand how the mean size and distribution of tip protrusion heights impacted overall polish performance. For all three discs, the tribological mechanism of the process (both before and after the marathon) was proven to be boundary lubrication, which highlighted the stability of the process even after each pad had worn out significantly. For the Si-face, the disc type only slightly affected the coefficient of friction (COF) and, as a result, the average process temperature (Fig. 1). However, when polishing the C-face, CVD-deposited discs resulted in consistently lower values of COF and temperature, likely because the C-face of SiC substrates is generally smoother than the Si-face (Fig. 1). Regardless of which face was being polished, CVD-deposited discs also resulted in lower levels of shear and normal vibrations, highlighting the importance of using advanced conditioning products, as excessive vibrations can impact wafer-level defects and may even cause the edge of the wafers to chip away. Just as important was our observation of a significant increase in removal rate (RR) when switching to CVD-deposited discs. Specifically, all else being equal, with the CVD-deposited discs, average RRs were higher by 20 to 32 percent for the Si-face and by 5 to 13 percent for the C-face (Fig. 2). At the same time, pad wear rates (PWR) were 3X lower with one of the CVD-deposited discs compared to the conventionally-gritted product; for the other one, PWR was lower by 60 percent (Fig. 3). In all cases, lower pad wear rates seemed to result in lower pad surface roughness (Fig. 3). These observations defined an interesting pathway towards developing more environmentally friendly SiC CMP processes in which, by using the right conditioning disc, slurry consumption could be reduced by 30 percent and pad life increased three-fold while increasing module productivity and reducing cost-of-ownership. Before and after the 10-hour marathon run, the RRs of the Si-face drifted down by 1.6 percent for the conventionally gritted discs and 6 percent for one of the CVD-deposited discs. The second CVD-deposited disc caused RR to drift up by only 2.7 percent (Fig. 4). Such low (and possibly within the margin of error) drifts indicated that all three products could perform well even after longer marathon runs, as we saw no signs of tip micro-wear within 10 hours of extended use. After accounting for the shear forces caused by the retaining ring (and subtracting them from the total shear force measured in each case), RRs followed the Shear Force Law [1] for both faces, with the resulting rays (or half-lines) all converging towards a common intercept. For the CVD-deposited discs, convergence occurred at the origin, indicating a predictable and scalable RR response to various pressures and velocities, possibly even beyond the range of parameters tested in this study (Fig. 5). For the conventionally-gritted disc, for a yet-to-be-understood reason, convergence took place at a positive shear force value (i.e., not zero), suggesting the existence of a shear force threshold value below which removal was impossible (Fig. 6). Finally, pad micro-texture analysis showed that the CVD-coated discs, despite their higher mean tip heights, resulted in significantly lower pad surface roughness parameters than the conventionally-gritted disc. As noted above, their resulting PWR values were also lower. Finally, the three conditioning discs showed no signs of groove edge damage or slurry build-up. [1] L. Borucki, Y. Sampurno, A. Philipossian, The Shear Force Law: A Guide to Modeling CMP Removal Rates, ECS J. Solid State Sci. Technol. 12, pp. 044003 (2023). |
Effects of Thermal and CVD Gate Oxides on Dielectric Properties and Sidewall Capacitance in SiC Trench MOS Capacitors PRESENTER: Hyung-Jin Lee ABSTRACT. Silicon carbide (SiC) is a wide bandgap semiconductor with high thermal conductivity, electron saturation velocity, and breakdown field, making it suitable for high-frequency and high-power applications in extreme environments [1,2]. Trench MOSFETs eliminate junction field-effect transistor (JFET) resistance, resulting in reduced ON-resistance and an improved figure of merit (FOM) compared to conventional planar structures. Furthermore, when the conductive channel is formed on crystallographic planes such as the (11–20) a-face rather than the (0001) Si-face, significant enhancement in channel mobility is observed [3]. Such advantages have made SiC trench MOSFETs a leading candidate for next-generation power device architectures. Gate oxides in SiC trench MOSFETs are typically formed via thermal oxidation or chemical vapor deposition (CVD). Thermal oxide tends to grow thicker on the sidewall compared to the mesa and bottom regions, and exhibits a stable dielectric constant (~3.9) due to its high quality. CVD oxide exhibits uniform thickness, while its dielectric properties vary due to impurities such as hydrogen and fluorine, which degrade material quality [4]. Furthermore, the relatively low density of these films contributes to increased defect levels, such as dangling bonds and charge trapping, which further deteriorate dielectric performance [5,6]. The capacitance–voltage (C–V) technique is commonly employed to assess oxide quality and interface properties in MOS structures. However, in trench MOSFETs, where the conductive channel lies along the trench sidewall, it is challenging to isolate the sidewall contribution, as it is superimposed with capacitance components from the trench bottom and mesa. In this work, we utilized a previously reported method to extract sidewall-specific MOS capacitance from standard C–V measurements [7]. Four gate oxide conditions, thermal oxidation at temperature A, thermal oxidation at temperature B, thermal oxidation followed by CVD, and CVD-only, were fabricated for comparison. Additionally, five groups of 4H-SiC trench MOS capacitors with varying trench bottom and mesa widths were designed to study the impact of structural parameters on the measured capacitance. Low-frequency C–V (LFCV) measurements were conducted to investigate the capacitance behavior of the fabricated trench MOS structures. The results revealed clear correlations between trench geometry (trench bottom and mesa widths) and the extracted MOS capacitance. Oxide thicknesses across all samples were found to be consistent when comparing the results obtained from transmission electron microscopy (TEM) analysis and the thickness values calculated from C–V measurements. In particular, the lower dielectric constant of the CVD-grown oxides, compared to thermally grown ones, was inferred from the discrepancy between the physical thickness obtained by TEM and the electrical thickness calculated from C–V measurements. This discrepancy could only be reconciled by reducing the dielectric constant value in the model. This observation aligns with the expectation of increased defect density in CVD oxides. |
Improved Silicide Formation in Vertical 4H-SiC JFET via Double Spacer Process PRESENTER: Gihoon Park ABSTRACT. Vertical-channel 4H-SiC junction field-effect transistors (JFETs) offer strong potential for high-power and high-temperature applications, owing to their ability to control current via PN junction depletion regions in the active area [1]. Figure 1 illustrates the cross-sectional structure of a high-voltage P⁺ ion-implanted device. In trench-based designs, forming low-resistance ohmic contacts in the source and gate regions is essential for reliable operation [2, 3]. A common approach is to use self-aligned contacts formed with dielectric spacers [4, 5], but process variations—such as inconsistent spacer thickness or incomplete etching—can hinder proper silicide formation. As shown in Figures 2(a) and 2(b), these issues may result in unexpected silicidation on trench sidewalls or residual dielectric remaining in the mesa region. To address these limitations, a refined self-aligned silicide process was developed. The method begins with over-etching the first spacer to fully expose the mesa, followed by the formation and etching of a thinner second spacer to improve uniformity and alignment across the wafer. A thermal oxidation step is then applied to stabilize the dielectric along the trench sidewalls, where the depletion region forms. Due to crystallographic differences between the Si-face of the mesa and the a- or m-face of the trench in 4H-SiC, a thicker oxide naturally forms along the sidewalls, enhancing structural integrity [6]. The slow oxidation rate of SiC also helps produce a thin, uniform oxide layer [7]. As confirmed by vertical SEM analysis in Figure 3, this process results in improved silicide formation and greater overall stability. |
Critical Wafer Processes for SiC Device Fabrication PRESENTER: Dave Thomas ABSTRACT. Critical Wafer Processes for SiC Device Fabrication D. Thomas, C Jones, R. Barnett, D Macfarlane and A Barker KLA Corporation, SPTS Division, Ringland Way, Newport NP18 2TA, UK E-mail: dave.thomas@kla.com Power semiconductors have widespread applications ranging from household appliances, electric vehicles, renewable energy systems and data centers. Si power dominates device revenues but the fastest growing sector for high voltage, high current use cases is SiC. Despite a recent softening in demand the SiC device market should exceed $10B by 2028 [1]. Trenched SiC devices (Fig. 1) offer a lower channel resistance, higher cell density and higher channel mobility compared to planar designs. This paper reviews the critical etch, PECVD and PVD processing steps required to fabricate these devices. Trench formation Central to trench formation is the SiC etch. Being strongly bonded SiC requires a high density plasma and a hard-mask. PECVD silicon oxide 2-3µm thick is typically used. This sacrificial layer must withstand the plasma etching conditions and requires a high deposition rate to maximize productivity. Deposition rates >1.7µm/min are achievable with a uniformity of ±3%. A typical hard-mask etch at 1.6µm deep is shown in Fig. 2a. A vertical profile is desirable with minimal sidewall roughness. A 1.1x1.7µm SiC trench with a flat base is shown Fig. 2b. Rounding of the trench base improves the gate oxide quality, prevents regions of high electrical field and allows device operation at higher voltages. An example of base rounding is shown in Fig. 2c. This is achieved using in-situ polymer deposition, avoiding the need to ‘flow’ the SiC crystal at up to 2000◦C in a furnace. The improvement in electrical performance is shown in Fig. 3 [2]. The trench top corner can also be rounded as in Fig 2d. Variations in trench depth can impact the device performance. We will report on a novel in-situ method for trench depth monitoring for improving wafer to wafer process control. After ion implantation α-C is deposited acting as an out-diffusion barrier during the high temperature implant anneal. The α-C film needs to cover the sidewalls sufficiently and survive ~1800◦C with minimal shrinkage. An example α-C film is in Fig. 4. The step coverage is >34% in the trench with a shrinkage of ~6.6nm/min. Front-side metallization and passivation NiSix forms the low resistivity contact involving Ni PVD followed by an anneal to form the silicide. Ni is ferromagnetic making it challenging to deposit by magnetron sputtering due to poor field penetration of the target. We report on a new magnetron that improves target life by ~75% and improves wafer thickness uniformity. Ti/TiN/Al is used as the main current carrying metal stack. The Al is typically 3-5µm thick and requires a relatively planar surface to assist subsequent process steps. Combining a clamp-less approach and close attention to high vacuum levels the Al grain growth is unrestricted so that ‘extrusions’ are avoided whilst maintaining a deposition rate >1.4µm/min as in Fig. 5. Once the metal interconnect is completed SiNx passivation is added by PECVD. An NH3-free approach results in a high film density due to low H incorporation and a breakdown voltage >10MV/cm (Fig. 6). Back-side metallization After back-side grinding and polishing (to ~250µm) the back-side metallization is completed. NiSix is repeated followed by a solderable metal stack of Ti/NiV/Ag. Edge wafer handling allows processing face-down. The film stresses require careful management to control wafer bow and avoid wafer breakage. We will report on methods of stress control as well as a novel in-tool bow measurement to enhance process stability (Fig. 7). Device Singulation Sawing is the most common method of SiC device singulation today. We will present on plasma dicing of SiC [3] to maximize die quality and yield, especially important for automotive use cases. As part of the ICSCRM 2025 Conference EyeQ Lab (a KLA tool user) will showcase their new SiC fab in Busan, South Korea. This will include toolsets for the processes described in this paper. [1] TD Cowen SiC Market Report (2024). [2] B Jones et al, ICSCRM (2023). [3] A Croot et al, CS Mantech (2024). |
Decoupled Plasma Nitridation of SiC surface for Interface States Density reduction in 4H-SiC MOS Capacitors PRESENTER: Patrick Fiorenza ABSTRACT. Since more than a decade, metal oxide-semiconductor field effect transistors based on 4H-SiC (4H-SiC MOSFETs) are commercially available and exhibit superior performance with respect to similar Si devices. However, for 4H-SiC power MOSFETs operating in the voltage range of 400-1200V, the channel resistance represents an important contribution to the overall device on-resistance (RDS,on) and it is significantly impacted by the high-density of SiO2/SiC interface traps that cause a decrease of the electron mobility in the inversion channel [1]. Post-oxidation-annealing (POA) of the SiO2/SiC interface using a combination of nitric oxide (NO) or nitrous oxide (N2O) is the most common method to reduce the interface states density (Dit) and increase the 4H-SiC MOSFET channel mobility. However, these nitridation processes present some issues, e.g. the generation of fast interface states near the conduction band edge or near-interface-traps in the oxide, which make difficult to control either the channel mobility or the threshold voltage stability of the device. Moreover, nitridation annealing typically require high temperatures (> 1150°C) in toxic ambient (NO), which may introduce additional complexity in the fabrication flow of 4H-SiC MOSFETs. Finally, the process is expensive and typically hours-long, causing a significant limitation in throughput for high-volume-manufacturing. Hence, alternative approaches for improving SiO2/SiC interface properties in 4H-SiC MOSFET technology are highly desired. In recent years, new techniques have been proposed to incorporate nitrogen atoms at SiO2/SiC interface [2-5]. Typically, these novel approaches involve: (i) direct nitridation of the SiC surface before the actual gate oxide formation, where a significant amount of nitrogen is inserted precisely at the at SiO2/SiC interface, (ii) formation of the gate oxide by deposition at relatively low temperatures, and (iii) an annealing step to further densify the SiO2. Among those pre-oxide-formation methods, the nitridation by plasma has demonstrated promising results [3-5]. In these works, plasma power is relatively low (<200W) and wafer temperature is in 250°-350°C range. In this study, we present the results of nitrogen inclusion at SiC surface, prior to gate oxide formation, by means of Decoupled Plasma Nitridation (DPN) process, via Applied Materials™ Centura™. The process is performed at room temperature on commercial n-type 4H-SiC (0001) samples, having ~6 m thick epitaxial layer with a nominal doping concentration of 2×1016cm-3 grown onto heavily doped SiC substrate. After sample cleaning in standard HF diluted solution, the sample surface was treated by DPN process and, in the same tool – without vacuum break – a 50 nm thick High Temperature Oxide (HTO) was deposited by low-pressure chemical vapor deposition process (LPCVD). A split in DPN power and processing time allows to tune the amount of Nitrogen introduced on the SiC surface. Post-oxidation annealing (POA) at 1200°C in N2 for 30 min was performed for HTO densification. Finally, test MOS capacitors were fabricated defining Al gate electrodes over the SiO2 layer by means of photolithography and metal wet etch. Backside electrode was formed by un-patterned Al metallization. The electrical quality of the SiO2/4H-SiC interface has been evaluated by means of capacitance-voltage (C-V) measurements on MOS capacitors. The flow of the above-described experiment is schematically shown in Fig. 1. The samples have been analyzed by a variety of techniques, including Transmission Electron Microscopy (TEM) and Electron Energy Loss Spectroscopy (EELS). Compositional analysis by EELS through the full SiO2/SiC region for a sample treated with DPN process is reported in Fig.2. The results clearly show a high amount of Nitrogen (exceeding 7.0E20cm-3) localized at the SiO2/SiC interface, whereas the Nitrogen signal in the rest of the oxide is negligible. Fig. 3 shows the C-V characteristics compared to the ideal curve for the untreated interface (Fig. 3a), for the DPN-treated interface (Fig. 3b) and the comparison of the corresponding interface state distribution extracted by Terman’s method (Fig. 3c). Table I summarizes the improvements of the DPN in terms of fixed (NF), oxide-trapped (NOT) charges and interface state densities (Dit). From these results, the benefit of the DPN process applied to SiC technology is clearly demonstrated. In the final paper, additional comparative electrical results by varying the process conditions of the gate oxide near the interface and/or the annealing conditions will be presented. Part of this work was carried out using the fabrication facilities of the Italian National Infrastructure Beyond Nano. Some of the work was done with the assistance from Clas-SiC Wafer Fab. |
Impact on SiC/SiO₂ interface by N₂/H₂ high temperature pretreatment and SiO₂ Deposition PRESENTER: Heng Wang ABSTRACT. 4H-SiC MOSFETs are emerging as high-speed high-power wide bandgap (WBG) power semiconductor devices. However, the SiC/SiO2 interface, known for its notoriously low MOS-channel mobility and interface trap states, continues to limit the device performance and reliability substantially below the intrinsic potential of this WBG material. Carbon-related defects (i.e., the carbon clusters) generated during the thermal oxidation process of SiC are identified as a predominant contributor to the high-density interface state (Dit). Thus, preventing the oxidation of SiC surface serves as a critical step to improve the quality the SiC/SiO2 interface. In this study, we propose a process flow to optimize the SiC/SiO2 interface quality by using N2/H2 high temperature pretreatment, followed by LPCVD SiO2 deposition, and NO Post-Deposition-Annealing (PDA). The hydrogen-containing pretreatment enables effective removal of the oxidation-generated surface defective layer through layer-by-layer etching mechanism and preparation of a high-quality SiC surface. The LPCVD deposition method effectively avoids the thermal oxidation of SiC and the associated carbon clusters. MOS capacitors were fabricated on an n-type 4H-SiC (0001) epilayer (donor density: 1 × 1016 cm-3) grown on a n-type substrate [Fig. 1]. The fabrication process commenced with a surface pretreatment in a furnace under a gas atmosphere of 95% N2 and 5% H2 at atmospheric pressure at 1350 ℃. In comparison with the pretreatment etching by pure H2, this gas mixture is compatible with standard industrial furnace with high level of safety. Gate oxide was subsequently deposited by LPCVD at 420 ℃, yielding a ~55 nm SiO2 layer. Afterwards, NO PDA was performed at 1250 ℃ for 70 min. Finally, circular Al electrode (diameter: 400 μm) and Al back contact were deposited and sintered. To evaluate the quality of SiC/SiO2 interface, Dit near the conduction band edge (Ec) is extracted from the C-V results by using high (100 kHz)-low (quasi-static) method. Fig.2 (a) shows the Dit distribution of samples pretreated in N2/H2 mixture gas at 1350 ℃ for different time duration. The lowest Dit level is obtained in the 30 min sample. Due to multiple components in the gas mixture, two main processes could be taking place simultaneously: 1) SiC surface layer being etched by H2 to expose the Si-rich layer; 2) Si dangling bonds being passivated by N2 to form Si-N bond. Further prolonging the treatment time to 40 min leads to a degradation of Dit, especially in shallow levels close to Ec. It could be attributed to the exposure of the C-rich layer due to the layer-by-layer etching mechanism of H2 or the diffusion of excessive Nitrogen atoms from SiC/SiO2 interface to bulk of SiO2 after two Nitrogen-based treatments. The etching effect of H2 is verified by the AFM image of the SiC surface selective region pretreatment experiment [Fig. 3]. After the 30-min N2/H2 pretreatment at 1350 ℃, a Si-C bilayer of ~ 0.5 nm is removed from the SiC surface, exposing the Si-rich surface to improve the quality of SiO2/SiC interface. The temperature dependence of the Dit level during the 30-min pretreatment is investigated [Fig.2 (b)]. Samples pretreated at 1350 ℃ exhibits the lowest Dit level. The insulating properties of the gate oxide from samples with and without the pretreatment (1350 ℃ for 30 min) were compared in Fig. 4. Both the leakage current and the breakdown electric field indicate the N2/H2 pretreatment does not negatively affect the gate oxide quality. TDDB test was further performed at room temperature to evaluate the reliability of the gate oxide pretreated at 1350 ℃ for 30 min [Fig.5 (a)]. The stress electric field is 8 MV/cm, 8.25 MV/cm, and 8.5 MV/cm, with the corresponding Weibull slope (β) value of 0.98, 1.16, and 0.94. This value is relatively low in comparison to that of thermal oxide, which is attributed to the poor quality of the LTO. To project the lifetime of the fabricated MOS capacitors, t63% is plotted against the applied gate electric field, as shown in Fig. 5 (b). From the projection, the lifetime of these devices can reach 10 years at room temperature with a maximum operating electric field of 6.74 MV/cm. To conclude, the discussed N2/H2 pretreatment in combination with the gate oxide deposition process demonstrated effective improvement of the SiO2/Si interface by removing the thermal-oxidation-related carbon clusters and the associated interface Dit. Meanwhile, the pretreatment does not affect the quality of the gate oxide is insignificantly influenced, which could be further optimized by the deposition method and conditions. |
Utilizing SiO₂ Reflow for Corner Rounding to Prevent Cracking in Passivation Layers Above 500 °C PRESENTER: Julien Koerfer ABSTRACT. The development of high-temperature circuit technologies is vital for applications exposed to harsh environments, found e.g. in aerospace, automotive, and energy industries, where reliable operation of electronic components surpassing 500 °C is required [1]. Compared to Si, 4H-SiC possesses a wider bandgap, which leads to both lower intrinsic carrier concentration and reduced thermal generation of electron-hole pairs, enabling device operation at temperatures up to 961 °C [2, 3]. To make full use of this capability, the temperature stabilities of ohmic contacts and metals require protection against oxidation and degradation, making the integrity of passivation layers essential [4, 5]. This study proposes a solution to minimize thermal stress induced crack formation in passivation layers due to underlying angular oxide tapering. A CMOS compatible SiO2 reflow technique is applied to smoothen said oxide topography steps. Several samples fabricated according to the process described in May et al. [6] exhibited significant crack formation in the passivation layers above metal covered oxide topography steps after thermal cycling between RT and 500 °C or beyond, as shown in Fig. 1, where samples annealed for 10 hours in air at 400 °C demonstrated no cracks (Fig. 1a), whereas those annealed at 500 °C (Fig. 1b) and 600 °C (Fig. 1c) exhibited notable cracking. To exclude stress from titanium oxidation as the anticipated root cause for crack formation, the sample shown in Fig. 1d was annealed at 600 °C for 10 hours in vacuum with a pressure lower than 5 × 10-6 mbar. The presence of cracks under vacuum conditions confirms that thermal stress is the root cause for crack initiation rather than oxidation induced volume expansion. Focused Ion Beam (FIB) imaging provides further insights into the crack origins. In Fig. 2a, the top view shows cracks forming at the metal-covered oxide edges. Fig. 2b provides a cross-sectional perspective of the same region, illustrating a single oxide layer with a 400 nm topography step at approximately 70°, which - when covered by metal - leads to crack initiation. In contrast, Fig. 2c depicts another region of the sample where a second oxide layer of 400 nm thickness was deposited over such a abrupt 400 nm oxide step leading to a significantly smoothed topography transition which alleviates stress, thereby preventing crack formation. When a second oxide deposition is not feasible, particularly at ohmic contacts that necessitate repeated etching to access the SiC, an additional SiO2 reflow process was integrated. This process involves heating the wafer above the glass transition temperature (Tg) of SiO2 at 1400 °C for 45 minutes in an N2 atmosphere, which induces viscous flow of the SiO2 layer and thereby rounding the oxide corners, as illustrated in Fig. 3a before and Fig. 3b after the reflow step. Implementing the reflow process before the ohmic contact formation allows for the simultaneous rounding of all etched steep oxide topographies. The full paper will elaborate on these results, providing a detailed analysis of the reflow process parameters and the significance of oxide corner rounding. Furthermore, the remaining metal deposition, interlayer dielectric and passivation layer formation will be described and correlated to the reduction of crack formation in the device passivation under temperature cycling. |
Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer PRESENTER: Shao-Yuan Huang ABSTRACT. Monocrystalline silicon carbide (SiC) has emerged as a critical material for next-generation power electronics for high-performance applications such as electric vehicles, renewable energy systems, and advanced communication technologies. As urgent demands of device integration, wafer thinning becomes essential to achieve packaging and reliability requirements. This study aims to develop an Electrochemical-Assisted Fixed-Abrasive Lapping (ECAL) process for wafer thinning of monocrystalline silicon carbide (SiC) wafers instead of diamond grinding. Configuration of ECAL tool is shown in Figure 1. The SiC wafer is connected to anode and the fixed-abrasive lapping wheel on tool plate works as cathode, with an external bias voltage and electrolyte between electrodes. It can induce an electrochemical reaction for generating a passivation layer on wafer surface to enhance the material removal rate (MRR) by fixed-abrasive lapping wheel and reduce the sub-surface damage (SSD) obtained in traditional diamond grinding processes. In the first stage, electrochemical passivation using an NaNO3 solution validated, and the electrochemical reaction compound have been tested and studied. Results by nanoindentation shows tremendous decrease of SiC hardness from 24.59 GPa to 1.34 GPa after electrochemical passivation. Results by AFM observing the passivation layer morphology and XPS have confirmed properties changed from carbide to oxide and SiCxOy. Then ECAL parameter of temperature and NaNO3 solution concentration are controlled to observe via potentiostatic and potentiodynamic polarization curves, identifying the optimized electrolyte concentration for the passivation region voltage. Ellipsometer measurements are used to select the voltage that can achieve the highest passivation layer growth rate. In the second stage, optimized parameters are applied on thinning of diameter 100 mm SiC wafers. Experiments investigate the effects of different down pressures and rotational speeds on MRR and wafer surface quality. Results can achieve the highest MRR of 3.181 μm³/hr. The surface morphology of as-lapped wafer has shown that the SiC wafer surface with electrochemical reactions can obtain passivation layer, which can be almost simultaneously removed by FA lapping wheel. Experimental results have verified the feasibility of the ECAL for wafer thinning of SiC through experimental tool. Further study can focus on efficiency of larger diameter SiC wafer thinning process tool development. |
SiO₂/SiC Interface Engineering via Low-temperature NO Oxynitridation of SiC Surface Feasible with Si Device Fabrication Equipment ABSTRACT. In this study, an ultra-thin SiO2 layer with sufficient interfacial nitrogen incorporation was found to be formed by low-temperature NO oxynitridation of the 4H-SiC(0001) surface. By depositing a thick SiO2 layer by CVD on top of it, a MOS structure that is comparable to or slightly superior to conventional NO-POA can be achieved with a maximum process temperature of 1100 degree C. |
Effect of Silicon and Oxygen Pre-Implantation on Thermal Oxidation of 4H-SiC PRESENTER: Enrico Sangregorio ABSTRACT. Silicon carbide (SiC) is a promising material for high-voltage and high-temperature power devices due to its superior properties, including a wide bandgap, high thermal conductivity, and high breakdown electric field. Among wide-bandgap semiconductors, SiC is particularly advantageous as it enables the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs) using thermally grown SiO2 as a gate oxide, similar to silicon, facilitating compatibility with existing Si-based industrial processes. However, the SiO2/4H-SiC interface exhibits a lower conduction band offset compared to SiO2/Si, making leakage current control critical for device reliability. Additionally, the thermal oxidation of 4H-SiC is slower than that of silicon, a behavior generally attributed to the presence of carbon in the crystal lattice [1, 2]. As a consequence, higher temperatures and longer oxidation times are required to achieve an optimal oxide thickness. Incomplete oxidation can lead to oxygen vacancies and carbon interstitials [3], introducing defect levels in the SiO2 bandgap, which facilitate charge transport from SiC and increase leakage current. The difficulties are even more pronounced in oxides for trench gate, where different crystal orientations have different oxidation behavior. Pre-oxidation ion implantation has been shown to reduce the thermal budget of oxidation, accelerate the oxidation rate, and effectively lower the interface state density [4]. Moreover, amorphizing implants can remove the crystal orientation dependence, enabling selective growth of the oxide in the implanted regions. However, high-dose phosphorus implantation, while increasing oxidation speed and lowering interface state density, has also been shown to modify the doping concentration of SiC, thereby influencing the device's electrical characteristics [4]. To overcome this limitation, the implantation of non-dopant species such as Si and O has been proposed, providing the benefits of pre-oxidation implantation without altering the electronic properties of the SiO2/SiC interface. Additionally, high-dose Si and O implantation may affect the SiC stoichiometry, modifying oxidation dynamics and resulting in a lower carbon content in the thermally grown SiO2. In this work, the effects of high-dose Si and O pre-implantation on the oxidation process and interface properties have been investigated. For this study, 4° off-axis n+ 4H-SiC wafers were used. Before the dry-thermal oxidation process, pre-implantation was carried out using a Purion high current ion implanter from Axcelis. Two samples were implanted with 9 keV oxygen at a dose of 1017 and 1016 atoms/cm2, and one with 15 keV silicon, at a dose of 1017 atoms/cm2. The implantation energies were selected to achieve a similar penetration depth for both species, as confirmed by SRIM simulations [5]. After the implantation, thermal oxidation was performed at 1100°C in a 100% oxygen ambient for 1 hour. An additional 4H-SiC wafer was oxidized under the same conditions without pre-implantation for comparison. The oxide thickness was monitored by ellipsometry at 36, 360, and 3600 seconds from the start of oxidation. Structural characterization of the SiO2/4H-SiC interface was conducted using transmission electron microscopy (TEM). Figures 1a, 1b and 1c show cross-sectional TEM micrographs of the 1017 cm–2 silicon-, 1017 cm–2 oxygen- and 1016 cm–2 oxygen-implanted samples, respectively. The crystal defects observed near the SiO₂/SiC interface in Figure 1a are attributed to end-of-range (EOR) damage induced by silicon implantation. These defects likely originate from a deeper collision cascade and/or the presence of excess Si self-interstitials, suggesting that the oxidation time was insufficient to fully consume the damaged region. Additionally, the silicon-implanted sample exhibits significant oxide surface roughness. In contrast, the oxygen-implanted sample in Figure 1b shows a smoother surface and no visible crystal damage to the SiC, indicating complete oxidation of the damaged region. The sample exposed to 1016 cm–2 oxygen (Figure 1c) shows comparable interface quality, suggesting that there is margin to reduce the dose for more industry-compatible processes. The oxide thicknesses measured in Figure 1 are in agreement with the ellipsometry measurements. These results demonstrate the minor impact of the studied dose on the overall oxide thickness, further underscoring the feasibility of lower-dose pre-oxidation implantation, with the type and energy of the implanted ion being more significant. The chemical composition of the SiO2/SiC near-interface region was investigated by scanning transmission electron microscopy (STEM) and sub-nanometer resolution electron energy loss spectroscopy (EELS). Figure 2a shows the self-aligned EELS signals for carbon, oxygen, and partially oxidized silicon, averaged along the scanned lines, together with the dark field signal (dashed line), acquired from the 1016 cm–2 oxygen implanted sample. The SiC crystal periodicity, visible in the dark field image in Figure 2b, corresponds to the oscillations of the dashed curve in the spectra. The position of the final SiC crystalline plane, marking the boundary between the ordered crystal lattice and the amorphous oxide phase, was taken as the origin of the X-axis. Here, a ~0.7 nm non-abrupt transition region, highlighted in light blue, is characterized by a gradual increase in oxygen content and is consistent with a partially oxidized silicon phase containing a certain amount of carbon, in agreement with literature [6]. However, unlike deposited oxides, the data revealed oxygen penetration into the crystalline SiC, extending 2–3 atomic layers. This incorporated oxygen, clearly visible in the EELS map of Figure 2c, may play a crucial role in the following stages of the oxidation process, potentially influencing interface formation and reaction kinetics. These findings provide valuable insights into the formation of the SiO2/4H-SiC interface through post-implantation thermal oxidation, and further electrical characterizations are planned to deepen understanding of the electronic properties. |
Exploring Backside Contact Formation on Bilayer SiC Engineered Substrates Using Nanosecond Laser Anneal PRESENTER: Guillaume Gelineau ABSTRACT. Recently, several studies have discussed the various advantages of bilayer SiC engineered substrates, that have proven to offer higher energy conversion yield and improved ruggedness to bipolar degradation as compared to industry standards. In the frame of this research, we sought to investigate laser anneal formation of backside ohmic contact on such polycrystalline wafers through morphological and electrical characterizations. We highlight distinct mechanisms of silicide formation upon nanosecond laser anneal on polySiC wafer surface versus the (0001̅) surface of monocrystalline 4H-SiC. The varying thermal conductivities or chemical potentials – due to changes in polytype, grain orientations and other structural factors – may play an important role in the dewettting of the Ni film before it reacts with SiC upon laser annealing, influencing the amount and possibly the stoichiometry of the Ni silicide formed during the process. |
Effect of Al₂O₃ and HfO₂ Interfacial Layers on Leakage Current in 4H-SiC MIS Diodes PRESENTER: Hyeon-Do Kang ABSTRACT. SiC-based Schottky Barrier Diodes (SBDs) are widely used in power semiconductor applications due to their excellent switching characteristics and low forward voltage drop. [1] However, their performance is limited by high reverse leakage current, which arises from Fermi level pinning (FLP) and metal-induced gap states (MIGS) at the metal-semiconductor interface. [2, 3] To address this issue, the metal-insulator- semiconductor (MIS) structure has emerged as a promising alternative. By introducing an insulating interfacial layer, the electrical properties at the interface can be modulated to effectively suppress leakage current. Fig. 1 illustrates the cross-sectional structures and fabrication processes of MS and MIS-based 4H-SiC diodes. (a) shows a typical MS SBD, while (b) and (c) depict MIS diodes incorporating Al2O3 and HfO2 insulating layers, respectively. The Al2O3-based MIS diode exhibited a leakage current of 6.56×10-12 A at -8 V, approximately two orders of magnitude lower than that of the conventional SBD (9.33×10-10 A), resulting in an on/off ratio of 1.28×1010, which is about 7.5 times higher than that of the SBD. These improvements are clearly demonstrated in the J-V and breakdown voltage (BV) characteristics shown in Fig. 2, where the Al2O3- and HfO2-based MIS diodes exhibit BV values of 340 V and 520 V, respectively representing more than a twofold enhancement compared to the MS structure. The Schottky barrier height (SBH) values extracted from the J-V and C-V measurements were 0.94 eV and 2.01 eV, respectively, for the Al2O3-based MIS diode, higher than those of the SBD (0.82 eV and 1.49 eV). As shown in Fig. 3, this enhancement is attributed to the insertion of the insulator layer, which suppresses FLP and increases the effective SBH. In contrast, the HfO2-based MIS diode exhibited higher leakage current under the same conditions despite the high-k nature of HfO2. [4] This behavior is attributed to the relatively low conduction band offset (CBO) between HfO2 and 4H-SiC (~0.7 eV), which is insufficient to suppress electron injection. On the other hand, Al2O3 provides a higher CBO of approximately ~1.9 eV, offering more effective electron-blocking capability. The ideality factor, presented in Figure 4b, approached unity at elevated temperatures, indicating that thermionic emission is the dominant transport mechanism. The Al2O3-based MIS diode consistently exhibited a lower ideality factor compared to the HfO2-based device over the entire temperature range. In conclusion, leakage current in MIS structures is strongly influenced by both the SBH and the CBO of the insulating layer. This study confirms that high-k dielectrics with relatively small bandgaps and low CBO values tend to exhibit increased leakage. The findings provide valuable design guidelines for selecting optimal insulating materials in 4H-SiC-based devices, particularly for applications such as high-voltage, low-loss switching devices and high-speed power converters. |
Improvement in On-Resistance of 1200 V 4H-SiC VDMOSFETs using SmartSiC™ Wafers PRESENTER: Servin Rathi ABSTRACT. Soitec's SmartSiC™ wafer technology represents a significant advancement over traditional silicon carbide (SiC) wafers, offering several key improvements in performance and efficiency. These single crystal SiC wafers are bonded to polycrystalline SiC handle wafers, resulting in superior device performance. [1] The enhanced performance and efficiency of SmartSiC™ wafers, hereinafter engineered wafers, make them particularly suitable for power electronics in electric vehicles and industrial applications. [2] In this work, we processed material containing both normal and engineered SiC 1200 V rated wafers to estimate the improvement in on-resistance and other device characteristics. |
The effect of different pulse widths on the laser slicing of 8-inch 4H-SiC PRESENTER: Haoyu Fan ABSTRACT. As a third-generation wide bandgap semiconductor material, silicon carbide has been widely applied. However, traditional wire sawing of 8-inch SiC wafers faces issues such as significant losses and high roughness. This paper employs 1064 nm picosecond laser combined with ultrasonic delamination to systematically study the impact of pulse width (1-10 ps) on the slicing quality of 4H-SiC wafers. The experiments found that under the pulse width of 5 ps can achieve the lowest surface roughness (≈9 µm) and the minimum grinding volume (≈50 µm), which is significantly better than both overly narrow and overly wide pulse conditions. The research results provide a process reference for low-loss laser slicing of large-size SiC wafers. |
UV Laser Annealing Effects on Highly Implanted 4H-SiC Epilayers PRESENTER: Kushani Hapuhinna Perera ABSTRACT. Silicon Carbide (SiC) is a leading material in next generation power electronics due to its wide bandgap, high thermal conductivity, and ability to operate under high voltages with minimal losses.[1]Commercially available devices with breakdown voltages in the range of 600 V < VBR< 3.3 kV still stand to benefit significantly from reductions in contact resistance.[2] To mitigate these losses, ultra-high doping (>10²¹ cm-³) achieved through ion implantation is highly sought after, but can generate extended defects.[3], [4] UV laser annealing has emerged as a promising post-growth technique for dopant activation in SiC epilayers, offering precise control over surface morphology, healing of crystal damage, and modification of defect structures.[5], [6], [7] This study presents a preliminary characterisation of laser annealing (LA) effects on n-type 4H-SiC epilayers, both as-grown and implanted with Al at a concentration of 1 × 10²¹ cm-³ (sample ID: UHD-SiO₂), under varying fluences and pulse counts. The primary objective is to investigate the influence of laser parameters on phase separation and energy thresholds, particularly in relation to SiC’s non-congruent melting behaviour. The samples, consisting of a standard n+ 0.02 Ohm-cm 4H-SiC 4° degree offcut substrate with a 10 μm-thick epilayer lightly doped with nitrogen (5 × 10¹⁶ cm-³) for the as-grown sample, and UHD-SiO₂, were divided into 49 adjacent test areas, each measuring 0.9 mm × 0.9 mm. Laser processing was conducted using an excimer laser (KrF, 248 nm), in an argon (Ar) atmosphere at 10 bar. Fluences ranged from 250 to 1600 mJ/cm², applied with varying pulse counts: 1-3, 5, 10, 20, 50, 70, and 100. Structural and morphological changes were analysed using Atomic Force Microscopy (AFM), White Light Interferometer (WLI) and micro-Raman spectroscopy. Raman mapping across all test areas revealed that the longitudinal optical (LO) phonon mode in 4H-SiC interacts with free carriers, leading to observable shifts or broadening, while the transverse optical (TO) modes remained more stable for structural analysis. As shown in Fig.1. 1(A), increasing both laser fluence and pulse count led to a reduction in TO peak intensity, particularly from 1000 to 1600 mJ/cm². However, for lower fluences (250 -750 mJ/cm²), TO intensity increased progressively with pulse number from 1 to 50. In Fig.1. 1 (B), a comparison of surface roughness using WLI in laser annealing (LA) with and without SiO₂ shows that, at the highest fluence (1600 mJ/cm², 100 pulses), samples treated with SiO₂ exhibit relatively lower roughness values. However, this trend is reversed at lower fluences (e.g., at 250 mJ/cm²), where samples without SiO₂ show smoother surfaces. Additional material characterization results will be presented in the full submission to support this observation. Fig.1. 2, displays monochromatic synchrotron x-ray diffraction imaging (XRDI) on crystal plane (1-107) by Cu-Kα₁ characteristic radiation corresponding to (8.05 keV) on UHD-SiO₂. Strain contrast and threading screw dislocations are evident, as circled. Image (e) in Fig.1. 2 shows the untreated control area, while image (d) suggests that even the gentlest laser pulse may induce minor strain in the crystal. Notably, even under the highest implantation dose and annealing condition, no significant extra surface defects were generated. In the full submission, we present additional material results alongside the electrical IVs to help define a safe operational window for laser annealing, supporting its potential for high-performance device fabrication. |
Surface engineering of the 4H-SiC SiO₂/SiC interface by combining atomic layer deposition and atomic layer etching PRESENTER: Arne Benjamin Renz ABSTRACT. Despite major material advances that resulted in the reduction of defect densities [1] and a move from substrate manufacturers towards 8inch wafer, silicon carbide (SiC) MOSFETs still majorly suffer from their lossy channel region. The channel resistance is estimated to contribute up to a third of the total device resistance in a 650 V SiC planar vertical power MOSFET. Reports have established that there are two root causes of low channel mobility in SiC MOSFETs. One is the reduction in the free electron density (nfree) in the metal-oxide-semiconductor (MOS) channel caused by a high density of interface states (DIT) near the bottom of the conduction band[1-4]. The second is the low free electron mobility (µfree) of the remaining mobile electrons in the MOS channel[1]. Here, atomic layer etching (ALE) offers an opportunity to modify the interface prior to oxide deposition, as reported by Michaels et al. [5]. This, in combination with atomic layer deposition (ALD), does allow for a high level of control of the SiO2/SiC in an attempt to engineer the interface exactly for its application, e.g., prevent the creation of DITs during deposition by terminating the substrate surface accordingly, or introduce a defined charge density to modify the threshold voltage in a SiC MOSFET. A 3-stage interface engineering approach could hence be established, comprising ALE, ALD and post-deposition anneal (PDA). A process flow can be seen in Fig. 1. In this investigation, we combine, for the first time, ALE, ALD and PDA in a SiC MOS system to show the elevated levels of control on basic n-type device parameters, such as flatband voltage (VFB), hysteresis (VH), breakdown electric field (EC). We demonstrate the ability to engineer the MOS interface. SiC metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated to analyse the effect of different ALE, ALD and PDA treatments on the interface quality. 4H-SiC epilayers were grown at Warwick using an LPE AciS M8 reactor. Growth temperature was 1550°C and used a trichlorosilane (TCS) and ethylene (C2H4) mix in an H2 ambient at a nominal growth rate of 30 µm/h. 10 µm thick epilayers were intentionally doped during growth at 4 × 1015 cm-3 with nitrogen on a highly nitrogen-doped (>5 × 1019 cm-3) substrate. The wafers were diced into a 10 × 10 mm chips and cleaned with a solvent clean, followed by a HF(10%)/RCA1/HF(10%)/RCA2/HF(10%) process. Samples were etched in an Oxford Instruments PlasmaPro 100 Cobra system. Chamber pressure, used chemistry and gas flow rates were varied according to Table I below, with the intent to investigate the impact of different chemistry on the surface quality. Figure 2(a)-(d) shows the key performance indicators of representative devices, e.g., flatband and hysteresis voltage, DIT and critical electric field. When observing Fig. 2(a), it is evident that, by utilising an ALE process, the SiC surface can be conditioned in various ways, resulting in modifications in interface such as a shift in the flatband voltage, e.g., a H2-based ALE process increases the presence of positive charge in the oxide, reducing flatband voltage, whereas O2-based processes do the opposite. This proves the general functionality of the interface engineering approach. In the final submission, we will show the full dataset, channel mobilities extracted from lateral MOSFETs as well as the bonding environment at the SiO2/SiC interface post – ALE and ALD treatment. [1] T. Hatakeyama, H. Hirai, M. Sometani, D. Okamoto, M. Okamoto, and S. Harada, "Dipole scattering at the interface: The origin of low mobility observed in SiC MOSFETs," Journal of Applied Physics, vol. 131, no. 14, 2022. [2] T. Hatakeyama et al., "Characterization of traps at nitrided SiO2/SiC interfaces near the conduction band edge by using Hall effect measurements," Applied Physics Express, vol. 10, no. 4, p. 046601, 2017. [3] T. Hatakeyama et al., "Impact of crystal faces of 4H-SiC in SiO2/4H-SiC structures on interface trap densities and mobilities," Applied Physics Express, vol. 12, no. 2, p. 021003, 2019. [4] T. Masuda, T. Hatakeyama, S. Harada, and H. Yano, "Demonstration and analysis of channel mobility, trapped electron density and Hall effect at SiO2/SiC (03) interfaces," Japanese Journal of Applied Physics, vol. 58, no. SB, p. SBBD04, 2019. [5] J. Michaels et al., "Bias-pulsed atomic layer etching of 4H-silicon carbide producing subangstrom surface roughness," Journal of Vacuum Science & Technology A, vol. 41, |
Channeling ion implantation along the <0001> direction in 4H-SiC: difference in the Si- and C-faces ABSTRACT. Channeling ion implantation has attracted attention to fabricate 4H-SiC devices because of the capability of deep ion implantation with relatively low acceleration energy. In case of the channeling to the crystal axes <0001> of 4H-SiC, there are two directions: [0001] and [000-1]. In this work, we performed channeling Al ion implantation to the [0001] and [000-1] directions in 4H-SiC by implantation to the Si- or C-faces. The results show that number of channeled ions to the [000-1] direction is larger compared to the case for implantation to the [0001] direction. Therefore, when we employ the channeling ion implantation for 4H-SiC device fabrication, utilization of the Si-face is preferable. |
4H-SiC p⁺/n diodes as environment to modify ⁷Be radioactive decay time PRESENTER: Marica Canino ABSTRACT. This work presents an original application of 4H-SiC diodes, used as the environment to modify the decay time of the radioactive isotope 7Be, that is expected to change due to the Stark effect when the 7Be atoms are inserted in a high electric field [1], such as the one that can be reached in the depletion region of a reverse-biased junction. The devices are required to withstand the implantation of 1015 at/cm3 atoms of 7Be close to the junction and maintain a high electric field, continuous and stable, for at least two months under high-voltage reverse bias, thus making 4H-SiC diodes a good choice as host material. Electrical characterization, carried out by current-voltage (I-V), capacitance-voltage (C-V), and conductance-voltage (G-V) measurements before, during, and after this long-term polarization period, enabled the evaluation of the electric field acting on the Be atoms over time. p+/n diodes were realized starting from a 4H-SiC wafer purchased from II-VI, with a 6 µm thick, 1×1016 cm-3 n-type doped epitaxy and 2 µm buffer layer. Epitaxial layer thickness and doping were determined by Synopsys TCAD Sentaurus simulations in order to achieve blocking voltage around 1100 V, a practical value for long-term reverse biasing. Anode and JTE regions, with 5×1019 cm-3 and 1.25×1017 cm-3 Al concentration respectively, are formed by Al ion implantation followed by 1950 °C 30 min annealing. The front side ohmic contact was made by thin Ti, Al, and Ni layers alloyed in vacuum at 1100 °C for 5 min. A first round of I-V and C-V characterization on the as-made devices allowed for the selection, out of a set of 32 devices, of the diodes exhibiting the lowest current before breakdown. The Be implantation and long-term reverse bias experiment was made on two diodes. Here we report the characteristics of a device with anode area 9.88×10-3 cm2 and 300 nA at -950 V. High energy 7Be ion implantation was performed at the Tandem Accelerator Laboratory, DMF, University of Campania. The beam energy was modulated to obtain a box-shaped depth profile with 5.5×1015 cm-3 7Be concentration extending between 2 µm and 4 µm below the sample surface. A double AZ10XT photoresist layer was used as mask to selectively implant 7Be in the inner region of the diode, a circle of 960 µm diameter. At 750 V reverse bias the electric field in the region comprising 7Be is expected to be (1.3±0.2) MV/cm. The diode layout is shown in Fig. 1. 750 V reverse bias was applied for 107 days at Gran Sasso National Laboratories (LNGS, Italy) on the wire-bonded device to measure the 7Be decay time in a high electric field. The current flowing through the diode was continuously monitored throughout the progress of the experiment. Finally, I-V, C-V and G-V curves were acquired after the experiment. The I-V curves of the as-made diodes (first round), after Be implantation, and at the end of the experiment (final), as well as the current measured during the 7Be radioactive decay, are shown in Figure 2, while Figure 3 shows the corresponding C-V curves at 100 kHz (a) together with the A2/C2 vs V plot (b). The reverse characteristics, though experiencing an increase following the 7Be implantation, recover during the long-term reverse bias. The final capacitance decreases (Fig. 3a) while the A2/C^2 vs V is not straight. The conductance, not reported, does not show any appreciable variation. These measurements set the basis for the calculation of the electric field acting on the 7Be atoms and demonstrate the suitability of 4H-SiC diodes as host material to probe the Stark effect possibly affecting 7Be. [1] J. T. Emery, “Perturbation of Nuclear Decay Rates”, Annu. Rev. Nucl. Part. Sci., vol. 22, pp. 165-202, Dec. 1972, DOI. 10.1146/annurev.ns.22.120172.001121. |
Effect of energy injection on the interfacial structure and mechanical behavior of Si/Al: A molecular dynamics study PRESENTER: Ji Hwan Kim ABSTRACT. While energy-assisted techniques such as laser processing and thermal annealing are widely used to tailor interfacial properties in microelectronic devices, the mechanical consequences of such modifications at the atomic scale remain poorly understood. In this study, molecular dynamics simulations were conducted to investigate how energy injection alters the interfacial structure and mechanical behavior of a Si/Al interface. Thermal energy input led to Si diffusion into Al, forming an amorphous intermixed region. Tensile simulations revealed that fracture initiated at the boundary between this intermixed zone and the pure Si region, accompanied by localized residual stress. Stress–strain analysis showed that while the elastic modulus increased, both fracture strength and strain were significantly reduced, with no clear correlation to energy magnitude. Local stress and strain analyses further indicated that Si atoms embedded in Al experienced high stress and deformation, contributing to mechanical degradation. These findings offer atomic-scale insights into the trade-offs introduced by interfacial intermixing, which can inform future strategies for designing mechanically robust electronic interfaces. |
Optical pump-terahertz probe spectroscopy for measuring 4H-SiC carrier lifetime through complex surface layers PRESENTER: Nikolaos Iosifidis ABSTRACT. This study demonstrates the use of Optical Pump–Terahertz Probe (OPTP) spectroscopy to measure carrier lifetime in 4H-SiC bipolar devices, where long lifetimes (>5 μs) are essential for conductivity modulation in thick drift regions (>100 μm), reducing conduction losses in ultra-high voltage applications such as IGCTs. The conventional μ-PCD method fails to resolve ultra-fast carrier dynamics through complex surface structures, such as heavily doped emitters and buried drift regions, due to its limited temporal resolution and bulk-averaged signal. OPTP overcomes these limitations by probing sub-nanosecond photoconductivity decay with depth-resolved sensitivity, even through asymmetric doping. Using OPTP, lifetime enhancements from ~1 μs (as-grown) to up to 4.5 μs were measured after high-temperature oxidation (1400 °C, 8 h), with a clear dependence on oxidation time and measurement geometry. These results confirm OPTP as a powerful tool for lifetime analysis in technologically relevant SiC devices where μ-PCD is inadequate. |
Dynamic Current-Voltage Behavior of SiC Power MOSFETs PRESENTER: Michel Nagel ABSTRACT. In comparison to mature Silicon technology, SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) still present performance and reliability concerns attributed to the quality of the SiC-oxide interface. The SiC-oxide interface defects can trap and release charges, which can impact the current-voltage and capacitance-voltage device characteristics. The trapping mechanism is time-dependent, and (near-) interface traps (NITs) can exhibit a large dispersion in time constants. Different characterization methods have been used to evaluate quantitatively NITs in terms of density of interface states, energy location in the bandgap, and capture cross section. However, the impact of NITs on dynamic device behavior in application, i.e. during fast switching, has not been fully investigated yet. In this work we focus on the current-voltage characteristics, further investigating the impact of NITs close to the conduction band in the channel region in terms of their effect on the device switching behavior. |
A Methodology for Channel Mobility Extraction in SiC Vertical Power MOSFETs PRESENTER: Yu-Chieh Chien ABSTRACT. Channel mobility is a critical parameter for SiC MOSFETs. Conventionally, lateral MOSFETs with long channel lengths (Lch) are typically employed to determine channel mobility using the transconductance (gm) method [1]. It is advantageous to characterize channel mobility directly using a vertical power MOSFET configuration from modeling and process development perspectives. However, substantial series resistance (Rs) in vertical power MOSFETs, including contact, JFET, drift, and substrate resistances, makes accurate channel mobility characterization challenging [2]. This work presents a new physics-based methodology for extracting effective channel mobility (eff) in SiC vertical power MOSFETs. Hereafter, eff denotes the channel mobility extracted using our proposed method, while FE refers to the field-effect mobility obtained from the gm method. Parameter extraction was performed on both lateral and vertical MOSFETs to validate the effectiveness and accuracy of the proposed approach. Fig. 1 summarizes the modeling framework and extraction procedure. First, an exponentially distributed acceptor-like interface trap (Dit) near the conduction band is assumed, with its characteristic temperature (To) higher than the ambient temperature (e.g., T = 300 K). Subsequently, Poisson’s equation is solved to establish the correlation between free carrier density (ns), trapped charge density (Dt), and surface potential (s) [3]. It is important to note that a key assumption is that the majority of the inversion charges are trapped by interface states. This assumption is validated by comparing the total inversion charge with the cumulative Dit. The drain current (ID) equation is then derived by integrating ns along the channel direction, considering the effect of Rs (e.g., Vs > 0 & Vd < VD = 0.1 V where VD is the applied drain voltage). Additionally, eff is defined as o(VG-VT), where o is a mobility pre-factor and is related to Dit distribution [ = 2(To/T-1)]. Therefore, can be extracted by performing a linear regression of the H(Y) function versus VG (Fig. 2a). o and VT are then determined from the slope and x-intercept of the Y-function (Fig. 2b), respectively. Once , o, and VT are known, eff can be calculated as a function of VG (Fig. 2b). Rs is determined by comparing the total resistance with the channel resistance (Fig. 2d). A constant Rs is assumed in the ID expression, which holds well for VG between 10 V and 25 V. On the other hand, Dit can be estimated using the subthreshold current method [4] once VT is known. Fig. 3a shows the exponential-like Dit energy profile, validating the assumed Dit distribution. The extracted parameters are summarized in Table I. To verify the accuracy of the extraction, the measured ID-VG curve is evaluated against the simulated one in Fig. 3b. The simulated ID-VG curve is constructed using the extracted parameters, including , o, VT, and Rs. Negligible differences in the curves are observed, demonstrating the accuracy of the methodology. Fig. 4 shows that the extracted , VT, and eff are independent of Lch, suggesting that a “true” effective channel mobility could be accurately reflected by our approach. However, FE, extracted using the gm method, exhibits a strong dependency on Lch. Moreover, the extraction is performed on vertical power MOSFETs with designed Lch values of 0.65 m and 0.55 m to validate the proposed method. Note that FE and eff extracted from lateral MOSFETs with Lch ≥ 20 m are considered reference values (e.g., FE,ref and eff,ref). It can be observed that FE/FE,ref decreases with Lch, and the ratio is less than one, indicating a non-negligible Rs effect. On the other hand, the extracted eff/eff,ref remains approximately 1, highlighting the effectiveness of eliminating the Rs effect. In conclusion, an accurate framework was developed to extract channel mobility from vertical power MOSFETs, without the need of long-channel lateral MOSFETs. |
Design of Robust Edge Termination Applied to 4.5kV SiC SBD Embedded MOSFET Against Humidity PRESENTER: Daichi Dansako ABSTRACT. As voltage ratings of SiC power devices becomes higher, size of edge termination increases, leading to larger chip size and higher production cost. To minimize the size of edge termination, humidity robustness and process robustness have become major concerns. Previous study shows that reducing maximum electric field on SiC surface in termination region improves durability of high voltage high humidity high temperature reverse bias (HV-H3TRB) tests for 3.3kV SBDs. In this study, a process-robust, cost-effective, and humidity-tolerant termination structure applied to 4.5kV was designed using simulations. Subsequently, we fabricated 4.5kV-rated SiC SBD embedded MOSFETs with three selected edge termination structures and evaluated their breakdown voltage characteristics. As a result, it was found that by optimizing parametars of single field limiting ring structure shrinkage of termination length can be realized without changing maximum electric field on the SiC surface and breakdown voltage, and also confirmed that fabricated devices exhibited good breakdown voltage characteristics. |
A Comparative Analysis of Proton Irradiated 1.2 kV SiC Edge Termination Test Group PRESENTER: Sangyeob Kim ABSTRACT. Cosmic rays can significantly impact the reliability of SiC power semiconductor devices [1]. In particular, the total ionizing dose (TID) effect generates fixed charge (QF) within the insulating layers, leading to long-term reliability problems [2]. In this study, the impact of proton-induced TID effects on the reverse characteristics of SiC power devices was investigated by fabricating a 1.2 kV SiC edge termination test group (TEG) with three different edge termination structures: ring-assisted junction termination extension (RA-JTE), multiple-floating-zone (MFZ)-JTE, and field-limiting-rings (FLR). Fig. 1 shows the cross-sectional views and layouts of 1.2 kV SiC edge termination TEG with (a) RA- JTE, (b) MFZ-JTE and (c) FLR. RA-JTE and FLR have multiple P+ rings while MFZ-JTE has multiple JTE rings. The detailed design parameters for each structure are summarized at Table I. Wtotal is total termination width. Wring is width of the P+ rings for RA-JTE and FLR and Wd is decrease in width of JTE rings for MFZ-JTE. Spacing between main junction and first ring is defined as S1 and Si is defined as incremental spacing between each ring and n indicate number of rings. The TEG was irradiated with protons containing 45 MeV of energy with fluences range of 1 × 1012 cm−2 - 1 × 1014 cm−2. Fig. 2 shows the breakdown voltages for SiC edge termination TEG before and after proton irradiation with fluence of 1 × 1012 cm−2. All structures exhibited negligible changes in breakdown voltage. In case of 1 × 1013 cm−2, the breakdown voltage of the FLR increased from 1008 V to 1044 V as shown in fig. 3. This phenomenon can be attributed to positive QF formed in the field oxide, which alter the curvature of the depletion region. Fig. 4 illustrates the breakdown voltages for edge termination TEG before and after proton irradiation with fluence of 1 × 1014 cm−2. The breakdown voltage of RA- JTE decreased by 19 V while MFZ-JTE exhibits a 96 V decrease in breakdown voltage, corresponding to a 6.1 % change compared to before irradiation due to the rapid depletion of the JTE rings region. Although the breakdown voltage of the FLR has increased, large percentage change in breakdown voltage compared to before irradiation are not suitable for edge termination of SiC power devices for space application. Fig. 5 illustrates the simulated electric field distributions for edge termination TEG with (a) RA-JTE, (b) MFZ-JTE and (c) FLR at 1.0 kV according to presence of the QF. Electric field becomes concentrated at the main junction when QF is generated in the field oxide. In the case of RA-JTE, the multiple P+ rings effectively prevent electric field crowding at the main junction, while MFZ-JTE exhibits an increased peak electric field at the main junction, resulting in a lower breakdown voltage. In contrast, the electric field of FLR is concentrated at the edge of the ring under zero QF condition. Positive QF distributes the electric field resulting in increases the breakdown voltage. |
Optimization of a 1200V SiC lateral SiC Schottky diode PRESENTER: Zhaoxue Yuan ABSTRACT. Reduced Surface Field (RESURF) structures are widely utilized in high-voltage devices due to their capability to spread the electric field laterally and vertically, thereby improving breakdown capability. SiC lateral devices offer an excellent alternative for Power ICs due to their easily to integrate structure (system-on-chip) and material properties. A conventional RESURF device typically employs uniform N-type drift structure (Fig. 1(a)), which often suffers from excessive leakage current and limited breakdown voltage (BV), especially under edge-related field crowding [2]. To overcome these limitations, various techniques have been proposed, including field plates, and corner protection structures [3], double RESURF [4] and two-zone RESURF structures [5], which enhances field control by using vertically stacked N-regions with different doping concentrations (Fig. 1(b)). While the lateral approach improves breakdown voltage, it still presents a challenge in terms of high on-resistance due to the presence of the lightly doped drift region part. In this work, a modified RESURF SBD structure is proposed, featuring a P ring at the device anode contact corner suppress the localized electric field, along with a two-layer N-type drift region consisting of a heavily doped lower layer (Zone-1-bottom) and a lightly doped upper layer (Zone-1-top), as shown in Fig. 1(c). This configuration is designed to maintain RESURF conditions and improve both field distribution and on-state performance. Devices were modelled and simulated using Synopsys TCAD, with carefully selected doping profiles and geometrical parameters (Table1). The P-pillar presence act to collect the holes from the P-epi layer during avalanche conditions. The simulation results, as shown in Fig. 2 and 3 (on-state characteristics and breakdown output respectively), indicate that the proposed Two-Zone-Pring RESURF SBD achieves on-resistance nearly equivalent to that of the single-zone reference device, while improving the leakage and BV. Compared to the Two-Zone device, the Two-Zone-Pring device exhibits a reduction in on-resistance by at least 75%. In comparison with the Single-Zone structure, the leakage current is reduced by five orders of magnitude, as summarized in Table 2. Therefore, the N-layer in Zone-1 not only decreases the on-state resistance, it also the contributes to the electric field uniform distribution (Fig. 4). Fig. 5 shows the breakdown voltage (BV) of the proposed Two-Zone-Pring RESURF SBD reaching its maximum value when the P-type epitaxial layer thickness is approximately 13μm, representing an optimal design condition where the electric field of the vertical junction is matched that of the topside junctions. However, increasing the P-epi doping concentration leads to a gradual reduction in BV. To achieve uniform electric field distribution along the interface and maintain consistency with the vertical diode field peaks, several structural configurations were explored. The optimized design, shown in Figure 6, This structure features a Zone-1-bottom layer, and a Zone-2 of slightly higher doping. The P-epitaxial layer has a doping concentration of 5×10¹⁵ cm⁻³ and a thickness of 7μm. This configuration yields a breakdown voltage of 1200V and an on-resistance of 20mΩ/cm2, indicating a well-balanced trade-off between high voltage blocking capability and low conduction loss. Additionally, Two-Zone-Pring RESURF structure exhibits potential for radiation-hardened applications especially in space environments. Prior studies by our colleagues have indicated that such vertical and corner-field-optimized structures enhance radiation tolerance [5], making them suitable for high-reliability environments. Further experimental validation is planned to confirm the practical feasibility and performance robustness of the structure. |
Impact of optical phonon scattering on Inversion Layer Mobility in 4H-SiC p-channel lateral MOSFETs PRESENTER: Ji-Hyun Kim ABSTRACT. Beyond discrete SiC power devices, SiC complementary MOS (CMOS) integrated circuits (ICs) offer promising potential for high-temperature operation (≥ 473 K), surpassing the thermal limitations of conventional Si CMOS due to the high intrinsic carrier concentration in Si [1]. However, a comprehensive understanding of p-channel SiC MOSFETs remains limited, posing challenges for accurate modeling of SiC CMOS circuits. This study investigates the temperature-dependent mobility behavior in 4H-SiC p-channel MOSFETs with channel lengths of 2 μm and 500 μm. Fig. 1 shows the temperature dependence of effective mobility (μeff) for 4H-SiC p-channel MOSFETs with two channel lengths. The device with L = 500 μm shows the expected decrease in mobility as temperature increases, whereas the device with L = 2 μm exhibits an opposite trend, indicating increased mobility. These contrasting behaviors suggest that μeff is significantly influenced by both gate voltage and temperature, with phonon scattering dominating in long-channel devices and Coulomb scattering prevailing in short-channel ones. Figure 2 models the mobility using Matthiessen’s rule, incorporating Coulomb scattering, surface roughness, and acoustic phonon scattering. However, for the L = 500 μm device, the calculated mobilities deviate significantly from experimental results at 123 K and 373 K, with errors of 54% and 96%, respectively. The short-channel device (L = 2 μm) shows even larger discrepancies—161% at 123 K and 32% at 373 K—indicating that surface roughness alone cannot account for the mobility degradation observed under high effective electric fields. To address this, Figure 3 introduces optical phonon scattering into the model. The significant electronegativity difference between silicon and carbon in SiC suggests strong polar interactions in the crystal lattice, implying that optical phonon scattering, in addition to conventional acoustic phonon scattering, should be incorporated into mobility models. With this addition, the model shows markedly improved agreement with experimental data, reducing errors at 123 K to 18% for L = 500 μm and 10% for L = 2 μm, and at 373 K to 19% and 8.3%, respectively. These improvements confirm that optical phonon scattering plays a critical role in short-channel transport behavior. In p-channel 4H-SiC MOSFETs, effective mobility is primarily limited by Coulomb scattering at low effective fields and by optical phonon scattering at high fields [2]. As the channel length decreases, the influence of Coulomb scattering becomes more pronounced. Since optical phonon scattering is strongly dependent on the material's intrinsic properties, efforts to enhance mobility in 4H-SiC devices should focus on reducing interface states to suppress Coulomb scattering and improve overall device performance. The results enhance understanding of transport phenomena in SiC MOSFETs and underscore the importance of further studies on p-channel devices to enable precise modeling and performance optimization of SiC CMOS ICs under high-temperature and high-efficiency operating conditions. |
5 MGy Gamma-ray Radiation Effects on 4H-SiC Active Pixel Sensors PRESENTER: Tatsuya Meguro ABSTRACT. Semiconductor devices operable in high-temperature and high-radiation environments have been requested. On the decommissioning of nuclear power stations, especially in Fukushima Daiichi Nuclear Power Station, radiation-hardened image sensors have been strongly requested for the operation. In this work, 5 MGy gamma-ray radiation effects on the SiC CMOS image sensor’s active pixel sensors, were investigated. The 4H-SiC CMOS image sensor’s APSs successfully operated even after high radiation exposure of 5 MGy. |
Fowler-Nordheim current at negative gate bias in SiC MOSFETs PRESENTER: Dick Scholten ABSTRACT. The minimum rated gate voltage of commercial SiC MOSFETs typically ranges between 15 V and 4 V. Lower gate voltages may be employed for accelerated testing, such as in time-dependent dielectric breakdown (TDDB) with negative gate voltage, threshold voltage drift under negative gate bias, or bipolar dynamic gate switching stress. However, at very low gate voltages, typically below 15 V, several studies report significant gate leakage currents that decrease with continued negative gate voltage stress [1–3]. To evaluate the impact of the gate leakage on the accelerated reliability tests, a comprehensive understanding of its root cause is necessary. The prevailing hypothesis in these studies suggests that near-interface traps discharge electrons, thereby increasing the barrier height for holes during prolonged negative gate voltage stress. In this paper, we propose an alternative hypothesis based on field enhancement at the edges of the poly-silicon gate electrode. We utilized commercially available SiC MOSFETs from four different vendors and applied bidirectional gate voltage ramps of ~1 V/s with varying maximum voltage values, as illustrated in Fig. 1a, where the ramp order is indicated by the legend. The gate leakage current under negative bias appears to converge to a curve similar to the forward Fowler-Nordheim (FN) curve, but with opposite polarity, as negative voltage stress continues. We therefore propose that the gate leakage current under negative bias is an FN current characterized by an initially low barrier or a high local electric field at the barrier. Continued negative gate voltage stress shifts the onset of the current to significantly lower voltages, either by increasing the barrier or reducing the local electric field. Before and after each gate voltage ramp, we measured the threshold voltage six times, as shown in Fig. 1b. The change in threshold voltage was significantly smaller than the shift in the onset of gate leakage, suggesting that the charging or discharging of near-interface traps in the channel region cannot account for the onset shift exceeding 10 V. To further test the literature-based hypothesis, we measured the gate leakage in an n⁺-doped SiC MOSCAP and observed similar behavior to that in commercial SiC MOSFETs, as shown in Fig. 2a. Since an n⁺ region does not permit significant hole current, we rule out the prevailing hypothesis. Additionally, we measured the leakage current at negative gate bias for a device from Vendor A with the source electrode floating, as shown in Fig. 2b, demonstrating that the leakage current does not originate from the drain. Fig. 3a, shows calculated equipotential lines for a square edge close to an infinite surface. By associating the infinite surface with the SiC/SiO₂-interface and a nearby equipotential line with the edge of the poly-silicon gate electrode, we estimate the field enhancement at a rounded corner of a SiC MOSFET gate electrode. The electric field was calculated using conformal mapping according to formulas (1) and (2) in the inset, adapted from [4]. The indicated field line roughly corresponds to the minimum radius of curvature of the equipotential lines, as indicated in the figure. Fig. 3b displays the radius of curvature, calculated using formula (3), versus the field enhancement factor, defined as the field at the corner relative to the field between parallel plates far from the corner. Note that at large radii of curvature, the field enhancement factor decreases along the electric field line below 1 due to the increased distance between the corner and the plane for u-values at the right-hand side of the corner. Based on the presented data, we propose the following hypothesis: With a corner radius of approximately 3 nm, the onset of FN current is expected to occur roughly twice as early as in the case of parallel plates. Typical SEM images reveal radii below 10 nm, which aligns with our simplified model explaining the early onset. Due to the anticipated high electron current density at the poly-silicon corners, we also assume that electron trapping is enhanced, leading to a reduction of the electric field at the corners and consequently a decrease in FN current with continued electron current stress. |
Advanced Simulation Methodology of Switching Performance and Reverse Recovery Effects of SiC MOSFET and Influence of Parasitic Components on Simulation Results PRESENTER: Dan Zurek ABSTRACT. With increasing demand for SiC MOSFETs in the switching applications designs, many characterization and modeling engineers aim to develop the most accurate SPICE models for simulating the switching losses and associated reverse recovery effects. This paper describes a complex SiC MOSFET switching performance simulation flow with a great focus on parasitic elements which are considerably affecting the overall switching performance and energy losses of SiC power MOSFET device. Specifically parasitic inductances play a pivotal role in accuracy of the simulation model. To precisely model switching characteristics of SiC MOSFET, mainly carriers’ life and transit time parameters of body diode need to be correctly extracted. However, this is not possible without prior extraction of parasitic elements of the test circuit. The following study demonstrates how not only intrinsic values of parasitic elements are influencing the simulation results, but it also shows the importance of having correct distribution and mutual coupling factors of these elements within simulation circuit. The innovative simulation approach described in this paper is using multiple levels of parasitic circuits which are device package, adapter, socket and the measuring board itself, and each level is carefully modeled. The usage of adapter and socket combination for measurements is usual industry practice used for high volume testing. It is also important to note that parasitic models of mentioned elements cannot be extracted piecewise and mutual field cancellation between package, adapter and socket must be taken into account. The findings of this study indicate that incorporating highly detailed models of all components used in measured circuit, with an increased focus on its parasitic elements, significantly enhances the accuracy of simulated energy losses and enables more precise SPICE models in general. By matching the power loop stray inductance through several hierarchically coupled models, the maximum error of the model was reduced from 30% to under 10% for the switching losses, emphasizing the importance of an accurate parasitic model. Furthermore, the importance of using detailed 3D models of the parts used in measurement setup is also demonstrated, highlighting their impact on the precision of the simulations. One of the undisputable advantages of having the accurate switching models is that it leads to very accurate energy loss predictions, which are critical for high quality of system level PLECS models used for higher level system simulations. Model performance under a variety of bias conditions has been validated with one of the most recent and advanced 650V EliteSiC MOSFET technology from onsemi’s portfolio. Although simulation results are decently matching on-state and reverse recovery losses, there is still space for off-state losses improvement. This discrepancy might be caused by additional parasitic capacitance effects and deeper investigation of this problem is currently underway. The final SPICE model is compatible with various industry standard simulation platforms. All of the results and the lessons learned during the model extraction process further contribute to a deeper understanding of SiC MOSFET technology, paving the way for more reliable SPICE models used in efficient power electronics designs. |
Experimental analysis of 4H-SiC CMOS NOT logic gate down to 100K PRESENTER: Luigi Di Benedetto ABSTRACT. Nowadays, 4H-Silicon Carbide semiconductor devices are largely used in power electronics or for high-temperatures applications. Its widespread availability permitted the fabrication of high-quality substrates together with the improvements of the oxidation and of the ion implantation processes provided the basis for the development of new technologies, like 4H-SiC Complementary Metal Oxide Semiconductor, CMOS. Although the typical application of 4H-SiC have been shown, some of them, like space explorations, need good radiation hardness, reducing the shielded package, and capability to operate at temperatures lower than 150K. In this context, our paper shows the electrical performance of a 4H-SiC CMOS NOT logic gate, which is the core circuit for digital electronics, in the temperature range from 300K down to 100K with the aim to analyze and understand the limits of 4H-SiC CMOS technology at cryogenic temperatures. Indeed, it is expected that the incomplete ionization of aluminum is an extremely limiting effect as well as the high carrier traps density at the interface SiO2/4H-SiC. VIN-VOUT characteristics, from 100K to 300K, show an evident shift toward lower VIN with decreasing the temperature which is due to a reduction of the threshold logic voltage. It can be ascribed to a reduction of the conductivity of the PMOSFET with the decreasing of the temperature. The shift of the curve causes a reduction of the low Noise Margin with decreasing temperature, but the high Noise Margin increases with decreasing because the high output voltage is almost the same. Indeed, low Noise Margin and high Noise Margin are equal to 8.18V and 10.09V, respectively, at 300K and, then, change to 5.5V and 12.5V at 100K. These last margins are still wide enough for practical applications, making the circuit still useful at cryogenic temperatures. |
4H-SiC CMOS D-type Flip-Flop Circuits for Logic Circuits in Harsh Environments PRESENTER: Taisei Ozaki ABSTRACT. Electronics that can operate stably even in harsh environments such as high temperatures and high radiation are in strong demand for advanced scientific fields and industries.4H-SiC has a wide band gap and high tolerance to high temperatures and radiation. Therefore, by using 4H-SiC, it is possible to fabricate integrated circuits that can operate stably even in such harsh environments. In this research, 4H-SiC CMOS D-type flip-flop circuits were designed and demonstrated. The flip-flop circuit stored the logical data and respond to clock signal and input signal the output signal was changed correctly. By the 4H-SiC CMOS technologies, the D-type flip-flop circuits were demonstrated successfully. |
Impact of Edge Termination Structure and Length on Switching Characteristics of SiC MOSFETs PRESENTER: Hyunyong Park ABSTRACT. Silicon Carbide (SiC) has emerged as a key material for high-voltage power devices due to its superior material properties [1]. To fully utilize these properties, effective edge termination design is critical for SiC-based devices [2]. The commonly employed edge termination techniques are the junction termination extension (JTE) and the floating field rings (FFR) [3]. The JTE is widely adopted for its ease of design and fabrication, offering near-ideal breakdown voltages [4], while the FFR offers process simplicity since they can be implemented during the same process step as the main P+ regions [2]. However, the JTE requires precise doping control [4], and the FFR demands fine patterning and etching steps [2]. To address these challenges, the ring-assisted JTE (RA-JTE) structures have been introduced, offering greater tolerance to doping and process variation [2], [4]. While many studies have explored the reliability and static characteristics of various edge termination structures, investigations on their influence on switching behavior remain limited. This is particularly critical in the low-current application range where SiC MOSFETs are commonly used [5], as edge termination design can significantly affect switching performance. Therefore, a more detailed understanding of how the edge termination structure and length influence parasitic capacitances and switching characteristics is essential for optimized SiC MOSFET design. This study analyzes the switching characteristics of SiC MOSFETs using TCAD Sentaurus simulation, focusing on the edge termination structures of the FFR, the JTE, and the RA-JTE (Fig. 1), as well as the impact of termination length. The FFR, the JTE, and the RA-JTE structures show different dynamic characteristics (Fig. 2). The JTE structure shows the highest drain-to-source capacitance (CDS), while the FFR structure exhibits the lowest. These structural differences in dynamic behavior directly influence the switching characteristics. The FFR structure required a shorter time to turn off the drain current (ID) compared to the RA-JTE and the JTE structures (Fig. 3). This indicates that the presence of a junction termination region introduces switching delays during the turn-off process. Reference [1] J. Millán et al., IEEE Trans. Power Electron., vol. 29, no. 5, 2014. [2] W. Sung and B. J. Baliga, IEEE Trans. Electron Devices, vol. 64, no. 4, 2017. [3] W. Sung et al., IEEE Electron Device Lett., vol. 32, no. 7, 2011. [4] R. Pérez et al., Mater. Sci. Forum, vols. 457–460, 2004. [5] B. J. Baliga, Wide Bandgap Semiconductor Power Devices, Woodhead Publishing, 2019. |
Influence of Cell Structure and Topology on Coss of 4H-SiC MOSFET PRESENTER: Ruei-Ci Wu ABSTRACT. This study demonstrates that the output capacitance (Coss) of a 4H-SiC MOSFET is proportional to the length of JFET (LJFET) at a low Vds. In addition, the Coss of MOSFETs with hexagonal cell topology is 25% higher than that of the MOSFETs with the strip topology. However, when Vds is higher, the Coss of MOSFETs with hexagonal cell topology become lower. As LJFET decreases, Cgd becomes lower, which may shorten the switching time, but due to the increased area of the Pwell in the MOSFET, the reverse recovery current (Irr) increases. Even so, when LJFET is reduced by 0.2 µm, the turn-on energy loss (Eon) decreases by approximately 8%. |
TCAD modeling of temperature dependent transfer characteristics of 4H-SiC Lateral MOSFETs PRESENTER: Hemant Dixit ABSTRACT. 4H-SiC power MOSFETs offer significant advantages compared to Silicon based technology for high frequency and high-power electronics. Although 4H-SiC power MOSFETs are being rapidly adopted for power electronics applications, critical material and processing issues are still under investigation. Particularly, the nature of the 4H-SiC/Oxide interface, which shows a significant presence of interface traps and fixed charges, is not well understood which makes it difficult to model using Technology Computer Aided Design (TCAD). Here, we present a carefully calibrated TCAD model for predicting the temperature dependence of the transfer characteristics of a 4H-SiC lateral MOSFET. A wide range of temperatures between -70°C and +225°C is considered, which provides a crucial dataset for model calibration. We developed model parameters that accurately predict temperature dependence of the threshold voltage, sub-threshold slope and overall channel mobility curves. Furthermore, the model parameters also provide critical insights into the complex scattering mechanism that determines the behavior of channel mobility, which is critical for improving the on-state resistance. |
Study of SiC Thyristors with Integrated Temperature Sensors PRESENTER: Yuan Lei ABSTRACT. SiC GTOs, with their high current handling capability, have a promising future in high-voltage, high-power applications, but they also pose temperature-related reliability issues, and therefore need to be able to monitor the junction temperature in real time. In this paper, a novel 4H-SiC switchable thyristor (Gate-Turn-Off Thyrsitor, GTO) structure with integrated temperature sensor is proposed. The proposed sensor is compatible with the SiC GTO process and enables real-time temperature monitoring. Simulation of integrated temperature sensor GTO using switching circuits.TCAD simulation results show that the integrated sensor has high sensitivity of 1.64 mV/K and linearity of 0.99891. And integrated device simulation results show that the temperature sensor can monitor the internal temperature of the GTO device in real time with an error of no more than 2 K during the complete GTO switching process. The new structure is conducive to enhancing the reliability of SiC thyristor applications and system miniaturisation. |
Simulation of highly sensitive 3C-SiC strain sensor PRESENTER: Angela Garofalo ABSTRACT. Silicon carbide (SiC) is an interesting semiconductor for MEMS devices. The high-value Young’s modulus of silicon carbide facilitates high frequencies and quality (Q) factors in resonant devices built with double-clamped beams. The aim of this work is to achieve the determination and modeling of the Q-Factor for samples of micromachined 3C-SiC film on <111> silicon substrates. This study demonstrates that the experimental datasets created by Romero, integrated with the thicker samples reported in this work, fit the theoretical model presented in the paper. Furthermore, the influence of the crystallographic defects present at the 3C-SiC/Si interface on the Q-factor can be observed both in the analytical model of Romero and in the numerical model present in COMSOL. 3C-SiC layers with thickness greater than 600 nm are needed to achieve an ideal performance from double-clamped beams. |
A Novel Structure Design of SiC-based SCR Structure with High Holding Voltage Using Segment Topology for High Voltage ESD Protection PRESENTER: Sang Gi Kim ABSTRACT. In this study, a novel SCR structure with significantly improved trigger and holding characteristics was fabricated in 4H-SiC process, and its electrical characteristics were analyzed. A typical SCR-based device fabricated using 4H-SiC formed a snap-back waveform in a very high voltage range due to its considerably high bandgap energy. Due to the structural features and application of the segmented topology, it showed an improved snap-back characteristic with a very high holding voltage against electrostatic discharge surge. The high-temperature reliability was verified through thermal reliability tests in the range of 300–500 K. Therefore, the proposed structure significantly improves the strong snap-back of SCR in 4H-SiC, and a device with excellent on-resistance and high-temperature reliability due to the physical properties of the material was fabricate |
A Physics-based SiC DSRD SPICE Model for Pulsed Power Circuit Simulation PRESENTER: Jingkai Guo ABSTRACT. This paper presents a SPICE subcircuit model for silicon carbide (SiC) drift step recovery diode (DSRD). Based on a power P-i-N diode framework, the model incorporates plasma recombination under high-level injection to reflect charge loss during operation. Key parameters were extracted through theoretical analysis and experimental fitting. The simulated I-V characteristics, current, and output voltage waveforms showed good agreement with measurements, confirming the model’s reliability. This SPICE model provides a useful tool for designing and optimizing DSRD-based pulse power circuit。 |
Ga₂O₃ film with ultrahigh breakdown field via novel aerosol deposition method PRESENTER: Jun-Woo Lee ABSTRACT. Power semiconductor devices play a crucial role in contemporary electronic systems, including electric vehicles, renewable energy systems, and high-power electronics, by facilitating efficient power management and conversion. Essential parameters for power switches, such as Baliga’s figure of merit (BFOM), Huang’s material figure of merit (HMFOM), Johnson’s figure of merit (JFOM), switching frequency, and on-field resistance, are critical for minimizing losses and ensuring reliable switching at elevated voltages. An increased breakdown field (Ec) is vital for enhancing BFOM (~Ec3), HMFOM (~Ec), JFOM (~Ec), and on-field resistance. Wide-bandgap materials like GaN and SiC have been utilized in power-switch applications due to their high breakdown fields. Nevertheless, ultrawide-bandgap materials, especially β-gallium oxide (Ga2O3), are gaining attention as potential candidates for future power-switch devices because of their substantial bandgap (4.9 eV) and theoretical breakdown field of 8 MV/cm. Ga2O3 also allows for cost-effective, large-scale production with minimal defect density. Recent studies on Ga2O3 power devices have concentrated on Schottky barrier diodes (SBDs) and metal–oxide–semiconductor field-effect transistors (MOSFETs). For example, Dhara et al. improved the breakdown field of Ga2O3 SBD from 2.2 MV/cm to 4.1 MV/cm through field termination [1]. Yan et al. achieved a breakdown field of 5.2 MV/cm using a Ga2O3/graphene heterostructure [2]. However, despite their intricate structures, these devices have yet to reach the theoretical 8 MV/cm breakdown field. Ga2O3 films are commonly fabricated using methods such as metal organic chemical vapor deposition, pulsed laser deposition, molecular beam epitaxy, and atomic layer deposition. These techniques generally demand high temperatures, incur significant costs, and require extended growth periods. In contrast, aerosol deposition (AD) offers a solution to these challenges as it is a room-temperature, powder-impact coating method. AD is efficient, produces dense films with strong adhesion, and operates in low-vacuum conditions. Additionally, it enhances surface smoothness and internal density through a straightforward nozzle-tilting technique. Despite these benefits, research on using AD for Ga2O3 power semiconductors is still limited. A prior study on Ga2O3 film fabrication via AD reported a deposition rate of 460 nm/min and a film thickness of 3 μm [3]. Although this film demonstrated a dense structure and low leakage current, its breakdown field was low (~1 MV/cm), likely due to high surface roughness and a high density of oxygen vacancies. Oxygen-vacancy defects in Ga2O3 significantly influence its electrical and structural properties, such as electrical conductivity and bandgap reduction. Numerous studies have indicated that an increase in oxygen vacancies enhances electrical conductivity and reduces the bandgap [4]. However, there is a scarcity of quantitative research on the correlation between oxygen vacancies and breakdown fields. This study tackles these issues by utilizing thickness optimization, post-annealing, and the nozzle-tilting method to fabricate Ga2O3 films using AD for high-power semiconductors. The films were created in dielectric structures with varying thicknesses to achieve a high breakdown field with minimal film thickness. Post-annealing decreased the oxygen vacancy density, and the nozzle-tilting method improved surface roughness and film density. As a result, the Ga2O3 film achieved a high breakdown field of 5.5 MV/cm, as shown in Fig. 1, the highest recorded for a single dielectric layer without passivation or field termination. This indicates that AD-manufactured Ga2O3 films could be suitable for producing cost-effective, reliable power switches like SBDs and MOSFETs, with low on-resistance, minimal losses, and high-voltage switching capabilities. [1] S. Dhara, N. K. Kalarickal, A. Dheenan, C. Joishi, S. Rajan, Appl. Phys. Lett. 121, 203501 (2022). [2] X. Yan, I. S. Esqueda, J. Ma, J. Tice, H. Wang, Appl. Phys. Lett. 112, 032101 (2018). [3] J. W. Lee, J. H. Won, D. G. Choi, J. B. Jeon, S. Kim, C. Park, W. H. Won, K. Won, S. M. Koo, J. M. Oh Ceram. Int. 50, 14067 (2024). [4] T. Kang, D. Yang, F. Du, P. Hu, F. Teng, H. Fan, J. Alloys Compd. 926, 166887 (2022). |
Electrical identification of color centers in 6H silicon carbide using a comparative study of deep level transient spectroscopy and density functional theory PRESENTER: Erlend Ousdal ABSTRACT. Point defects in semiconductors are a highly promising platform for quantum technology (QT) offering advantages such as scalability, potential room-temperature operation, and relatively low manufacturing and maintenance costs [1]. Moreover, for some of the material platforms where quantum compatible defects have been demonstrated, such as silicon (Si) and silicon carbide (SiC), there already exists a mature infrastructure for the fabrication of components. Most work on QT-compatible point defects in SiC is performed on the 4H polytype, primarily due its mature growth techniques and commercial availability. However, other polytypes of SiC can host similar, or even preferable, colour centres for quantum applications, although this is a far less studied field. A structurally similar polytype to 4H-SiC is the 6H-SiC which shares the same lattice structure, but with two more stacking layers per stacking sequence. The same point defects in 4H-SiC exist in the 6H polytype, however the additional stacking layers means that each defect can exist in more inequivalent configurations than what is possible in 4H-SiC. This increases the potential for selectivity in applications which are highly dependent on the emission wavelength of the defect, as the 6H polytype provides a wider range of alternatives. In addition, the ability to shift wavelengths via e.g. Stark effect and strain is less studied in 6H- than in 4H-SiC, and it is possible that defects in 6H are more susceptible to these kinds of perturbation due to the slightly more complex lattice structure. A body of work exist on the electrical identification of defects in 6H-SiC using deep level transient spectroscopy (DLTS), but with conflicting identification of multiple peaks. In addition, the DLTS-spectrum of 6H-SiC shows almost twice as many signatures as what is normally observed in 4H-SiC, further complicating the understanding. In this work we investigate the origin of DLTS-peaks in 6H-SiC. We employ a 6H-SiC material grown epitaxially with two different carrier concentrations, 5x1014 cm-3 and 1.5x1016 cm-3, and compare their DLTS-spectrum to that of 4H-SiC grown under the exact same conditions. The samples are then subjected to different proton irradiation and annealing treatments such that the behaviour of already known DLTS-signatures in 4H-SiC can be compared and mapped over to the DLTS-signatures in 6H-SiC which are shown in Figure 1. The DTLS-results are also compared to our previous work on the formation and stability of quantum compatible defects in 6H-SiC using photoluminescence spectroscopy [2]. To aid identification, DFT-calculations are performed on relevant defects in 6H-SiC to find their formation energy dependence and study the charge transition levels, as shown in Figure 2. This is compared to activation energies extracted from Arrhenius plots from the DLTS-data. As a result, we present a thorough understanding of the thermodynamics of defects in 6H-SiC and attempt to identify key defects observed with DLTS. This represents an important step in the maturing of this polytype for potential application in QT. |
Aerosol-Deposited Ga₂O₃–SiC Composite Films for Enhanced Thermal Performance in Power Semiconductor Devices. PRESENTER: Hyeong-Seok Oh ABSTRACT. In recent years, power semiconductor devices have become increasingly important for efficient energy management and conversion particularly in emerging technologies such as renewable energy systems and electric vehicles. As a promising power semiconductor material, gallium oxide (Ga2O3) has gained significant attention as a next-generation material for power semiconductor applications, because of its ultra-wide bandgap (~4.8eV) and high breakdown field strength (~8MV/cm). However, its low thermal conductivity (~10–30 W/m·K) significantly limits its use in high-power systems, as excessive heat can lead to thermal breakdown and reduced device reliability. To address this issue, silicon carbide (SiC) has been widely considered as thermal management solution due to its high thermal conductivity (~300W/ m·K). Several thermal management strategies for Ga2O3 using SiC have been studied, including its integration as a substrate and the formation of heterostructures, and now Ga2O3- SiC composite structures are being considered as a promising new approach. Conventional deposition techniques such as physical vapor deposition and chemical vapor deposition often involve high temperatures and long processing times with significant costs. However, aerosol deposition (AD), a room-temperature process capable of rapidly forming thick and dense ceramic films, is simple, cost-effective, and particularly well-suited for fabricating composite structures from mixed powders. Therefore, in this study, Ga2O3-SiC composite films were fabricated using aerosol deposition (AD) with varying SiC content. The effects of SiC content on the microstructure and temperature-dependent electrical properties of the composite films were investigated. The results indicate that AD-fabricated Ga2O3-SiC composite films could provide an effective approach to improving the thermal performance of Ga2O3 based power semiconductor devices. |
Ag:AZO Electrodes Deposited by Co-sputtering Using FTS to Improve Photodetector Performance PRESENTER: Hanbi Jung ABSTRACT. As ultraviolet (UV) radiation plays a vital role in both daily life and various industrial fields, UV-C (100 - 280 nm) photodetectors, particularly those capable of detecting arc discharges, have garnered significant attention due to the increasing risk of electrical fires. To advance these devices, employing transparent conductive oxide (TCO) electrodes with high visible-range transmittance and excellent electrical conductivity is essential. In this study, a self-powered solar-blind UV-C photodetector was fabricated based on an Ag2O/β-Ga2O3 heterojunction structure, employing Ag:AZO electrodes deposited as TCO layers via Facing Targets Sputtering (FTS). The Ag:AZO electrodes were prepared by a co-sputtering method using Ag and AZO targets, with film thicknesses ranging from 20 nm to 50 nm. As a result, the fabricated Ag2O/β-Ga2O3 photodetector exhibited a high on/off current ratio of 2.01 × 108, a responsivity of 56 mA/W, and a detectivity of 6.99 × 1011 Jones, indicating its superior performance. The Ag:AZO electrodes, at a thickness of 20 nm, showed a smooth surface morphology along with excellent electrical conductivity and optical transmittance. |
Investigation of phase transition and its impact on the crystal structure and material properties of polycrystalline α/β Ga₂O₃ thin film PRESENTER: Jeong-Min Youn ABSTRACT. Gallium oxide (Ga₂O₃) is a promising ultra-wide bandgap semiconductor material with several polymorphs. Among them, the α- and β-phases have received much attention due to their distinct structural, electrical, and optical properties. The α-Ga₂O₃, a metastable phase of Ga₂O₃, has a corundum structure and a wider bandgap compared to the β-Ga₂O₃, around 5.0 - 5.3 eV. It can be grown epitaxially on isostructural sapphire (α-Al₂O₃), which is commercially available in large sizes at relatively low cost. On the other hand, the monoclinic β-Ga₂O₃, with a bandgap of 4.8 eV, is the most thermally stable phase and shows excellent breakdown field strength. In this study, Ga2O3 thin films were deposited on c-plane (0001) sapphire substrates by sol-gel process followed by post-annealing at various temperatures of 400, 450, 500, 550, 600, and 700℃ to investigate the phase transition behavior from α- to β-Ga₂O₃. The relationship between annealing temperature and structural phase transformation was systematically analyzed, and its effect on the physical properties of the films was evaluated. The characteristics of the fabricated films were evaluated using X-ray diffraction (XRD), selected area electron diffraction (SAED), X-ray photoelectron spectroscopy (XPS) and UV-Vis spectroscopy. X-ray diffraction (XRD) analysis confirmed the formation of α-Ga₂O₃ (006) phase in samples annealed between 400 °C and 700 °C, with the highest crystallinity at 500 °C. Above 550 °C, the intensity of the (006) diffraction peak decreased, while β-Ga₂O₃ (-201) plane group began to appear, indicating a phase transition, clearly evident at 700 °C. These phase transitions were further supported by SAED analysis, while XPS and UV-Vis analyses indicated corresponding variations in oxygen vacancy concentration and optical bandgap. This study demonstrated how annealing-induced phase transitions influence the structural and material properties of Ga₂O₃ thin films. |
Low-pressure Mist-CVD technique for Sn-assisted epitaxial growth of high-crystallinity κ/ε-Ga₂O₃ PRESENTER: Yan Wang ABSTRACT. The orthorhombic ε-phase (commonly referred to as κ-Ga₂O₃ or ε-Ga₂O₃, hereafter denoted as ε-Ga₂O₃ in this work) of Ga₂O₃ has emerged as a groundbreaking ultrawide-bandgap material for high-power electronic devices due to its exceptional properties. With a large spontaneous polarization of ~25µC/cm², a high piezoelectric constant (d33 ≈ 10.8–11.2 pm/V), and a high dielectric constant of ~32, ε-Ga₂O₃ is ideally suited for applications such as high electron mobility transistors (HEMTs), radio frequency resonators, and advanced gate architectures [1-3]. These characteristics position it as a frontrunner in the development of next-generation semiconductor technologies. Despite its potential, synthesizing high-quality ε-Ga₂O₃ films remains a significant challenge. Conventional epitaxial techniques like MOCVD, ALD, and HVPE often struggle with high-cost，interfacial transition layers and poor thickness control (in HVPE).These limitations have hindered the material’s transition from research to industrial-scale applications. To address these issues, we developed a novel low-pressure mist chemical vapor deposition(LP-Mist-CVD) method，this is also the first low-pressure attempt in Mist-CVD system. This approach combines Sn-mediated nucleation with optimized low-pressure conditions to achieve unprecedented control over film growth. Our LP-Mist-CVD process has yielded ε-Ga₂O₃ films on c-plane sapphire substrates with record crystallinity, as evidenced by an XRD rocking curve FWHM of 0.08°(Fig. 1) — the narrowest reported to date. The films also exhibit atomically smooth surfaces, with a root mean square (RMS) roughness of 1.51 nm (Fig. 2). Key advancements include the true layer-by-layer deposition (Fig.2), complete suppression of interfacial layers (Fig. 3), and precise thickness control at a rate of 60 nm/h (Fig. 3). Additionally, the technique’s cost-effectiveness and compatibility with in situ elemental doping make it highly adaptable for industrial use. These metrics surpass those achieved by traditional epitaxial methods, highlighting the technique’s superior precision and reproducibility. While sapphire substrates currently serve as the growth platform, 4H-SiC could further enhance film quality due to its smaller lattice mismatch with ε-Ga₂O₃. Our preliminary experiments on 4H-SiC substrates show reduced defect densities, though stabilizing the ε-phase requires further optimization of epitaxial parameters. By capitalizing on SiC’s superior thermal conductivity, reduced lattice mismatch, and high carrier mobility, this ε-Ga₂O₃/4H-SiC heterostructure platform not only stabilizes the metastable ε-phase but also enhances interfacial coherence and strain management，enabling devices with lower dislocation densities, improved breakdown fields, and enhanced thermal dissipation. This dual innovation—advanced growth technology paired with optimized substrate engineering—propels ε-Ga₂O₃/SiC toward realizing its full potential in ultrahigh-frequency power electronics, radiation-hardened sensors, and quantum well architectures. As we refine epitaxial technique and heterointerface design, the ε-Ga₂O₃/SiC system is poised to set new benchmarks for efficiency and reliability in next-generation semiconductor platforms. |
Impact of Socket and Current Shunt on Switching Characteristics of GaN HEMTs PRESENTER: Yeonwoo Seo ABSTRACT. GaN HEMT(Gallium-Nitride High Electron Mobility Transistor) is an emerging wide-bandgap device with high-speed switching, low power loss, and compact package design [1]. The fast switching characteristics significantly cause unwanted overshoots and oscillations during turn-on and turn-off transients [2]. This causes electrical stress on the device, increases switching losses, and contributes to high-frequency electromagnetic interference (EMI) problems [2]. Therefore, minimizing parasitic inductance in the switching platform is critical for achieving optimal performance. Several strategies can be employed to reduce parasitic inductance, including optimized device connection methods and current shunt structure design. For instance, surface-mounted lead-free packages are commonly used to minimize parasitic inductance and fully utilize GaN HEMTs' performance [3]. However, directly soldering the lead-free packaged device onto the PCB for the Double Pulse Test resulted in inefficiency due to the need for repeated soldering and desoldering for each measurement. To address this, a socket was introduced to contact the device to the PCB without soldering. However, the parasitic inductance exists in the socket. Therefore, it is crucial to use a socket with low parasitic inductance to enhance the accuracy and reliability of evaluating the device’s dynamic characteristics. In addition to the socket types, the structure of the current shunt used for current measurement also significantly affects the overall parasitic inductance of the system. Two types of current shunts were considered in this study: a leaded shunt, which introduces an additional loop due to its extended legs, and a screw-type shunt that provides a more compact current path. The difference in the current loop between these two structures results in varying levels of parasitic inductance. This study investigates the impact of both the socket type and the current shunt structure on the switching characteristics of GaN HEMTs. A 650 V E-mode GaN HEMT manufactured by GaN Systems with an 8-by-8 mm PDFN package was used. Two switching platforms were evaluated using the Double Pulse Test with an identical PCB layout: one using an interposer socket with a leaded-type shunt, and the other using a direct press socket with a screw-type shunt. The comparison of the energy losses and the rise/fall time revealed that the direct press socket with the screw-type shunt effectively reduced the parasitic inductance. As a result, oscillations in voltage and current waveforms were reduced, and the lower switching losses were observed. This study highlights the importance of the socket and current shunt selection for the precise characterization of the high-speed GaN HEMT devices. |
Application of ALD-derived Hf₀.₂₅Al₀.₇₅O-based as Gate Dielectric in AlGaN/GaN High Electron Mobility Transistor PRESENTER: Chun-Yu Lin ABSTRACT. Gallium Nitride (GaN) has a wide bandgap, which enables operation at high voltages and high temperatures. The wide bandgap allows for reduced leakage currents and improved device reliability, making it ideal for high-power and high-temperature applications.Atomic Layer Deposition (ALD) technology fine-tunes the ratio of these oxides, ensuring uniform growth and precise control. This method effectively reduces leakage currents and improves the transistor's switching speed and overall performance. This study demonstrates that using Hf0.25Al0.75O as the gate dielectric effectively improves the electrical performance of HEMTs by reducing leakage current, enhancing the ION/IOFF ratio, and improving interface quality. These results confirm the potential of Hf0.25Al0.75O for high-performance HEMT applications. |
Growth and Properties of SiGe - AlN Core-Shell Crystals PRESENTER: Eunmin Kwon ABSTRACT. Si and Ge materials exhibit high potential for application in the fabrication of semiconductor devices, solar cells, and light-emitting devices. Especially, SiGe semiconductor shows an indirect bandgap in the natural cubic phase and a direct or quasi-direct bandgap in the hexagonal phase. Several studies on the theoretical interpretation of direct-bandgap structures and the growth of nanoscale hexagonal SiGe has opened new frontiers in the design and development of next-generation high-speed electronic and optoelectronic devices [1]. In this study, SiGe-AlN core-shell crystals were synthesized via the formation of SiGe droplets on Al-based nano-absorbers based on the Plateau–Rayleigh instability (PRI), which is similar to the formation of dewdrops on spider webs [2]. Herein we propose the growth of nanoscale to microscale semiconductors by employing a new strategy involving a unique nanomaterial-based phenomenon. The results of this study indicate that the occurrence of PRI, a natural phenomenon similar to the arrangement of dewdrops on a spider web, in the nanoscale facilitates microscale crystal growth. In this study, microscale SiGe-AlN core-shell crystals were grown by the formation of a nanoscale elliptical Al membrane, followed by the adsorption of random materials onto the membrane to form droplets that functioned as a source material for the crystal-growth process. By employing the mixed-source HVPE method, Al-based nano-absorbers were derived from AlCl and NH3 at a high growth temperature of 1250 ℃; Al membranes were also derived from NH3 and AlCl. Subsequently, elliptical Al membranes were formed by PRI, which absorbed GeCln or SiCln to form droplets. The droplets inside wurtzite-structure Al-based nano-absorbers grew into fully formed core-shell crystals. Unlike the typically observed core-shell formation process, the growth process of core-shell crystals in this study involved shell formation followed by core filling. The diameter of the droplets of core-shell crystals that separate from Al-based nano-absorbers after reaching a specific weight is estimated to be >20 μm. Although the length of such core-shell crystals varies with the amount of HCl used, it is typically below 300 μm. The Raman spectral properties of the fully grown SiGe-AlN core-shell crystals differ from those of cubic SiGe [3]. The as-prepared samples, which possibly exhibit the characteristics of 2H-SiGe semiconductor, are expected to exhibit direct bandgap properties; therefore, they could facilitate the development of next-generation high-speed electronic and optoelectronic devices. This work was supported by the Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Korea government (MOTIE) (RS-2022-00154720, Technology Innovation Program Development of next-generation power semiconductor based on Si-on-SiC structure). [1] E.M.T. Fadaly, A. Dijkstra, J.R. Suckert, D. Ziss, M.A.J. v. Tilburg, C. Mao, Y. Ren, V.T. v. Lange, S. Kölling, M. A. Verheijen, D. Busse, C. Rödl, J. Furthmüller, F. Bechstedt, J. Stangl, J. J. Finley, S. Botti, J.E.M. Haverkort, E.P.A.M. Bakkers, Nature 580, 205–209 (2020). [2] Y Zheng, H Bai, Z Huang, X Tian, FQ Nie, Y Zhao, J Zhai, L Jiang, Nature 463, 640-643 (2010). [3] D. de Matteis, M. De Luca, E. Fadaly, M. Verheijen, M. López-Suárez, R. Rurali, E. Bakkers, I. Zardo, ACS Nano 14, 6845−6856 (2020). |
Si Layer Formation on SiC Substrates by HVPE Sublimation Sandwich Method PRESENTER: Donghyeon Jeong ABSTRACT. Silicon carbide (SiC) has attracted attention as the most important material for high-temperature, high-power, high-frequency, and low-loss device applications owing to its wide energy bandgap, high-breakdown voltage, and high-thermal conductivity properties [1]. The sublimation sandwich method allows the independent adjustment of three critical process parameters, namely the substrate temperature, temperature difference between the substrate and source wafer, and the temperature of the material source that provides the atmosphere within the reaction chamber. The most significant feature is the short distance between the source and the wafer. Consequently, the mechanism of element transfer from the source wafer to the substrate can be controlled effectively. The combination of Si and SiC has many potential applications in electronic and optoelectronic fields. The technology used to grow high-quality Si epilayers on a SiC substrate is emerging as a very important one because of the combination of Si technology and SiC, a wide bandgap material [2]. In this study, the HVPE method was improved by placing a mixture of metals to be grown in the source area of the boat, separating the source and growth areas vertically, and reacting all sources with HCl simultaneously in one temperature area. In addition, an Si layer was formed by applying an advanced sublimation sandwich method, in which the Si layer deposited by sputtering was placed in contact with the two substrates (without any space between them) to prevent damage from the effects of high temperature and HCl. The internal pressure was increased through a graphite boat structure in which the source zone and the growth zone were arranged vertically. The sublimation sandwich method was improved by overlapping the two substrates, and the recrystallization process of crystals by supersaturation was executed. SiCln was used as the source to grow the Si layer through the chemical influences of HCl, NH3, AlCl, and GaCl3 at a temperature of 1250 °C. The reaction between the sputtered Si layer and the newly introduced SiCln source was induced within a very narrow space, maintaining saturation in a supersaturated state to grow new crystals. The growth of a recrystallized Si epilayer, which was different from the Si layer deposited via sputtering, was confirmed. FE-SEM analysis revealed the formation of a new layer with an increase in the grain size, which was completely different from the heat treatment effect of the Si sputtering layer. Based on the XRD analysis, the peak of Si in the crystal was confirmed, and an Si 2p peak was observed in the XPS analysis. These results suggest that Si layers of various sizes can be formed using the advanced HVPE sublimation sandwich method. This is another new method that can be used to grow Si layers on SiC substrates easily. We also expect that the advanced HVPE sublimation sandwich method can form recrystalline layers of other materials, such as AlN and GaN, regardless of the size and type of the substrate. Therefore, the advanced HVPE sublimation sandwich method can be proposed as a new method for growing layers on heterogeneous substrates, and this is considered to be significant compared to conventional methods. This work was supported by the Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Korean government (MOTIE) (RS-2022-00154720, Technology Innovation Program Development of next-generation power semiconductor based on Si-on-SiC structure). [1] J.G. Kassakian, T.M. Johns, IEEE, J. Emerg. Sel. Top. Power Electron. 1, 47 (2013). [2] K. Tachiki, M. Kaneko, T. Kimoto, Appl. Phys. Express 14, 031001 (2021). |
Optical characterization of doping-induced defects in n-type 4H-SiC PRESENTER: Aurora Teien ABSTRACT. Phosphorous (P) and nitrogen (N) are common dopants used to make n-type silicon carbide (SiC) [1], which is important for high-frequency and high-power applications. However, the doping process can result in the formation of native and impurity related defects and defect complexes. These defects may be detrimental in electrical devices or favorably employed as color centers for quantum technology (QT) applications. In this work, P- and N-implanted 4H-SiC samples fabricated with different implantation and annealing steps are investigated using photoluminescence (PL) spectroscopy. The samples used in this work are of n-type 4H-SiC with a 30 µm epitaxial layer and free carrier concentration of 2.8×1015 cm-3 as measured by CV. The epi-layers have been grown on highly doped n-type 4H-SiC substrates with carrier densities of ∼8×1018 cm−3 and are purchased from CREE/Wolfspeed. The following processing steps have been chosen to optimize dopant-related defect formation [2, 3]. SRIM-simulations [4] were used to predict the projected range of the ions into the substrate. Two different types of samples were created. In sample set 1, only one implantation series of the dopant in question (either N or P) was performed with varying fluences, followed by a subsequent anneal at 1000 °C for 30 min. The N-implantations were performed at energy 300 keV, and P-implantation at 500 keV. Sample set 2 has a two-stage processing procedure. The initial stage involved making a box-profile of dopants of depth 400 nm and concentration 1×1018 cm-3. After the creation of the box-profile, an activation anneal at 1700 °C for 30 min was performed for the dopants to occupy native SiC lattice sites. In the second stage of the processing, the samples were irradiated with high energy (1.8 MeV) helium (He) of varying fluences to form intrinsic native defects, before a final anneal at 1100 °C for 1 h was performed to enable defect migration and subsequent complex formation. Samples from sample set 1 are labeled N1-3 and P1-3, see overview in Table I, and samples from set 2 are labeled NB1-3 and PB1-3. PL measurements in the UV-visible region were performed using an iHR320 imaging spectrometer with a H10330C-75 photomultiplier tube. The samples were cooled down to cryogenic temperatures (8-13 K) using a closed-cycle He refrigerator system (CCS-450 Janis Research, Inc.) and excited using a 405 nm continuous wave (cw) laser. High resolution (HR) PL has been used for inspecting ∼30 nm sized windows of central wavelengths from 800 nm to 1000 nm. PL trends for different He fluences in sample set 1 have been investigated in Fig. 1 for an unknown defect of wavelength 884 nm named O2 herein. Additionally, PL spectra of samples PB1 and NB1 from sample set 2 for UV wavelengths of range 800-1000 nm are shown in Fig. 2. Interestingly, unidentified defect signatures appear in the PL spectra that are not present in reference samples not exposed to He-implantation (not shown). The most prominent unknown peaks and their energies are listed in Table II. The unknown defects seem to be unrelated to the different implanted ions as the peaks are consistent for both samples. Thus, the defects are assumed to be intrinsic. Further work will include inspecting the different sample sets with PL in the infra-red (IR) regime with wavelengths ranging from 1000 nm – 1600 nm to reveal additional differences and similarities between the different types of dopants and implantation profiles. Other processing details such as additional annealing steps or different annealing times and temperatures will also be explored. [1] Bockstedte, M., Mattausch, A., & Pankratov, O. (2004). Applied Physics Letters, 85(1), 58–60. [2] Lemva Ousdal, E. et al. (2024). Journal of Applied Physics, 135(22), 225701. [3] Bathen, M. E. et al. (2018). Materials Science Forum 924, 200–203. [4] Ziegler, J. F., Ziegler, M. & Biersack, J. (2010). Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms 268, 1818– 1823. |
Towards High-Efficiency Photonic Interfaces for Colour Centres in Silicon Carbide PRESENTER: Nien-Hsuan Lee ABSTRACT. Colour centres in solid-state materials can implement key building blocks for scalable quantum communication networks, providing both robust spin and stable optical properties. Among these, divacancy (VV) centres in silicon carbide (SiC) are particularly promising. Their spin-optical properties mimic the ones of the leading nitrogen-vacancy centre in diamond, including extremely long coherence times in the minute range [1]. And the SiC material makes this platform compatible with standard semiconductor manufacturing processes. However, colour centres share a major challenge of all solid-state quantum systems: the limited optical collection efficiency, especially when attempting to couple the emitted photons into optical fibres for long-distance communication. Various approaches have demonstrated to enhance the light collection efficiency, including nanopillar structures [2], solid immersion lenses (SIL) [3-4], triangular waveguides [5-6], and cavities integrated on waveguides [7-8]. While waveguide-based structures offer – in principle – the highest light collection efficiencies, their nanofabrication comes along with several challenges: inevitable imperfections, such as surface and sidewall roughness are a major source of optical scattering loss [9], which reduces the overall efficiency. Besides this, the rather popular free-standing triangular waveguides fabricated via reactive ion etching under a Faraday cage often suffer from low reproducibility across different fabrication runs, limiting their scalability. In this work, we present a systematic investigation on SiC photonic waveguide fabrication using reactive ion etching processes aimed at optimising photonic structures for VV centres in SiC. We explore a wide range of fabrication parameters, including the use of metallic and non-metallic etch masks, variations in plasma chemistries, as well as different etching strategies to reduce surface and sidewall roughness while improving process reproducibility. Structural and optical characterisation of the resulting waveguides will be presented, aiming at identifying the critical parameters for high-efficiency photon transmission. While this study is performed on bulk SiC substrates, the developed fabrication techniques can be translated to the recently established quantum SiC-on-insulator platform [10]. In summary, our work provides an important step forward towards maximising the optical efficiency of SiC nanophotonics, which will have a significant impact in the quest towards quantum applications based on spin-photon interfaces. |
Impact of oxidation temperature on the formation and annihilation of color centers at SiO₂/SiC interfaces PRESENTER: Yu Kaneko ABSTRACT. Optically active point defects (i.e., color centers) in semiconductors are a key element in quantum applications such as quantum communication and sensing. SiC is attractive as a host for color centers due to its wide bandgap and mature process technologies. Point defects such as V_Si and V_CV_Si have been reported as color centers in SiC. In addition to these bulk defects, color centers of extremely high brightness have been reported at the SiO_2/SiC interface. Nevertheless, the origin of interface color center is not yet clarified. In the present study, we investigated the formation and annihilation processes of interface color centers in a wide temperature range to provide a clue to their origin. |
Generation of Divacancy Colour Centres in 4H-Silicon Carbide for Quantum Nanophotonics with Optically Active Spins PRESENTER: Leonard K.S. Zimmermann ABSTRACT. Colour centres acting as optically active spins in a solid-state matrix have emerged as excellent systems for quantum technologies. While much of the traditional groundwork has been accomplished with diamond colour centres, there are now challenges in terms of upscaling: the diamond substrates are very costly, limited in availability, and incompatible with existing semiconductor manufacturing. Recently, silicon carbide (SiC) has emerged as a promising colour centre platform, offering the opportunity to leverage industrial processing for the development of scalable quantum systems based on nanophotonics and nanoelectronics [1]. A well-studied colour centre in SiC is the silicon vacancy (VSi) in 4H-SiC, which holds exciting potential in quantum sensing [2], with impressive demonstrations showing coherent spin-photon interfacing, as well as integration into nanophotonic and electronic devices [3]. Another promising colour centre is the divacancy (VSiVC) holding the current records for qubit control related to quantum computing and quantum memories, including reasonable performance even at room temperature [4, 5]. To unlock the ultimate scalability potential of SiC colour centres, two steps are instrumental: (1) Integration into nanophotonic circuits to maximise the optical efficiency [3]. (2) Implementation of post-fabrication electric tuning mechanisms to enhance spin-optical coherence times, e.g., as offered by integration in p-i-n diode structures [6,7]. Both steps require sub-micron three-dimensional positioning control of colour centres within these electro-optical devices. Initial studies have indicated that this can be achieved based on ion implantation to create vacancies (VSi and VSiVC) [8], followed by thermal annealing to repair some of the unwanted collateral damage to the crystal lattice [9]. However, there appears to be a large variability in spin-optical quantum coherence properties between different implantation parameters. Here we present our initial results from an ongoing in-depth implantation-annealing study for the generation of VSiVC colour centres in 4H-SiC. Our studies include the implantation of various ion species with different atomic masses, i.e. He, CO, N2, Ar, Sn and Bi at implantation doses from single ions to several hundred ions. This provides an overview of the ratio between colour centre generation yield and collateral crystal damage. We also investigate the influence of different thermal annealing processes, including standard thermal annealing and rapid thermal annealing. We summarise the single-emitter yield and show basic spin coherence measurements for the different implantation-annealing methods. Our study represents an important step toward a comprehensive guide to the optimum generation conditions for VSiVC colour centres in 4H-SiC, which are a promising platform for quantum applications. |
The Impact of Pre-Growth Treatment of Si- and C-face 4H-SiC Substrates on the Heteroepitaxial Growth of β-Ga₂O₃ by Plasma-Assisted Molecular-Beam Epitaxy PRESENTER: Raouf Hayyak ABSTRACT. β-Ga₂O₃ is regarded as a representative of the new generation of ultrawide energy gap (UWEG) semiconductors in electrical devices due to its strong breakdown electric field ranging from 6-8 MV/cm, which is three times greater than the corresponding values of SiC and GaN [1]. However, the low thermal conductivity (11-27 Wm-1k-1) of β-Ga₂O₃ compared to GaN (253 Wm-1k-1) and SiC (370 Wm-1k-1) makes it a challenging material for thermal management in β-Ga₂O₃ power devices, which produce heat, leading to a rise in the lattice temperature [2-4]. It causes devices to degrade faster at high powers, limiting their performance. Therefore, it is crucial to have precise substrate temperature control. One approach to overcome this challenge and enhance the performance of high-temperature Ga₂O₃-based devices is introducing ∆a=40 off-oriented (000±1) 4H-SiC as a wide energy gap and superior growth substrate candidate for heteroepitaxial growth of β-Ga₂O₃ due to its excellent thermal conductivity and small lattice mismatch for high-quality epitaxial films [5]. In this context, we present the growth and characterization of (-201) β-Ga₂O₃ epitaxial films on Si- and C-face 4H-SiC substrates with ∆a=40 off-oriented by plasma-assisted molecular beam epitaxy (PAMBE). Initially, the PAMBE growth parameters were optimized on non-off-oriented sapphire substrates and then employed those for the growth of β-Ga₂O₃ on off-oriented 4H-SiC substrates. Pre-growth surface treatments of 4H-SiC substrates by employing: (i) Ga exposure, (ii) unintentional oxygen exposure, and (iii) Ga flash-off process followed by Ga exposure prior to the β-Ga₂O₃ growth. Growth behaviors, as assessed by reflection high-energy electron diffraction (RHEED) and surface morphological features by atomic force microscopy (AFM) were studied. The (i) Ga exposure and (iii) Ga flash-off process, followed by Ga exposure, resulted in well-ordered Si-face 4H-SiC substrates, likely due to morphological modification and suppression of SiOx (or delaying SiOx) formation. The grown β-Ga₂O₃ films resulted in enhanced surface morphology and crystallite quality of films. However, the (ii) unintentional oxygen exposure caused the formation oxide layer on the Si-face 4H-SiC substrate, which caused the uncontrolled disordered nucleation and growth due to the restricts in Ga and oxygen atoms mobility. In contrast, growth β-Ga₂O₃ on the C-face 4H-SiC substrates, the crystallinity, surface morphology, and uniformity of β-Ga₂O₃ films are much improved compared to the growth β-Ga₂O₃ on the Si-face. This is likely because the C-face is being less prone to forming a stable oxide layer at high temperature, resulting in better nucleation and crystallinity, surface morphology, and dense films. In conclusion, the crystallinity and surface morphology of β-Ga₂O₃ films are strongly affected by pre-growth surface treatments and substrate polarity of 4H-SiC substrates in PAMBE. In addition, we noted that introducing the off-oriented substrates causes an increasingly high density of dangling bonds on the surface, resulting in kink positions (step edges) being ideal sites for Ga adatom incorporation and in enhancing the crystallinity and morphology structure of the β-Ga₂O₃ epitaxial films. This research was supported by National Research Foundation of Korea (NRF) (grant No. 2020R1I1A3073787). [1] M. Higashiwaki, K. Sasaki, H. Murakami, Y. Kumagai, A. Koukitu, A. Kuramata, T. Masui, and S. Yamakoshi, Semicond Sci Technol 31, (2016) [2] H. Shibata, Y. Waseda, H. Ohta, K. Kiyomi, K. Shimoyama, K. Fujito, H. Nagaoka, Y. Kagamitani, R. Simura, and T. Fukuda, Mater Trans 48, 2782 (2007). [3] Z. Guo, A. Verma, X. Wu, F. Sun, A. Hickman, T. Masui, A. Kuramata, M. Higashiwaki, D. Jena, and T. Luo, Appl Phys Lett 106, (2015). [4] M.D. Santia, N. Tandon, and J.D. Albrecht, Appl Phys Lett 107, (2015). [5] S.A.O. Russell, A. Perez-Tomas, C.F. McConville, C.A. Fisher, D.P. Hamilton, P.A. Mawby, and M.R. Jennings, IEEE Journal of the Electron Devices Society 5, 256 (2017). |
Coherent Control and Narrow-Linewidth Spectroscopy of a Four-Level Silicon Vacancy Spin in Silicon Carbide PRESENTER: Seung-Jae Hwang ABSTRACT. Spin-photon interfaces are key components for next-generation quantum technologies, including quantum communication and distributed quantum computing [1]. Spins can act as stable quantum memories thanks to their long coherence times, while photons enable long-distance information transfer through optical networks. Establishing a reliable and scalable spin-photon interface is therefore crucial for constructing quantum-repeater networks and distributed quantum processors. Among various platforms, point defects in silicon carbide (SiC) have emerged as promising candidates. They offer excellent spin coherence, bright photoluminescence, and compatibility with mature semiconductor fabrication technologies, making them well-suited for scalable quantum devices [3]. In particular, silicon-vacancy-related defects in 4H-SiC, such as the V1 center, have attracted significant attention because of their robust spin and optical characteristics [2]. The V1 center exhibits a spin-3/2 ground state and allows spin-selective optical transitions under resonant excitation. These properties make it an excellent platform for studying spin-photon interfaces in the solid state. In this study, we report the construction of an experimental setup for demonstrating a spin-photon interface based on the V1 center in 4H-SiC. Our setup consists of a cryogenic confocal microscope operating at 5 K, equipped with a high-NA objective for efficient light collection. Resonant excitation is provided by a tunable narrow-linewidth laser, and spin manipulation is achieved with a broadband microwave antenna placed over the sample. Photoluminescence-excitation (PLE) measurements reveal two distinct narrow peaks associated with spin-selective optical transitions, enabling resonant addressing of the desired spin state (Fig. 1). We also apply spin-resonant MW pulses to control the spin populations and measure spin-dependent variations in photon-emission intensity. Using our refined cryogenic confocal setup, we achieved photoluminescence excitation spectroscopy with a full width at half maximum (FWHM) below 100 MHz. This spectral resolution enables high-contrast Ramsey interferometry measurements of spin dephasing time (T₂*) exceeding 20 μs under certain conditions at 5 K in isotopically purified 4H-²⁸Si¹²C samples (Fig. 2). These results demonstrate high-contrast, spin-state-dependent photon emission from single V1 centers and establish the essential toolkit of narrow resonant spectroscopy, coherent microwave control, and low-temperature stability for forthcoming work. Building on this platform, we will investigate universal control of the full four-level manifold, quantify how restricting the system to an effective two-level qubit impacts gate fidelity and read-out contrast, and carry out a systematic study of coherence under various experimental conditions. Preliminary results on ququart manipulation and environment-dependent coherence will be presented at the conference. |
Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs Under Heavy-Ion Irradiation PRESENTER: Zhiwen Zhang ABSTRACT. The next generation of aerospace power systems demands higher efficiency power technologies to achieve lower system costs and enhanced performance. Silicon carbide (SiC) power devices, owing to their superior material properties—including a wide bandgap, high ionization energy, and high defect formation energy [1]—are considered to possess inherent radiation resistance. However, experimental studies have shown that the single-event effect (SEE) tolerance of SiC MOSFETs falls far short of expectations: single-event burnout (SEB) and single-event leakage current (SELC) can occur at blocking voltages exceeding just 30% of the rated voltage [2-3], while single-event gate leakage degradation (SEGLD) has been observed at blocking voltages as low as 10% of the rated value. These vulnerabilities significantly limit the application of SiC MOSFETs in aerospace environments. In recent years, significant progress has been made in understanding the mechanisms of heavy-ion irradiation effects on SiC power devices. In this study, 1200V SiC VDMOSFETs developed in-house were subjected to heavy-ion irradiation using Ta ions with a LET value of 75 MeV·cm²/mg at the Institute of Modern Physics, Lanzhou. The TO-254 packaged devices under test (DUTs) were decapsulated to minimize energy loss of the incident ions. Real-time monitoring of the gate current and drain current, combined with post-irradiation electrical characterization—including gate characteristics, blocking characteristics, and transfer characteristics—as well as focused ion beam (FIB) analysis, was conducted to systematically investigate the single-event damage modes of SiC MOSFETs under various bias conditions. The experimental results reveal a clear evolution of failure behaviors with increasing bias voltage, sequentially exhibiting no significant changes, single-event gate leakage degradation (SEGLD), single-event leakage current degradation (SELC, including Id=Ig and Id>Ig modes), and finally SEB. Specifically, under a bias of 100V, SEGLD was observed, characterized by a significant increase in gate leakage current after irradiation while the threshold voltage remained stable. FIB analysis revealed approximately 1 μm deep fractures in the gate oxide located at the center of the JFET region [4]. When the bias was raised to 300V, the device entered the Id=Ig mode of SELC, with the gate oxide fracture depth increasing to 2 μm and the breakdown voltage decreasing to 500V. Under a 400V bias, the device exhibited the Id>Ig mode of SELC, with cracks extending 3.5 μm deep into the P+ source region, accompanied by source metal melting, and the breakdown voltage further degraded to 250V. At a bias of 500V, SEB occurred, resulting in catastrophic damage exceeding 14 μm in depth and complete device failure [5]. It is noteworthy that, although the gate and breakdown characteristics continuously deteriorate during the degradation process, the device threshold voltage remains stable throughout [6]. This indicates that damage to a limited number of unit cells has a relatively minor impact on the overall threshold voltage characteristics. These findings provide critical experimental evidence for a deeper understanding of the radiation damage mechanisms in SiC MOSFETs and offer valuable guidance for the design of radiation-hardened devices. [1] X. She, IEEE Transactions on industrial Electron. vol. 64, no. 10, pp. 8193-8205, Oct. 2017, [2] D. R. Ball, IEEE Transactions on Nuclear Science, vol. 66, no. 1, pp. 337-343, Jan. 2019. [3] J. -M. Lauenstein, IEEE International Reliability Physics Symposium (IRPS), pp. 1-8, Mar. 2021 [4] Leshan Qiu, IEEE Transactions on Electron Devices, vol. 71, no. 4, pp. 2524-2529, Apr. 2024. [5] Chao Peng, IET Power Electronics, no. 14, pp. 1700-1712, 2021. [6] Qifei Yuan, IEEE Transactions on Nuclear Science, Early Access, 2025. |
Experimental study of Single-Event Irradiation Hardness of 4H-SiC Power MOSFET with Trench Well and Corner P-Pillar PRESENTER: Keyu Liu ABSTRACT. Silicon carbide (SiC) power devices have excellent electrical and thermal properties, such as higher power density, higher thermal conductivity, and wider operation temperature than silicon-based devices [1]. Therefore, SiC has great potential in aerospace and aviation power electronic applications. Although SiC materials have strong radiation resistance, it has been found that SiC power devices are susceptible to heavy-ion irradiation, including leakage current degradation (SELC) and single-event burnout (SEB). Single-event leakage current (SELC) at a lower bias voltage (lower than 30% of the rated voltage) than single-event burnout (SEB) has been found in SiC MOSFET [2], which is not found in Si MOSFET. Jiang Lu et al. [3] proposed the varied buffer layer designs to reduce the electric field peak in the planar MOSFETs and proposed the widened split gate designs to suppress the influence of the parasitic transistor in the trench MOSFETs. Most investigations into the single-event irradiation hardening designs evaluation and underlying failure mechanisms are focused on numerical simulated performance based on TACD [4]. However, there is still a lack of sufficient research on how to enhance the single-event leakage current of SiC devices by the heavy ion irradiation experiment results. Therefore, it is worthwhile to study how to protect the sensitive area and raise the SELC thresholds of SiC MOSFET. In this work, 4H-SiC power MOSFET with Trench Well and Corner P-Pillar (TWCP-MOSFET) is proposed and fabricated. Fig. 1 shows the schematic cross-section, the FIB&SEM cross-sectional images, and layout structure views of 4H-SiC Conventional MOSFET (C-MOSFET) and TWCP-MOSFET. It can be seen that the structure of the TWCP-MOSFET is essentially the same as that of the C-MOSFET, except by increasing N&P-well depth and the P-pillars at P-well corners. This demonstrates that the TWCP-MOSFET process has a very high process compatibility with conventional processes. The TWCP structure could modulate the N-well and P-well corner electric fields by increasing the well depth through trench process. For the diagonal JFET corners, TWCP structure could enhance the carrier extraction in the JFET region by introducing P+ pillars with high doping concentration. The major structural parameters of TWCP-MOSFET are shown in Table I. Fig. 2 shows the evolution of leakage currents as a function of fluence during irradiation of C-MOSFET and TWCP-MOSFET during the irradiation, and bias voltage increasing from 200 to 450 V. The heavy-ion irradiation experiments were performed at the Heavy Ion Research Facility in Lanzhou (HIRFL). The heavy ion used was 181Ta at 1.6 GeV and possessed the LET of about 83.5 MeV·cm2/mg in 4H-SiC. The experimental results indicate that TWCP-MOSFET have a higher single-event gate leakage current threshold. The single-event leakage current threshold for the TWCP-MOSFET biased is about 350 V, which is 40% higher than that of C-MOSFET. The major single-event thresholds of the two devices are shown in Table II. |
Reducing Parasitic Inductance Through Power Terminal Grouping in SiC Power Modules for EV Applications PRESENTER: Jaejin Jeon ABSTRACT. The adoption of wide bandgap (WBG) semiconductors, such as silicon carbide (SiC), has accelerated in automotive power electronics due to their superior efficiency, high-temperature tolerance, and fast switching characteristics [1]. These properties enable higher power density and system-level efficiency in electrified vehicles (xEVs), making WBG devices highly attractive for applications such as inverters and DC-DC converters [2]. However, these advantages are frequently compromised by parasitic inductance in the module packaging, which becomes increasingly problematic as switching speeds increase. Parasitic inductance causes voltage overshoot, current ringing, electromagnetic interference (EMI), and switching losses, all of which degrade system performance and reliability [3]. Therefore, effective mitigation of parasitic inductance is a critical design goal in WBG power modules. This work proposes a straightforward yet effective approach to reduce parasitic inductance in automotive-grade power modules by employing selected parallelization of power terminals. Instead of altering the internal structure of the power module, an additional positive or negative terminal is externally paralleled to the original terminal. This modified layout shortens the high-current loop and redistributes the current path, which reduces both self and mutual inductance in the switching path. Unlike more complex solutions that require complete internal redesign, the proposed method can be applied to existing module configurations with minimal structural change and cost. This makes it especially suitable for automotive applications where design constraints, reliability, and manufacturability are all critical. To evaluate the effectiveness of this strategy, both electromagnetic simulations and experimental validations were conducted on a commercial SiC power module. Finite element analysis (FEA) was used to simulate the current distribution and calculate the parasitic inductance in both the conventional and modified terminal layouts. The simulation results, shown in Fig. 1, indicate that the addition of a parallel P-terminal results in a parasitic inductance reduction of approximately 12.2%. The diagram illustrates the modified current paths and provides quantitative results for the respective configurations, confirming the reduced loop inductance due to shortened path lengths. Complementary experimental validation was carried out using a double pulse test (DPT) setup. A custom gate driver board was developed to provide a gate-source voltage of 15 V during turn-on and -10 V during turn-off, mimicking realistic operating conditions for SiC MOSFETs in xEV powertrans. The measured switching waveforms, as shown in Fig. 2, demonstrate a clear improvement in performance with the proposed terminal configuration. Specifically, the voltage overshoot across the switch during turn-off was reduced by approximately 7.1%, and the amplitude of ringing in the V_DS waveform was noticeably decreased. These results indicate not only improved efficiency, but also a reduced risk of device overstress and EMI emission which are factors that are vital in achieving automotive qualification. The advantage of this approach lies in its simplicity, scalability, and effectiveness. It does not rely on complex internal redesigns, new materials, or advanced packaging technologies. Instead, it utilizes the concept of current path control by leveraging terminal configuration. Moreover, this strategy has the potential to improve thermal performance indirectly by reducing switching loss, thereby lowering junction temperature rise and extending device lifetime. From a system integration perspective, the method is compatible with standard module footprints and can be readily implemented in multi-module systems, making it an attractive solution for automotive and industrial power conversion systems alike. In conclusion, this study presents a practical method to mitigate parasitic inductance in WBG power modules by selectively paralleling power terminals. The method is validated through both detailed simulation and hardware experimentation, showing consistent improvements in parasitic inductance, voltage overshoot, and switching waveform quality. These enhancements are particularly relevant for SiC-based power modules used in traction inverters, where high switching frequency, compactness, and reliability are essential. |
Fast Speed SiC IPM Module with Zero Voltage Gate Driving Utilizing Active Miller Clamp Function on Drive IC PRESENTER: Samuell Shin ABSTRACT. The Silicon Carbide Intelligent Power Module (SiC IPM) offers significant advantages over conventional silicon (Si) devices, including stable operation at higher junction temperatures (Tj), superior insulation, higher power density, and excellent voltage endurance, allowing for a more compact IPM design. Additionally, its low on-resistance (Rds(on)) reduces conduction losses, enhancing overall system efficiency. The capability for high-speed switching also minimizes switching losses. While the high-temperature operation, low Rds(on), and fast switching characteristics make SiC devices highly attractive for IPMs, they also present several challenges. As shown in Figure 1(a), during high-speed switching, a rapid change in the drain-source voltage (Vds) can cause a transient rise in the gate voltage (Vgs) due to the Miller capacitance (Cgd) between the gate and drain. This Miller effect can lead to an unintended turn-on of the MOSFET, which should remain off, resulting in a shoot-through current and increased losses. Furthermore, because of the extremely fast switching speed of SiC devices, they are highly sensitive to even minor gate voltage fluctuations, increasing the risk of unintended turn-on. To mitigate this issue, it is common practice to apply a negative gate voltage during turn-off to maintain a sufficiently low gate-source voltage (Vgs) and prevent malfunction. However, as depicted in Figure 1(a), in the SiC IPM configuration where both high-side and low-side SiC MOSFETs are driven by a single power supply, it is difficult to implement a negative voltage supply within the system. Therefore, in the case of a typical SiC IPM (Intelligent Power Module) that employs a single power supply, unintended turn-on events may occur due to the Miller effect. In addition, to prevent such issues caused by the Miller capacitance in advance, the gate resistance (Rg) must be set sufficiently high. However, this requirement increases the switching delay, switching loss, and dead-time, thereby diminishing the inherent advantages of the SiC IPM. Figure 1(b) shows an application circuit with an Active Miller Clamp (AMC), which effectively mitigates the issues commonly observed in the conventional circuit shown in Figure 1(a). The AMC functions by preventing unintended turn-on events that may occur during the turn-off process. Specifically, during turn-off, variations in the drain-source voltage (Vds) can induce gate current through the Miller capacitance (Cgd), potentially causing the device to unintentionally turn on again. The key advantages of employing the AMC include improved immunity to the Miller effect, secure and reliable turn-off behavior, and the ability to significantly reduce the gate resistance (Rg), which otherwise needs to be large to suppress false triggering. As a result, faster switching performance can be achieved, along with reduced power losses. In this paper, we present experimental results on a SiC IPM that incorporates an Active Miller Clamp (AMC) function to address the limitations of single-supply gate drive systems, while enhancing the high-speed switching capability and power loss characteristics of SiC devices. Figure 2 illustrates the test circuit and operating sequence used for verifying the effectiveness of the AMC. Figure 3 presents experimental results related to dead-time and shoot-through behavior. Figure 3(a) shows the evaluation of turn-on loss versus dead-time, indicating that the SiC IPM with AMC exhibits more than a 50% reduction in turn-on loss compared to the version without AMC. Figure 3(b) presents the Irr (reverse recovery current) versus dead-time evaluation, demonstrating that the dead-time of the AMC-applied module is approximately 1.0 μs shorter. These results indicate that applying AMC to a SiC IPM allow the use of lower gate resistance (Rg) values, which enables the creation of SiC IPMs with fast switching and low power loss by enabling short DT and stable turn-off |
Novel 1.2kV SiC MOSFET with New Top-side Cooling Package for Automotive Applications ABSTRACT. This paper presents the new 1.2kV SiC MOSFETs employing a novel device and package technology that significantly decouples the trade-off between figure of merits (FOMs) and short-circuit withstand time (SCWT). Compared to the conventional design, the new 1.2kV SiC MOSFETs exhibit a 20% reduction in on-resistance (Rsp), a 15% improvement in SCWT, and a 45% reduction in switching losses. Furthermore, new top-side cooling pacakge offers superior thermal performance, lower parasitic iniductances, high efficiency, power density and reliability, making it ideal for a variety of automotive applications. |
Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications PRESENTER: Jang-Kwon Lim ABSTRACT. Introduction As the adoption of electric vehicles (xEVs) continues to expand, the demand for effective and energy-efficient cabin heating systems is becoming increasingly critical. Unlike internal combustion engine vehicles, BEVs do not benefit from waste engine heat and instead rely on Positive Temperature Coefficient (PTC) heaters to maintain cabin temperature. However, conventional PTC systems using silicon Insulated Gate Bipolar Transistors (Si-IGBTs) exhibit significant energy inefficiencies. These devices suffer from high conduction losses due to their inherent knee voltage characteristics and substantial switching losses caused by long tail currents during turn-off [1]. In practical usage, electric taxis in Seoul report up to a 40% drop in battery capacity utilization for heating alone during winter, reducing their effective driving range from 135 km to approximately 80 km per charge [2]. In response to these limitations, we present the development and implementation of a next-generation PTC controller based on Silicon Carbide (SiC) MOSFET technology. SiC devices offer superior performance characteristics, including significantly lower switching and conduction losses, higher breakdown voltages, and excellent thermal robustness [3, 4]. These advantages make SiC MOSFETs ideal candidates for high-frequency, high-efficiency PTC controllers tailored for xEV (electric vehicle) applications where thermal and energy constraints are vital. Engineering of SiC MOSFET Devices To improve the thermal stability of the PTC controller across operational temperatures, we analyzed the trade-off between conduction and switching losses in our 1200 V SiC MOSFETs, specifically focusing on the temperature dependencies of threshold voltage (VTH) and on-resistance (RDSon) as shown in Fig 1. As temperature increases, VTH tends to decrease, increasing the risk of false turn-on or higher leakage currents, while RDSon increases, raising conduction losses. Our devices maintained predictable trends in both parameters up to 175°C, allowing us to balance switching speed and conduction efficiency. This optimized thermal behavior minimizes total power loss under real PTC load conditions, enhancing the controller's robustness under high ambient and transient heating environments. These findings confirm that with careful device selection and thermal-aware driving strategies, SiC MOSFETs enable highly stable and efficient PTC controllers suitable for next-generation xEVs. PTC Operation Circuit Analysis Detailed circuit analysis focused on the interaction of resistive PTC loads with high parasitic capacitance under high switching frequencies, revealing several critical insights. Thermal imaging in Fig 2 and power loss analysis showed that PCB temperature increased non-linearly with switching frequency, making effective thermal management and optimized PCB layout essential for long-term reliability. Through equivalent RC modelling as shown in Fig 3, we simulated load conditions using a 150 nF capacitor and a 200 Ω resistive element. This configuration allowed quantification of transient overshoot currents, EMI behaviour, and energy loss distributions. The stored energy in the capacitor at 525 V was calculated at 21 mJ, and we determined total system losses by subtracting measured load dissipation from the simulated input energy, including DC-link capacitor contributions. The integration of 1.2 kV SiC MOSFETs into PTC heating systems led to substantial reductions in energy loss, improved thermal behavior, and more compact system designs. The results confirm the effectiveness of SiC MOSFET-based PTC controllers in achieving energy-efficient, thermally stable, and electromagnetically resilient performance suitable for next-generation xEV platforms. [1] Kim, H., et al. (2021). Performance comparison of Si IGBT and SiC MOSFET in automotive heating applications. IEEE Transactions on Power Electronics, 36(4), 4012–4023. [2] Jung, S., & Park, H. (2020). Field measurement of EV range reduction under cold climates in South Korea. Transportation Research Part D, 88, 102584. [3] Palmour, J. W., et al. (2018). Silicon carbide power MOSFETs: Breakthrough performance from 650 V to 1700 V. IEEE Transactions on Electron Devices, 65(10), 4216–4224. [4] Wang, R., & Huang, A. Q. (2019). SiC MOSFET application in electric vehicle traction systems. IEEE Transactions on Industry Applications, 55(3), 2840–2848. |
High-Density Packaging Approaches for SiC Power MOSFET Modules PRESENTER: Saeed Jahdi ABSTRACT. The advancement of silicon carbide (SiC) power devices demands innovative packaging solutions that can fully exploit their superior electrical, thermal, and switching performance. Traditional silicon-based packaging techniques often fall short in meeting the high-temperature operation, fast switching speeds, and reduced parasitics that SiC devices enable. As a result, novel packaging approaches are being developed to address these challenges. These include double-sided cooling configurations, the use of advanced substrates such as silicon nitride (Si₃N₄) and aluminum nitride (AlN) for improved thermal conductivity and mechanical reliability, and the integration of 3D packaging structures. Additionally, low-inductance interconnections using wide metal clips or embedded die technology are gaining traction, aiming to minimize loop inductance and enable high-speed switching with reduced voltage overshoot and oscillations which could have serious reliability consequences. This paper presents novel designs of SiC power MOSFET modules, coupled with finite element models which have evaluated the performance of the designs. |
Comparative Numerical Analysis of Cu Clip and Al Wire Bonding Structures in SiC Schottky Barrier Diodes PRESENTER: Na-Yeon Choi ABSTRACT. In power semiconductor packaging, aluminum (Al) wire bonding has long been the standard technology due to its low cost and proven reliability [1], but recently, new interconnect technologies such as copper (Cu) clip bonding have been gaining attention due to the increase in power density and the intensification of thermal management requirements [2]. Cu clip bonding is emerging as an alternative to overcome the thermal and electrical limitations of high power density devices by providing excellent electrical and thermal conductivity [3]. In this study, the effects of Al wire bonding and Cu clip bonding on two types of commercial SiC Schottky barrier diode (SBD) devices were quantitatively compared and evaluated through electrical, thermal, structural, and electromagnetic analyses. This enabled the analysis of the performance differences between the two technologies and the examination of the applicability of Cu clip bonding. The effects of Al wire bonding and Cu clip bonding on two commercialized SiC SBD devices (IDH06G65C6 and FFSP0465A) were analyzed using finite element analysis (FEA). The geometric data of the elements required for analysis was constructed using cross-sectioning, CT scanning, and decapsulation techniques. The electrical-thermal-structural analysis and electromagnetic analysis were conducted using ANSYS Workbench and ANSYS Q3D, respectively, utilizing the ANSYS Academic Research at the Converging Materials Core Facility of Dong-Eui University. The evaluation parameters selected included forward voltage, maximum junction temperature, power dissipation, thermal resistance, maximum stress, DC resistance, parasitic inductance, and capacitance to quantitatively compare the performance differences due to the bonding methods. In this study, two types of SiC Schottky barrier diodes (FFSP0465A, IDH0665) were used to compare the performance differences between the packaging structures of aluminum (Al) wire bonding and copper (Cu) clip bonding. In terms of electrical characteristics, Cu clip bonding reduced the forward voltage by up to 12% and also reduced power consumption by up to 12%. The DC resistance differed depending on the device, with a slight increase in FFSP0465A and a significant decrease in IDH0665. In addition, Cu clip bonding has contributed to the improvement of thermal performance by lowering the maximum junction temperature in both devices and reducing the thermal resistance in the IDH0665 device. In terms of mechanical properties, Cu clip bonding reduced the maximum stress by 42-77%, greatly improving structural stability. In terms of electromagnetic properties, the parasitic inductance was slightly reduced, but the capacitance did not show a significant difference between the two methods. These results suggest that Cu clip bonding is a technology that can ensure mechanical reliability while minimizing electrical loss and parasitic effects. In conclusion, Cu clip bonding showed overall better performance in electrical, thermal, and mechanical properties than conventional Al wire bonding. However, some items showed different trends depending on the device, so optimization is required when applying Cu clip bonding to match the device characteristics. This study suggests that Cu clip bonding can be a promising alternative in SiC SBD packages that require high power density and excellent thermal management. |
Highest efficiency and best performance for inverter motor drives in smallest form factor with new SiC MOSFET-based IPM PRESENTER: Sangmin Park ABSTRACT. As the adoption of electrification continue to raise energy demands, the need to reduce energy consumption in applications across these sectors becomes more critical. Power semiconductors capable of efficiently converting electric power are the key in this transition to a low-carbon world. onsemi introduced the first generation of its 1200V silicon carbide (SiC) metal oxide semiconductor field-effect transistor (MOSFET) based intelligent power modules (IPMs). Compared to insulated-gate bipolar transistor (IGBT) technologies, Silicon carbide (SiC) technology has many advantages. Silicon carbide (SiC) has higher switching frequencies, lower losses, better capability of handling higher junction temperature and higher current and voltage capacities. SiC based IPM deliver the highest energy efficiency, reliability and power density in the smallest form factor compare to using Si IGBT based IPM, resulting in lower total system cost than any other leading solution on the market. SiC based IPM could be an excellent alternative to Si IGBT based IPM in redesigned systems, while meeting new efficiency standards. And also, SiC based IPM can enable the use of smaller heatsinks to deliver the same thermal performances, while also enabling smaller systems overall. This paper describes the comparison result of the electrical performance between SiC based IPM and Si IGBT based IPM for inverter module in detail. |