ABSTRACT. Silicon carbide (SiC) substrates are increasingly used in power electronics due to their high thermal conductivity, wide bandgap, and high breakdown field. High-quality, large-diameter substrates are essential for improving performance and reducing manufacturing costs of SiC-based electronic devices. Coherent Corporation has commercialized n-type 150mm and 200mm SiC substrates in recent years [1]. Typical crystal defects in SiC substrates include micropipes, dislocations, stacking faults, and inclusions. In this paper, we report on our method and progress in achieving high-quality 200mm 4H n-type substrates. SiC crystals with diameters larger than 200mm are grown using a patented physical vapor transport process [1-2]. SiC source material and single crystal seed are loaded into a crucible and heated in excess of 2000°C. The temperature gradient is controlled by precise arrangement of the heating element, insulation, and the location of the source material and seed. During crystal growth, the silicon carbide source vaporizes non-congruently, and the vapor is deposited on the seed, forming a single crystal. Crystal defects typically originate from two sources: inherited from seed crystals and formed during the crystal growth process. By using Design-of-Experiment approaches, we optimized the crystal growth process to achieve minimal inclusions and stacking faults. With the optimized growth process, the dislocation density typically reduces naturally over time during crystal growth due to the annihilation of dislocation pairs with opposite Burgers vectors. Figure 1 shows total dislocation density (DD), threading screw dislocation density (TSD), and basal plane dislocation density (BPD) as a function of distance from the seed for a 4H n-type boule grown under optimized conditions. The boule was sliced into wafers, and the distance from the seed was determined from wafer thickness and kerf loss. Dislocation densities (DD, TSD, BPD) were determined by polishing the silicon face of the wafers, etching the wafers in a potassium hydroxide molten flux, and counting the etch pits of various sizes and shapes [3-4]. The dislocation density decreased dramatically in the earlier stage of growth when the initial dislocation density was high. The rate of dislocation density reduction decreased in the later stage of growth. The measured dislocation density data can be fitted nicely with the distance from the seed in a log-log fashion. Figure 2 shows the DD, TSD, and BPD as a function of distance from the seed for another crystal. The initial defect densities were lower, and the reduction of defect densities from seed to tail of the growth was also decreased; however, they still fit nicely with the distance from the seed in a log-log fashion. Another factor that impacts the quality of the grown crystal is the quality of the seed crystal. Threading screw dislocations and micropipes typically propagate from the seed to the crystal. The density of these defects will continuously decrease during growth under optimized conditions, although the rate of reduction decreases when the density is low. We have developed a manufacturing process to continuously improve 200mm 4H n-type wafer crystal quality by feeding the line with the best quality seed crystals and growing boules under optimized conditions. Figure 3 shows defect maps of recent 200mm 4H n-type wafers, indicating TSD of 78 cm-2, BPD of 88 cm-2, and MPD of 0.00 cm-2. Typical wafer shape parameters are TTV ≤5µm, bow ±5µm, warp ≤10µm, SFQR ≤ 1um for 10mmx10mm. Figure 4 shows SICA map for a recent wafer with TUA >99.5%.

ABSTRACT. Physical vapor transport (PVT) is currently the primary method used for the production of bulk SiC crystals. To grow the crystals that would satisfy current industry requirements in terms of size and quality, it is crucial to design optimal thermal fields. Since PVT is an essentially long-term process, thermal design should cover the whole duration of the growth. However, over time, inherent changes to the crystal, source, and furnace elements can have significant cumulative effect on thermal profiles. Thus, for high accuracy of thermal design, these changes should be understood and accommodated into respective design tools. Among these inherent changes, evolution of the powder charge and crystal shape have been studied previously both experimentally and with simulations. However, other notable effects such as erosion of the graphite crucible and degradation of the graphite felt insulation received much less attention. Moreover, chemical processes inside the porous walls of the crucible and felt insulation as well as associated changes of the material properties, to our knowledge, have not been simulated directly. In this work, we use modeling to get an insight into the processes experimentally observed as changes of the crucible and felt insulation. Graphite structural elements of the hot zone exposed to the high temperature of 2000-2300°C and chemically aggressive environment can undergo noticeable physical and chemical changes. For instance, it is generally acknowledged that the internal walls of the graphite crucible serve as a supplementary source of carbon, which can be beneficial for the growing crystal [1]. At the same time, accumulated material loss can cause significant damage to the crucible. Degradation of the felt insulation, in turn, can have a pronounced effect on the temperature field in the hot zone. The latter is particularly important since deviation from the optimal thermal gradients can have detrimental effect on the crystal shape, stress, and related defects. To perform conjugated simulations of the chemical reactions, heat, and mass transport inside the porous media of the insulation and the crucible walls, computational domain for the mass transport and chemical reactions was extended to include the flow in the entire reactor chamber, chemical reactions inside the graphite felt insulation and the crucible walls. In the porous media, the approach implemented in VR-PVT SiC software [2] for modeling of the powder evolution was used: solution of the heat and mass transfer problems inside the porous media was coupled with the prediction of the local phase composition, surface chemical reactions, and automatic adjustment of local porous medium properties (porosity, heat conductivity, specific interfacial surface, etc.). Simulations show that the crucible degradation is predicted to be mostly contained within thin superficial layer facing the crucible interior, see Fig. 1. In the outer felt insulation, the areas of material evaporation and SiC deposition are expected over entire insulation thickness, Fig. 2. Experimental demonstration was performed by a 200 hrs growth run in a conventional PVT furnace. The hot zone differs from the model case, but all the phenomena predicted by the simulation are observed. The internal graphite wall is etched to a certain depth, the inner surface of the outer soft felt insulation is degraded, and the region containing a solid deposit exists inside the felt (Fig. 2b). Very good qualitative agreement was demonstrated, and further experiments are planned to evaluate the level of quantitative prediction. The etching of the graphite walls of the growth chamber may alter the growth chemistry and the geometry of the crystal surroundings. The densification and erosion of the thermal insulation can have significant effect on the global thermal field through variation of insulating properties of the felt. Hence, accounting for these processes can increase the modeling accuracy, enhance the level of process control, provide valuable insight into details of the PVT process, and stimulate new directions of SiC crystal growth development.

[1] J. Liu et al., Diamond & Related Materials 15 (2006), pp. 117–120 [2] VR PVT SiC, https://str-soft.com/crystal-growth/pvt-sic/

ABSTRACT. Key aspects of physical vapor transport (PVT) growth of silicon carbide (SiC) bulk crystals are the influence of process parameters on defect formation (such as polytypes, dislocations, voids, or parasitic secondary phases), the growth rate, the C/Si ratio, and the evolution of the boule and the powder, as well as their interdependencies. Based on these fundamentals, favorable process conditions for the growth of SiC have been identified, with a particular focus on the thermal field, as it mainly determines the crystal growth and defect evolution dynamics.

While PVT simulations have been successfully employed to evaluate the suitability of new reactor designs for the growth of crystals of large size and low defect density, a key challenge remains: optimizing reactor designs and the PVT process itself. The optimization goal is to determine the optimal process parameters (e.g., power, crucible position) and reactor geometry (e.g., insulation or crucible thickness) that best meet the thermal objectives and constraints derived from the fundamentals. In this context, machine learning (ML) enables the creation of efficient surrogates that approximate simulations at a targeted accuracy while being computationally cheap. These advantages of ML-based methods allow for the exploration of a wide range of process settings and geometric configurations to identify the most suitable one.

We present an approach for reactor optimization where we build an ML surrogate trained on COMSOL Multiphysics finite element method (FEM) PVT simulations for SiC single-crystal growth. Unlike PVT optimization strategies in the literature, our work demonstrates an improved scheme to optimize temperature profiles by employing a ML model capable of generating higher-dimensional output [1-3]. This model utilizes Singular Value Decomposition (SVD) to reduce the dimensionality of the thermal profiles and fields. Specifically, SVD extracts principal component (PC) basis functions from the training dataset, and a ML model learns the dependence of each basis function’s weight on the process parameters and the reactor geometry (Fig. 1). Given the critical role of the thermal field in the optimization, the objectives include (i) the radial temperature profile/gradient along the seed, (ii) the axial temperature profile/gradient between the source and the seed, and (iii) uniform temperature distribution within the source. The optimized temperature profiles along the seed and from the source to seed for a given PVT reactor design (see Fig. 2 (c)) are shown in Fig. 2 (a) and (b), respectively.

Our framework enables efficient multi-objective optimization of the PVT reactor using a surrogate model combined with optimization algorithms such as NSGA-II. This approach is expected to accelerate the discovery of optimal reactor designs and process settings by facilitating the optimization of growth reactors regardless of the PVT furnace operation principle (resistive or inductive) or seed crystal diameter (6-inch, 8-inch, etc.).

Acknowledgement The authors gratefully acknowledge the financial support provided by the Christian Doppler Forschungsgesellschaft (CDG). The project is supported by funding from the Important Project of Common European Interest on Microelectronics (IPCEI ME) grant agreement No FO999917424bbg. The project is also supported by the Chips Joint Undertaking (JU) via the European Union’s Horizon Europe research and innovation programme and its members, including top-up funding by Austria, France, Germany, Romania, and Slovakia, under grant agreement No 101139788.

ABSTRACT. In the silicon carbide (SiC) solution growth method, a graphite crucible is typically employed to contain the silicon-based solution and simultaneously serve as a carbon source [1]. However, the use of graphite crucibles inevitably reduces the Si concentration in the solution. Additionally, the imbalance between the carbon supplied by the crucible dissolution and the carbon consumed during SiC growth can easily lead to the formation of SiC microcrystals in the solution. This in turn causes macrodefects in the grown crystals, specifically SiC inclusions. To eliminate this issue, we proposed the use of SiC liner crucibles fabricated through physical vapor transport (PVT) for SiC solution growth, successfully achieving complete suppression of SiC inclusions [2]. In addition, we introduced liquid Si infiltration (LSI) using a SiC/carbon mixed powder with fine carbon as a cost-effective method for fabricating SiC polycrystals for liners, thereby enabling the production of dense SiC [3]. In this study, we conducted the solution growth of 2-inch SiC using a SiC liner crucible fabricated by LSI. The efficacy of the LSI-SiC liner crucible as a SiC source was evaluated by comparing the results of the SiC solution growth with those obtained using alternative SiC sources. SiC powder with an average grain size of 2.3 µm and carbon black with an average grain size of 0.1 µm were mixed to obtain a carbon mole fraction of 0.67. This mixture was then formed in a crucible with an outer diameter of 120 mm through uniaxial pressing. The preform was placed in a graphite crucible filled with Si and maintained at 1450 °C for 30 min under vacuum to promote reactive Si infiltration. A Si-Cr based solvent alloy was retained in the LSI-SiC liner crucible. Solution growth of SiC was conducted using a 2-inch-diameter on-axis 4H-SiC (000-1) seed crystal at 1940 °C for 3 h in a He atmosphere. Fig. 1 presents the cross-sections of the SiC crystals obtained using a PVT-SiC liner crucible [2], a commercially available sintered SiC crucible, and an LSI-SiC liner crucible. Although the PVT-SiC liner is not optimal for mass production, it is composed of high-purity dense SiC, which results in high-quality SiC crystals devoid of macrodefects [2]. Conversely, the use of a commercial SiC crucible resulted in numerous voids attributed to oxide sintering aids. These voids proved to be challenging to eliminate when the crucible served as the SiC source, rendering it unsuitable for solution growth. In contrast, the LSI-SiC liner crucible exhibited no voids. However, SiC inclusions were detected, originating from the detachment of a portion of the LSI-SiC liner rather than from SiC microcrystals formed in the solution when graphite crucibles were employed. Consequently, although improvements in the LSI process are necessary to mitigate SiC detachment, the LSI-SiC liner is anticipated to be an effective and relatively cost-efficient SiC source.

ABSTRACT. For physical understanding of mobility enhancement in SiC FinFETs, the electron scattering mechanism in 4H-SiC FinFETs with different fin widths was theoretically analyzed, taking account of the self-consistently calculated electronic states. High mobility in SiC FinFETs is mainly attributed to reduction of Coulomb scattering, resulting from the lowering of potential energy across the fin due to the merger of depletion layers extending from both the sidewalls. Although the influence of trapped charges on channel mobility is negligibly small in SiC FinFETs owing to the reduction, the Coulomb scattering due to fixed charges at the SiO2/SiC interface remains as the dominant limiting factor for channel mobility.

ABSTRACT. This study focuses on a novel vertical-channel (VC) Fin-SiC structure for power devices, showing superior performance with an ultra-narrow fin channel. The 1.2-kV-class VC Fin-SiC achieves reduced threshold voltage and improved mobility, enhancing efficiency in electric vehicles and power systems. These findings pave the way for developing high-efficiency power devices.

ABSTRACT. The high density of traps at the oxide semiconductor interface (4H-SiC/SiO2) and various scattering centers [1, 2] at the channel are believed to be responsible for limited channel performance in silicon carbide MOSFETs. Studying the behavior of these traps and the corresponding scattering mechanisms influenced by physical parameters such as doping concentration, oxidation method, and post-oxidation treatment, among others, is crucial. In this work, gated Hall measurements are used to investigate the impact of doping concentration on interface traps and then Hall mobilities are modeled using different scattering mechanisms present at the channel to study universalities in SiC MOSFETs. Figure 1(a) shows a cross section and (b) top-view of the fabricated MOS gated Hall bar. The Hall bar is fabricated on a Si-face 4° off-axis 4H-SiC (0001) wafer, on uniform Al-doped implanted p-well layers ranging from 2×1017 to 3×1018 cm-3. This device is a long channel (Lch=1 mm, Wch=200 um) lateral MOSFET with Hall voltage contacts, fabricated with a thermal oxide passivated with a NO anneal. Figure 2 (a) shows the measured field effect 〖(μ〗_FE) and (b) Hall mobility (μ_Hall) for different p-well concentrations at room temperature. The difference between μ_FE and μ_Hall occurs due to the high density of interface traps. The total charge density at the interface is calculated using a split CV measurement between G to SD keeping the B contact grounded. The typical split CV measurement is shown in Fig 3. The total charge (n_total) measured is consistent with the value calculated from the measured Cox. The free carrier concentration (n_free) is obtained from the gated Hall measurements and then subtracted from n_total to extract occupied trapped charge density (n_trap). These are plotted in Fig 4 (a) and (b), the measured value of n_free is decreasing with the increasing p-well concentrations, and therefore the value of n_trap increases as a result. These traps could be either very shallow traps near the conduction band edge or border traps. To observe the effect of these traps on scattering mechanisms at the channel, the Hall mobility is modeled using different types of mobility components arising due to scattering such as bulk mobility (μ_Bulk), Coulomb limited mobility (μ_C), phonon limited mobility (μ_Ph), and surface roughness limited mobility (μ_SR). Figure 5 shows Hall mobility versus effective field at the channel. The field dependence of μ_Bulk,μ_Ph,and μ_SR is taken from earlier observation from literature [1,3]. The Coulomb limited mobility is then calculated from the measured Hall mobility using Mattheisen’s rule 1/μ_Hall =1/μ_Bulk +1/μ_C+1/μ_Ph +1/μ_SR . The red dotted line is the fit line to the data by considering all the scattering components. Fig. 6 shows the effect on these scattering mechanisms on different doping concentrations. The values of μ_Ph and μ_SR remain constant; however, the values of μ_Bulk and μ_C change. Due to increased remote coulomb scattering centers, μ_C drops with increasing p-well concentration. The increase in total occupied trap density with increasing p-well doping concentration occurs as the threshold voltage moves closer to the conduction band edge and therefore accessing more traps. These traps do not seem to affect phonon or surface roughness scattering properties. These results from Hall measurements and the analysis regarding scattering mechanisms reveal intricate details that are useful in modelling mobilities and improving 4H-SiC/SiO2 channel characteristics.

[1] M. Noguchi et al., IEEE Trans. Elec. Dev., 68, 12, (2021). [2] S. Das et al., MDPI Materials, 15, 19 (2022). [3] S. Takagi et. al., IEEE Trans. Elec. Dev. 41, 12 (1994).

ABSTRACT. SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/ SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage(I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we investigate the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

ABSTRACT. The aim of this paper is to compare ramp- and ac-based C-V methods to explore the footprint of these traps within the capacitance-voltage (C-V) characteristics of SiC power MOSFETs, which potentially affect the dynamic performance of SiC power MOSFETs in actual applications. For understanding the fast and slow switching capabilities of SiC power MOSFETs, it becomes crucial to investigate frequency (f)-dependent C-V MOSFET characteristics captured by the ramp- and the ac- C-V measurement methods. Such an analysis is performed in this work by means of TCAD simulations, which allows for distinguishing physical effects contributing to the f-dependent behavior of SiC power MOSFET’s C-V characteristics that is rather challenging to comprehend from the measurements solely. This work contributes to a deeper understanding of the differences between C-V characteristics obtained from ramp- and ac-C-V measurements, and points out that detailed C-V characterization of SiC power MOSFETs is relevant for specific applications.

ABSTRACT. We fabricated aluminum-gate metal-silicon oxide-semiconductor (MOS) diodes in the 4H-SiC and 3C-SiC regions on the surface of a single 4H-SiC wafer by the simultaneous lateral epitaxy (SLE) method and evaluated their high-frequency differential capacitance-voltage (C-V) characteristics. It is confirmed that the formation of accumulation and depletion layers and the clear difference in flat-band voltage. Moreover, inversion layer carrier transport at high-frequency signals was observed only on the 3C-SiC, suggesting the possibility of 2-dimensional hole accumulation at the 3C-SiC/4H-SiC heterointerface due to spontaneous polrization.

ABSTRACT. Lasers have become indispensable for machining 4H-SiC, offering precision, wear-free operation, and scalability driven by increasing laser power [1]. This is especially valuable in wafer splitting and dicing, where lasers improve material efficiency and reduce costs as substrate sizes grow [2-3]. However, hardness, wide bandgap, and complex absorption mechanisms—including nonlinear, free-carrier, and defect-induced absorption—make laser-SiC interactions highly complex. Doping variations [4] and intrinsic stress introduce spatial inhomogeneities, causing incubation effects and variability that challenge robustness, especially for larger (200 mm) wafers. To address these issues, our research spans three interconnected stages: 1. Fundamental Understanding of Laser Modifications: To quantify spatial inhomogeneities and laser response variability in n-type 4H-SiC, we performed z-scan, absorption, and Raman measurements across full wafers. These revealed ±20% variations in absorption (α) and LO-phonon shifts correlated with doping levels ranging from 5–20 × 10¹⁷ cm⁻³, pointing to inhomogeneous free-carrier absorption as a key influence. We calculated single-pulse damage thresholds with a tunable femtosecond–picosecond source (185 fs to 2.5 ps, w₀ = 8–13 µm), obtaining fluence values from 1.2 to 1.9 J/cm² that increased with pulse duration. Normalized Ablation Efficiency was then evaluated as a function of pulse number, revealing rapid saturation for femtosecond pulses and slower, near-linear accumulation for picosecond pulses over hundreds of shots (Fig. 1a–c). These trends, together with spatial variations in α, indicate that incubation dynamics and local variations in doping could critically affect modification consistency across surface and subsurface machining. 2. Process Development: Based on these physical insights, we investigated processing behaviors in both subsurface and surface regimes. We examined how localized defect generation during subsurface processing triggers amorphization, carbonization, and stress-induced crack initiation, and how these effects can be controlled through tailored hatching patterns (Fig. 2a). Full-wafer splitting was achieved at adjustable depths (Fig. 2b), but residual cleaving forces—linked to laser pattern geometry, crack orientation and extent—promoted vertical crack formation under mechanical loading (Fig. 2e). Surface micromachining experiments demonstrated strong sensitivity of groove depth and uniformity to pulse overlap and energy input. Increased overlap resulted in a clear transition from laser-induced periodic surface structures (LIPSS) to well-defined microgrooves, signifying a critical regime shift driven by cumulative energy input and pulse-to-pulse interactions (Fig. 3a–f). These findings underscore the need for precise spatial control in subsurface splitting to ensure consistent crack propagation and for managing total energy input in surface dicing to increase throughput. 3. Optimized Setups: To overcome these limitations, we developed dedicated experimental setups optimized for each processing regime. For wafer splitting, integrating a nanosecond laser and a high-numerical-aperture objective with in-situ focus control significantly improved spatial stability and minimized Z-position uncertainty, enabling reproducible subsurface cracking. For surface dicing, we employed a high-power ps laser system (τ = 3 ps, 200 W, 1MHz) coupled with a high-speed polygon scanner (w₀≅20μm) achieving scan speeds exceeding 1 km/s. The study examined the impact of normalized fluence (F/Fth, where Fth ≈ 1.82 J/cm²), spatial pulse separation (∆x), and the number of scans (n). As shown in Fig. 3g, ablated depth scaling with total energy input shows that faster deflection speeds maintain micromachining efficiency at high scanning rates, delivering a ten-fold increase in throughput compared to conventional galvo-based dicing. Optimizing laser parameters, understanding incubation phenomena, and enhancing spatial stability collectively enable robust, efficient, and scalable laser-based wafer splitting and high-speed dicing, establishing a pathway to sustainable and high-yield 4H-SiC manufacturing.

ABSTRACT. SiC is still undergoing development to improve its crystal quality, aiming to achieve electrical yields above 90% on 200 mm wafer scale. At present, the main challenge is the presence of crystallographic defects in both substrates and epitaxial layers. A primary focus is to evaluate the "killer ratio" of each defect type, categorizing them into negligible and harmful defects, with the latter negatively impacting the device’s final electrical performance. This classification facilitates thorough product screening before final application.

Reliability testing is a critical component in the semiconductor industry, concentrating on assessing the performance, durability, and quality of electronic components and devices under various conditions. These tests are typically customized based on specific technology, device, and possible failure mechanisms during production and qualification. Examples of such tests include High Temperature Reverse Bias (HTRB), High Temperature Gate Bias (HTGB), Dynamic Reverse Bias (DRB), and Body Diode Stress (BDS). These tests help establish lifetime and durability models for the devices.

Although SiC MOSFET devices offer promising performance in terms of high voltage blocking, high-temperature operation, and fast switching frequencies, several challenges remain. Beyond electrical failures caused by defects introduced during front-end processing steps such as implantation, oxidation, and thermal annealing—which can lead to issues like threshold voltage instability primarily due to a suboptimal MOS interface [1]—it is important to assess how epitaxial defects affect device electrical performance.

To investigate failures in SiC devices (e.g., 650V MOSFETs) following reliability testing, Emission Microscopy (Em.Mi.) is used to pinpoint the exact failure location. Once the emission site, indicative of a possible epitaxial defect, is identified, the device layers are removed via chemical wet etching. Subsequently, molten KOH etching is applied to expose surface defects on the SiC, enabling correlation between the emission failure and the underlying material structure.

The KOH etching of delayered devices was conducted at 500°C for 10 minutes, followed by optical microscopy to classify defects and establish any correlation with the device failure sites. Over time, a classification system for dislocations observed in KOH-etched SiC has been developed through numerous experiments on n-type epitaxial layers with a typical doping concentration of about 1.6×10​¹⁶​​ atoms/cm³. Literature indicates that this doping level is ideal for accurate defect detection and classification [2–3].

Figure 1 (a-d) presents the case of a threading screw dislocations (TSD) related failure. The morphological characteristics of the SiC surface after full device delayering were examined using SEM and AFM, as shown in Figure 1a. A low-magnification SEM image (10 kV) reveals the hotspot area corresponding to the Emission Microscopy (Em.Mi.) emission, with a FIB cross-section serving as a reference to identify this region at higher magnification.

In Figures 1b and 1c, SEM analysis at higher magnification (3 kV) reveals a triangular-shaped defect at the hotspot site, indicating a dislocation originating from the substrate and propagating into the epitaxial layer. AFM imaging (Figure 1d) further confirms surface pitting associated with this defect. As noted in [4], small depressions measuring 0.5–1 μm appear at the locations of TSD. These depressions result from uneven step flow around dislocations during growth and are typically shallow, with depths between 3 and 20 nm. The shape and depth of these features are strongly influenced by growth conditions, including in situ etching and cooling. When deeper depressions form, geometric effects such as electric field crowding can adversely affect device performance, potentially causing failure.

Furthermore, KOH etching at the die level has shown a clear link between device failures and the presence of TSDs. This method effectively uncovers that electrical failures are closely tied to the initial material quality. Although KOH molten etching is a destructive process, it remains a cost-effective and straightforward technique for evaluating dislocation density [5].

The etching is conducted in molten KOH within a nickel crucible heated to 500°C for 5 minutes. The etching duration varies significantly depending on the material’s doping level, resulting in different etching times and optimized temperatures for the substrate and the epitaxial layer. Dislocation exposure, which can severely affect device performance, is a highly effective technique for correlating defects with failure.

Figure 1(e-h) presents also a micropipe related hard failure caused by a crystallographic defect. The drain current leakage monitoring, depicted in Figure 1e, reveals a sudden increase after about 0.5 hours, indicating a hard failure where the device becomes entirely unusable. Leakage currents between the drain and gate (with the source disconnected) and between the gate and source (with the drain disconnected) are also shown. Both current profiles indicate a short circuit between terminals (IDGO and IGSO). Moreover, the IDSS test (drain leakage with gate and source shorted and grounded) demonstrates similar short-circuit behavior.

The Em.Mi analysis pinpoints the emission site across the device. Further examination involved delayering, with all chemical etching performed in wet conditions using 40% hydrofluoric acid (HF) on a chemical bench. Layers were sequentially removed until the SiC epitaxial surface was exposed. A hexagonal hole is shown at the bottom of Figure 1e. Subsequent KOH etching revealed a structured defect, which was analyzed by SEM, as presented in Figure 1 (f-h).

ABSTRACT. Research and development of SiC integrated circuits for harsh environments, such as nuclear reactors and space applications, have recently attracted significant attention. Previous studies have investigated the effects of accumulated gamma-ray doses on non-operating (floating) SiC devices and circuits. Although some studies have examined the behavior of SiC circuits under operation during gamma-ray irradiation, the detailed effects of irradiation during active operation remain insufficiently understood. In this study, we conducted in-situ measurements on a SiC JFET operational amplifier operating under gamma-ray irradiation. The results revealed that no abnormal noise appeared in the output signal, and the voltage gain remained consistent with that observed prior to irradiation. However, the output offset voltage decreased by approximately 2 V within a few minutes after the start of irradiation.

ABSTRACT. The issue with the use of power devices in a space environment is improving tolerance against Single-Event Effects induced by heavy-ion irradiation [1]. Single-Event Gate Rupture (SEGR) is the catastrophic breakdown of a gate oxide caused by an increased electric field in SiO2 [2]. In the case of SiC MOSFET, SEGR is a major concern because the electric field in the gate oxide (Eox) is higher than that of the Si-MOSFET in the off state, owing to the high breakdown electric field of SiC. In this study, we demonstrate the improvement in SEGR tolerance by decreasing Eox in a 4H-SiC planar-gate MOSFET (DMOSFET).

ABSTRACT. Currently, the trench silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention in power electronic fields owing to their higher channel mobility, higher power density, and low ON-State resistance, and they have the potential to be the candidates that used in aerospace missions [1-2]. However, the total ionizing dose (TID) effect with the high bias conditions, i.e., high drain voltage bias, can heavily degrade the electrical characteristics of the devices and further reduce the operation life [3-4]. As a result, it is of significance to investigate the degradation behaviors and mechanism of the trench SiC MOSFETs under TID radiation with high drain bias conditions comprehensively. Among the electrical characteristics of the SiC MOSFETs, the ON-State resistance has an importance position, which has a strong relation with the current variations and radiation tolerance capability. In fact, the resistance degradation induced by the TID effect makes the current increase, illustrating the ON-State resistance is deeply influenced by the TID effect. In this work, the resistance degradation of the double trench (DT) and the asymmetric trench (AT) SiC MOSFETs are investigated in detailed. The commercial DT (SCT3160KL) and the AT SiC MOSFETs (IMW120R140M1H) with the breakdown voltage over 1200V are selected as the samples and the schematic cross sections of them are shown in Fig. 1. The Cobalt-60 gamma-ray at dose rate of 100 rad(Si)/s is the radiation source in this experiments and the rest of radiation and bias conditions for the samples are listed in Table I. Fig. 2 illustrates the output characteristics of DT and AT SiC MOSFETs, it can be observed that the TID effect makes the drain current (IDS) increase, especially in DT samples. Meanwhile, the drain voltage bias has no impact on the IDS. Notably, when the gate source voltage (VGS) is 12V, the IDS has a drastic increase for the samples A1, B1, and C1, while the IDS has a slight increase for the samples A2, B2, and C2. Actually, the IDS variations results from the channel resistance. Considering that the resistance component under different VGS has changed a lot, the main resistance values are calculated and are depicted in Fig. 3. Here, the RCH1 is the channel resistance when the VGS is 6V, the RCH2 is the channel resistance when the VGS is 12V, and the RD is the drift region resistance, it shows that the channel resistance of the DT samples has obviously decrease compared to the AT samples, which causes the differences of the IDS variations under different VGS. Subsequently, the threshold voltage (VTH), leakage current (IDSS), and the gate leakage current (IGSS) results are shown in Figs. 4-6. Fig. 4 illustrates the TID effect damages the channel region of the devices and the DT samples has more heavily negative shifting than the AT samples, which causes more current increase and the resistance decrease. It also reflects the AT samples have better radiation tolerance capability. Fig. 5 depicts the IDSS increase results, which is resulted from the VTH negative shifting. Apparently, the DT samples have larger IDSS than the AT samples because of the differences in VTH shifting. Fig. 6 shows that the IGSS has no obvious change for both of DT and AT samples, because the IGSS keeps at nA or pA level. It indicates that the IGSS has no sensitive to the TID effect. Finally, the Silvaco TCAD simulations are shown in Figs. 7-8. It is observed that the TID effect causes the oxide trapped charges in oxide, which leading to the channel opened and the current increase than before. The DT structure also exhibits more obvious increase trend than the AT structure under the same radiation and bias conditions, which has good agreements with the tests results.

ABSTRACT. Silicon carbide (SiC) has emerged as an attractive semiconductor material due to its exceptional physical and electrical properties [1]. In addition to its conventional applications in power electronics—such as electric motors and vehicles—SiC also shows strong potential for use in the aerospace industry [2-3]. Furthermore, continuous advancements in SiC complementary metal-oxide-semiconductor (CMOS) technology over the past years have significantly expanded its range of applications [4-5]. Therefore, the electrical performance and stability of PMOSFETs under harsh environments require thorough investigation. In this study, a channel-length-dependent threshold voltage (Vth) instability in PMOSFETs was identified, and a corresponding mechanism was proposed to explain this behavior. Fig. 1 presents the cross-sectional schematic and simplified process flow of the fabricated PMOSFETs. The devices were subjected to gamma irradiation at a dose rate of 0.515 kGy(Si)/hr for a duration of 2 hours. During irradiation, the gate electrode was biased at –20 V, while the source, drain, and body terminals were grounded. The Vth was defined as the gate voltage at which the normalized drain current, |ID| × (L/W)—where L and W denote the channel length and width, respectively—reached 10 nA. The subthreshold swing (S.S.) was extracted based on the normalized current in the range of 10 to 100 pA. To eliminate the influence of S.S. on Vth, an additional parameter, Vi, was defined as the gate voltage at which the normalized current reached 1 pA. Devices with channel lengths of 0.8 μm and 50 μm were selected to represent the short- and long-channel regimes, respectively. The transfer characteristics of the PMOSFETs before and after irradiation are illustrated in Fig. 2, with the corresponding measured values summarized in Table I. As expected, I-V curves exhibited a leftward shift after 1 kGy gamma exposure due to hole trapping in the gate oxide. The shift observed in short-channel devices was significantly more pronounced than that in their long-channel counterparts. It was estimated that the density of positive charges trapped in the gate oxide of short-channel devices was approximately 2.7 times higher than that in long-channel devices, based on the shift in ΔVi. In order to isolate the effects of gate stress from those of radiation, additional stress tests were conducted on PMOSFETs under gate bias for 2 hours. The results of these tests are shown in Fig. 3. As shown in Table I, the gate-length-dependent effect remained evident; however, it was unexpectedly found that the majority of trapped charges were induced by gate bias stress rather than radiation. Additionally, an improvement in ΔS.S. was observed to reduce the magnitude of |ΔVth|. The limited contribution of radiation to ΔVi can be attributed to the direction of the electric field, which drives positive charges toward the gate electrode. In contrast, radiation primarily contributes to subthreshold swing degradation. The gate oxide contamination is suspected to originate from aluminum (Al) implantation used for the source and drain regions. Fig. 4 presents the secondary ion mass spectrometry (SIMS) analysis of the P+ region after thermal oxidation, confirming that a significant amount of Al dopants remains within the oxide. Despite the low diffusivity of Al in oxide [6], these dopants are still capable of diffusing laterally at elevated temperatures, such as 1200 °C or higher, which are typical gate oxide processing conditions for SiC devices. This suggests that Al atoms diffuse from the edges of the implantation region toward the center of the gate. As the channel length decreases, a larger proportion of the gate oxide becomes contaminated by Al, thereby resulting in degraded performance stability. In summary, a channel-length-dependent Vth instability was observed under gate bias stress and gamma-ray exposure. The majority of positive charge trapping is attributed to hole injection induced by the external bias. SIMS analysis confirmed the presence of aluminum species retained in the gate dielectric after thermal oxidation. Based on the experimental results, it is concluded that dopant contamination in the gate oxide is the primary cause of the channel-length-dependent instability.

ABSTRACT. Low angle grain boundaries (LAGB) are aggregation of dislocations, usually threading edge dislocations (TEDs) or edge type basal plane dislocations (BPDs) to accommodate the misorientation of lattice planes[1-2], that lower yield of PVT 4H-SiC substrates and prevent the implementation of large size SiC devices. Therefore, establishing a clear understanding on the dislocation nature of LAGBs and their formation mechanisms is of great significance. Classical formation mechanisms of <1-100> orientation LAGBs are generally associated with threading screw/mixed dislocations (TSDs/TMDs), which act as growth centers by generating spiral steps[3]. TED LAGBs formed as TEDs align along the <1-100> direction to accommodate the c-axis rotation between the TSDs and surrounding regions when growth centers converge. Recently, a step flow based mechanism [4] was proposed which indicates that steps originating from the facet region propagate faster near the boule edges than at the central region of the crystal due to radial temperature difference, forming a horseshoe shaped growth step morphology. Growth fronts encounter each other on the far side of the boule away from the facet forming TED LAGBs to accommodate the misorientation of the two step fronts. In this study, unique distribution patterns of LAGBs observed in physical vapor transport (PVT) grown off-axis 4H-SiC wafers is investigated. Synchrotron X-ray topography (XRT) reveal the presence of LAGBs networks around the facet regions as well as associated with micropipes in two different wafers. For wafer A, LAGBs networks are observed near the facet region (Fig. 1a) consisting of LAGB arrays with white and dark contrast TEDs extending from the facet region. All individual TED arrays in each LAGB set extend along the < 1-100 > directions, with identical 1/3<11-20> Burgers vectors perpendicular to the array direction. Comparison with ray tracing simulated images [4] allows unambiguous identification of the different Burgers vectors and resultant tilt directions. Three spikes are observed on the left edge of facet (Fig. 1b). Based on the horse-shoe shaped mechanism [4], these obesrvations indicate that growth fronts associated with the outer spikes propagate faster than the inner one due to radial temperature gradients. When the growth fronts of the outer spikes encounter each other first, LAGBs are formed along [01-10] & [10-10] directions to accommodate misorientation in this region. Growth front associated with the central spike will keep moving forward and encounter the other two fronts to form the LAGBs along the [1-100] direction. A similar step flow mechanism can explain the formation of LAGBs from a group of micropipes (MPs) observed in the left edge of the wafer A (Fig. 2). Step growth fronts propagates around the MPs and similar to the horse-shoe shaped mechanism, the growth fronts encounter each other to form LAGBs. For wafer B, LAGBs networks are observed in the facet region (Fig. 4) and it consists of LAGB arrays with white and dark contrast TEDs extending from the center of facet to left side of it. Several micropipes (MPs) observed on the right side in the facet region suggest the classical formation mechanism applicable here with MPs acting as growth centers during the growth process and TED LAGBs network formed to accommodate the c-axis rotation between the MPs and the surrounding regions.

ABSTRACT. Various kinds of stacking faults (SFs) have been reported in 4H-SiC epitaxial wafers, and identification of SFs and structure determination have been investigated by using characteristic photoluminescence (PL) emissions from SFs, high-resolution transmission electron microscope, and high-angle annular dark-field high-resolution scanning transmission electron microscope (HHADF HR-STEM) [1-9]. SFs on close-packed planes like {111} for FCC and {0001} for HCP structures can be classified into Shockley-type SF (SSF) and Frank-type SF (FSF). SSFs are formed by gliding of Shockley partial dislocations, i.e., Shockley gliding of dislocation [6,9,10]. FSFs are formed by removal of layer through the coalescence of vacancies or inserting an additional layer with or without the Shockley gliding. In forming the FSFs Shockley gliding can be engaged additionally [6,9,10]. On the other hand, SFs can be classified into intrinsic and extrinsic SFs [6,9,10]. The key criteria for assigning to intrinsic and extrinsic SFs is whether an extra layer is inserted (extrinsic) or not (intrinsic) [6,10]. In the international standard document that classified typical standard SFs in 4H-SiC with characteristic PL emission wavelengths (C-PLWs), Shockley-type SFs are four kinds of single, double, triple, and quadruple as (3,1), (6,2), (5,3) and (4,4) SFs, respectively. In case of Frank-type SFs, there are three kinds of SFs as intrinsic (5,2) and (4,2), and extrinsic (4,1) SFs. The C-PLWs these 7 kinds of standard SFs in 4H-SiC are well summarized although there are some differences [5,10]. In this study, we investigated commercial 6-inch 4H-SiC epitaxial wafers and substrates by employing PL mapping and spectra analyses, HAADF HR-STEM, and DFT calculations. Based on the investigated results, we claim two critical issues on (4,1) FSF; 1) Is it extrinsic or intrinsic SF? 2) What is the characteristic PL emission wavelength?

In the literatures, there are several formation mechanisms for the (4,1) FSF have been proposed, and it was classified to extrinsic FSF [3,8]. Table 1 summarizes the proposed formation mechanisms for the (4,1) FSF. In most cases the (4,1) FSF forms from the intrinsic (5,2) FSF by the ways of the “missing layer” process. If the (4,1) FSF was formed by the “missing layer” processes without the “inserting layer” process, the (4,1) FSF should be the intrinsic FSF not the extrinsic FSF. Fig. 1 shows TEM images for three mechanisms investigated in this study (the SF structures were confirmed by HR-STEM, will be presented at the site) for the (4,1) FSF formations through the “missing layer” process. Fig. 2(a) is HR-STEM image showing the transforming point from the (5,2) FSF to the (4,1) FSF, directly. Our observations are strong evidences for the formation mechanism of the (4,1) FSF from the (5,2) FSF through the “missing layer” process. The other way to form the (4,1) FSF is forming from the (3,2) FSF. The (3,2) FSF is an extrinsic SF without any argument [10,11], which could be formed from the perfect (2,2) 4H-SiC by inserting one layer, simply [6,9]. If the (4,1) FSF was formed in this way it should be extrinsic SF [10]. However, there is no direct TEM imaging result showing the transformation of the (4,1) FSF from the (3,2) FSF. Next issue is the C-PLW for the (4,1) FSF. The C-PLW for the (4,1) FSF was assigned to 424 nm [3,4,8]. However, there are no direct results showing the 424 nm PL emission from the (4,1) FSF by providing both PL and HRTEM (or HR-STEM) picture. Here we can deduce following summary for the C-PLWs from various SFs by surveying investigation in literatures [1-9,11,12 or references therein]; i) the SFs composed with the Zhdanov notation numbers of “3” and “2” like (3,2), (3,3), (3,3,3,2) (3,3,3,3), (3,3,3,3,2), (3,3,3,3,3,2), (3,2,2,3), (3,3,3,2,3,2), and (3,2,3,3,3,2) SFs have the C-PLWs between 420-430 nm. ii) the SFs with the Zhdanov notation number of “4” like (4,4), (4,2), (3,3,3,4), (3,3,2,2,4,2), and (4,3,2,3) SFs have C-PLW between 454-460 nm except the reported 424 nm for the (4,1) SF. iii) the SFs with the Zhdanov notation number of “5”, like (5,2), (5,3), and (5,3,3,2) SFs appeared at the C-PLWs of 482-485 nm. iv) the SF with the Zhdanov notation number “6” like (6,2) SF showed the C-PLW of about 503 nm.

The C-PLWs from investigated SFs in the literatures since the late 2000s have shown a robust tendency of the C-PLWs of ~425 nm  ~455 nm  ~483 nm  ~503 nm as the Zhdanov notation changed by (3,#)  (4,#)  (5,#)  (6,#), except the 424 nm of the (4,1) FSF. Therefore, having a question on the C-PLW of 424 nm for the (4,1) SF is reasonable. Fig.2 (b) shows PL map image corresponding to the HR-STEM image of Fig. 2(a). Fig.2(c) shows a spectrum line scan result from the SF and the corresponding C-PLWs are 483 and 459 nm as shown in Fig. 2(d). Fig. 2 clearly showed that the C-PLWs for the (4,1) FSF is 459 nm. This is the first direct evidence for the C-PLW of the (4,1) FSF. The 483 nm C-PLW is from the (5,2) FSF [5,6]. In conclusion, the (4,1) FSF should be the intrinsic SF if formed through the missing process and its C-PLW should be 459 nm not 424 nm. Detailed further results including formation mechanisms, DFT calculations of stacking fault energies and band structures with SFs will be presented, additionally.

This work was supported by the Technology Innovation Program (25A02037) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

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ABSTRACT. In this study, we evaluated 3C-SiC/4H-SiC stacked epilayers on trenched 4H-SiC substrates. We discussed the relationship between the substrate trench structures prior to epitaxial growth and the SiC polytype based on the peak intensity ratio of Raman spectra.

ABSTRACT. Silicon carbide (SiC) is a semiconductor with a wide bandgap and exceptional electronic and physical properties, including high saturation velocity, high breakdown field, and excellent thermal conductivity [1]. These attributes make SiC a highly promising material for demanding applications involving high voltage, high power, and high temperature environments. The development of large-scale, high-quality single crystal SiC is crucial for enhancing device performance and broadening its application scope. Among the available growth techniques, physical vapor transport (PVT) [2] is the most widely used method, as it allows the production of large SiC substrates with controllable growth rates. However, the presence of various crystallographic defects, such as threading screw/mixed dislocations (TSDs/TMDs) and micropipes (MPs) can significantly impact device performance, limiting the full potential of SiC-based technologies [3,4]. Therefore, the generation and impact of such defects during PVT growth should be thoroughly investigated to improve the growth processing and furnace design. In this study, one 4H-SiC wafer was analyzed by synchrotron white beam X-ray topography (SWBXT)while mappings of TSDs/TMDs density for the sequence of wafers sliced from the same boule were conducted by high resolution X-ray topography (HRXRT) in 0008 reflection. Fig. 1(a) and 1(b) show the SWBXT in 1-100 and 1-101 reflections, where formation of mixed Frank and Shockley type stacking faults due to deflection of the TSDs/TMDs can be observed in the region between the spoke pattern which is highlighted by the dotted lines. Fig. 1(c) to 1(e) show some selected density maps of TSDs/TMDs from the seed side to the dome side, where higher density of TSDs/TMDs were observed in the earlier growth stage near the facet region (Fig.1(c)) and the TSD/TMD density decreases as the wafer is closer to the dome side. Here, the spoke feature near the center of the wafer, highlighted by the dotted box, will be specifically analyzed. Two areas with lower TSDs/TMDs density between the central spoke are highlighted by the white solid line box. The TSD/TMD density decreases due to the deflection process as the growth progresses, where deflections occur in between the central spokes (Fig. 1(d)) then more deflections take place on the central spokes. Generally, TSDs/TMDs will have a faster growth rate than other parts of the crystal and form spiral steps during the growth [5], then when these steps merge, a growth island will be formed on the surface as shown in Fig.2(a). When the growth proceeds, step bunching occurs and deflects TSDs/TMDs toward the step flow direction (Fig.2(b) and (c)). Since the density of TSDs/TMDs are lower between the central spoke, as shown in the white box of Fig.1(c), the growth rate along [000-1] will be slower, leading to ridge formation on the spoke position, as shown in Fig.2(d). Therefore, macrosteps can be accumulated between the spokes that then cause the deflection of TSDs/TMDs in that region, as shown in Fig.2 (e). Finally, as the growth interface becomes convex, all the TSDs/TMDs will be deflected as shown in Fig. 2(f) and (g)). The detailed mechanism of the spoke pattern of stacking faults will be developed with supporting microstructure data and presented.

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ABSTRACT. A major challenge for the expansion of the SiC power device market is to improve the quality of the SiC epitaxial wafers. To address this issue, a non-contact process technology (Dynamic AGE-ing (DA) process) that integrates thermal etching and crystal growth is being investigated. By applying the DA process, it is possible to remove the damaged layer of SiC bulk wafers and form a BPD-free buffer layer, which is expected to result in low-defect density SiC epitaxial wafers. The application of the DA process can affect the electrical characteristics of SiC devices, but there are no reports on the characteristics of SiC MOSFETs to which the DA process has been applied. Therefore, in this study, we experimentally verified the effect of the DA process on the device characteristics. We fabricated 3.3 kV SiC MOSFETs by applying the DA process to the buffer layer and experimentally investigated the effect of the DA layer on the electrical characteristics. The results showed that the recovery loss can be reduced by 50% without deteriorating the static characteristics. As a next step, we plan to proceed with the reliability evaluation of SiC MOSFETs with a DA layer.

ABSTRACT. Junction Barrier Schottky (JBS) Diode integrated MOSFET (JBSFETs) are promising for high-voltage 4H-SiC power applications, offering superior 3rd quadrant performance and unipolar current conduction. This becomes critical for high-voltage devices, where an integrated JBS diode helps mitigate bipolar degradation caused by basal plane dislocations (BPDs) [1]. While JBSFETs may exhibit higher specific on-resistance (Ron,sp) due to increased cell pitch, structural innovations with efficiently integrated JBS diode enhance the forward conduction, achieving performance comparable to that of MOSFET [2]. Although such performance has been demonstrated in low-voltage devices, it has yet to be achieved in high-voltage applications. Building on prior work where Stripe JBSFET showed reduced 3rd quadrant forward voltage drop (VF) compared to nominal MOSFET [1], this study extends the technique to enhance the 3rd quadrant conduction, while offering the same Ron,sp. A comparative analysis of JBSFET structures and MOSFET is presented, focusing on structural evolution, trade-offs in Ron, sp, VF, and the role of Schottky width in reducing leakage current for enhanced high-voltage device reliability. Fig. 1 illustrates the structural differences between the JBSFETs and the MOSFET. These include: (1) Nominal MOSFET with a P+ source is placed in the orthogonal direction, with the linear topology of the MOSFET, (2) the Stripe JBSFET features the widest cell pitch with a linear Schottky region, (3) the Island P+ JBSFET with the Schottky opening placed in the orthogonal direction shielded solely by the P-well in X-direction. Fig. 2 illustrates that, along the X-direction, the Schottky region in the Stripe and Island P+ JBSFET is shielded by a P+ region and the P-well, respectively. The exclusion of the P⁺ region in the X-direction leads to a significant reduction in cell pitch, resulting in the most compact JBSFET design, which is slightly larger than that of the nominal MOSFET [2]. To ensure a fair comparison, all devices were fabricated with the same active area, JFET width, and channel length. Fig. 3 shows the forward conduction, where the Island P+ JBSFET achieves a significantly lower Ron,sp than the Stripe JBSFET due to its reduced cell pitch, and closely matches the MOSFET performance, offering a 7.55% improvement over the Stripe JBSFET. Fig. 4 shows that the Island P+ JBSFET exhibits a lower VF than the Stripe JBSFET and outperforms the MOSFET during the 3rd quadrant operation. Notably, despite the discontinuity of the Schottky region in the Island P+ JBSFET, the aggressive cell pitch design increases Schottky density, resulting in highly efficient unipolar current conduction and a substantial reduction in VF. In Fig. 5, the nominal MOSFET and Island P+ JBSFET showed avalanche breakdown with a high breakdown voltage of 8.3kV, where the Stripe JBSFET showed soft-breakdown due to high leakage current governed by the high electric field beneath its large Schottky region. Although leakage was high in the Island P+ JBSFET, this can be reduced by reducing the Schottky width to 0.8 µm with a cell pitch of 5.2µm, as shown in Fig. 6. However, this also impacts 3rd quadrant conduction and requires further optimization of Schottky width and process conditions. Among these JBSFET variants and MOSFET, the Stripe structure demonstrates improved 3rd quadrant performance but suffers from the highest Ron,sp, and leakage current with the largest cell pitch compared to the nominal MOSFET. In contrast, the Island P+ design achieves the lower Ron,sp than the Stripe structure, which offers almost the same Ron,sp as the nominal MOSFET. The superior 3rd quadrant performance of the Island P+ structure, thanks to the design innovation to achieve a smaller cell pitch, as illustrated in Fig. 7. Despite a slightly larger cell pitch than the MOSFET, the Island P+ JBSFET demonstrates well-balanced performance in forward conduction, 3rd quadrant behavior, and leakage current, underscoring its strong potential as a next-generation high-voltage, reliable power device.

ABSTRACT. Ultra-High-Voltage (UHV) SiC devices are drawing attention as leading candidates for next-generation power systems, enabling performance advantages, topology simplifications and footprint reductions in the expanding market of MV high-power converters [1]. A critical aspect for UHV-SiC devices with blocking ratings exceeding 10 kV, is the design of effective edge-termination structures. Conventional edge structures with UHV blocking capabilities often entail large termination footprints. Such area consumption is particularly critical as UHV capabilities require the use of expensive SiC wafers with drift region thickness exceeding 100 µm [2]. Therefore, minimizing termination footprint while ensuring robust blocking performance is paramount for the commercialization of UHV-SiC devices. In this work, compact UHV terminations are investigated by TCAD simulations and designs achieving >10 kV blocking within a < 350 µm footprint are experimentally demonstrated. Fig. 1 summarizes the concept and parameters of the termination of this work. This is a derivation the RA-JTE concept [3-4] where, differently from conventional design, high dose p-rings are used to enhance blocking capabilities. Table 1 summarizes the parameters of the four investigated designs (D1-D4). Fig. 2 compares the blocking capabilities extracted by TCAD for the investigated designs, comparatively to that of their constituent parts (rings and JTE only terminations), highlighting how the careful addition of p-rings in the JTE implant allows larger blocking voltages without increasing the footprint. The working principle of the terminations is further examined in Fig. 3. Fig. 3 (a) reports the electric field (EF) intensity in SiC as a function of the blocking voltage, showing that up to 10 kV all designs contain the maximum EF below the 2-2.5 MV/cm range. As further highlighted in Fig. 3(b), the EF peak is initially located at the JTE implant edge whereas, during the depletion of the main JTE implant at larger voltages, the p-rings get progressively engaged and the peak EF travels towards the active-transition overlap. Following the TCAD investigation, the terminations have been implemented in SiC-MOSFETs realized on 6-inch 4H-SiC wafers with a 100 µm thick epitaxial layer. A multi-mask approach has been employed to replicate the different termination designs on the same wafer. The implanted JTE dose has been varied across different wafers within a 50% range from the simulation optimal dose, while the p-ring dose has been fixed to a level that minimizes their depletion at increased blocking voltages. Experimental results are reported for the optimal dose only. The blocking capability of the MOSFETs has been characterized up to 10 kV directly at the wafer level. Fig. 4 exemplifies the blocking characteristics of MOSFETs employing D3 terminations. Within the investigated blocking range, the leakage current is mostly contained below 10 nA. Further experimental data is reported in Fig. 5. Fig. 5 (a) shows the cumulative distribution of the blocking voltage reached by the four designs (VBD defined at IDS(VDS)=1µA). While for designs D1, D2 and D3, around 60% of the population exhibit a blocking voltage exceeding 10 kV, samples employing D4 design do not block over 3 kV, highlighting the role of the p-ring distribution in enhancing the blocking voltage and desensitizing the design from JTE dose variations. Fig. 5 (b) reports on the leakage current probability distribution for designs D1, D2 and D3, measured at 9 kV. On average, design D1 exhibits the lowest leakage current, with almost 70% of the population leaking less than 100 nA. Such result highlights the impact of the JTE width on the leakage current, where the reduced depletion area achieved by a smaller JTE allows to limit the average leakage current. Additional details and experimental characterization will be included in the final paper.