ABSTRACT. We investigated basal plane dislocation (BPD) behaviors in physical vapor transport (PVT) grown 4H-SiC crystals, focusing on the interaction between BPDs and point defects through photoluminescence (PL) imaging of BPDs. We observed spatially diffuse PL emission around BPDs in 4H-SiC crystals grown by the PVT growth method. The emission showed a characteristic wavelength and thus was likely to originate from some type of point defects in the crystals. This result suggests the formation of Cottrel atmosphere around BPDs via the interaction of BPDs with point defects in PVT-grown 4H-SiC crystals.

ABSTRACT. Silicon carbide (SiC) is a promising wide-bandgap semiconductor for power electronic devices, where excess carriers from doping and operation can influence mechanical reliability. Electrical stimuli are known to affect mechanical behavior, exemplified by recombination-enhanced dislocation glide (REDG) and enhanced material removal in electrochemical mechanical polishing (ECMP). Understanding these effects is crucial for device advancement. This study investigates how excess carriers affect the elastic constants and ideal strength of SiC using first-principles calculations. Building on our previous work on group IV diamond-structured materials, we extend the analysis to 3C-, 2H-, and 4H-SiC. We analyzed tensile deformation along [0001] and shear deformation along [-1100] on the (11-20) plane. Results show that elastic constants decrease with increasing carrier density, indicating softening. Tensile strength decreased with electron injection and increased with hole injection, with ~20% change at 5 × 10^21 cm^-3. In contrast, shear strength responses varied: 3C-SiC followed Si trends, while 2H- and 4H-SiC showed decreases for both carrier types. These findings highlight the carrier-induced softening mechanisms and provide insight into REDG and material processing improvements.

ABSTRACT. SiC power devices are manufactured using expensive SiC substrates, with significant material loss occurring during the grinding process, which increases both costs and environmental impact. A wafer reuse method utilizing laser slicing instead of grinding has been proposed, enabling multiple uses of a single wafer. This study investigates the effects of laser slicing on 1200 V SiC Junction Barrier Schottky (JBS) diodes. The results show that at specific laser power levels and focal distances, the diodes' characteristics remain unaffected. However, at shallow focal distances, the breakdown voltage decreases due to the laser beam. From our data, proper laser settings make this method practical for wafer thinning.

ABSTRACT. Body diode reliability and reverse recovery characteristics of SiC-SJ-MOSFET whose p-columns was short, tapered and formed by deep Al ion implantation (MeV-SJ) was investigated in comparison with that of conventional Multiepi-SJ. The short tapered p-column of MeV-SJ causes soft reverse recovery.The body diode of MeV-SJ exihited higher reliability than that of Multiepi-SJ in spite of shorter p-columns. The PL images of stacking faults (SFs) suggest that the expansion of SFs would be stopped in the buffer layer of MeV-SJ.

ABSTRACT. Ultraviolet (UV) radiation has a wide application field reaching from scientific applications such as astronomy [1] and the detection of chemical and biological molecules [2] to civil uses such as water purification [3] and flame monitoring [4]. In many of these applications the detectors must detect only weak UV signals. A semiconductor-based solution can be avalanche-photodiodes (APDs), which provide an internal gain over classical photodiodes. Especially silicon carbide (SiC) yields advantages for the detection of UV radiation such as a wide bandgap resulting in a cutoff-wavelength of around 380 nm. Longer wavelengths can therefore not be detected by SiC-APDs. This property is often referred to as visible blindness. A more challenging property of SiC for the usage as an APD is its high electrical breakdown field strength. To prevent high operation voltages a so called SACM (separate absorption, charge and multiplication) [5] device was fabricated. Despite the reduction of the operating voltage due to the SACM design, the power density in the diodes is so high that self-heating of the APDs causes challenges in the characterization of the spectral responsivity under applied bias. The APDs were fabricated on highly conductive commercial n-type 4H-SiC substrates with an epitaxially grown layer stack (Fig. 1). The targeted doping profile of the epitaxial layer stack was validated via secondary ion mass spectroscopy (SIMS, Fig. 2). A so-called bevel edge termination was applied for the fabrication of the APDs to suppress electric field crowding at the surface of the device (Fig. 1) [6]. At the top of the bevel the diodes have a diameter of 500 μm. The devices were passivated with thermally grown oxide and oxide deposited by Low Pressure Chemical Vapor Deposition of Tetraethylorthosilicat (LPCVD-TEOS). Ohmic contacts were formed at the highly p-doped front side and the backside of the n-type substrate. For probing, contact pads were structured out of aluminum. To validate the functionality of the SiC-APDs, current-voltage characteristics in the dark and under illumination were measured (Fig. 3). The APDs exhibit a breakdown voltage V_BD of roughly 150 V (I(V_BD) = 10 μA). The dark current stays below 50 pA before reaching the breakdown voltage, which implies a sufficient suppression of surface leakage currents. To investigate the impact of the temperature on the devices and to validate, that the breakdown is indeed due to the avalanche effect, the dark current was measured for various temperatures (Fig. 4). The increased dark current could be explained by the increasing amount of thermally generated charge carriers. Fig. 4 also shows that the breakdown voltage increases with temperature. This indicates that the breakdown of the devices is caused by the avalanche effect: Due to increased interaction between phonons and charge carriers the mean free path of the charge carriers decreases, such that higher electrical fields are necessary to yield enough energy for the process of impact ionization [7]. To analyze the wavelength dependent response of the APDs, the spectral responsivity was measured as a function of the applied bias. However, the measured results are strongly dependent on the measurement parameters used for the characterization. Especially at higher bias voltages, where the power density in the devices becomes large, pulsed measurements were necessary to obtain reproducible results. A DCpulse with a certain bias voltage and pulse duration was applied and the photocurrent was integrated over one Power-Line-Cycle at the end of the pulse. Fig. 5 illustrates the impact of different pulse durations. Near breakdown voltage, longer pulse durations result in increased self-heating due to extended periods of high current densities inside the APD. Therefore, the breakdown voltage shifts to larger voltages due to the increased temperature, which in turn changes the operation point relative to the breakdown voltage (compare Fig. 4). This ultimately results in a decreased photocurrent. Due to capacitances in the measurement setup, the pulse duration could not be chosen to be arbitrarily short. Otherwise, the voltage would not be fully applied to the APD and the results obtained were not reproducible. Therefore, a compromise between the performance loss due to self-heating and the impact of capacitive effects of the measurement setup had to be found (Fig. 6).

ABSTRACT. The far-UVC band (200–240 nm) has garnered significant attention due to its unique advantages in germicidal applications and solar-blind detection [1–3]. Silicon carbide (SiC), a wide-bandgap semiconductor, has emerged as a suitable material for next-generation UV optoelectronics owing to its intrinsic radiation hardness, high thermal stability and spectral selectivity. Despite these merits, conventional epitaxial SiC photodetectors, particularly bipolar phototransistors (PTs), face critical limitations in far-UVC responsivity due to inefficient carrier collection at deep epitaxial junctions [4–6], where short-wavelength photons are strongly absorbed near the surface. To address this challenge, we designed four types of fully ion-implanted phototransistors with varying base-collector spacings and systematically investigated the influence of the base width (dce) on device performance. The corresponding optical images, cross-sectional structural diagrams and the relationship between incident optical power density and wavelength used during the testing process are presented in Fig. 1. The devices were fabricated on N-type 4H-SiC epitaxial layers with a doping concentration of 7×10¹⁵ cm⁻³ using a CMOS-compatible process flow. This included multiple ion implantation steps, high-temperature annealing, multi-layer metallization and dielectric layer formation. Considering the exponential attenuation of light within semiconductor materials, the doped region within the P-well was utilized as the collector. The final P-well doping concentration was approximately 1×10¹⁷ cm⁻³, while the emitter and collector regions exhibited doping concentrations around 2×10¹⁹ cm⁻³. Fig. 2(a) illustrates the spectral responsivity curves of the devices under identical optical excitation conditions (d4). It can be observed that as the base width decreases, the amplification capability of the devices improves. Notably, the device with dce = 1 μm exhibited the highest overall responsivity, reaching 100.7 A/W at 200 nm and 60.0 A/W at 240 nm, significantly outperforming other epitaxial-based SiC phototransistors reported in the literature. This result highlights the superior detection capability of ion-implanted structures in the far-UVC region. Additional figures compare the responsivity of different devices under varying optical wavelengths and excitation intensities. It is evident that phototransistors with narrower base widths demonstrate better amplification performance under weak illumination, whereas the performance difference among devices diminishes under stronger light intensities. Fig. 3(a) shows the dark current characteristics of the devices. Under a 4 V bias, the dark current levels for all devices are comparable, around the 10⁻¹¹ A range. Below 4 V, the dark current densities remain close, with the 2 μm spacing device exhibiting a slight advantage. Combined with the responsivity analysis, a trade-off relationship between dark current density and responsivity is identified. The key performance metrics of the phototransistors are summarized in Table 1. It can be seen that under low-light conditions, the device with dce = 1 μm achieves a superior detectivity of 33.4×1013 Jones, while under high illumination intensities, the device with dce = 2 μm demonstrates better detectivity. These results collectively demonstrate that careful optimization of the device structure, particularly the base width, plays a critical role in balancing responsivity, dark current and detectivity in ion-implanted SiC phototransistors. Our study offers important insights for the future design of high-performance photodetectors targeting the far-UVC spectral region.

[1] Li, Jiaqi, Zhou, Yue, Yi, Xiangyu, et al., Current Optics and Photonics 1, 196–202 (2017). [2] G. Wang, K. Wang, C. Gong, et al., IEEE Photonics J. 10, 1–13 (2018). [3] D. Guo, Y. Su, H. Shi, et al., ACS Nano 12, 12827–12835 (2018). [4] Y. Wang, W. Li, W. Xu, et al., IEEE Electron Device Lett. 45, 617–620 (2024). [5] Y. Wang, W. Li, D. Zhou, et al., IEEE Trans. Electron Devices 1–8 (2022). [6] C. Sun, H. Guo, L. Yuan, et al., IEEE Trans. Electron Devices 70, 2342–2346 (2023).

ABSTRACT. The objective of the proposed work was to investigate the electrical performance of a 250 µm-thick 4H-SiC p–n junction detector after irradiation with DT neutrons (14.1 MeV energy) at high temperature (500 °C). The results showed that the current–voltage (I–V) characteristics of the unirradiated SiC detector were ideal, with an ideality factor close to 1.5. A high electron mobility (µn) and built-in voltage (Vbi) were also observed. Additionally, the leakage current remained very low in the temperature range of 298–523 K. High-temperature irradiation caused a deviation from ideal behaviour, leading to an increase in the ideality factor, decreases in the µn and Vbi values, and a significant rise in the leakage current. Studying the capacitance–voltage (C–V) characteristics, it was observed that neutron irradiation induced reductions in both Al-doped (p+-type) and N-doped (n--type) 4H-SiC carrier concentrations. A comprehensive investigation of the deep defect states and impurities was carried out using deep-level transient spectroscopy (DLTS) in the temperature range of 85–750 K. In particular, high-temperature neutron irradiation influenced the behaviours of both the Z1/2 and EH6/7 traps, which were related to carbon interstitials, silicon vacancies, or anti-site pairs.

ABSTRACT. This work uses technology computer-aided design (TCAD) simulations to investigate heavy ion induced degradation and charge collection in Silicon Carbide devices under various irradiation conditions. The goal is to develop a physics-based understanding of the interaction between the response of the device after particle impact and the permanent degradation or damage of the device leading to increased single event leakage current (SELC). The 3D TCAD simulations are compared with irradiation experiments (Schottky diodes, MOS-devices). The simulations support the experimental result that not only linear energy transfer (LET) and range but also the bias voltage determine the onset of SELC. In the final contribution, the interplay of LET, range, and electric field is examined using an extensive matrix of TCAD simulations, providing a detailed overview of the effects and processes leading to degradation. Possible technology and design improvements are discussed.

ABSTRACT. In this paper, we show the electrical characteristics of lateral NMOSFET and PMOSFET in 4H-SiC CMOS technology with channel length and width of L=6µm and W=24µm, respectively, from 298K up to 773K. NMOSFET and PMOSFET output characteristics are shown, respectively, under strong inversion operation, i.e. VGS=20V, whereas their transfer characteristics are at |VDS|=0.1V. Observing the curves, it is evident that NMOSFET current tends to saturate with temperature, reaching a maximum at T=623K and, then, slightly decreases. This effect can be linked to two mechanisms. On one hand, the threshold voltage, VTH,N, reduces with temperature due to the increase of free carriers and to the release of charges from the interface traps. On the other hand, the electron mobility increases up to T=623K, reaching a maximum value of µCH,N=21cm^2/Vs, due to the reduction of Coulomb scattering mechanisms at the SiO2/4H-SiC interface, but it starts to reduce when carrier scattering with lattice vibrations becomes dominant, causing the current reduction for T>623K. These mechanisms could also explain the PMOSFET current behaviour, which tends to saturate at T=523K and then decreases. Indeed, a hole channel mobility peak is at T=523K, whit a value of µCH,P=8.25cm^2/Vs, whereas a reduction of VTH,P with temperature is observed in all temperature range. Channel resistance has been also extracted for both NMOSFET and PMOSFET polarized with VGS=20V in triode-like region, subtracting the parasitic resistance associated with drain and source implanted region in each temperature. In accordance with channel mobility behaviour, the channel resistance reaches a minimum at T=623K and T=523K for NMOSFET and PMOSFET, respectively, and then increases with the temperature. That implies an increase of the current with temperature and therefore possible self-heating effects that can lead to the thermal instability of the devices. However, it is also shown that there is a further increase of resistance at higher temperatures, which reduces the thermal-run-away of the current and allows to obtain a thermally stable device.

ABSTRACT. SiC MOSFETs excel in high frequency power switching because their wide bandgap and superior thermal conductivity minimize conduction and switching losses [1]. Replacing the conventional SiO₂ gate oxide for a higher k dielectric to enhance the device transconductance can also suppress interface trap density [2] and stabilize the threshold voltage (Vₜh) [2], though at the risk of higher gate leakage [3] and low Vth. However, the impact of the high-k gate dielectric on the dynamic performances is not yet fully explored. In this work, a SiC MOSFET with a SiN gate dielectric is demonstrated to outperform a reference MOSFET with SiO₂ gate oxide in both static and dynamic performance. First, the static properties of the two devices are compared. Fig. 1 shows the input capacitance (Ciss) vs. gate-source voltage (VGS) graph. Considering that the SiN film is made 62.5% thicker than the SiO2 layer, the higher Ciss exhibited by the SiN MOSFET is determined by its higher dielectric constant. This property leads to an improved inverse subthreshold slope (STS-1), as illustrated in Fig. 2. Moreover, the SiN MOSFET exhibits superior stability of the current-voltage characteristics, as displayed in Fig. 3. Second, the dynamic properties of the two devices are compared. During the MOSFET turn-on and turn-off processes, a significant amount of the switching losses is determined during the Miller Plateau phase, when the drain votage (VD) commutates, while the gate voltage (VG) keeps almost constant [1]. The time required for this transition is linearly dependent on the gate-drain component of the gate capacitance (CGD) [1]. Fig. 4 shows a simplified model of CGD, defined as the series combination of two terms, marked as Cox,dep and Cdep, where Cox,dep is determined by the charge modulation at the oxide/semiconductor interface, while Cdep arises from the charge modulation in the JFET and drift region [4]. The charge modulation in the JFET and drift region defines a depleted region width (wdep). Leveraging from the analytical equations derived in [1], a qualitative model was created to show how wdep changes at sufficiently high VD values for increasing dielectric constants, as shown in Fig. 5 (a). It is observed that a higher gate oxide capacitance induces a wider wdep, especially at lower VD voltages. Since wdep is inversely proportional to Cdep, it follows that a higher gate oxide capacitance induces a lower Cdep, as shown in Fig. 5 (b). Fig. 6 presents the CGD values experimentally measured for VGD swept from 10 to 800 V, for both the SiO2 and the SiN MOSFETs. For VD > 50 V, the CGD curve follows the same log-log trend indicated in the qualitative model shown in Fig. 5 (b). It is observed that the SiN split exhibits a 5 % lower CGD value on average in the VD range between 10 to 800 V. Fig. 7 presents the turn-on switching losses (Eon) measured for RG = 10, 20 and 40 Ω. The SiN MOSFET exhibits comparable losses at lower di/dt rates. About turn-off, the peak amplitude of the VGS oscillations (∆VGSpeak) was measured and plotted in Fig. 8 against the losses (Eoff). The SiN MOSFET exhibits lower ∆VGSpeak at lower Eoff. The voltage oscillations observed at the drain node with RG = 10 Ω are comparable in the two splits (VDS,peakSiO2 = 995 V and VDS,peakSiN = 1007 V). In conclusion, a 1.2 kV rated SiC vertical MOSFET incorporating a SiN gate dielectric was demonstrated to outperform a reference device with SiO2 gate oxide in switching performances, while also showing the expected STS-1 enhancement and better Vth stability. The reduced switching losses are attributable to the lower CGD shown by the SiN MOSFET for VGD > 10 V.

ABSTRACT. Electrical spin detection with the photocurrent detection of magnetic resonance (PDMR) is a key technique for room-temperature scalable integrated quantum device applications based on spin-active color centers, such as a nitrogen-vacancy (NV) center in diamond and a silicon vacancy in silicon carbide (SiC). PDMR was first demonstrated by using NV centers and developed to detect a single spin and its coherence of an NV center. For SiC, a more advanced semiconductor platform, PDMR detection of electron-spin coherence of ensemble silicon vacancies and nuclear-spin-resonance signal of their surrounding nuclear spins has been demonstrated. However, the PDMR readout of single spins in SiC has not yet been realized. In this study, we demonstrate the photoelectric coherent detection of a single silicon vacancy’s spin at room temperature. Also, we demonstrate the superior spin-readout efficiency with PDMR to the conventional optical spin-detection method, which has been previously predicted but not realized.

ABSTRACT. Spin center defect-based technologies in silicon carbide (SiC) have emerged as an important platform for solid-state quantum sensing applications which exhibit long coherence times [1] and susceptibility to magnetic [2-4], electric [5], and temperature fluctuations [6]. In regards to quantum sensing of magnetic fields, optical [2] and electrical readout capabilities [3-4] exist. Although optical readout usually offers superior sensitivity at the cost of optical components, magnetic field sensing using electrical readout is more attractive due to its simplicity, its ease of integration into electronic circuitry, and reduced size, weight, and power (SWaP). These sensors also have the ability to self-calibrate, a significant advantage over Hall-sensors, anisotropic magnetoresistance sensors, and fluxgate magnetometers. In electrical devices such as pn junctions, shallow-deep-level pairs allow for the manipulation of spin-dependent recombination (SDR) current channels across the depletion region with external fields. One promising spectroscopic tool used to read out the electrical response of these defect pairs to external fields is electrically detected magnetic resonance (EDMR).

In EDMR, an applied bias generates a nonequilibrium population of electrons and holes in the device active region; in the subsequent electron-hole recombination that produces SDR current a carrier is first captured by a shallow level defect and then by a deep level defect. A Pauli-spin blockade occurs depending on the resulting angular momentum selection rules that produces a bottleneck in the SDR current channel, which is relieved when one or both spins (deep and shallow) are resonantly flipping. In EDMR, an applied Zeeman magnetic field brings the energy levels of both spins into resonance with the applied oscillating magnetic field, relieving the bottleneck. This produces a characteristic change in the measured SDR current, as the conditions for magnetic resonance are determined by the spin Hamiltonian of the shallow-deep-level pair. Due to the complexity of this two-spin recombination mechanism, a detailed theory is necessary to inform future research directions into magnetic field sensor optimization.

Here we show the first quantitative theory for simulating the EDMR spectrum of silicon vacancy-related defect pairs in 4H-SiC with Lindblad equations and fit to a measured room-temperature spectrum attributed to silicon vacancies [4]. Importantly, we identify the shallow donor in the spin pair as a nitrogen-related silicon dangling bond complex [7] and link its formation to nitric oxide anneals, commonly used to attenuate the SDR response of silicon vacancies. We also simulate the EDMR spectra of V1 and V2 silicon vacancy-related defect pairs at low temperature, predicting the regime of device operation in which the underlying hyperfine structure becomes resolved. These results will motivate additional work exploring the effects of nitric oxide anneals on silicon vacancy-based magnetometer technology.

This material is based upon work supported by the Air Force Office of Scientific Research under award number FA9550-22-1-0308.

[1] M. Widmann et al., Nature Materials 14, 164-168 (2015). [2] K. Tahara et al., npj Quantum Information 11, 58 (2025). [3] A. Gottscholl et al., Scientific Reports 14, 14283 (2024). [4] C. J. Cochrane et al., Scientific Reports 6, 37077 (2016). [5] P. V. Klimov et al., Phys. Rev. Lett. 112, 087601 (2014). [6] H. Kraus et al., Scientific Reports 4, 5303 (2014). [7] E. Higa et al., Appl. Phys. Lett. 116 (17), 171602 (2020).

ABSTRACT. Color centers such as silicon vacancies (VSi) in 4H-SiC crystals are promising candidates for quantum sensing, communication and computing applications [1, 2]. Electric fields of pin-diodes (E||c) have been shown to reduce spectral diffusion and tune the resonant excitation and emission from color centers and thereby improve the optical properties of VSi [1]. Unlike commonly used 4H-SiC c-plane wafers, a-plane wafers allow a scalable fabrication of lateral pin-diodes (E||c) in a CMOS compatible process with convenient access to resonant excitation perpendicular to the VSi dipole moment, which aligns with the c-axis. This allows laser excitation of the VSi perpendicular to the wafer surface (a⊥c) and in-plane excitation using a waveguide aligned to the m-axis (m⊥a), supporting high scalability and co-integration of advanced electronics and photonics, which is a key step towards quantum photonic integrated circuits (QPICs) [2].

This work shows a CMOS-compatible process on 4H-SiC a-plane wafers for scalable production of lateral pin-diodes with optical access to VSi inside the intrinsic region. The lateral pin-diodes as shown in Fig. 1a were fabricated using a CMOS-compatible process [3] on 35 mm on-axis 4H-SiC a-plane substrates [4]. As reference, the same devices were also manufactured on 150 mm c-plane wafers. Two differently doped epitaxial layers for either standard power electronics (n-type) or quantum applications (i-type) were used (see Table I, top row). The 10 µm thick epitaxial layers were grown in an Aixtron G5 WW C planetary reactor. The correspondingly doped samples were fabricated in the same process. [4] The fully processed 4H-SiC a-plane wafer is shown in Fig. 1b, enabling scalability and allowing future on-chip integration of a wide range of additional devices and photonics. The VSi were generated via full area electron irradiation with a dose of 3E12 cm-2 with subsequent annealing at 600 °C for 30 min in vacuum. For room temperature measurements multiple chips with different design variations totaling to at least 300 pin-diodes on each wafer were investigated. Cryogenic measurements down to 4 K (using a closed-cycle cryostat from attocube) and optical measurements (using a commercial PL setup from SQUTEC) were conducted at selected representative devices.

The pin-diodes show a consistent electrical behavior across substrates (Fig. 1c). In forward regime the turn-on voltage is approximately 2 V followed by an exponential increase of the current until being limited by series resistance (see Table I) for higher voltages. Under reverse bias up to 200 V the measured current is still determined by the leakage current of the measurement setup, suggesting a low noise wide range optical tunability of the resonance frequency of VSi. The dielectric breakdown voltages, defined as the voltage, where the current exceeds 100 nA/µm, reach up to 350 V (Fig. 2a) and are in accordance with the theoretical principles [5] increasing with the length of the low doped region and decreasing with higher epitaxial layer doping. Ideality and series resistance of the pin-diodes show < 10% variation (see Table I). Combined with a production yield exceeding 97% for the n-type a-plane sample a stable and reproducible process is demonstrated. The variance in series resistance between the different samples mainly correlates with the availability of free charge carriers in the drift region determined by the doping of the different epitaxial layers.

At cryogenic temperatures, the turn-on voltage increases (Fig. 2b). This is explained by the need to re-ionize frozen-out charge carriers using the internal electric field [6], which results in a current jump into on-state as soon as sufficient voltage is applied. Reverse currents remain negligible and limited by the leakage current of the measurement setup at all temperatures. Electron irradiation and annealing have little influence on the I-V characteristic (not shown). The generated color centers are homogeneously distributed inside the pin-diode and its electrical field (Fig. 2c), allowing tuning of the optical properties. ODMR measurements at 300 K on the color centers reveal a contrast at 70 MHz (not shown), thus confirming successful creation of VSi.

In conclusion a CMOS-compatible process on 4H-SiC a-plane wafers for scalable production of lateral pin-diodes with optical access to VSi inside of the intrinsic region is demonstrated. The fabricated pin-diodes show excellent blocking characteristics, with breakdown voltages of up to 350 V and low reverse currents at room temperature and 4 K allowing a low-noise Stark tuning over a broad frequency range. This enables compensation of process-related variances in resonance frequency [7], thereby allowing entanglement of multiple color center qubits [2].

ABSTRACT. 4H-SiC does not only host favorable color centers for quantum applications, it also offers the opportunity to couple the relevant transitions to mechanical degrees of freedom, which provides, for example, opportunities for long-living quantum register on a SiC chip as integrated solution. SiC permits to display the possible highest quality factors, because the intrinsic damping is much lower than for any other material [1]. However, high quality factors imply narrow resonances, and a strategy is sought for matching the high quality-factors of the mechanical resonator to the frequency of the quantum degree of freedom such that spectral overlap will be achieved reliably. Previously, we proposed a tuning of the color center relying on Stark effect [2], which has excellent fine tuning capabilities, but a limited tuning range. We could recently demonstrate that an electrochemical etching strategy similar to previous results [3] can lead to monolithic nano/micromechanical oscillators of high quality, which are even stable upon annealing to 1500°C [4]. This is of utmost importance, because it allows annealing of the crystalline device and its surface, thus avoiding surface damping of the mechanical resonator. With these samples, a detailed analysis of the mechanical parameters became possible, in particular we could demonstrate that the bridges were essentially unstrained. Highest quality factors exceeding 200,000 were reported [5]. Here, we present experiments that demonstrate the tunability of nanomechanical resonators in a wide range. Starting from entirely unstrained material, we achieved a tuning of the cantilevers by bending the underlying SiC substrate, see sketch in Fig. 1(a) and optical image in Fig. 1 (b). Here, the monolithic architecture of our cantilevers is quite favorable, because the cantilevers can not relax strain by detachment, that has been reported for many other material stacks. The measurement was performed using a Laser-Doppler vibrometer that measures the oscillating frequencies at room temperature in a broad frequency range without explicit excitation (hence, under thermal excitation). Even on the first attempt, we could tune the resonance frequency, characterized by a Lorentzian in Fig. 2 (c), by more than one octave. Associated with building up strain, the dissipation is diluted and the quality factors that are associated to the width of the mechanical resonance are are rising by a factor of five, from 20,000 to over 100,000, see Fig. 1(d). The paper demonstrates that despite the requirement of sharp resonances, a spectral matching can be achieved by bending the substrate. The intricate interplay of mechanical strain and spin (quantum) degrees of freedom can now be exploited for unprecedented experiments and quantum applications.

ABSTRACT. Recently silicon carbide (SiC) has proven to offer physical properties which are not only advantageous for power electronics, but also for photonic applications like photocatalytic water splitting, fluorescent SiC, and waveguide applications. In this field of application, special SiC bulk materials exhibiting intrinsic properties and p-type doping are needed. In addition to 4H-SiC, also 3C-SiC and 6H-SiC are of importance. Close Space PVT (CS-PVT), which is a modification of standard PVT exhibiting a short source-to-seed-distance, enables a large variety of growth process variations to meet the specific requirements of the SiC material (i.e. special polytype and/or doping) to be grown. This for example enabled the bulk growth of 3C-SiC [1] which profits from a high supersaturation and a Si-rich gas phase composition. Indication for the high crystalline quality of CS-PVT grown hexagonal SiC was already proven in the early work of Syväjärvi and Yakimova [2, 3]. In this work, we study the growth of 4H-SiC p-i-n structures to be used as SiC solar cells for remote power transfer in space. Note: The presented growth method is also applicable for the fabrication of large area SiC wafers and p-/i-/n-layer stacks as used in power electronics. We used the CS-PVT method [4], which bridges the gap between the state-of-the-art bulk growth of SiC using the PVT method (boule thickness of 1-50 mm) and the chemical vapor deposition (CVD) of thin SiC films in the thickness range of ca. 1 to 100 µm. In addition to the SiC growth study, we will also introduce the newly developed TableTopCSTM growth machine which meets special requirements for advanced CS-PVT growth. While this work mainly shows results of 100mm 4H-SiC layers, growth cells of 150mm and 200mm CS-PVT are already applied in the lab. Scientifically we are addressing in this study (i) the achieved 4H-SiC polytype stability and (ii) new aspects of advanced p-type doping by aluminum which are possible in the ballistic mass transport regime of CS-PVT. The p-i-n structures were fabricated in two consecutive CS-PVT growth runs. As substrate we used 100 mm 4H-SiC wafers (4° off-axis) either C-face or Si-face oriented to carry out homoepitaxial nucleation and growth of 4H-SiC (figure 1), respectively. The growth temperature measured at the top of the CS-PVT growth cell was 1900°C (growth rate ca. 50 µm/h). The background gas pressure was < 0.1 mbar. In the first step nitrogen doped n-type or nominally undoped, quasi-intrinsic layers (either residual n-type or residual p-type) with a thickness of ca. 100 µm layer were deposited (growth time = 2 h). As indicated by the Raman spectroscopy study in figure 2, a high polytype stability is observed on both seed faces. In PVT growth above 2000°C it is standard to grow a 4H-SiC crystal on c-face seeds. However, Si-face seeding fails, because of a heteroepitaxial transition of the polytype to 6H-SiC and 15-SiC. Note: CVD growth of 4H-SiC performed at 1600 to 1700°C, however, is performed routinely on Si-face seed wafers. One important finding of this work is that 4H-SiC CS-PVT growth at 1900°C is possible on Si-face substrates making CS-PVT growth compatible with the SiC device processing routine (on Si-face substrates) exhibiting comparably high growth rates of 50 to 200 µm/h. Intentional p-type doping of the second thin top layer (growth time = 10 min) was performed by using aluminum doped solid 4H-SiC:Al and 6H-SiC:Al sources which were prepared by the M-PVT method [5]. In sublimation growth doping of SiC by aluminum is rather challenging because of the much greater partial pressure of the Al gas species compared to Si- and C-related gas species (i.e. Si, Si2C and SiC2). Without special emphasis like in the M-PVT growth process, it is basically impossible to obtain homogeneous dopant incorporation. CS-PVT, however, enables a new growth mode for advanced doping which makes use of ballistic mass transport. At a low background gas pressure of <0.1 mbar we showed earlier [6] that ballistic mass transport dominates the mass transport between the closely spaced SiC source and SiC seed (distance < 1mm). In such ballistic growth mode, the phenomenon of the partial pressure of atomic or molecular species does not exist and species are directly transported from source to seed. This kind of direct Al-transfer from source to seed was experimentally proven for two doping level regimes (see table I) and is the second important result of this work.. This work is funded by the European Union, Horizon Europe contract #101160868 (RePowerSiC).

[1] La Via, Zimbone, Bongiorno, La Magna, Fisicaro, Deretzis, Scuderi, Calabretta, Giannazzo, Zielinski, Anzalone, Mauceri, Crippa, Scalise, Marzegalli, Sarikov, Miglio, Jokubavicius, Syväjärvi, Yakimova, Schuh, Schöler, Kollmuss, Wellmann, Materials, 14, 18, 5348 (2021) [2] Syväjärvi, Yakimova, Glans, Henry, MacMillan, Johansson, Janzen, J.Crys.Growth 198 (1999) [3] Yakimova, Vouroutzis, Syväjärvi, Stoemenos, J.Appl.Phys. 98, 3, 034905 (2005) [4] Kollmuss, Schöler, Anzalone, Mauceri, La Via, Wellmann, Mat.Sci.For. 1062 (2022) [5] Wellmann, Desperrier, Mueller, Straubinger, Winnacker, Baillet, Blanquet, Dedulle, Pons, J.Crys. Growth, 275, 1-2, e555 (2005) [6] Hupfer, Hens, Kaiser, Jokubavicius, Syväjärvi, Wellmann, Mat.Sci.For.740 (2013)

ABSTRACT. Multi-wafer close-space sublimation (MCSS) has been proposed as a method for producing single-crystal SiC wafers, in which Si-C molecules sublimated from polycrystalline or sintered SiC substrates (source) recrystallize on substrates with a single-crystal SiC surface (seed). This process is carried out under uniform temperature, so that the driving force for the physical vapor transport (PVT) of Si-C molecules is not the temperature gradient, but the difference in equilibrium vapor pressure between the source and seed surfaces (ΔP). This allows simultaneous growth of SiC on multiple seed surfaces. At constant temperature, one of the factors determining ΔP is the grain size (dsource) of the source. To increase ΔP and achieve SiC growth on the seed surface, reducing dsource is effective. The SiC growth rate (rg) on the seed surface shows a positive correlation with the growth temperature (Tg). At Tg = 2200 °C, rg exceeds 10 μm/hour. The material transport efficiency (i.e. the ratio of the increase in seed weight to the decrease in source weight) exceeds 85%. This indicates a significant reduction in material loss.

ABSTRACT. A high-potential alternative to conventional SiC wafers consists in transferring a single-crystal thin film onto a polycrystalline SiC receiver fabricated by chemical vapor deposition (CVD), which must be thick, flat and highly thermally and electrically conductive [1]. To fulfill the last condition, nitrogen doping is necessary. Although in-situ nitrogen doping of polycrystalline SiC during CVD has been the subject of several work in the literature [2–6], it was restricted to a rather limited set of growth conditions (low temperature), hence the process-microstructure-composition relationship was only partially covered. In addition, the microstructure-composition-electrical properties relationship was not investigated in details. In this work, we aim at presenting new insights on these topics. To investigate the process-microstructure-composition relationship, CVD was conducted on flexible and rigid graphite substrates with a mix of methyltrichlorosilane (MTS), hydrogen (H2), and ammonia (NH3) in a vertical hot-wall lab-scale reactor which possesses a strong temperature gradient along its height (1100°C-1500°C), allowing us to explore multiple growth conditions in a single experiment. These local conditions (e.g. temperature) are obtained from modelling. The NH3/MTS ratio was adjusted as a way to modify the nitrogen content in the deposits. To further increase the high-throughput aspect of our approach, we deposited either single-layer or multi-layered deposits, with varying NH3/MTS during growth. Samples were then collected at different positions in the reactor for further characterization. Secondary ion mass spectrometry (SIMS) and X-ray photoelectron spectroscopy (XPS) were used to characterize the nitrogen content of the different samples, the latter also providing information on the nature of the chemical bonding. Owing to the high reactivity of NH3, high nitrogen content was reached (1019-1022 at.cm-3). Interestingly, while the solubility limit of nitrogen in SiC has been established at around 1020 at.cm-3, XPS showed that for any nitrogen content, nitrogen was always incorporated in substitution of carbon, without the apparition of a secondary Si3N4 phase, as confirmed with X-ray diffraction (XRD). Discussion on the solubility of nitrogen in polycrystalline 3C-SiC is then made. From the process-microstructure side, electron backscattered diffraction (EBSD) and X-ray diffraction (XRD) revealed that high amount of nitrogen could result in changes of grain size and preferential orientations in some growth conditions and notably led to the apparition of <100> orientation, which was never reported in the literature, in opposition to the common <111>, <110> and <211> orientation [7,8]. In case of multilayered samples with varying NH3/MTS ratio, this transition to <100> orientation with nitrogen was only observed for the first deposited layer and was shown to return to <111> orientation when NH3 supply was stopped. Then when NH3 was once again added, the apparition of the <100> orientation was not observed, but in such case, grain size and crystalline quality was strongly degraded, as confirmed by EBSD. These observations are discussed through the lens of polycrystalline SiC growth mechanisms. Then, based on the various samples produced, a qualitative relationship between grain size/crystalline quality, nitrogen content and electrical resistivity was established, notably by comparing the couple {resistivity - nitrogen content} for our samples with data from literature. The effect of grain size is then interpreted through the lens of Seto model [9], which stipulates that in doped semiconductor, grain boundaries act as traps for free charge carriers, affecting both their concentration and mobility. Going back to the applicative aspect of this work, resistivity of the order of 1 mOhm.cm were reached for as-deposited samples, whereas the lowest resistivity values found in the literature were around 10 mOhm.cm. This 10-fold reduction in the electrical resistivity of polycrystalline SiC deposits will further increase the efficiency of engineered substrates made from them.

ABSTRACT. The silicon vacancy in 4H-SiC is a promising candidate as a platform for future quantum networks, mainly due to their favourable spin and optical properties [1-2], and compatibility with integration in nanophotonic structures [3-5]. However, an open challenge is to enhance the emission of zero phonon line (ZPL) photons to increase the rate of entanglement generation between separated V2 defects. A viable method to enhance the optical properties of the V2 defect are 1d-nanobeam photonic crystal cavity (PCC). We present the ‘skyfish’ PCC, specifically designed for TM like modes because of the vertical electrical dipole orientation of the V2 defect in c-plane 4H-SiC. In order to efficiently couple to the cavity, we simulate a cavity-to-waveguide interface and collection efficiency through a tapered optical fiber. Together with the simulations, we show the fabrication process and experimental characterization of our PCCs in 4H-silicon-carbide-on-insulator [4], with quality factors up to ~40.000. Additionally, we demonstrate efficient transfer printing techniques that enable hybrid integration of 4H-SiC photonics with SiN photonics. Combining high quality factor PCCs in 4H-SiC with SiN photonics will open new opportunities for quantum networks and distributed quantum computation.

[1] Nagy, R. et al. Nature Communications. 10.1: 1-8. (2019) [2] Widmann, M. et al. Nature Materials. 14, 164–168 (2015) [3] Babin, C, et al. Nature Materials. 21, 67–73 (2022) [4] Lukin, D.M. et al. Nature Photonics. 14, 330–334 (2020) [5] Krumrein, M. et al. arXiv preprint.2401.06096 (2024)

ABSTRACT. Silicon carbide (SiC) has emerged as a promising material for integrated photonic devices in quantum information processing. Due to its exceptional physical and optical properties, SiC is gaining increasing attention as a scalable platform for quantum communication and networking. For instance, its wide transparency window from the visible to the mid-infrared range stems from its large bandgap. SiC also exhibits both second- and third-order optical nonlinearities, enabling nonlinear processes such as second-harmonic generation and Kerr comb formation. Furthermore, its high thermal conductivity and mechanical robustness make it ideal for applications in harsh environments and green technologies. Additionally, SiC supports a variety of color centers with desirable quantum properties, observed across multiple.

The National Institute of Standards and Technology (NIST) and Carnegie Mellon University (CMU) are collaborating to develop SiC-based devices for quantum communication applications. As part of this effort, we have demonstrated an integrated entangled photon source on a silicon-carbide-on-insulator (SiCOI) platform. In this work, Highly correlated photon pairs are efficiently generated at telecom C-band wavelengths using spontaneous four-wave mixing in a compact microring resonator fabricated on the 4H-SiCOI platform. The source achieves a maximum coincidence-to-accidental ratio (CAR) exceeding 600 at a pump power of 0.17 mW, corresponding to a pair generation rate of 9×10³ pairs/s. We created and verified energy-time entanglement, with two-photon interference fringes showing a visibility greater than 99%.

To ensure compatibility with current quantum networking infrastructure, we aligned the signal and idler photon wavelengths to standard DWDM ITU-grade channels. This enables seamless integration with quantum network testbeds such as NG-QNet (NIST Gaithersburg) and DC-QNet (Washington D.C. area). Moving forward, we aim to integrate additional functionalities, including quantum memories and quantum interfaces, into the same SiC platform. This effort will support the development of scalable, practical, and fully integrated quantum photonic devices for next-generation quantum communication networks.

ABSTRACT. Spin centers in crystals are considered prime candidates for the implementation of large-scale quantum networks. They combine conveyable quantum states encoded in light with the stability and storage capabilities of solid-state electron and nuclear spins. While historically diamond was the most promising host crystal, defects in silicon carbide (SiC) have recently emerged as a highly suitable platform for quantum devices, offering robust optical transitions, sufficiently long spin lifetimes and coherence. Particularly of interest are vanadium defects in silicon carbide, which exhibit optical transitions within the telecom band and therefore enable seamless integration with existing optical fiber networks. This removes the need for wavelength conversion, positioning them as an attractive platform for quantum nodes in quantum communication networks. Our investigations yield significant advances in understanding this remarkable system, the control of its electron spin, and the development of photonic interfaces for quantum networks. We show a significant extension of the spin lattice relaxation time (T1) of vanadium at cryogenic temperatures, of up to 25s at 100mK. The implantation of single vanadium defects has been successfully demonstrated and revealed spin-dependent optical transitions. We further investigate the electronic ground state structure by using strong radiofrequency oscillating magnetic fields at low temperatures. Here, we observe a severe influence of strain on the system Hamiltonian, altering the selection rules. To interpret the observed behavior, we employ a recently developed theoretical framework that describes the defect ground state under crystal strain. In this strained crystalline lattice, we show direct hyperfine transitions in the vanadium defect ground state. This opens new possibilities towards future state preparation and more robust encoding of quantum information.

References:

[1] P Koller, T Astner, et al., Phys Rev Materials, 9(4), L043201. (2025) [2] T. Astner, P. Koller, et al., Quantum Sci. Technol. 9 035038 (2024) [3] S. Ecker, et al., preprint arXiv:2403.03284 (2024) [4] P. Cilibrizzi, et al., Nat Commun 14, 8448 (2023) [5] B. Tissot et al., Phys. Rev. Research 4, 044107 (2022) [6] G. Wolfowicz, et al., Sci. Adv. 6, eaaz1192 (2020) [7] L. Spindlberger, et al., Phys. Rev. Applied 12, 014015 (2019)

ABSTRACT. Achieving reliable and reproducible breakdown performance in ultra-high-voltage (>10 kV) silicon carbide (SiC) power devices presents considerable challenges, particularly in the design of edge termination structures. These terminations must effectively suppress electric field crowding at the device periphery while simultaneously maintaining compactness and manufacturability. In such high-voltage devices, the epitaxial layer typically has a low background doping concentration (~4×1014 cm-3), which significantly impacts the lateral and vertical distribution of implanted dopants. This low background doping increases the lateral straggle during ion implantation, resulting in poor electric field control and requiring wider ring spacing in conventional floating field ring (FFR) structures [1]. Edge termination size becomes increasingly important for high-voltage devices above 10 kV, as it constitutes a large portion of the total chip area. As demonstrated in Fig. 1, in 10 kV-class SiC devices, the edge termination accounts for approximately 80% of the chip area in a 1 A-rated device and about 50% in a 10 A-rated device.

To overcome this limitation, this study proposes a novel edge termination scheme that reduces the lateral dopant straggle in the FFR structure by introducing a moderately doped N-type region – referred to as background doping modulation (BDM) – along with P+ ring implantation; the profile of the proposed implantations is shown in Fig. 2. This pre-doped region acts as a confinement layer, effectively reducing the effect of the lateral straggle during the P+ ring creation and enabling tighter spacing between floating rings [2]. As a result, more compact terminations can be achieved without compromising electric field control. Consequently, the total chip area can be significantly reduced which is critical advantage for ultra high-voltage devices. Notably, this additional N-type implantation can coincide with the JFET region in standard MOSFET process flows, allowing seamless integration of the proposed structure without adding process complexity. In the case of Schottky or JBS diodes, however, an additional implantation step would be required. It should be noted that the proposed BDM (Background Doping Modulation) FFRs do not require high energy implantation as the primary goal is to accomplish narrow spacing design between P+ concentric rings without increasing the electric field at their corners.

In this work, three edge termination designs were fabricated and evaluated: the proposed BDM FFRs (as shown in Fig. 3) and two conventional FFRs (FFR1 and FFR2 as shown in Fig. 4). BDM-FFR employed tighter ring spacing (0.8µm) with 100 rings, while FFR1 and FFR2 used wider spacings (1.0 µm and 1.5µm) and different numbers of rings as shown in Table I. Focused Ion Beam (FIB) SEM imaging (Fig. 5) confirmed that lateral dopant straggle was significantly suppressed in the BDM-FFR. Experimentally, as shown in Fig. 6, BDM-FFR achieved a breakdown voltage exceeding 13 kV—30% higher than conventional FFR devices which have a BV of 10kV. Moreover, the leakage current of BDM-FFR is maintained below 10 nA at 10kV. As for conventional FFRs, FFR1 exhibited a higher leakage current compared to FFR2 due to the insufficient ring separation (1µm instead of 1.5µm). Moreover, BDM-FFR structures reduced termination area by 18.6% compared to FFR1 and FFR2, offering a clear advantage in chip size efficiency for high-voltage integration. These findings provide valuable design guidance for implementing compact, scalable, and high-performance edge termination strategies in next-generation ultra-high-voltage SiC power devices.

Acknowledgement: We would like to thank Alexander Bialy and Cobert Johnson from NY CREATES for helping in taking FIB and SEM images in Fig. 5.

[1] J. Lynch et. al., 31st ISPSD, Shanghai, China, 223-226 (2019). [2] N. Yun et al., IEEE Transaction on Electron Devices (TED), 67 (10), 4346-4353, (2020).

ABSTRACT. The heavily nitrogen-doped N+ source region plays a pivotal role in minimizing contact resistance, which is critical for reducing conduction losses in 4H-SiC Power MOSFETs [1]. Consequently, the depth of the N+ source region emerges as a key design parameter influencing overall device specific on-resistance (Ron,sp). This study presents a comparative evaluation of the electrical characteristics of 1.2 kV rated 4H-SiC MOSFETs fabricated with 3 different N+ source depths, analyzed across both Linear MOSFET (Nominal) and Hexagonal (HEXFET) architectures (shown in Fig. 1(a) and (b), respectively). In this study, the two device types were fabricated on 3 separate 4H-SiC substrates, each incorporating a distinct N+ implantation profile. To distinguish between the variants, the N+ implant conditions will be referred according to their implantation depths: shallow, moderate, and deep. Implantation depths were acquired by systematically increasing the ion implantation energy across the three wafers while maintaining a constant implant dose. TCAD simulated cross-sections and SEM images of the fabricated Nominal devices are shown in Fig. 2(a) and 2(b), respectively. The vertical doping profiles extracted along the A–B cutline in Fig. 2(a) is shown in Fig. 3(a). The N+ junction depths are of approximately 0.16 µm, 0.19 µm, and 0.21 µm for the shallow, moderate, and deep implants, respectively. The lateral doping profiles along the C–D cutline, are presented in Fig. 3(b). These profiles reveal that the lateral extent of the N+ region also increases with implantation energy, primarily due to enhanced lateral ion straggle at higher energies. Transfer Length Method (TLM) structures were used to extract the contact resistance of the N+ implant on each wafer. A clear reduction in contact resistivity was observed with increasing implantation energy, yielding values of 3.91×10⁻5, 2.40×10⁻6, and 1.22×10⁻6  Ω·cm², respectively as seen in Fig. 4. The trade-off relationship between Ron,sp and threshold voltage (Vth), as well as between Breakdown Voltage (BV) and Vth, are illustrated in Fig. 5(a) and 5(b), respectively. As observed here, both Ron,sp and Vth exhibit a decreasing trend with increasing N+ source depth for both device types. For Nominal devices, the BV remains mostly above 1600 V under moderate and shallow N+ conditions; however, a noticeable degradation in BV (1465 V) is observed in deep N+ condition. The average values of electrical characteristics are summarized in Table 1. With HEXFET, the reduction in BV with increasing N+ depth is more impactful due to its higher channel density. The BV degradation is attributed to increased leakage current arising from the reduction in Vth, which is influenced by lateral straggle of Nitrogen ions. The lateral straggle shortens the effective channel length, as demonstrated by the reduced channel potential with increasing N+ depth shown in Fig. 6. Therefore, it is evident that although increasing the N+ depth contributes to the reduction of Ron,sp, it concurrently leads to elevated leakage current in the blocking state, thereby adversely impacting the BV. Fig. 7 depicts a successful effort to suppress the increased leakage current associated with the deep N+ condition by implementing an optimized JFET doping profile fabricated with a different wafer. This process modification led to an improvement in BV, increasing from 1465 V to 1560 V, though it also resulted in an increment of Ron,sp. Nonetheless, the results indicate potential for further optimization to reduce Ron,sp while maintaining low leakage current by enhancing the channel potential barrier. In conclusion, increasing the N+ junction depth is significantly effective in reducing contact resistance in 1.2 kV 4H-SiC power MOSFETs, however, it can also lead to an increase in leakage current during the blocking mode. Thus, simultaneous optimization of the P-well and JFET regions is proposed to achieve balanced performance in both conduction and blocking characteristics using the deep N+ implantation.

ABSTRACT. Silicon Carbide (SiC) Superjunction (SJ) technology presents a promising pathway for scaling unipolar devices beyond 3.3 kV, and addressing the challenge of high conduction losses at elevated temperatures caused by the increased resistance of thick drift layers [1]. GE has successfully demonstrated 3.5–5kV SiC SJ MOSFETs through multiple rounds of epitaxial regrowth and ultra-high-energy implantation [2-3]. These devices utilize n-type and p-type deep pillars formed using a tandem accelerator, which generates a multi-energy beam reaching up to 20 MeV for Aluminum (Al) and Nitrogen implantation. In this study, a new high-energy channeled implantation process using a commercial system from Axcelis [4] was evaluated as a viable alternative to tandem accelerator. This approach could enable deep implants, while preventing significant crystal damage. Commercially grown, 4° offcut, 150 mm SiC wafers with a 30 µm n-doped epitaxial layer received blanket on-axis Al channeled implantation using the Axcelis Purion EXE™ SiC Power Series high energy implant system. Precise sample alignment was achieved by measuring the wafer’s miscut angle using X-ray Diffraction (XRD), and adjusting the tilt along the [0001] axis towards [112̅0] direction. Al implantation was performed at 0.5 MeV and 5 MeV, with a fluence of 1×10¹³ cm⁻² at each energy. Fig.1 shows the Secondary Ion Mass Spectrometry (SIMS) analysis of the channeled implanted wafer from the center and edge regions, showing minimal dose variations and high uniformity across the wafer. The results confirm successful channeling at both energy levels, demonstrating accurate control of tilt and twist during implantation. Synchrotron X-ray topographic grazing incidence 22-4 16 contour maps of the un-implanted and channel implanted epiwafers were recorded with high penetration depth of 45µm [5] to image the entire epilayer thickness of 30µm. The contour map of the un-implanted epiwafer (Fig.2(a)) shows few broad contours indicating relatively low lattice distortion typical of high quality epiwafers. The microstructure of the epilayers (Fig. 2(c),(d)) consists of few micropipes, TMDs at 400-500 cm-2, TEDs at 500-600cm-2, few 3C inclusions mainly near the wafer edges and near complete conversion of substrate BPDs into TEDs in epilayer, is relatively unaffected by the implantation process. Fig.3 presents ultra-High resolution x-ray diffraction (HRXRD) analysis of the wafers before and after activation annealing at 1750 °C, using 9kW Cu rotating anode, collimating mirror, 4-bounce Ge(220) monochromator and high sensitivity 1d detector. Carbon cap formation and 1750 oC/10 min anneal was performed in custom chamber under positive argon pressure. HRXRD spectra shows narrower damage peaks, compared to conventional implantation [6], indicating lower crystal damage from the channeling process. Post-annealing at a moderate temperature of 1750 °C led to the disappearance of the defect peaks and complete lattice recovery. This was also confirmed using high-resolution asymmetric reciprocal space mapping. To calibrate channeling implantation models, ongoing efforts include simulations using the Sentaurus SProcess TCAD package. Fig.4 illustrates a comparison between simulation results, which shows good agreement with the SIMS data. Further refinement is underway to enhance the model by tuning various parameters such as electronic stopping power parameters and energy-dependent Debye temperature.

ABSTRACT. In SiC device roadmap, significant effort for next generation device is focused on superjunction (SJ) devices. Benefits of SJ are well known for silicon-based devices, and are currently being researched in SiC devices. However, the complexity in SiC manufacturing has limited the first demonstrations to manufacturing processes that are not industrially scalable, such as multi-epitaxial step [1], or not sufficiently controllable, such as trench etching followed by EPI-filling [2] or sidewall implant [3]. A promising path uses very high energy conventional implantation to form the SJ pillar [4], however this approach also presents limitations such as damage-induced [5], lateral straggle and the complexity of such very high energy equipment. These limitations can be mitigated by implantation in channeling to reduce induced damages, lateral straggle and increasing the projected ion range [6]. In this paper we describe the latest effort for industrialization of SJ devices, combining high energy ion implantation (over 10MeV) with this channeling approach. A schematic of the different approaches is presented in Figure 1. In the paper we describe the effort to develop this manufacturing process and report initial results. The new industrial process includes: (i) capability to do higher energy implant (over 10MeV) than historically available. (ii) capability to control ion channeling in SiC. (iii) ability to monitor post-implant to ensure the process control required is attained. We started from a high energy implant platform based on a LINAC (Linear Accelerator) beamline, established for silicon substrates [7] and modified for SiC. The accelerator beamline has a large ion energy range, reaching up to 14.5 MeV for Phosphorous and Aluminum energies up to approximately 12MeV with industry-compatible productivity. In Figure 2, we reported two examples of SIMS profile for middle range energy 5MeV 1×1013atm/cm2. Ion projected ranges reach up to ≈5μm, offering the possibility to form SJ in a single EPI-implantation cycle for MOSFET in sub-kV voltage class. In Figure 2 we also compare the experimental SIMS profiles with existing ion implantation models [8]. With the appropriate calibration, models can now predict with sufficient accuracy the channeling phenomena in SiC crystal. Applying the calibrated model, we determined the full spectrum of Aluminum and Phosphorus projected range that our platform can provide as a function of the energy with or without channeling conditions. Particularly as reported in Figure 3, at 12MeV the projected ranges for Aluminum and Phosphorous ions is respectively 4.5μm and 3.6μm in non-channeling, and 7μm and 6μm in channeling condition. This can be sufficient to form a full SJ of a 1.2kV MOSFET. Nevertheless, the complexity of channeling ions at these energies increases with a critical angle estimated at 0.11° [9]. To reach this level of accuracy we developed the capability to correct any wafer miscut measuring either by an integrated or a remote XRD system. The integrated system offers the ability to detect and correct errors down to < 0.02° within a few seconds, allowing errors from the wafer miscut to be corrected with minimal impact to productivity. Remote XRD system measurements are used to adjust implant angle, using a feed forward approach. The first experimental profiles are reported in Figure 2. Finally, to ensure sufficient repeatability for industrialization a method to monitor the process is required. Therma-Wave (TW) has been commonly used as empirical method to study implant-induced defectivity including for SiC. The intensity of the TW response signal has been directly correlated to defect concentration [10]. A significant difference in defect concentration has been reported between channeling and non-channeling conditions. Therefore, we anticipated a minimum defect concentration for perfect channeling conditions with a corresponding minimum TW response signal. The TW signal progressively increases with drifts away from the perfect channeling condition as the defect concentration rises. In Figure 4 we report both SIMS (Fig. 4.a), to confirm the best channeling conditions and variation induced by beam average angle variation and corresponding TW (Fig. 4.b). After a first feasibility demonstration, the study will show continuous improvement of a cost-effective industrialization process of SJ by single step using very high energy channeling implants. The process implies a very high energy implant adapted to SiC with wafer miscut correction capability, and high angle control accuracy with associated methods to monitor the process repeatability.

[1] Kosugi, Ryoji, et al. Materials Science Forum. Vol. 778. Trans Tech Publications Ltd, 2014. [2] Harada, S., et al. 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018. [3] Tian, Run, et al. Journal of Semiconductors 42.6 (2021): 061801. [4] Ghandi, Reza, et al. IEEE Electron Device Letters (2025).. [5] Belanche, Manuel, et al. Materials Science in Semiconductor Processing 179 (2024): 108461. [6] Scholze, Andreas, et al. Solid State Phenomena 359 (2024): 47-51. [7] Satoh, Shu, et al. MRS Advances 7.36 (2022): 1490-1494. [8] Tomoaki Nishimura, scatGUI,ion implantation & channeling simulation software [9] R.B. Simonton, et al., Chapter 7, ed. Ion implantation science and technology. Elsevier, 2004. [10] Mazzamuto, Fulvio, et al. Solid State Phenomena 359 (2024): 21-28.

ABSTRACT. In this work the power cycling capability of 7 different SiC MOSFET designs in TO-247 package are assessed. All designs were tested at least at three different temperature swings between 60K and 120K to derive the relationship between the temperature swing and power cycling lifetime for all tested designs. The data was used to compare the lifetime of different SiC MOSFET design and derive possible impact factors. The test results show, that even though all devices have similar electrical ratings, they show significantly different power cycling performances and that the chip thickness is a major impact factor. Furthermore, two design exhibit a much higher lifetime than predicted by the fitted lifetime curve at low temperature swings of 60K and below. Thus, the power cycling capability of discrete SiC MOSFETs must be thoroughly assessed for each device design and experiences from other designs are not generally transferrable.

ABSTRACT. Short-circuit (SC) events in Silicon Carbide (SiC) power MOSFETs are very critical failure cases, which may arise e.g. in motor drives systems. In such SC events, the MOSFETs are subjected to extreme electrical and thermal stress, possibly operating outside their safe operating area (SOA). Therefore, it is critical for SiC MOSFETs to possess enough robust short-circuit withstand capability, until the external protection circuitry turns-off the SC safely. In this work, the SC robustness limit of 1200 V rated SiC MOSFETs from two different manufacturers (M1 and M2) were studied up to the destruction limit. Further, dominant failure mechanisms should be described. Both devices are packaged in TO-247 4-pin configuration and exhibited a nominal on-state resistance (RDS,on) of 80 mΩ. The gate technology of the M1 device is a planar-gate and an asymmetric trench-gate for the M2 device. In addition to evaluating the SC withstand capability, the study also systematically examined the influence of the negative gate-source voltage (VGS,off) on the SC robustness. All SC measurements were performed at a positive gate-source voltage (VGS,on) of 15 V and a fixed DC-link voltage of 800 V. The SC capability was determined by gradually increasing the pulse width duration (tSC) in steps of 100 ns for a fixed VGS and DC-link voltage. To determine their robustness limit, the measurements were carried out until the destruction of the DUTs or a strong drift in the electrical parameters such as gate leakage current (IGSS), loss of blocking capability or increased drain-source leakage current (IDSS) is detected, which indicate damage in the device.

ABSTRACT. Bipolar degradation (BD) is caused by the carrier recombination induced propagation of Shockley-type stacking faults (SSFs) from basal plane dislocations in epitaxial layers of 4H-SiC power devices. SSFs increase the material resistance, leading to forward voltage (VF) drift (ΔVF), limiting reliability in high-voltage applications [1]. Evaluation of BD can be performed using various protocols with stress times ranging from a few µs to min, and current densities varying from 100 to almost 10000 A.cm-2. The impact of high current densities on BD has already been reported [2], but to enable a fair comparison of different test protocols and materials, we investigate how the BD dynamics is impacted by the stress-test conditions and parameters, namely load current (IL), effective pulse duration (ton), maximum temperature during the pulse (Tmax) and accumulated injected charge (Qinj). For this purpose, we used bare PiN diode dies (1200V/10A) soldered on direct bonded copper substrates (solder paste SAC- 305). The front side was connected by an Al Bonded Wire (BW). Stress was performed using either millisecond Power Cycling pulses ("PCmsec" test setup developed by Fraunhofer IISB [3], test conditions in Table I and toff =110 ms for cooling), or long, DC-like, pulses (PCDC, test conditions in Table II and toff =200 ms). Special care needs to be taken to properly conduct the study. To evaluate the injected charge per cycle, the current rise time should be accounted for to properly determine ton (Fig. 1). Then Qinj can be computed as ton x IL x number of cycles. During aging, ΔVF is impacted not only by BD but also by BW degradation, as illustrated in Fig. 2. Post stress ΔVF appears larger when measured using the degraded BW (dashed green curve) than under Kelvin probe (KP) measurement (red curve). We are currently implementing a setup to perform in-situ KP measurements during the stress tests. Tmax depends on IL as well as on ton. We evaluated the impact on Tmax of increasing ton from 300 to 500µs at the highest IL of 30A. The induced 15°C increase in Tmax (Fig. 3) has little impact on ΔVF vs. Qinj, for low Qinj (Fig. 4). Please note that ΔVF exhibits a logarithmic dependence on Qinj. For higher Qinj (around 1000C on Fig. 4), an acceleration of the drift is observed, that we feel could come from either the BW degradation of the development of additional SSF. Discrimination between those hypotheses will be allowed by our in-situ KP setup. The dependence on IL of ΔVF vs. Qinj is represented on Fig. 5 for PCmsec and Fig. 6 for PCDC. Two distinctive features are seen on Fig. 5: (i) the onset of VF drift appears at larger Qinj for higher IL and (ii) the logarithmic VF drift rate (ΔVF per decade of Qinj) increases with IL. While the latter appears straightforward (faster degradation under stronger stress), we do not explain the former (delayed degradation under stronger stress). The PCDC results from Fig. 6 seem consistent with (ii). The inset in Fig. 6 represents the VF drift rate (in % per decade) for both PCDC (triangles) and PCmsec (circles). The 2 sets of data sit on different curves though, demonstrating that another parameter plays a part in the drift rate. The PCDC results from Fig. 6 are not consistent with (i), suggesting that the onset of VF drift is likely linked to material parameters such as initial defect nature and size. To refine our findings, ΔVF vs. Qinj measurements, void of BW degradation impact (in-situ KP setup) will be presented at the conference and included in the full paper, allowing a unique monitoring of the evolution of BD during the stress.

[1] P. Bergman et al., MSF 2001;353–356:299–302. [2] N. Hatta et al., KEM 2023;948:107–13., doi: 10.4028/p-628fu5. [3] S. Laha et al., CIPS 2024; 13th International Conference on Integrated Power Electronics Systems, Düsseldorf, Germany, 2024, pp. 619-624.

ABSTRACT. Silicon carbide is a promising material for low-loss and high-voltage automotive power devices, and long-term reliability is important for practical application. Generally, current conduction through the body diode embedded in a SiC MOSFET can cause the bipolar degradation phenomenon. Recently, it has been reported that both bipolar degradation and epi-carrier lifetime vary depending on the substrate vendor, even under the same epitaxial growth conditions, highlighting the importance of substrate quality.In this study, we evaluated the temperature dependence of substrate carrier lifetime for different substrate vendors, and the defect density, energy levels, and capture cross-sections of killer defects were systematically explored. As a result, it was cleared that substrates with carrier lifetimes limited by a killer defect known as the D-Center can suppress the expansion of single Shockley stacking faults. Understanding the impacts of substrate carrier lifetime on the bipolar degradation phenomenon is important for improving the reliability of SiC power devices.

ABSTRACT. This study proposes a non-destructive method to predict the reliability of silicon carbide (SiC) MOSFETs by analyzing initial threshold voltage (Vth) characteristics. Due to charge trapping issues that affect long-term reliability, early detection is essential. This study statistically analyzes initial threshold voltage (Vth) characteristics and their relationship with device degradation. We used 133 SiC MOSFET samples fabricated on AIST’s pilot production research line. Prior to reliability testing, we measured the gate voltage-drain current (Vgs-Id) characteristics using the triple-sense measurement method to minimize instability in Vth measurement caused by charge trapping. Six Vth-related features were extracted and analyzed using principal component analysis (PCA). The first two principal components (PC1 and PC2) accounted for 94.9% of data variance. PC2, reflecting short-time trapping, enabled identification of a minority group of samples. Seventeen samples were selected for gate stress testing. A regression model using PC1, PC2, stress time, and tbottom (time to max negative Vth shift) showed high predictive accuracy (R² = 0.977). PC2 and tbottom were key factors. This approach enables early, data-driven screening of SiC MOSFETs using only initial measurements, offering a scalable method for assessing device reliability without prolonged testing.