ABSTRACT. As emerging technologies and the fast-evolving e-mobility reshape our future, the global shift toward electric vehicles and sustainable transportation is accelerating a transformation that merges information, energy, and mobility. In this landscape, semiconductors are no longer limited to computing and data storage – they are becoming the essential building blocks of intelligent, connected systems.

However, this transformation also reveals the limitations of traditional silicon-based power devices, which struggle to meet the growing demands for efficiency, voltage, and reliability. To break through these physical and performance barriers, the industry is shifting toward wide bandgap materials such as Silicon Carbide (SiC) and Gallium Nitride (GaN), the key enablers of higher thermal performance and system-level reliability in EVs and industrial power systems. Although wide bandgap technologies have matured significantly in the past decades, continued innovations are still needed to meet the growing demands for enhanced performance, robustness, and long-term reliability under harsh environments. To address these challenges, it will be critical to secure advanced process capability, manufacturing infrastructure and stringent quality management for stable and scalable production of next-generation power semiconductors.

Samsung, with over three decades of global leadership in semiconductors, is now extending its vision toward the frontier of power devices. Leveraging its deep expertise in materials innovation, process excellence, and manufacturing scale, Samsung is stepping forward to expand the boundaries of what’s possible in next-generation power technologies.

In this Plenary Lecture, Hong will explore key industry trends and outline Samsung’s vision for power device solutions including its strategy for SiC technology that features proactive exploration of 300mm wafer platforms and advancements in super-junction MOSFETs. While the transition from 150mm to 200mm wafers is still ongoing, recent developments suggests that the shift to 300mm may happen faster than previous transitions. This acceleration, driven by collective advances in materials and process technologies, could pave the way for enhanced scalability and cost-effectiveness in SiC, with growing momentum across the ecosystem pointing toward broader and more accelerated adoption.

As the industry moves toward scaling SiC technology, success will hinge on investment capacity, manufacturing maturity, and deep expertise—factors that will define the next wave of leadership in power semiconductors. Samsung is aligning its full-stack capabilities as an IDM, from device design to mass production, backed by robust quality assurance, localized supply chains, and system-level optimization. With this comprehensive approach, Samsung is set to become a true end-to-end solution provider, ready to shape the future of e-mobility and beyond.

ABSTRACT. We investigated basal plane dislocation (BPD) behaviors in physical vapor transport (PVT) grown 4H-SiC crystals, focusing on the interaction between BPDs and point defects through photoluminescence (PL) imaging of BPDs. We observed spatially diffuse PL emission around BPDs in 4H-SiC crystals grown by the PVT growth method. The emission showed a characteristic wavelength and thus was likely to originate from some type of point defects in the crystals. This result suggests the formation of Cottrel atmosphere around BPDs via the interaction of BPDs with point defects in PVT-grown 4H-SiC crystals.

ABSTRACT. Silicon carbide (SiC) is a promising wide-bandgap semiconductor for power electronic devices, where excess carriers from doping and operation can influence mechanical reliability. Electrical stimuli are known to affect mechanical behavior, exemplified by recombination-enhanced dislocation glide (REDG) and enhanced material removal in electrochemical mechanical polishing (ECMP). Understanding these effects is crucial for device advancement. This study investigates how excess carriers affect the elastic constants and ideal strength of SiC using first-principles calculations. Building on our previous work on group IV diamond-structured materials, we extend the analysis to 3C-, 2H-, and 4H-SiC. We analyzed tensile deformation along [0001] and shear deformation along [-1100] on the (11-20) plane. Results show that elastic constants decrease with increasing carrier density, indicating softening. Tensile strength decreased with electron injection and increased with hole injection, with ~20% change at 5 × 10^21 cm^-3. In contrast, shear strength responses varied: 3C-SiC followed Si trends, while 2H- and 4H-SiC showed decreases for both carrier types. These findings highlight the carrier-induced softening mechanisms and provide insight into REDG and material processing improvements.

ABSTRACT. SiC power devices are manufactured using expensive SiC substrates, with significant material loss occurring during the grinding process, which increases both costs and environmental impact. A wafer reuse method utilizing laser slicing instead of grinding has been proposed, enabling multiple uses of a single wafer. This study investigates the effects of laser slicing on 1200 V SiC Junction Barrier Schottky (JBS) diodes. The results show that at specific laser power levels and focal distances, the diodes' characteristics remain unaffected. However, at shallow focal distances, the breakdown voltage decreases due to the laser beam. From our data, proper laser settings make this method practical for wafer thinning.

ABSTRACT. Body diode reliability and reverse recovery characteristics of SiC-SJ-MOSFET whose p-columns was short, tapered and formed by deep Al ion implantation (MeV-SJ) was investigated in comparison with that of conventional Multiepi-SJ. The short tapered p-column of MeV-SJ causes soft reverse recovery.The body diode of MeV-SJ exihited higher reliability than that of Multiepi-SJ in spite of shorter p-columns. The PL images of stacking faults (SFs) suggest that the expansion of SFs would be stopped in the buffer layer of MeV-SJ.

ABSTRACT. Ultraviolet (UV) radiation has a wide application field reaching from scientific applications such as astronomy [1] and the detection of chemical and biological molecules [2] to civil uses such as water purification [3] and flame monitoring [4]. In many of these applications the detectors must detect only weak UV signals. A semiconductor-based solution can be avalanche-photodiodes (APDs), which provide an internal gain over classical photodiodes. Especially silicon carbide (SiC) yields advantages for the detection of UV radiation such as a wide bandgap resulting in a cutoff-wavelength of around 380 nm. Longer wavelengths can therefore not be detected by SiC-APDs. This property is often referred to as visible blindness. A more challenging property of SiC for the usage as an APD is its high electrical breakdown field strength. To prevent high operation voltages a so called SACM (separate absorption, charge and multiplication) [5] device was fabricated. Despite the reduction of the operating voltage due to the SACM design, the power density in the diodes is so high that self-heating of the APDs causes challenges in the characterization of the spectral responsivity under applied bias. The APDs were fabricated on highly conductive commercial n-type 4H-SiC substrates with an epitaxially grown layer stack (Fig. 1). The targeted doping profile of the epitaxial layer stack was validated via secondary ion mass spectroscopy (SIMS, Fig. 2). A so-called bevel edge termination was applied for the fabrication of the APDs to suppress electric field crowding at the surface of the device (Fig. 1) [6]. At the top of the bevel the diodes have a diameter of 500 μm. The devices were passivated with thermally grown oxide and oxide deposited by Low Pressure Chemical Vapor Deposition of Tetraethylorthosilicat (LPCVD-TEOS). Ohmic contacts were formed at the highly p-doped front side and the backside of the n-type substrate. For probing, contact pads were structured out of aluminum. To validate the functionality of the SiC-APDs, current-voltage characteristics in the dark and under illumination were measured (Fig. 3). The APDs exhibit a breakdown voltage V_BD of roughly 150 V (I(V_BD) = 10 μA). The dark current stays below 50 pA before reaching the breakdown voltage, which implies a sufficient suppression of surface leakage currents. To investigate the impact of the temperature on the devices and to validate, that the breakdown is indeed due to the avalanche effect, the dark current was measured for various temperatures (Fig. 4). The increased dark current could be explained by the increasing amount of thermally generated charge carriers. Fig. 4 also shows that the breakdown voltage increases with temperature. This indicates that the breakdown of the devices is caused by the avalanche effect: Due to increased interaction between phonons and charge carriers the mean free path of the charge carriers decreases, such that higher electrical fields are necessary to yield enough energy for the process of impact ionization [7]. To analyze the wavelength dependent response of the APDs, the spectral responsivity was measured as a function of the applied bias. However, the measured results are strongly dependent on the measurement parameters used for the characterization. Especially at higher bias voltages, where the power density in the devices becomes large, pulsed measurements were necessary to obtain reproducible results. A DCpulse with a certain bias voltage and pulse duration was applied and the photocurrent was integrated over one Power-Line-Cycle at the end of the pulse. Fig. 5 illustrates the impact of different pulse durations. Near breakdown voltage, longer pulse durations result in increased self-heating due to extended periods of high current densities inside the APD. Therefore, the breakdown voltage shifts to larger voltages due to the increased temperature, which in turn changes the operation point relative to the breakdown voltage (compare Fig. 4). This ultimately results in a decreased photocurrent. Due to capacitances in the measurement setup, the pulse duration could not be chosen to be arbitrarily short. Otherwise, the voltage would not be fully applied to the APD and the results obtained were not reproducible. Therefore, a compromise between the performance loss due to self-heating and the impact of capacitive effects of the measurement setup had to be found (Fig. 6).

ABSTRACT. The far-UVC band (200–240 nm) has garnered significant attention due to its unique advantages in germicidal applications and solar-blind detection [1–3]. Silicon carbide (SiC), a wide-bandgap semiconductor, has emerged as a suitable material for next-generation UV optoelectronics owing to its intrinsic radiation hardness, high thermal stability and spectral selectivity. Despite these merits, conventional epitaxial SiC photodetectors, particularly bipolar phototransistors (PTs), face critical limitations in far-UVC responsivity due to inefficient carrier collection at deep epitaxial junctions [4–6], where short-wavelength photons are strongly absorbed near the surface. To address this challenge, we designed four types of fully ion-implanted phototransistors with varying base-collector spacings and systematically investigated the influence of the base width (dce) on device performance. The corresponding optical images, cross-sectional structural diagrams and the relationship between incident optical power density and wavelength used during the testing process are presented in Fig. 1. The devices were fabricated on N-type 4H-SiC epitaxial layers with a doping concentration of 7×10¹⁵ cm⁻³ using a CMOS-compatible process flow. This included multiple ion implantation steps, high-temperature annealing, multi-layer metallization and dielectric layer formation. Considering the exponential attenuation of light within semiconductor materials, the doped region within the P-well was utilized as the collector. The final P-well doping concentration was approximately 1×10¹⁷ cm⁻³, while the emitter and collector regions exhibited doping concentrations around 2×10¹⁹ cm⁻³. Fig. 2(a) illustrates the spectral responsivity curves of the devices under identical optical excitation conditions (d4). It can be observed that as the base width decreases, the amplification capability of the devices improves. Notably, the device with dce = 1 μm exhibited the highest overall responsivity, reaching 100.7 A/W at 200 nm and 60.0 A/W at 240 nm, significantly outperforming other epitaxial-based SiC phototransistors reported in the literature. This result highlights the superior detection capability of ion-implanted structures in the far-UVC region. Additional figures compare the responsivity of different devices under varying optical wavelengths and excitation intensities. It is evident that phototransistors with narrower base widths demonstrate better amplification performance under weak illumination, whereas the performance difference among devices diminishes under stronger light intensities. Fig. 3(a) shows the dark current characteristics of the devices. Under a 4 V bias, the dark current levels for all devices are comparable, around the 10⁻¹¹ A range. Below 4 V, the dark current densities remain close, with the 2 μm spacing device exhibiting a slight advantage. Combined with the responsivity analysis, a trade-off relationship between dark current density and responsivity is identified. The key performance metrics of the phototransistors are summarized in Table 1. It can be seen that under low-light conditions, the device with dce = 1 μm achieves a superior detectivity of 33.4×1013 Jones, while under high illumination intensities, the device with dce = 2 μm demonstrates better detectivity. These results collectively demonstrate that careful optimization of the device structure, particularly the base width, plays a critical role in balancing responsivity, dark current and detectivity in ion-implanted SiC phototransistors. Our study offers important insights for the future design of high-performance photodetectors targeting the far-UVC spectral region.

[1] Li, Jiaqi, Zhou, Yue, Yi, Xiangyu, et al., Current Optics and Photonics 1, 196–202 (2017). [2] G. Wang, K. Wang, C. Gong, et al., IEEE Photonics J. 10, 1–13 (2018). [3] D. Guo, Y. Su, H. Shi, et al., ACS Nano 12, 12827–12835 (2018). [4] Y. Wang, W. Li, W. Xu, et al., IEEE Electron Device Lett. 45, 617–620 (2024). [5] Y. Wang, W. Li, D. Zhou, et al., IEEE Trans. Electron Devices 1–8 (2022). [6] C. Sun, H. Guo, L. Yuan, et al., IEEE Trans. Electron Devices 70, 2342–2346 (2023).

ABSTRACT. The objective of the proposed work was to investigate the electrical performance of a 250 µm-thick 4H-SiC p–n junction detector after irradiation with DT neutrons (14.1 MeV energy) at high temperature (500 °C). The results showed that the current–voltage (I–V) characteristics of the unirradiated SiC detector were ideal, with an ideality factor close to 1.5. A high electron mobility (µn) and built-in voltage (Vbi) were also observed. Additionally, the leakage current remained very low in the temperature range of 298–523 K. High-temperature irradiation caused a deviation from ideal behaviour, leading to an increase in the ideality factor, decreases in the µn and Vbi values, and a significant rise in the leakage current. Studying the capacitance–voltage (C–V) characteristics, it was observed that neutron irradiation induced reductions in both Al-doped (p+-type) and N-doped (n--type) 4H-SiC carrier concentrations. A comprehensive investigation of the deep defect states and impurities was carried out using deep-level transient spectroscopy (DLTS) in the temperature range of 85–750 K. In particular, high-temperature neutron irradiation influenced the behaviours of both the Z1/2 and EH6/7 traps, which were related to carbon interstitials, silicon vacancies, or anti-site pairs.

ABSTRACT. This work uses technology computer-aided design (TCAD) simulations to investigate heavy ion induced degradation and charge collection in Silicon Carbide devices under various irradiation conditions. The goal is to develop a physics-based understanding of the interaction between the response of the device after particle impact and the permanent degradation or damage of the device leading to increased single event leakage current (SELC). The 3D TCAD simulations are compared with irradiation experiments (Schottky diodes, MOS-devices). The simulations support the experimental result that not only linear energy transfer (LET) and range but also the bias voltage determine the onset of SELC. In the final contribution, the interplay of LET, range, and electric field is examined using an extensive matrix of TCAD simulations, providing a detailed overview of the effects and processes leading to degradation. Possible technology and design improvements are discussed.

ABSTRACT. In this paper, we show the electrical characteristics of lateral NMOSFET and PMOSFET in 4H-SiC CMOS technology with channel length and width of L=6µm and W=24µm, respectively, from 298K up to 773K. NMOSFET and PMOSFET output characteristics are shown, respectively, under strong inversion operation, i.e. VGS=20V, whereas their transfer characteristics are at |VDS|=0.1V. Observing the curves, it is evident that NMOSFET current tends to saturate with temperature, reaching a maximum at T=623K and, then, slightly decreases. This effect can be linked to two mechanisms. On one hand, the threshold voltage, VTH,N, reduces with temperature due to the increase of free carriers and to the release of charges from the interface traps. On the other hand, the electron mobility increases up to T=623K, reaching a maximum value of µCH,N=21cm^2/Vs, due to the reduction of Coulomb scattering mechanisms at the SiO2/4H-SiC interface, but it starts to reduce when carrier scattering with lattice vibrations becomes dominant, causing the current reduction for T>623K. These mechanisms could also explain the PMOSFET current behaviour, which tends to saturate at T=523K and then decreases. Indeed, a hole channel mobility peak is at T=523K, whit a value of µCH,P=8.25cm^2/Vs, whereas a reduction of VTH,P with temperature is observed in all temperature range. Channel resistance has been also extracted for both NMOSFET and PMOSFET polarized with VGS=20V in triode-like region, subtracting the parasitic resistance associated with drain and source implanted region in each temperature. In accordance with channel mobility behaviour, the channel resistance reaches a minimum at T=623K and T=523K for NMOSFET and PMOSFET, respectively, and then increases with the temperature. That implies an increase of the current with temperature and therefore possible self-heating effects that can lead to the thermal instability of the devices. However, it is also shown that there is a further increase of resistance at higher temperatures, which reduces the thermal-run-away of the current and allows to obtain a thermally stable device.

ABSTRACT. SiC MOSFETs excel in high frequency power switching because their wide bandgap and superior thermal conductivity minimize conduction and switching losses [1]. Replacing the conventional SiO₂ gate oxide for a higher k dielectric to enhance the device transconductance can also suppress interface trap density [2] and stabilize the threshold voltage (Vₜh) [2], though at the risk of higher gate leakage [3] and low Vth. However, the impact of the high-k gate dielectric on the dynamic performances is not yet fully explored. In this work, a SiC MOSFET with a SiN gate dielectric is demonstrated to outperform a reference MOSFET with SiO₂ gate oxide in both static and dynamic performance. First, the static properties of the two devices are compared. Fig. 1 shows the input capacitance (Ciss) vs. gate-source voltage (VGS) graph. Considering that the SiN film is made 62.5% thicker than the SiO2 layer, the higher Ciss exhibited by the SiN MOSFET is determined by its higher dielectric constant. This property leads to an improved inverse subthreshold slope (STS-1), as illustrated in Fig. 2. Moreover, the SiN MOSFET exhibits superior stability of the current-voltage characteristics, as displayed in Fig. 3. Second, the dynamic properties of the two devices are compared. During the MOSFET turn-on and turn-off processes, a significant amount of the switching losses is determined during the Miller Plateau phase, when the drain votage (VD) commutates, while the gate voltage (VG) keeps almost constant [1]. The time required for this transition is linearly dependent on the gate-drain component of the gate capacitance (CGD) [1]. Fig. 4 shows a simplified model of CGD, defined as the series combination of two terms, marked as Cox,dep and Cdep, where Cox,dep is determined by the charge modulation at the oxide/semiconductor interface, while Cdep arises from the charge modulation in the JFET and drift region [4]. The charge modulation in the JFET and drift region defines a depleted region width (wdep). Leveraging from the analytical equations derived in [1], a qualitative model was created to show how wdep changes at sufficiently high VD values for increasing dielectric constants, as shown in Fig. 5 (a). It is observed that a higher gate oxide capacitance induces a wider wdep, especially at lower VD voltages. Since wdep is inversely proportional to Cdep, it follows that a higher gate oxide capacitance induces a lower Cdep, as shown in Fig. 5 (b). Fig. 6 presents the CGD values experimentally measured for VGD swept from 10 to 800 V, for both the SiO2 and the SiN MOSFETs. For VD > 50 V, the CGD curve follows the same log-log trend indicated in the qualitative model shown in Fig. 5 (b). It is observed that the SiN split exhibits a 5 % lower CGD value on average in the VD range between 10 to 800 V. Fig. 7 presents the turn-on switching losses (Eon) measured for RG = 10, 20 and 40 Ω. The SiN MOSFET exhibits comparable losses at lower di/dt rates. About turn-off, the peak amplitude of the VGS oscillations (∆VGSpeak) was measured and plotted in Fig. 8 against the losses (Eoff). The SiN MOSFET exhibits lower ∆VGSpeak at lower Eoff. The voltage oscillations observed at the drain node with RG = 10 Ω are comparable in the two splits (VDS,peakSiO2 = 995 V and VDS,peakSiN = 1007 V). In conclusion, a 1.2 kV rated SiC vertical MOSFET incorporating a SiN gate dielectric was demonstrated to outperform a reference device with SiO2 gate oxide in switching performances, while also showing the expected STS-1 enhancement and better Vth stability. The reduced switching losses are attributable to the lower CGD shown by the SiN MOSFET for VGD > 10 V.

ABSTRACT. In recent years, spin defects in silicon carbide (SiC) have emerged as a promising candidate for quantum technological applications, particularly for operability at at room-temperature and availability of photonic devices. Silicon carbide’s wide bandgap and low-spin crystal basis allow for stable optical emission and long coherence times [1]. This presentation will highlight the development of a desktop- format quantum computer based on spin defects in silicon carbide. A significant challenge in utilizing silicon carbide for quantum computing lies in the near-infrared (NIR) fluorescence emission of most defects [2]. While this is a benefit for photonically distributed quantum systems and promises scalability through optically entangled qubit register, this wavelength range poses a challenge for the optical systems. Next to the availability of high-transmission objectives, compact and afforable single photon detectors suffer from low collection efficiencies and long dead times compared to the visible range. Overcoming these challenges requires precise engineering of the SiC defect centers and the development of photonic integration techniques. Overcoming these hurdles is essential for realizing scalable, efficient quantum systems that can fully exploit the potential of silicon carbide as a quantum computing platform. We aim to overcome these challenges and demonstrate the feasibility of a two-qubit educational quantum computer, designed to teach the formation and calibration of quantum gates and the execution of basic quantum algorithms. The system leverages modified divacancy spin defects in SiC as qubits [3]. By integrating this setup into a compact, user-friendly desktop format, we provide a hands-on approach for introducing fundamental quantum computing principles. This work serves not only to showcase the application of silicon carbide in quantum computing but also to emphasize its role as a contender for scalable quantum systems. While truly scalable and applicable quantum computers are still machines of the future, silicon carbide holds many key advantages to overcome crucial challenges. Tough much research remains to solve all obstacles, the initial steps have been made and the silicon carbide quantum field is steadily growing.

[1] J.R. Weber et al., J. Appl. Phys. 109, 102417 (2011) [2] Jun Zhang et al., Light: Science & Applications volume 4, pagee286 (2015) [3] N.T. Son et al., J. Appl. Phys. 132, 025703 (2022)

ABSTRACT. Electrical spin detection with the photocurrent detection of magnetic resonance (PDMR) is a key technique for room-temperature scalable integrated quantum device applications based on spin-active color centers, such as a nitrogen-vacancy (NV) center in diamond and a silicon vacancy in silicon carbide (SiC). PDMR was first demonstrated by using NV centers and developed to detect a single spin and its coherence of an NV center. For SiC, a more advanced semiconductor platform, PDMR detection of electron-spin coherence of ensemble silicon vacancies and nuclear-spin-resonance signal of their surrounding nuclear spins has been demonstrated. However, the PDMR readout of single spins in SiC has not yet been realized. In this study, we demonstrate the photoelectric coherent detection of a single silicon vacancy’s spin at room temperature. Also, we demonstrate the superior spin-readout efficiency with PDMR to the conventional optical spin-detection method, which has been previously predicted but not realized.

ABSTRACT. Spin center defect-based technologies in silicon carbide (SiC) have emerged as an important platform for solid-state quantum sensing applications which exhibit long coherence times [1] and susceptibility to magnetic [2-4], electric [5], and temperature fluctuations [6]. In regards to quantum sensing of magnetic fields, optical [2] and electrical readout capabilities [3-4] exist. Although optical readout usually offers superior sensitivity at the cost of optical components, magnetic field sensing using electrical readout is more attractive due to its simplicity, its ease of integration into electronic circuitry, and reduced size, weight, and power (SWaP). These sensors also have the ability to self-calibrate, a significant advantage over Hall-sensors, anisotropic magnetoresistance sensors, and fluxgate magnetometers. In electrical devices such as pn junctions, shallow-deep-level pairs allow for the manipulation of spin-dependent recombination (SDR) current channels across the depletion region with external fields. One promising spectroscopic tool used to read out the electrical response of these defect pairs to external fields is electrically detected magnetic resonance (EDMR).

In EDMR, an applied bias generates a nonequilibrium population of electrons and holes in the device active region; in the subsequent electron-hole recombination that produces SDR current a carrier is first captured by a shallow level defect and then by a deep level defect. A Pauli-spin blockade occurs depending on the resulting angular momentum selection rules that produces a bottleneck in the SDR current channel, which is relieved when one or both spins (deep and shallow) are resonantly flipping. In EDMR, an applied Zeeman magnetic field brings the energy levels of both spins into resonance with the applied oscillating magnetic field, relieving the bottleneck. This produces a characteristic change in the measured SDR current, as the conditions for magnetic resonance are determined by the spin Hamiltonian of the shallow-deep-level pair. Due to the complexity of this two-spin recombination mechanism, a detailed theory is necessary to inform future research directions into magnetic field sensor optimization.

Here we show the first quantitative theory for simulating the EDMR spectrum of silicon vacancy-related defect pairs in 4H-SiC with Lindblad equations and fit to a measured room-temperature spectrum attributed to silicon vacancies [4]. Importantly, we identify the shallow donor in the spin pair as a nitrogen-related silicon dangling bond complex [7] and link its formation to nitric oxide anneals, commonly used to attenuate the SDR response of silicon vacancies. We also simulate the EDMR spectra of V1 and V2 silicon vacancy-related defect pairs at low temperature, predicting the regime of device operation in which the underlying hyperfine structure becomes resolved. These results will motivate additional work exploring the effects of nitric oxide anneals on silicon vacancy-based magnetometer technology.

This material is based upon work supported by the Air Force Office of Scientific Research under award number FA9550-22-1-0308.

[1] M. Widmann et al., Nature Materials 14, 164-168 (2015). [2] K. Tahara et al., npj Quantum Information 11, 58 (2025). [3] A. Gottscholl et al., Scientific Reports 14, 14283 (2024). [4] C. J. Cochrane et al., Scientific Reports 6, 37077 (2016). [5] P. V. Klimov et al., Phys. Rev. Lett. 112, 087601 (2014). [6] H. Kraus et al., Scientific Reports 4, 5303 (2014). [7] E. Higa et al., Appl. Phys. Lett. 116 (17), 171602 (2020).

ABSTRACT. Color centers such as silicon vacancies (VSi) in 4H-SiC crystals are promising candidates for quantum sensing, communication and computing applications [1, 2]. Electric fields of pin-diodes (E||c) have been shown to reduce spectral diffusion and tune the resonant excitation and emission from color centers and thereby improve the optical properties of VSi [1]. Unlike commonly used 4H-SiC c-plane wafers, a-plane wafers allow a scalable fabrication of lateral pin-diodes (E||c) in a CMOS compatible process with convenient access to resonant excitation perpendicular to the VSi dipole moment, which aligns with the c-axis. This allows laser excitation of the VSi perpendicular to the wafer surface (a⊥c) and in-plane excitation using a waveguide aligned to the m-axis (m⊥a), supporting high scalability and co-integration of advanced electronics and photonics, which is a key step towards quantum photonic integrated circuits (QPICs) [2].

This work shows a CMOS-compatible process on 4H-SiC a-plane wafers for scalable production of lateral pin-diodes with optical access to VSi inside the intrinsic region. The lateral pin-diodes as shown in Fig. 1a were fabricated using a CMOS-compatible process [3] on 35 mm on-axis 4H-SiC a-plane substrates [4]. As reference, the same devices were also manufactured on 150 mm c-plane wafers. Two differently doped epitaxial layers for either standard power electronics (n-type) or quantum applications (i-type) were used (see Table I, top row). The 10 µm thick epitaxial layers were grown in an Aixtron G5 WW C planetary reactor. The correspondingly doped samples were fabricated in the same process. [4] The fully processed 4H-SiC a-plane wafer is shown in Fig. 1b, enabling scalability and allowing future on-chip integration of a wide range of additional devices and photonics. The VSi were generated via full area electron irradiation with a dose of 3E12 cm-2 with subsequent annealing at 600 °C for 30 min in vacuum. For room temperature measurements multiple chips with different design variations totaling to at least 300 pin-diodes on each wafer were investigated. Cryogenic measurements down to 4 K (using a closed-cycle cryostat from attocube) and optical measurements (using a commercial PL setup from SQUTEC) were conducted at selected representative devices.

The pin-diodes show a consistent electrical behavior across substrates (Fig. 1c). In forward regime the turn-on voltage is approximately 2 V followed by an exponential increase of the current until being limited by series resistance (see Table I) for higher voltages. Under reverse bias up to 200 V the measured current is still determined by the leakage current of the measurement setup, suggesting a low noise wide range optical tunability of the resonance frequency of VSi. The dielectric breakdown voltages, defined as the voltage, where the current exceeds 100 nA/µm, reach up to 350 V (Fig. 2a) and are in accordance with the theoretical principles [5] increasing with the length of the low doped region and decreasing with higher epitaxial layer doping. Ideality and series resistance of the pin-diodes show < 10% variation (see Table I). Combined with a production yield exceeding 97% for the n-type a-plane sample a stable and reproducible process is demonstrated. The variance in series resistance between the different samples mainly correlates with the availability of free charge carriers in the drift region determined by the doping of the different epitaxial layers.

At cryogenic temperatures, the turn-on voltage increases (Fig. 2b). This is explained by the need to re-ionize frozen-out charge carriers using the internal electric field [6], which results in a current jump into on-state as soon as sufficient voltage is applied. Reverse currents remain negligible and limited by the leakage current of the measurement setup at all temperatures. Electron irradiation and annealing have little influence on the I-V characteristic (not shown). The generated color centers are homogeneously distributed inside the pin-diode and its electrical field (Fig. 2c), allowing tuning of the optical properties. ODMR measurements at 300 K on the color centers reveal a contrast at 70 MHz (not shown), thus confirming successful creation of VSi.

In conclusion a CMOS-compatible process on 4H-SiC a-plane wafers for scalable production of lateral pin-diodes with optical access to VSi inside of the intrinsic region is demonstrated. The fabricated pin-diodes show excellent blocking characteristics, with breakdown voltages of up to 350 V and low reverse currents at room temperature and 4 K allowing a low-noise Stark tuning over a broad frequency range. This enables compensation of process-related variances in resonance frequency [7], thereby allowing entanglement of multiple color center qubits [2].

ABSTRACT. 4H-SiC does not only host favorable color centers for quantum applications, it also offers the opportunity to couple the relevant transitions to mechanical degrees of freedom, which provides, for example, opportunities for long-living quantum register on a SiC chip as integrated solution. SiC permits to display the possible highest quality factors, because the intrinsic damping is much lower than for any other material [1]. However, high quality factors imply narrow resonances, and a strategy is sought for matching the high quality-factors of the mechanical resonator to the frequency of the quantum degree of freedom such that spectral overlap will be achieved reliably. Previously, we proposed a tuning of the color center relying on Stark effect [2], which has excellent fine tuning capabilities, but a limited tuning range. We could recently demonstrate that an electrochemical etching strategy similar to previous results [3] can lead to monolithic nano/micromechanical oscillators of high quality, which are even stable upon annealing to 1500°C [4]. This is of utmost importance, because it allows annealing of the crystalline device and its surface, thus avoiding surface damping of the mechanical resonator. With these samples, a detailed analysis of the mechanical parameters became possible, in particular we could demonstrate that the bridges were essentially unstrained. Highest quality factors exceeding 200,000 were reported [5]. Here, we present experiments that demonstrate the tunability of nanomechanical resonators in a wide range. Starting from entirely unstrained material, we achieved a tuning of the cantilevers by bending the underlying SiC substrate, see sketch in Fig. 1(a) and optical image in Fig. 1 (b). Here, the monolithic architecture of our cantilevers is quite favorable, because the cantilevers can not relax strain by detachment, that has been reported for many other material stacks. The measurement was performed using a Laser-Doppler vibrometer that measures the oscillating frequencies at room temperature in a broad frequency range without explicit excitation (hence, under thermal excitation). Even on the first attempt, we could tune the resonance frequency, characterized by a Lorentzian in Fig. 2 (c), by more than one octave. Associated with building up strain, the dissipation is diluted and the quality factors that are associated to the width of the mechanical resonance are are rising by a factor of five, from 20,000 to over 100,000, see Fig. 1(d). The paper demonstrates that despite the requirement of sharp resonances, a spectral matching can be achieved by bending the substrate. The intricate interplay of mechanical strain and spin (quantum) degrees of freedom can now be exploited for unprecedented experiments and quantum applications.

ABSTRACT. Currently, commercially available SiC power devices such as MOSFETs and SBDs are fabricated on n-type 4H-SiC substrates with 6- or 8-inches diameters. To improve device performance and yield, the quality of large-diameter SiC wafers is critically important [1]. In particular, using high- quality SiC substrates with low defect density and reduced warpage is essential for achieving high- quality epitaxial layers, which directly impact device performance. Accordingly, the technological challenges in the SiC wafer manufacturing industry include enhancing crystal quality, reducing warpage, minimizing kerf loss during wafering processes, and improving cost competitiveness.

In the PVT process for SiC single crystal growth, it is necessary to precisely control the temperature gradient and heat transfer design in the growth zone to reduce defects and thermal stress in the crystal ingot, while simultaneously achieving higher growth rates to enhance overall cost-efficiency. This presentation introduces several research efforts aimed at improving both the quality and productivity of SiC crystals grown by the PVT method. Fig. 1 shows an 8-inch crystal ingot and wafer prepared under optimized process conditions. In terms of defect density, a modified crucible design with optimized heat transfer conditions demonstrated lower defect levels. The resulting optimized growth conditions are expected to enable even higher crystal quality when seeds grown by the TSSG method -an emerging approach for improving SiC quality- are adopted. The results of this approach are presented here.

Furthermore, a case study is introduced in which high-purity CVD-SiC blocks, used as semiconductor process materials, were employed in large particle form as a raw material for high- speed PVT growth under a steep vertical temperature gradient. The crushed CVD-SiC block, which has a low specific surface area, is advantageous as a raw material since it prevents the generation of dust even under high fluid flow conditions inside the reactor. Additionally, under a high thermal gradient, enhanced mass transport enables a high growth rate. At the growth front, heat tends to accumulate and form excess crystal facets, acting as a mechanism of thermal dissipation; thus, controlling the temperature gradient toward the backside of the crystal is important. As shown in Fig. 2, a high-quality SiC crystal was successfully grown at a rate of 1.46 mm/h under these controlled process conditions.

Lastly, this presentation highlights recent applications of artificial intelligence (AI) across various semiconductor materials and device fields. In particular, Process Informatics (PI)-based databases and AI technologies are emerging as promising solutions for optimizing SiC single crystal growth processes, which suffer from low productivity, complex process variables, and limited real-time monitoring capabilities. As an example, Fig. 3 introduces the architecture of a SiC single crystal growth DB-AI solution currently under development in Korea.

ABSTRACT. Recently silicon carbide (SiC) has proven to offer physical properties which are not only advantageous for power electronics, but also for photonic applications like photocatalytic water splitting, fluorescent SiC, and waveguide applications. In this field of application, special SiC bulk materials exhibiting intrinsic properties and p-type doping are needed. In addition to 4H-SiC, also 3C-SiC and 6H-SiC are of importance. Close Space PVT (CS-PVT), which is a modification of standard PVT exhibiting a short source-to-seed-distance, enables a large variety of growth process variations to meet the specific requirements of the SiC material (i.e. special polytype and/or doping) to be grown. This for example enabled the bulk growth of 3C-SiC [1] which profits from a high supersaturation and a Si-rich gas phase composition. Indication for the high crystalline quality of CS-PVT grown hexagonal SiC was already proven in the early work of Syväjärvi and Yakimova [2, 3]. In this work, we study the growth of 4H-SiC p-i-n structures to be used as SiC solar cells for remote power transfer in space. Note: The presented growth method is also applicable for the fabrication of large area SiC wafers and p-/i-/n-layer stacks as used in power electronics. We used the CS-PVT method [4], which bridges the gap between the state-of-the-art bulk growth of SiC using the PVT method (boule thickness of 1-50 mm) and the chemical vapor deposition (CVD) of thin SiC films in the thickness range of ca. 1 to 100 µm. In addition to the SiC growth study, we will also introduce the newly developed TableTopCSTM growth machine which meets special requirements for advanced CS-PVT growth. While this work mainly shows results of 100mm 4H-SiC layers, growth cells of 150mm and 200mm CS-PVT are already applied in the lab. Scientifically we are addressing in this study (i) the achieved 4H-SiC polytype stability and (ii) new aspects of advanced p-type doping by aluminum which are possible in the ballistic mass transport regime of CS-PVT. The p-i-n structures were fabricated in two consecutive CS-PVT growth runs. As substrate we used 100 mm 4H-SiC wafers (4° off-axis) either C-face or Si-face oriented to carry out homoepitaxial nucleation and growth of 4H-SiC (figure 1), respectively. The growth temperature measured at the top of the CS-PVT growth cell was 1900°C (growth rate ca. 50 µm/h). The background gas pressure was < 0.1 mbar. In the first step nitrogen doped n-type or nominally undoped, quasi-intrinsic layers (either residual n-type or residual p-type) with a thickness of ca. 100 µm layer were deposited (growth time = 2 h). As indicated by the Raman spectroscopy study in figure 2, a high polytype stability is observed on both seed faces. In PVT growth above 2000°C it is standard to grow a 4H-SiC crystal on c-face seeds. However, Si-face seeding fails, because of a heteroepitaxial transition of the polytype to 6H-SiC and 15-SiC. Note: CVD growth of 4H-SiC performed at 1600 to 1700°C, however, is performed routinely on Si-face seed wafers. One important finding of this work is that 4H-SiC CS-PVT growth at 1900°C is possible on Si-face substrates making CS-PVT growth compatible with the SiC device processing routine (on Si-face substrates) exhibiting comparably high growth rates of 50 to 200 µm/h. Intentional p-type doping of the second thin top layer (growth time = 10 min) was performed by using aluminum doped solid 4H-SiC:Al and 6H-SiC:Al sources which were prepared by the M-PVT method [5]. In sublimation growth doping of SiC by aluminum is rather challenging because of the much greater partial pressure of the Al gas species compared to Si- and C-related gas species (i.e. Si, Si2C and SiC2). Without special emphasis like in the M-PVT growth process, it is basically impossible to obtain homogeneous dopant incorporation. CS-PVT, however, enables a new growth mode for advanced doping which makes use of ballistic mass transport. At a low background gas pressure of <0.1 mbar we showed earlier [6] that ballistic mass transport dominates the mass transport between the closely spaced SiC source and SiC seed (distance < 1mm). In such ballistic growth mode, the phenomenon of the partial pressure of atomic or molecular species does not exist and species are directly transported from source to seed. This kind of direct Al-transfer from source to seed was experimentally proven for two doping level regimes (see table I) and is the second important result of this work.. This work is funded by the European Union, Horizon Europe contract #101160868 (RePowerSiC).

[1] La Via, Zimbone, Bongiorno, La Magna, Fisicaro, Deretzis, Scuderi, Calabretta, Giannazzo, Zielinski, Anzalone, Mauceri, Crippa, Scalise, Marzegalli, Sarikov, Miglio, Jokubavicius, Syväjärvi, Yakimova, Schuh, Schöler, Kollmuss, Wellmann, Materials, 14, 18, 5348 (2021) [2] Syväjärvi, Yakimova, Glans, Henry, MacMillan, Johansson, Janzen, J.Crys.Growth 198 (1999) [3] Yakimova, Vouroutzis, Syväjärvi, Stoemenos, J.Appl.Phys. 98, 3, 034905 (2005) [4] Kollmuss, Schöler, Anzalone, Mauceri, La Via, Wellmann, Mat.Sci.For. 1062 (2022) [5] Wellmann, Desperrier, Mueller, Straubinger, Winnacker, Baillet, Blanquet, Dedulle, Pons, J.Crys. Growth, 275, 1-2, e555 (2005) [6] Hupfer, Hens, Kaiser, Jokubavicius, Syväjärvi, Wellmann, Mat.Sci.For.740 (2013)

ABSTRACT. Multi-wafer close-space sublimation (MCSS) has been proposed as a method for producing single-crystal SiC wafers, in which Si-C molecules sublimated from polycrystalline or sintered SiC substrates (source) recrystallize on substrates with a single-crystal SiC surface (seed). This process is carried out under uniform temperature, so that the driving force for the physical vapor transport (PVT) of Si-C molecules is not the temperature gradient, but the difference in equilibrium vapor pressure between the source and seed surfaces (ΔP). This allows simultaneous growth of SiC on multiple seed surfaces. At constant temperature, one of the factors determining ΔP is the grain size (dsource) of the source. To increase ΔP and achieve SiC growth on the seed surface, reducing dsource is effective. The SiC growth rate (rg) on the seed surface shows a positive correlation with the growth temperature (Tg). At Tg = 2200 °C, rg exceeds 10 μm/hour. The material transport efficiency (i.e. the ratio of the increase in seed weight to the decrease in source weight) exceeds 85%. This indicates a significant reduction in material loss.

ABSTRACT. A high-potential alternative to conventional SiC wafers consists in transferring a single-crystal thin film onto a polycrystalline SiC receiver fabricated by chemical vapor deposition (CVD), which must be thick, flat and highly thermally and electrically conductive [1]. To fulfill the last condition, nitrogen doping is necessary. Although in-situ nitrogen doping of polycrystalline SiC during CVD has been the subject of several work in the literature [2–6], it was restricted to a rather limited set of growth conditions (low temperature), hence the process-microstructure-composition relationship was only partially covered. In addition, the microstructure-composition-electrical properties relationship was not investigated in details. In this work, we aim at presenting new insights on these topics. To investigate the process-microstructure-composition relationship, CVD was conducted on flexible and rigid graphite substrates with a mix of methyltrichlorosilane (MTS), hydrogen (H2), and ammonia (NH3) in a vertical hot-wall lab-scale reactor which possesses a strong temperature gradient along its height (1100°C-1500°C), allowing us to explore multiple growth conditions in a single experiment. These local conditions (e.g. temperature) are obtained from modelling. The NH3/MTS ratio was adjusted as a way to modify the nitrogen content in the deposits. To further increase the high-throughput aspect of our approach, we deposited either single-layer or multi-layered deposits, with varying NH3/MTS during growth. Samples were then collected at different positions in the reactor for further characterization. Secondary ion mass spectrometry (SIMS) and X-ray photoelectron spectroscopy (XPS) were used to characterize the nitrogen content of the different samples, the latter also providing information on the nature of the chemical bonding. Owing to the high reactivity of NH3, high nitrogen content was reached (1019-1022 at.cm-3). Interestingly, while the solubility limit of nitrogen in SiC has been established at around 1020 at.cm-3, XPS showed that for any nitrogen content, nitrogen was always incorporated in substitution of carbon, without the apparition of a secondary Si3N4 phase, as confirmed with X-ray diffraction (XRD). Discussion on the solubility of nitrogen in polycrystalline 3C-SiC is then made. From the process-microstructure side, electron backscattered diffraction (EBSD) and X-ray diffraction (XRD) revealed that high amount of nitrogen could result in changes of grain size and preferential orientations in some growth conditions and notably led to the apparition of <100> orientation, which was never reported in the literature, in opposition to the common <111>, <110> and <211> orientation [7,8]. In case of multilayered samples with varying NH3/MTS ratio, this transition to <100> orientation with nitrogen was only observed for the first deposited layer and was shown to return to <111> orientation when NH3 supply was stopped. Then when NH3 was once again added, the apparition of the <100> orientation was not observed, but in such case, grain size and crystalline quality was strongly degraded, as confirmed by EBSD. These observations are discussed through the lens of polycrystalline SiC growth mechanisms. Then, based on the various samples produced, a qualitative relationship between grain size/crystalline quality, nitrogen content and electrical resistivity was established, notably by comparing the couple {resistivity - nitrogen content} for our samples with data from literature. The effect of grain size is then interpreted through the lens of Seto model [9], which stipulates that in doped semiconductor, grain boundaries act as traps for free charge carriers, affecting both their concentration and mobility. Going back to the applicative aspect of this work, resistivity of the order of 1 mOhm.cm were reached for as-deposited samples, whereas the lowest resistivity values found in the literature were around 10 mOhm.cm. This 10-fold reduction in the electrical resistivity of polycrystalline SiC deposits will further increase the efficiency of engineered substrates made from them.

ABSTRACT. Most of our classical digital technology relies on semiconductor integration. This successful strategy is currently being applied to quantum technology, to transition today’s complex research laboratory experiments towards applications and market- readiness. In this presentation, I will briefly motivate the prospects of quantum technologies, especially secure quantum communication. I will then summarise the quantum research of the last decade that focused on identifying quantum systems based on wide-bandgap semiconductors. Much of the research has been carried out using the diamond and silicon carbide platforms, in which quantum systems are implemented via addressing vacancy-related atomically small defects (colour centres). These colour centres have proven to cover all the necessary ingredients for quantum applications: (1) The spin properties of these defects can be used for quantum computing and quantum memory tasks, with demonstrations covering both the diamond [1,2] and silicon carbide platforms [3,4]. (2) The optical properties of these defects provide an interface for the transmission of quantum information, on-chip, or via the (quantum) internet [5,6,7].

Current efforts are now seeking to improve the scalability of these demonstrations. This requires adapting semiconductor fabrication to quantum technology, i.e.: (1) Integration of colour centres into (nano-)photonic chips to maximise the optical efficiency [8,9]; (2) High-density electrical circuitry around colour centres for control and compensation of fabrication-related imperfections [10,11,12,13].

In this regard, the silicon carbide platform is very promising since multiple pathways for quantum photonics have been developed, including the promising silicon-carbide-on- insulator platform [14]. Additionally, the excellent semiconductor properties of silicon carbide provide a straightforward solution for electrical control of colour centres. E.g.,recent demonstrations showed tuning/stabilisation of colour centres in electrical devices (Schottky and pin diodes) [10,11,12,13]. After introducing these developments, I will finalise the presentation with an overview of the Luxembourgish activities in the framework of integrating colour centres in silicon carbide nanophotonic circuits. This includes fabrication of individual colour centres using focused ion beam implantation, fabrication of photonic nanostructures based on reactive ion etching techniques, and high-throughput quantum characterisation based on a new widefield photoluminescence microscopy setup. Our overall work is outlined to identify ideal strategies for surface charge passivation, which remains the key challenge towards maximising the quantum coherence of integrated colour centres. Based on near-term advances in quantum-grade surface passivation, we foresee that the silicon carbide platform can become the leading technology in the fields of quantum communication and the quantum internet.

References: [1] Nature 606, 884 (2022) [2] Nat. Commun. 9, 2552 (2018) [3] Nat. Commun. 15, 10256 (2024) [4] Sci. Adv. 8, eabm5912 (2022) [5] Nature 605, 663 (2022) [6] Nat. Commun. 11, 2516 (2020) [7] Phys. Rev. Lett. 132, 160801 (2024) [8] PRX Quantum 1, 020102 (202) [9] Optica 7, 1232 (2020) [10] Science 366, 1225 (2019) [11] arXiv:2410.10750 (2024) [12] arXiv:2410.09021 (2024) [13] arXiv:2504.13164 (2025)

ABSTRACT. The silicon vacancy in 4H-SiC is a promising candidate as a platform for future quantum networks, mainly due to their favourable spin and optical properties [1-2], and compatibility with integration in nanophotonic structures [3-5]. However, an open challenge is to enhance the emission of zero phonon line (ZPL) photons to increase the rate of entanglement generation between separated V2 defects. A viable method to enhance the optical properties of the V2 defect are 1d-nanobeam photonic crystal cavity (PCC). We present the ‘skyfish’ PCC, specifically designed for TM like modes because of the vertical electrical dipole orientation of the V2 defect in c-plane 4H-SiC. In order to efficiently couple to the cavity, we simulate a cavity-to-waveguide interface and collection efficiency through a tapered optical fiber. Together with the simulations, we show the fabrication process and experimental characterization of our PCCs in 4H-silicon-carbide-on-insulator [4], with quality factors up to ~40.000. Additionally, we demonstrate efficient transfer printing techniques that enable hybrid integration of 4H-SiC photonics with SiN photonics. Combining high quality factor PCCs in 4H-SiC with SiN photonics will open new opportunities for quantum networks and distributed quantum computation.

[1] Nagy, R. et al. Nature Communications. 10.1: 1-8. (2019) [2] Widmann, M. et al. Nature Materials. 14, 164–168 (2015) [3] Babin, C, et al. Nature Materials. 21, 67–73 (2022) [4] Lukin, D.M. et al. Nature Photonics. 14, 330–334 (2020) [5] Krumrein, M. et al. arXiv preprint.2401.06096 (2024)

ABSTRACT. Silicon carbide (SiC) has emerged as a promising material for integrated photonic devices in quantum information processing. Due to its exceptional physical and optical properties, SiC is gaining increasing attention as a scalable platform for quantum communication and networking. For instance, its wide transparency window from the visible to the mid-infrared range stems from its large bandgap. SiC also exhibits both second- and third-order optical nonlinearities, enabling nonlinear processes such as second-harmonic generation and Kerr comb formation. Furthermore, its high thermal conductivity and mechanical robustness make it ideal for applications in harsh environments and green technologies. Additionally, SiC supports a variety of color centers with desirable quantum properties, observed across multiple.

The National Institute of Standards and Technology (NIST) and Carnegie Mellon University (CMU) are collaborating to develop SiC-based devices for quantum communication applications. As part of this effort, we have demonstrated an integrated entangled photon source on a silicon-carbide-on-insulator (SiCOI) platform. In this work, Highly correlated photon pairs are efficiently generated at telecom C-band wavelengths using spontaneous four-wave mixing in a compact microring resonator fabricated on the 4H-SiCOI platform. The source achieves a maximum coincidence-to-accidental ratio (CAR) exceeding 600 at a pump power of 0.17 mW, corresponding to a pair generation rate of 9×10³ pairs/s. We created and verified energy-time entanglement, with two-photon interference fringes showing a visibility greater than 99%.

To ensure compatibility with current quantum networking infrastructure, we aligned the signal and idler photon wavelengths to standard DWDM ITU-grade channels. This enables seamless integration with quantum network testbeds such as NG-QNet (NIST Gaithersburg) and DC-QNet (Washington D.C. area). Moving forward, we aim to integrate additional functionalities, including quantum memories and quantum interfaces, into the same SiC platform. This effort will support the development of scalable, practical, and fully integrated quantum photonic devices for next-generation quantum communication networks.

ABSTRACT. Spin centers in crystals are considered prime candidates for the implementation of large-scale quantum networks. They combine conveyable quantum states encoded in light with the stability and storage capabilities of solid-state electron and nuclear spins. While historically diamond was the most promising host crystal, defects in silicon carbide (SiC) have recently emerged as a highly suitable platform for quantum devices, offering robust optical transitions, sufficiently long spin lifetimes and coherence. Particularly of interest are vanadium defects in silicon carbide, which exhibit optical transitions within the telecom band and therefore enable seamless integration with existing optical fiber networks. This removes the need for wavelength conversion, positioning them as an attractive platform for quantum nodes in quantum communication networks. Our investigations yield significant advances in understanding this remarkable system, the control of its electron spin, and the development of photonic interfaces for quantum networks. We show a significant extension of the spin lattice relaxation time (T1) of vanadium at cryogenic temperatures, of up to 25s at 100mK. The implantation of single vanadium defects has been successfully demonstrated and revealed spin-dependent optical transitions. We further investigate the electronic ground state structure by using strong radiofrequency oscillating magnetic fields at low temperatures. Here, we observe a severe influence of strain on the system Hamiltonian, altering the selection rules. To interpret the observed behavior, we employ a recently developed theoretical framework that describes the defect ground state under crystal strain. In this strained crystalline lattice, we show direct hyperfine transitions in the vanadium defect ground state. This opens new possibilities towards future state preparation and more robust encoding of quantum information.

References:

[1] P Koller, T Astner, et al., Phys Rev Materials, 9(4), L043201. (2025) [2] T. Astner, P. Koller, et al., Quantum Sci. Technol. 9 035038 (2024) [3] S. Ecker, et al., preprint arXiv:2403.03284 (2024) [4] P. Cilibrizzi, et al., Nat Commun 14, 8448 (2023) [5] B. Tissot et al., Phys. Rev. Research 4, 044107 (2022) [6] G. Wolfowicz, et al., Sci. Adv. 6, eaaz1192 (2020) [7] L. Spindlberger, et al., Phys. Rev. Applied 12, 014015 (2019)

ABSTRACT. Achieving reliable and reproducible breakdown performance in ultra-high-voltage (>10 kV) silicon carbide (SiC) power devices presents considerable challenges, particularly in the design of edge termination structures. These terminations must effectively suppress electric field crowding at the device periphery while simultaneously maintaining compactness and manufacturability. In such high-voltage devices, the epitaxial layer typically has a low background doping concentration (~4×1014 cm-3), which significantly impacts the lateral and vertical distribution of implanted dopants. This low background doping increases the lateral straggle during ion implantation, resulting in poor electric field control and requiring wider ring spacing in conventional floating field ring (FFR) structures [1]. Edge termination size becomes increasingly important for high-voltage devices above 10 kV, as it constitutes a large portion of the total chip area. As demonstrated in Fig. 1, in 10 kV-class SiC devices, the edge termination accounts for approximately 80% of the chip area in a 1 A-rated device and about 50% in a 10 A-rated device.

To overcome this limitation, this study proposes a novel edge termination scheme that reduces the lateral dopant straggle in the FFR structure by introducing a moderately doped N-type region – referred to as background doping modulation (BDM) – along with P+ ring implantation; the profile of the proposed implantations is shown in Fig. 2. This pre-doped region acts as a confinement layer, effectively reducing the effect of the lateral straggle during the P+ ring creation and enabling tighter spacing between floating rings [2]. As a result, more compact terminations can be achieved without compromising electric field control. Consequently, the total chip area can be significantly reduced which is critical advantage for ultra high-voltage devices. Notably, this additional N-type implantation can coincide with the JFET region in standard MOSFET process flows, allowing seamless integration of the proposed structure without adding process complexity. In the case of Schottky or JBS diodes, however, an additional implantation step would be required. It should be noted that the proposed BDM (Background Doping Modulation) FFRs do not require high energy implantation as the primary goal is to accomplish narrow spacing design between P+ concentric rings without increasing the electric field at their corners.

In this work, three edge termination designs were fabricated and evaluated: the proposed BDM FFRs (as shown in Fig. 3) and two conventional FFRs (FFR1 and FFR2 as shown in Fig. 4). BDM-FFR employed tighter ring spacing (0.8µm) with 100 rings, while FFR1 and FFR2 used wider spacings (1.0 µm and 1.5µm) and different numbers of rings as shown in Table I. Focused Ion Beam (FIB) SEM imaging (Fig. 5) confirmed that lateral dopant straggle was significantly suppressed in the BDM-FFR. Experimentally, as shown in Fig. 6, BDM-FFR achieved a breakdown voltage exceeding 13 kV—30% higher than conventional FFR devices which have a BV of 10kV. Moreover, the leakage current of BDM-FFR is maintained below 10 nA at 10kV. As for conventional FFRs, FFR1 exhibited a higher leakage current compared to FFR2 due to the insufficient ring separation (1µm instead of 1.5µm). Moreover, BDM-FFR structures reduced termination area by 18.6% compared to FFR1 and FFR2, offering a clear advantage in chip size efficiency for high-voltage integration. These findings provide valuable design guidance for implementing compact, scalable, and high-performance edge termination strategies in next-generation ultra-high-voltage SiC power devices.

Acknowledgement: We would like to thank Alexander Bialy and Cobert Johnson from NY CREATES for helping in taking FIB and SEM images in Fig. 5.

[1] J. Lynch et. al., 31st ISPSD, Shanghai, China, 223-226 (2019). [2] N. Yun et al., IEEE Transaction on Electron Devices (TED), 67 (10), 4346-4353, (2020).

ABSTRACT. The heavily nitrogen-doped N+ source region plays a pivotal role in minimizing contact resistance, which is critical for reducing conduction losses in 4H-SiC Power MOSFETs [1]. Consequently, the depth of the N+ source region emerges as a key design parameter influencing overall device specific on-resistance (Ron,sp). This study presents a comparative evaluation of the electrical characteristics of 1.2 kV rated 4H-SiC MOSFETs fabricated with 3 different N+ source depths, analyzed across both Linear MOSFET (Nominal) and Hexagonal (HEXFET) architectures (shown in Fig. 1(a) and (b), respectively). In this study, the two device types were fabricated on 3 separate 4H-SiC substrates, each incorporating a distinct N+ implantation profile. To distinguish between the variants, the N+ implant conditions will be referred according to their implantation depths: shallow, moderate, and deep. Implantation depths were acquired by systematically increasing the ion implantation energy across the three wafers while maintaining a constant implant dose. TCAD simulated cross-sections and SEM images of the fabricated Nominal devices are shown in Fig. 2(a) and 2(b), respectively. The vertical doping profiles extracted along the A–B cutline in Fig. 2(a) is shown in Fig. 3(a). The N+ junction depths are of approximately 0.16 µm, 0.19 µm, and 0.21 µm for the shallow, moderate, and deep implants, respectively. The lateral doping profiles along the C–D cutline, are presented in Fig. 3(b). These profiles reveal that the lateral extent of the N+ region also increases with implantation energy, primarily due to enhanced lateral ion straggle at higher energies. Transfer Length Method (TLM) structures were used to extract the contact resistance of the N+ implant on each wafer. A clear reduction in contact resistivity was observed with increasing implantation energy, yielding values of 3.91×10⁻5, 2.40×10⁻6, and 1.22×10⁻6  Ω·cm², respectively as seen in Fig. 4. The trade-off relationship between Ron,sp and threshold voltage (Vth), as well as between Breakdown Voltage (BV) and Vth, are illustrated in Fig. 5(a) and 5(b), respectively. As observed here, both Ron,sp and Vth exhibit a decreasing trend with increasing N+ source depth for both device types. For Nominal devices, the BV remains mostly above 1600 V under moderate and shallow N+ conditions; however, a noticeable degradation in BV (1465 V) is observed in deep N+ condition. The average values of electrical characteristics are summarized in Table 1. With HEXFET, the reduction in BV with increasing N+ depth is more impactful due to its higher channel density. The BV degradation is attributed to increased leakage current arising from the reduction in Vth, which is influenced by lateral straggle of Nitrogen ions. The lateral straggle shortens the effective channel length, as demonstrated by the reduced channel potential with increasing N+ depth shown in Fig. 6. Therefore, it is evident that although increasing the N+ depth contributes to the reduction of Ron,sp, it concurrently leads to elevated leakage current in the blocking state, thereby adversely impacting the BV. Fig. 7 depicts a successful effort to suppress the increased leakage current associated with the deep N+ condition by implementing an optimized JFET doping profile fabricated with a different wafer. This process modification led to an improvement in BV, increasing from 1465 V to 1560 V, though it also resulted in an increment of Ron,sp. Nonetheless, the results indicate potential for further optimization to reduce Ron,sp while maintaining low leakage current by enhancing the channel potential barrier. In conclusion, increasing the N+ junction depth is significantly effective in reducing contact resistance in 1.2 kV 4H-SiC power MOSFETs, however, it can also lead to an increase in leakage current during the blocking mode. Thus, simultaneous optimization of the P-well and JFET regions is proposed to achieve balanced performance in both conduction and blocking characteristics using the deep N+ implantation.

ABSTRACT. Silicon Carbide (SiC) Superjunction (SJ) technology presents a promising pathway for scaling unipolar devices beyond 3.3 kV, and addressing the challenge of high conduction losses at elevated temperatures caused by the increased resistance of thick drift layers [1]. GE has successfully demonstrated 3.5–5kV SiC SJ MOSFETs through multiple rounds of epitaxial regrowth and ultra-high-energy implantation [2-3]. These devices utilize n-type and p-type deep pillars formed using a tandem accelerator, which generates a multi-energy beam reaching up to 20 MeV for Aluminum (Al) and Nitrogen implantation. In this study, a new high-energy channeled implantation process using a commercial system from Axcelis [4] was evaluated as a viable alternative to tandem accelerator. This approach could enable deep implants, while preventing significant crystal damage. Commercially grown, 4° offcut, 150 mm SiC wafers with a 30 µm n-doped epitaxial layer received blanket on-axis Al channeled implantation using the Axcelis Purion EXE™ SiC Power Series high energy implant system. Precise sample alignment was achieved by measuring the wafer’s miscut angle using X-ray Diffraction (XRD), and adjusting the tilt along the [0001] axis towards [112̅0] direction. Al implantation was performed at 0.5 MeV and 5 MeV, with a fluence of 1×10¹³ cm⁻² at each energy. Fig.1 shows the Secondary Ion Mass Spectrometry (SIMS) analysis of the channeled implanted wafer from the center and edge regions, showing minimal dose variations and high uniformity across the wafer. The results confirm successful channeling at both energy levels, demonstrating accurate control of tilt and twist during implantation. Synchrotron X-ray topographic grazing incidence 22-4 16 contour maps of the un-implanted and channel implanted epiwafers were recorded with high penetration depth of 45µm [5] to image the entire epilayer thickness of 30µm. The contour map of the un-implanted epiwafer (Fig.2(a)) shows few broad contours indicating relatively low lattice distortion typical of high quality epiwafers. The microstructure of the epilayers (Fig. 2(c),(d)) consists of few micropipes, TMDs at 400-500 cm-2, TEDs at 500-600cm-2, few 3C inclusions mainly near the wafer edges and near complete conversion of substrate BPDs into TEDs in epilayer, is relatively unaffected by the implantation process. Fig.3 presents ultra-High resolution x-ray diffraction (HRXRD) analysis of the wafers before and after activation annealing at 1750 °C, using 9kW Cu rotating anode, collimating mirror, 4-bounce Ge(220) monochromator and high sensitivity 1d detector. Carbon cap formation and 1750 oC/10 min anneal was performed in custom chamber under positive argon pressure. HRXRD spectra shows narrower damage peaks, compared to conventional implantation [6], indicating lower crystal damage from the channeling process. Post-annealing at a moderate temperature of 1750 °C led to the disappearance of the defect peaks and complete lattice recovery. This was also confirmed using high-resolution asymmetric reciprocal space mapping. To calibrate channeling implantation models, ongoing efforts include simulations using the Sentaurus SProcess TCAD package. Fig.4 illustrates a comparison between simulation results, which shows good agreement with the SIMS data. Further refinement is underway to enhance the model by tuning various parameters such as electronic stopping power parameters and energy-dependent Debye temperature.

ABSTRACT. In SiC device roadmap, significant effort for next generation device is focused on superjunction (SJ) devices. Benefits of SJ are well known for silicon-based devices, and are currently being researched in SiC devices. However, the complexity in SiC manufacturing has limited the first demonstrations to manufacturing processes that are not industrially scalable, such as multi-epitaxial step [1], or not sufficiently controllable, such as trench etching followed by EPI-filling [2] or sidewall implant [3]. A promising path uses very high energy conventional implantation to form the SJ pillar [4], however this approach also presents limitations such as damage-induced [5], lateral straggle and the complexity of such very high energy equipment. These limitations can be mitigated by implantation in channeling to reduce induced damages, lateral straggle and increasing the projected ion range [6]. In this paper we describe the latest effort for industrialization of SJ devices, combining high energy ion implantation (over 10MeV) with this channeling approach. A schematic of the different approaches is presented in Figure 1. In the paper we describe the effort to develop this manufacturing process and report initial results. The new industrial process includes: (i) capability to do higher energy implant (over 10MeV) than historically available. (ii) capability to control ion channeling in SiC. (iii) ability to monitor post-implant to ensure the process control required is attained. We started from a high energy implant platform based on a LINAC (Linear Accelerator) beamline, established for silicon substrates [7] and modified for SiC. The accelerator beamline has a large ion energy range, reaching up to 14.5 MeV for Phosphorous and Aluminum energies up to approximately 12MeV with industry-compatible productivity. In Figure 2, we reported two examples of SIMS profile for middle range energy 5MeV 1×1013atm/cm2. Ion projected ranges reach up to ≈5μm, offering the possibility to form SJ in a single EPI-implantation cycle for MOSFET in sub-kV voltage class. In Figure 2 we also compare the experimental SIMS profiles with existing ion implantation models [8]. With the appropriate calibration, models can now predict with sufficient accuracy the channeling phenomena in SiC crystal. Applying the calibrated model, we determined the full spectrum of Aluminum and Phosphorus projected range that our platform can provide as a function of the energy with or without channeling conditions. Particularly as reported in Figure 3, at 12MeV the projected ranges for Aluminum and Phosphorous ions is respectively 4.5μm and 3.6μm in non-channeling, and 7μm and 6μm in channeling condition. This can be sufficient to form a full SJ of a 1.2kV MOSFET. Nevertheless, the complexity of channeling ions at these energies increases with a critical angle estimated at 0.11° [9]. To reach this level of accuracy we developed the capability to correct any wafer miscut measuring either by an integrated or a remote XRD system. The integrated system offers the ability to detect and correct errors down to < 0.02° within a few seconds, allowing errors from the wafer miscut to be corrected with minimal impact to productivity. Remote XRD system measurements are used to adjust implant angle, using a feed forward approach. The first experimental profiles are reported in Figure 2. Finally, to ensure sufficient repeatability for industrialization a method to monitor the process is required. Therma-Wave (TW) has been commonly used as empirical method to study implant-induced defectivity including for SiC. The intensity of the TW response signal has been directly correlated to defect concentration [10]. A significant difference in defect concentration has been reported between channeling and non-channeling conditions. Therefore, we anticipated a minimum defect concentration for perfect channeling conditions with a corresponding minimum TW response signal. The TW signal progressively increases with drifts away from the perfect channeling condition as the defect concentration rises. In Figure 4 we report both SIMS (Fig. 4.a), to confirm the best channeling conditions and variation induced by beam average angle variation and corresponding TW (Fig. 4.b). After a first feasibility demonstration, the study will show continuous improvement of a cost-effective industrialization process of SJ by single step using very high energy channeling implants. The process implies a very high energy implant adapted to SiC with wafer miscut correction capability, and high angle control accuracy with associated methods to monitor the process repeatability.

[1] Kosugi, Ryoji, et al. Materials Science Forum. Vol. 778. Trans Tech Publications Ltd, 2014. [2] Harada, S., et al. 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018. [3] Tian, Run, et al. Journal of Semiconductors 42.6 (2021): 061801. [4] Ghandi, Reza, et al. IEEE Electron Device Letters (2025).. [5] Belanche, Manuel, et al. Materials Science in Semiconductor Processing 179 (2024): 108461. [6] Scholze, Andreas, et al. Solid State Phenomena 359 (2024): 47-51. [7] Satoh, Shu, et al. MRS Advances 7.36 (2022): 1490-1494. [8] Tomoaki Nishimura, scatGUI,ion implantation & channeling simulation software [9] R.B. Simonton, et al., Chapter 7, ed. Ion implantation science and technology. Elsevier, 2004. [10] Mazzamuto, Fulvio, et al. Solid State Phenomena 359 (2024): 21-28.

ABSTRACT. In this work the power cycling capability of 7 different SiC MOSFET designs in TO-247 package are assessed. All designs were tested at least at three different temperature swings between 60K and 120K to derive the relationship between the temperature swing and power cycling lifetime for all tested designs. The data was used to compare the lifetime of different SiC MOSFET design and derive possible impact factors. The test results show, that even though all devices have similar electrical ratings, they show significantly different power cycling performances and that the chip thickness is a major impact factor. Furthermore, two design exhibit a much higher lifetime than predicted by the fitted lifetime curve at low temperature swings of 60K and below. Thus, the power cycling capability of discrete SiC MOSFETs must be thoroughly assessed for each device design and experiences from other designs are not generally transferrable.

ABSTRACT. Short-circuit (SC) events in Silicon Carbide (SiC) power MOSFETs are very critical failure cases, which may arise e.g. in motor drives systems. In such SC events, the MOSFETs are subjected to extreme electrical and thermal stress, possibly operating outside their safe operating area (SOA). Therefore, it is critical for SiC MOSFETs to possess enough robust short-circuit withstand capability, until the external protection circuitry turns-off the SC safely. In this work, the SC robustness limit of 1200 V rated SiC MOSFETs from two different manufacturers (M1 and M2) were studied up to the destruction limit. Further, dominant failure mechanisms should be described. Both devices are packaged in TO-247 4-pin configuration and exhibited a nominal on-state resistance (RDS,on) of 80 mΩ. The gate technology of the M1 device is a planar-gate and an asymmetric trench-gate for the M2 device. In addition to evaluating the SC withstand capability, the study also systematically examined the influence of the negative gate-source voltage (VGS,off) on the SC robustness. All SC measurements were performed at a positive gate-source voltage (VGS,on) of 15 V and a fixed DC-link voltage of 800 V. The SC capability was determined by gradually increasing the pulse width duration (tSC) in steps of 100 ns for a fixed VGS and DC-link voltage. To determine their robustness limit, the measurements were carried out until the destruction of the DUTs or a strong drift in the electrical parameters such as gate leakage current (IGSS), loss of blocking capability or increased drain-source leakage current (IDSS) is detected, which indicate damage in the device.

ABSTRACT. Bipolar degradation (BD) is caused by the carrier recombination induced propagation of Shockley-type stacking faults (SSFs) from basal plane dislocations in epitaxial layers of 4H-SiC power devices. SSFs increase the material resistance, leading to forward voltage (VF) drift (ΔVF), limiting reliability in high-voltage applications [1]. Evaluation of BD can be performed using various protocols with stress times ranging from a few µs to min, and current densities varying from 100 to almost 10000 A.cm-2. The impact of high current densities on BD has already been reported [2], but to enable a fair comparison of different test protocols and materials, we investigate how the BD dynamics is impacted by the stress-test conditions and parameters, namely load current (IL), effective pulse duration (ton), maximum temperature during the pulse (Tmax) and accumulated injected charge (Qinj). For this purpose, we used bare PiN diode dies (1200V/10A) soldered on direct bonded copper substrates (solder paste SAC- 305). The front side was connected by an Al Bonded Wire (BW). Stress was performed using either millisecond Power Cycling pulses ("PCmsec" test setup developed by Fraunhofer IISB [3], test conditions in Table I and toff =110 ms for cooling), or long, DC-like, pulses (PCDC, test conditions in Table II and toff =200 ms). Special care needs to be taken to properly conduct the study. To evaluate the injected charge per cycle, the current rise time should be accounted for to properly determine ton (Fig. 1). Then Qinj can be computed as ton x IL x number of cycles. During aging, ΔVF is impacted not only by BD but also by BW degradation, as illustrated in Fig. 2. Post stress ΔVF appears larger when measured using the degraded BW (dashed green curve) than under Kelvin probe (KP) measurement (red curve). We are currently implementing a setup to perform in-situ KP measurements during the stress tests. Tmax depends on IL as well as on ton. We evaluated the impact on Tmax of increasing ton from 300 to 500µs at the highest IL of 30A. The induced 15°C increase in Tmax (Fig. 3) has little impact on ΔVF vs. Qinj, for low Qinj (Fig. 4). Please note that ΔVF exhibits a logarithmic dependence on Qinj. For higher Qinj (around 1000C on Fig. 4), an acceleration of the drift is observed, that we feel could come from either the BW degradation of the development of additional SSF. Discrimination between those hypotheses will be allowed by our in-situ KP setup. The dependence on IL of ΔVF vs. Qinj is represented on Fig. 5 for PCmsec and Fig. 6 for PCDC. Two distinctive features are seen on Fig. 5: (i) the onset of VF drift appears at larger Qinj for higher IL and (ii) the logarithmic VF drift rate (ΔVF per decade of Qinj) increases with IL. While the latter appears straightforward (faster degradation under stronger stress), we do not explain the former (delayed degradation under stronger stress). The PCDC results from Fig. 6 seem consistent with (ii). The inset in Fig. 6 represents the VF drift rate (in % per decade) for both PCDC (triangles) and PCmsec (circles). The 2 sets of data sit on different curves though, demonstrating that another parameter plays a part in the drift rate. The PCDC results from Fig. 6 are not consistent with (i), suggesting that the onset of VF drift is likely linked to material parameters such as initial defect nature and size. To refine our findings, ΔVF vs. Qinj measurements, void of BW degradation impact (in-situ KP setup) will be presented at the conference and included in the full paper, allowing a unique monitoring of the evolution of BD during the stress.

[1] P. Bergman et al., MSF 2001;353–356:299–302. [2] N. Hatta et al., KEM 2023;948:107–13., doi: 10.4028/p-628fu5. [3] S. Laha et al., CIPS 2024; 13th International Conference on Integrated Power Electronics Systems, Düsseldorf, Germany, 2024, pp. 619-624.

ABSTRACT. Silicon carbide is a promising material for low-loss and high-voltage automotive power devices, and long-term reliability is important for practical application. Generally, current conduction through the body diode embedded in a SiC MOSFET can cause the bipolar degradation phenomenon. Recently, it has been reported that both bipolar degradation and epi-carrier lifetime vary depending on the substrate vendor, even under the same epitaxial growth conditions, highlighting the importance of substrate quality.In this study, we evaluated the temperature dependence of substrate carrier lifetime for different substrate vendors, and the defect density, energy levels, and capture cross-sections of killer defects were systematically explored. As a result, it was cleared that substrates with carrier lifetimes limited by a killer defect known as the D-Center can suppress the expansion of single Shockley stacking faults. Understanding the impacts of substrate carrier lifetime on the bipolar degradation phenomenon is important for improving the reliability of SiC power devices.

ABSTRACT. This study proposes a non-destructive method to predict the reliability of silicon carbide (SiC) MOSFETs by analyzing initial threshold voltage (Vth) characteristics. Due to charge trapping issues that affect long-term reliability, early detection is essential. This study statistically analyzes initial threshold voltage (Vth) characteristics and their relationship with device degradation. We used 133 SiC MOSFET samples fabricated on AIST’s pilot production research line. Prior to reliability testing, we measured the gate voltage-drain current (Vgs-Id) characteristics using the triple-sense measurement method to minimize instability in Vth measurement caused by charge trapping. Six Vth-related features were extracted and analyzed using principal component analysis (PCA). The first two principal components (PC1 and PC2) accounted for 94.9% of data variance. PC2, reflecting short-time trapping, enabled identification of a minority group of samples. Seventeen samples were selected for gate stress testing. A regression model using PC1, PC2, stress time, and tbottom (time to max negative Vth shift) showed high predictive accuracy (R² = 0.977). PC2 and tbottom were key factors. This approach enables early, data-driven screening of SiC MOSFETs using only initial measurements, offering a scalable method for assessing device reliability without prolonged testing.

ABSTRACT. In this work we demonstrate strain relief etching using an advanced chemical etching (ACE) process of the full wafer surface on commercial grade n-type 4H-SiC at production throughputs (µm’s/hr). The data shows >4x improvement of breakage strength in laser split wafers. Warp and bow of ground wafers is reduced to match wafers that have been CMP processed showing the potential of stronger, flatter wafers being available for chemical mechanical polishing.

Strain relief etching is a critical wet process technique use in high volume manufacturing of semiconductor substrates and device wafers. The goal of a strain relief etch is application dependent but can generally be considered for removal of warp/bow or improving mechanical strength by removing sub-surface damage thereby optimizing yields. Silicon Carbide (SiC) has a high chemical resistance which has blocked the manufacturing community from using strain relief etching to date.

Without an effective wet etch, the SiC substrate manufacturing community has resorted to expensive mechanical techniques for the polishing and thinning of wafers, which imparts significant stress and strain within the layer[2, 3]. Use of extensive mechanical techniques is also expensive and difficult to perform at volume where wafers are fragile early in the substrate manufacturing line. Research has explored mechanisms of wet etching for creating microstructures on 4H-SiC[4] and trenches in 6H-SiC[5].

ABSTRACT. We report on the development and systematic validation of an advanced silicon carbide (SiC) source material produced via chemical vapor deposition (CVD), using ultra-high purity chlorosilane and methane precursor gases. The material is specifically engineered for physical vapor transport (PVT) growth of single-crystalline 4H-SiC and represents a major step forward in purity, structural homogeneity, and stoichiometric accuracy. The CVD process reliably deposits dense polycrystalline 3C-SiC with a fully closed microstructure and minimal defect density, enabling reproducibility across extended production cycles.

ABSTRACT. Commercially available silicon carbide (SiC) crystals are produced by the physical vapor transport (PVT) or seeded sublimation process. Especially, bonding the seed substrate to the graphite seed holder is one of the most important processes to suppress generation of defects and dislocations in the PVT growth. The pores in the seed/graphite holder interface often form by volumetric shrinkage during baking process. Since the pores act as a thermal resistance which form macro-defects in the grown crystal,[1] severe control of the seed bonding process is required for the crystal growth with 6 and 8 inch diameter. It is important to understand how the pores affect the thermal field of a growing crystal. We investigated an effect of interfacial pores on thermal field and crystal-shape uniformity in the initial growth stage by the Virtual Reactor (VR) simulation software.[2] We have reported that thinner seed and thicker interfacial-planer-shaped pore (IP) can cause the crystal shape to become concave just above IP. [3] In this study, we investigated an effect of IP width on thermal field and crystal-shape uniformity at the initial growth stage. Figure.1 shows a schematic illustration of (a) a crucible model used for PVT growth and (b) the model of the IP filled with argon. Model parameters on the simulation were listed in table.1. The time evolution of the crystal shape was calculated for 1 to 5 time steps up to 30 hours. The ratio of the thickness just above the center of the IP (dIPC) to the growth thickness at the center of the crystal (dSC) was used to crystal-shape uniformity and named” the uniformity index (UI)” here. Figure 2(a) shows the simulated grown crystal shapes on the 1.5 mm-thick seed with different IP width after PVT growth of 30 hours. Without the IP, grown crystal shape was smooth convex. With the IP except 2-mm-width IP condition, grown crystal shapes were locally concave just above the IP. In order that a decrease in growth rate might be caused by distortion of thermal field which has already been formed before growth, we investigated distribution of the temperature difference (ΔT) at the first time step shown in Fig. 2(b). The ΔT can be defined as ΔT = T1 – T2, where T1 and T2 are temperatures of seed/IP interface and IP/graphite holder interface, respectively. With increasing IP width, ΔT increase at IP center position and around IP. These results suggest that the IP placed in the heat extraction path from the seed to the graphite holder functions as a thermal resistance, resulting in a vertical temperature gradient corresponding to the size of the IP. It was confirmed that the IP greatly affects to thermal field distortion and hindering heat removal, as a result, the crystal surface would be distorted. We compared the uniformity index and ΔT at IP center with different IP width at the time step of 30 hours. Figure 3 (a) shows the dependence of IP width on the dIPC/dGC ratio and ΔT. As increasing IP width, the dIPC/dSC ratio clearly decrease and tend to saturate. It was found that the presence of a 2 mm width IP did not affect the crystal shape uniformity using a 1.5 mm-thick seed. In contrast, as increasing IP width, the Δ T increases and tends to saturate. These results suggest the existence of a threshold value for ΔT which affects crystal distortion with same seed and IP thickness conditions at the initial growth stage. Although increasing the IP width expands the area of thermal resistance that hinders effective heat flux removal in the seed/graphite holder interface, it is thought that ΔT and dIPC/dGC ratio saturates when the IP width becomes sufficiently large onto seed diameter. This result suggests that even in the presence of IPs, the uniformity of the grown crystals can be maintained as long as the width of the IP is small. These results will help to quantitatively interpret the effects of IPs occurring in real experiments and the acceptable size of IPs.

ABSTRACT. Silicon carbide (SiC) exhibits excellent thermal conductivity of 5 W/cm·K and a wide bandgap of 3.3 eV, demonstrating remarkable applicability when used in conjunction with Gallium Oxide (Ga2O3), which possesses an even wider bandgap of 4.7 eV and responds to lower UV wavelengths than SiC. However, its low thermal conductivity of 0.2 W/cm·K remains a drawback. In this study, we fabricated Ga2O3/SiC heterojunction diodes by controlling the phase of the Ga2O3 film by deposition conditions and investigated their UV responsiveness, which exhibits favorable properties for UV sensor applications. Among the phases of Ga2O3 (α,β,ε,κ,γ), the β-phase features a high breakdown field of 8 MV/cm, making it suitable for power devices, while the ε-phase possesses ferroelectric properties that are advantageous for sensor applications. Thus, phase control is a critical challenge in effectively utilizing Ga2O3. We deposited Ga2O3 films on SiC substrates using pulsed laser deposition (PLD) and analyzed phase changes and characteristics of the Ga2O3 films based on oxygen partial pressure conditions. An n-type SiC epitaxial layer with a doping concentration of 1.0 × 1016 cm-3 and a thickness of 7 μm was utilized. Ga2O3 layers approximately 400 nm thick were deposited at oxygen partial pressures of 0 mTorr, 20 mTorr, and 50 mTorr, followed by rapid thermal annealing (RTA) at 1050 °C. Schottky contacts were then formed using nickel (Ni), completing the Ni/Ga2O3/4H-SiC heterojunction Schottky barrier diode (SBD) structure. The uniform deposition was confirmed using scanning electron microscopy (SEM), as shown in Fig. 1. X-ray diffraction (XRD) results in Fig. 2. indicated peaks corresponding to β-Ga2O3 at 2θ = 18.8°, 38.3°, and 59.1°. Additionally, an ε-Ga2O3 (006) peak was observed at 50 mTorr, confirming that phase transformations occur during the PLD process depending on the oxygen partial pressure. In Fig. 3., The reverse current-voltage characteristics under UV illumination (λ = 256 nm) were measured to assess UV responsiveness, showing that Ga2O3/SiC heterojunction diodes exhibited superior Photo-to-Dark Current Ratios (PDCR) compared to SiC SBD and Ga2O3 SBD. The PDCR values for oxygen pressures of 0, 20, and 50 mTorr were calculated as 548, 1740, and 12200, respectively, confirming that PDCR increases with oxygen pressure. Fig. 4. X-ray photoelectron spectroscopy (XPS) analysis revealed that the density of oxygen vacancies (VO) was substantially reduced at 50 mTorr, leading to the formation of a thick depletion region within the Ga2O3, with a depletion width of 1.41 μm at this pressure. This enhancement contributes to increased electron-hole pair generation when absorbing 256 nm light. Furthermore, reducing the density of oxygen vacancies can improve carrier transport, confirming the improved device characteristics. And show in Fig. 5., The hysteresis effect at higher oxygen pressures was also measured, indicating the presence of ferroelectric characteristics. In conclusion, this study successfully achieved phase control of Ga2O3 films during the fabrication of Ga2O3/SiC heterojunction SBD based on deposition conditions, with the most pronounced performance observed at 50 mTorr. This presents promising potential applications in future power semiconductor and sensor technologies.

ABSTRACT. Optimizing the physical vapor transport (PVT) growth of high-quality, single-crystal silicon carbide (SiC) relies heavily on the selection and performance of consumable materials within the hot zone. Due to the extreme temperatures required for crystal growth, only a limited range of construction materials, primarily graphitic, are suitable for use. Common components include isographite crucibles, which serve as induction-heated susceptors in the reactor; graphite felt, used for thermal insulation; and porous graphite that facilitates a regulated growth rate and improves crystal quality. Carbon plays a critical thermodynamic role in the PVT process, and its availability within the system often leads to the gradual consumption of these carbon-based components during growth. Porous graphite, strategically placed between the source powder and the seed crystal, serves as a supplementary carbon source, helping to maintain the correct stoichiometric balance. This configuration enables precise control over the carbon vapor species and the Si/C vapor phase ratio within the crucible. As a result, structural defects such as micropipes are minimized, and the formation of the desired 4H-SiC polytype is promoted [1]. These carbon materials are required to be of high purity to avoid crossover contamination of the crystal. The graphites are subjected to high-temperature advanced purifications that reduce impurities to ppb levels. The properties of porous graphite impact crystal growth rates and quality. Incorporating porous graphite in the reactor enables controlled growth rates, better crystal quality, and an improved radial temperature gradient as compared with PVT reactors run without the use of porous graphite [1].

During the sublimation of SiC source powder, there is often a carbon deficit in the vapor phase. One solution to contend with this is to alter the reactivity of the porous graphite, in combination with its porosity, to meet the growth profile. Tuning the porous graphite’s properties allows for an increase or decrease of carbon atoms available for stoichiometric balance during the growth process. Modeling the reactivity of the carbon phase using reactive molecular dynamics to achieve optimum stoichiometry for SiC growth speeds up the material science developments, see illustration in Fig. 1.

Graphite felt insulation is crucial in high-temperature vacuum environments, particularly in advanced materials manufacturing such as SiC crystal growth via PVT. Its unique thermal stability and insulating properties make it indispensable for thermal management in these specialized environments. Felt's fibrous composition significantly reduces heat transfer through radiation and residual gas conduction, even in near-vacuum conditions. This exceptional thermal resistance allows for precise temperature control in critical processes, ultimately enhancing product quality and process efficiency. We have continuously optimized the properties of our graphite felts via computer simulation and experimental testing throughout several felt material development efforts to achieve a 30% reduction in energy consumption at near-crystal growth temperature. Fig. 2 shows a progressive reduction in power consumption following our materials development work.

Collaboration with the Silicon Carbide Innovation Alliance (SCIA) at The Pennsylvania State University will allow for a better understanding and optimization of the graphite-based hot zone.

[1] H.J. Lee, H.T. Lee, H.W. Shin, M.S. Park, Y.S. Jang, W.J. Lee, I.G. Yeo, T.H. Eun, J.Y. Kim, M.C. Chun, S.H. Lee, J.G. Kim, Effect of porous graphite for high-quality SiC crystal growth by PVT method, in: Materials Science Forum, Trans Tech Publications Ltd, 2015: pp. 43–46. https://doi.org/10.4028/www.scientific.net/MSF.821-823.43.

ABSTRACT. Diamond abrasives are well known in the manufacturing of silicon carbide wafers and are used at various process points from ingot shaping to wafer isolation to lapping and fine grinding. Because of its extreme hardness, diamond provides a mechanical removal action on a silicon carbide surface in both fixed bond systems and in a slurry as a free abrasive. We have demonstrated that an etched surface can be produced on diamonds as fine as 0.25 microns in diameter and that the nano-scale features of this diamond can significantly enhance the material removal rate and surface finish of the Si-side of a SiC wafer when used in a polishing slurry. As shown in Fig. 1, we have also demonstrated that epi-layers grown on a diamond-polished surface with an additional reduced conventional CMP can achieve the same quality epi-layer as just CMP alone for the same overall thickness removal. This modified process, which uses conventional CMP polishing platforms, can generate significant savings by reducing overall usage of slurry as well as in reduced waste disposal costs. This poster reports on the impact of key process parameters on the material removal rate (MRR), surface roughness and total thickness variation (TTV) using a diamond slurry/CMP process.

The key objective of this study is to measure the effect that process parameters have on the performance of the diamond slurry using an industrial-scale single wafer CMP polishing machine. As an example, it was found that by reducing the diamond slurry flow rate to the polishing pad from 50 ml/min to 10 ml/min, the material removal rate of the wafer was not reduced. In fact, as shown in Fig. 2, the thickness removal rate increased at the lower flowrate. This is a key finding because the slurry consumption per wafer is a significant portion of the cost of CMP. Maintaining high thickness removal rates at low flowrates enables diamond slurry to be used at much lower consumption levels than conventional CMP. This feature of the diamond slurry did not adversely affect the surface roughness or TTV of the wafers. Another behavior of diamond slurry is that it is responsive to the platen temperature. In contrast to conventional CMP, our tests have shown that the material removal rate achieved using diamond slurry can be significantly increased when the platen temperature is reduced from 50°C to 28°C. Since the diamond slurry does not chemically interact with silicon carbide, the process runs cool, and lower temperature control is easy to maintain. Again, this feature of diamond slurry improves the value proposition and potential for cost savings by reducing process time and slurry consumption.

Additional process parameters were adjusted and measured to determine the performance response. These include platen/carrier rpm’s, wafer pressure control, pad conditioning and pad types, and different slurry characteristics. The polished wafers were all measured for MRR, surface roughness and TTV. This poster describes the outcome of this work and the impact the optimization has on the cost and throughput value proposition.

ABSTRACT. High-purity silicon carbide (SiC) semiconductor material, with its exceptional refractive index, extreme hardness, and outstanding thermal conductivity, has emerged as the premier candidate for fabricating AR lenses, solidifying its position as the optimal choice for next-generation diffractive waveguide optical components. 8-inch (Φ200 mm) high-purity 4H-SiC single crystals were grown by physical vapor transport method (PVT) and cut into 8-inch semi-insulating 4H-SiC substrates with thickness of 500 μm by laser cutting. The polytype, crystalline quality, micropipe density, resistivity and wafer shape of the substrates were characterized by Raman spectroscopy, high resolution X-ray diffraction (HRXRD), automatic microscope scanning, noncontact resistivity measurement and wafer flatness tester. Raman spectra show that 8-inch substrate consists only 4H polytype. The average full-width at half-maximum of (004) diffraction peaks is 34.8 arcsec, which indicates the good crystalline quality of the wafer. Micropipe density is 0.01 cm-2. Resistivity of whole wafer is higher than 1E12 Ω•cm. TTV and Warp are 1.08 μm and 4.09 μm, respectively. All results indicate the high quality of the 8-inch high-purity 4H-SiC substrate, which meets the requirements for AR lens applications.

ABSTRACT. Polytypism is a special one dimensional form of polymorphism and a general behaviour of layered structures. The structural reason for this phenomenon is a low stacking fault energy and the possibility to form different modes of stacking of two dimensional structural compatible units along a defined di¬rection. Physically the phenomena of polytypism and polymorphism are quite different from one an¬other. The polymorphs of a material represents well defined thermodynamic phases, with well specified stability ranges of temperature, composition and pressure. The transition from one polymorph to another is a first-order phase transformation. On contrary, except for a very few short period modifications, no such physical factors have been found to govern the formation of polytypes. Different polytypes of a given material appear under identical conditions of temperature and pressure and display syntactic coa¬lescence of polytypes. This cause the generation of undesired microheterogeneous systems in the form of syntactical inclusions of different individual polytypes during device processing and operation. The occurrence of such transitions was observed in all semiconductors manufacturing processing steps, i.e. impurity diffusion, ion implantation, sputtering, oxidation, metallization and epitaxial growth. Further¬more, polytype transitions occur during the operation of semiconductor devices. The polytype transi¬tions are caused by the evolution of existing disorder or the generation of disorder in the initial structure due to energy dissipation. The dissipated energy is related to thermodynamic fluxes and forces of the ongoing processes leading and the interconnected nonequilibrium state. This cause entropy production as shown schematically in Fig. 1. The entropy production can be described using the approach of nonequilibrium thermodynamics: dS⁄(dt= ∫▒(∑_i▒∑_j▒〖B_ij I_i 〗 X_j )dV), with S – Entropy, t – time, V – Vo¬lume, Bij – coupling coefficient, Ii – thermodynamic flux of the ith process, Xj – thermodynamic force of the jth process acting on the polytype material. From the structural point of view The disorder is strongly connected to the formation and propagation of stacking faults (SF) and partial dislocations (PD). The local structural changes induced by the SFs are polytype inclusions, i.e. are able to act as information centers for the nucleation and growth of extended regions having a polytype structures. Energy dissipation in the crystal lead to an information excess with respect to the polytype structure (Fig. 2). Collective and selective interactions between these defects result in a stability loss of the original structure. Reaching the critical situation nonequilibrium polytype phase transition occur which lead to the formation of a new polytype structure which is better adapted to the exterior conditions. Schematically, the non-equilibrium phase transitions can be described as: Order  stacking fault generation  defined disorder  “catastrophe”  new order. Introducing an ordering time of the initial polytype i ord i necessary to incorporate the defects into the lattice and to rearrange the lattice stacking the critical situation for polytype transformation within the framework of nonequilibrium thermodynamics can be described using the following criteria: ∆S_(exs i)= dS⁄dt τ_(ord i)< ∆S_(exs crit), ∆S_(exs crit) – critical excess entropy leading to polytype transitions. It is given in Fig. 3. In the presentation the implication for crystal growth, ion implantation and plasic deformation will be demonstrated.

ABSTRACT. To improve large-diameter 4H-SiC crystal growth by solution method, we investigated the effect of interfacial supersaturation on growth rate and surface morphology. Experiments using a 2-inch seed crystal were combined with thermo-fluid simulations, suggesting that interfacial supersaturation at the growth front, induced by the temperature distribution in the solvent, varies with the growth conditions, thereby affecting the growth rate and crystal morphology.

ABSTRACT. This paper reports on studies of the defect formation during the early stage of SiC physical vapor transport (PVT) growth through a combined analysis of the near-seed crystal region of grown crystal using X-ray topography and UV-excited photoluminescence imaging. The results revealed that threading screw dislocations and threading edge dislocations showed different behaviors in terms of their formation and recombination near the grown crystal/seed interface. At the conference, we will present detailed data of their behaviors near the interface, and based on the data, discuss the defect formation mechanism during the early stage of PVT-growth of 4H-SiC crystals.

ABSTRACT. Sonic Lift-off (SLO) technology provides a pathway for greater utilization of the SiC material as an alternative to backgrinding. Contrary to methods such as laser split and spalling, SLO creates smooth surfaces with no subsurface damage, leaving the parent substrate surface ready for reprocessing. In this work, we demonstrate the impact of applied stress on surface roughness for n-type SiC wafers. Three regimes are defined based on the stress level: no crack propagation, controlled propagation and uncontrolled propagation. By controlling the amount stress in the system the surface roughness can be reduced from 14.5±2.3um to 0.7±0.2um. This fine crack control enables SLO to become a valuable alternative to backgrinding with the additional benefit of reusing the SiC wafer.

ABSTRACT. Silicon carbide (SiC) is one of the third generation semiconductor materials that have received wide attention, with excellent properties such as wide band-gap, high breakdown field, high saturation electron drift rate and high thermal conductivity, which is an excellent material for making high temperature, high frequency, high power and low loss devices. Besides high quality SiC substrate with larger diameter, high quality SiC epitaxial layer is another key factor that will affect device performance. Two aspects of high quality SiC epitaxial layer should be payed attentioned to. One is the uniformity of thickness and carrier concentration, and the other is decreasing of epitaxial defect numbers. The following shows the progress of our team on the these two aspects: The uniformity and accuracy of epitaxial thickness and carrier concentration would affect the electrical performance of devices. Poor uniformities of epitaxial thickness and carrier concentration would causes fluctuations in breakdown voltage, resistance, current and even failure of devices. Compared with the 6-inch epitaxial growth process, we have adopted a better thermal field structure and the gas distribution is also more uniform for the 8-inch epitaxial growth. The growth temperature, carbon-silicon ratio and growth rate are further optimized which is more adaptable to 8-inch SiC substrates. As a result, our concentration uniformity of the 8-inch epitaxial products can be controlled at ≤2%, and the thickness uniformity can be controlled at ≤1%, which are shown in Figure 1. The morphological defects such as carrots, shallow triangles, triangles, large pits and BPDs in SiC epitaxial layers would seriously affect the performance of SiC devices and sometimes also caused failure of devices. By optimizing the process temperature, C/Si ratio, growth rate and growth pressure, most of the defects are elimated and the yield of the 8-inch epitaxial products can be achieved above 98% (3mm*3mm), which are shown in Fig. 2.

ABSTRACT. The development of novel materials demands a long cycle from design through commercialization, and conventional trial‐and‐error research alone cannot achieve high‐performance materials. In the semiconductor industry, single‐crystal substrates must maintain both high quality and cost competitiveness; however, uncontrollable process variables degrade reproducibility, and the application of design of experiments (DOE) becomes difficult, prolonging optimization timelines. Recently, Process Informatics (PI)–based databases and artificial intelligence (AI) technologies have emerged as promising solutions for optimizing SiC single‐crystal growth processes, which suffer from low reproducibility, diverse variables, and the impracticality of real‐time monitoring. Process Informatics, a subfield of Materials Informatics, leverages process data to analyze, design, and improve manufacturing workflows. In particular, adopting an ontology‐based data structure to define hierarchies among material properties, process variables, and measurement results enables efficient integration and management of heterogeneous data, thereby facilitating process design, optimization, and AI solution development. Figure 1 illustrates an example schema in which this ontology structure is mapped onto a relational database to store and query various experimental and simulation data in a consistent format. Figure 2 presents a conceptual diagram of a Knowledge Base (KB) that combines a large language model (LLM) with retrieval‐augmented generation (RAG). This KB delivers query‐optimized information to researchers based on literature and experimental data, with a real‐time feedback loop supporting continuous learning. Because SiC crystal growth is cost‐intensive and time‐consuming—making purely experiment‐driven machine learning models impractical—Figure 3 shows how we collected thousands of simulation results from a multi‐physics model of the PVT process, compressed them into a latent space via a Variational Autoencoder (VAE), and trained a regression network to build a lightweight surrogate model. This surrogate can rapidly predict growth patterns from input conditions without requiring full FEM analysis. By integrating an ontology‐based database, an RAG‐powered KB, and a VAE surrogate model, this PI–AI platform offers a novel approach to overcoming the lengthy development cycles in semiconductor and crystal‐growth research and is expected to see broad application in both research and industry.

ABSTRACT. Silicon carbide power devices are now key components for high-power electronics, including inverters, power supplies, DC/DC converter for the markets of electrical mobility, industry, data centers, energy grids and solar plants. Among its unique properties, high electric field breakdown capability and high thermal conductivity both make SiC a material of choice for power devices [1]. SmartCut™ technology proposed by Soitec allows the transfer of a thin layer of commercially available monocrystalline Silicon Carbide (mSiC) on a polycrystalline Silicon Carbide (pSiC) substrate, according to process scheme shown on Figure 1, leading to the already presented SmartSiCTM engineered substrate [2]. SmartSiCTM substrate demonstration in both 150mm and 200mm diameter has also been reported [3].

Manufacturing and product cost optimisation of SiC power devices is pushing the industry for the use of 200mm diameter SiC Semiconductor wafers with a thickness of 350 microns. To follow this trend, SiC enginnered substrate, fully compatible with such industry demand is reported, confirming the versatility of SmartCutTM technology to deliver high quality layer transfer on ultra-low resistivity handle material whatever substrate diameters & thicknesses.

pSiC substrate wafering is key to support preparation of the SmartSiCTM substrate, from 150 to 200mm diameter and from 500 down to 350µm thickness. Thanks to the CVD growth technology and its associated pSiC material homogeneous properties in depth [4], electrical performance, among other identified critical parameters, is kept unchanged whatever the substrate diameter/thickness as shown on Figure 2a. Also we demonstrate equivalent substrate geometry performance other such product window, as shown through bow and warpage parameters on Figure 2b.

SmartSiCTM substrate surface defect density is controlled thanks to KLA Tencor SPA2, allowing to monitor low threshold signal down to 300nm [5]. As shown on Figure 3a, 300nm surface defect density is kept unchanged whatever the wafer thickness, as expected regarding defect origin pareto. Figure 3b emphasize such results, showing typical a SmartSiCTM 300nm surface defect mapping. Similarly, thanks to finishing process control, same transferred layer thickness, measured thanks to ellipsometry, is obtained on all SmartSiCTM products, while total wafer thickness is adapted according to product target as reported on Figure 4a & 4b respectively.

Acknowledgment This work is funded by the Chips Joint Undertaking (JU) under grant agreement No 101139788, FASTLANE project ‘Boosting the European Value Chain for Sustainable Power Electronics’.

[1] T. Kimoto, Jpn. J. Appl. Phys. 54 04 0103 (2015) [2] S. Rouchier et al., “150 mm SiC engineered substrates for high-voltage power devices”, ECSCRM Conference, 2021 [3] W. Schwarzenbach et al., “SmartSiCTM : Boosting SiC performance for high-voltage power applications“, ICSCRM Conference, 2022 [4] H. Biard et al., “Masterization of poly-SiC characterization and properties for SmartSiCTM substrates enabling high performance power devices“, ICSCRM Conference, 2023 [5] E. Cela et al., “DUV laser-based defect inspection of single-crystal 4H-SiC and SmartSiCTM engineered substrates for high volume manufacturing”, ICSCRM Conference, 2024

ABSTRACT. High temperature processes such as the PVT process intended to grow SiC monocrystals use graphite as crucible material and carbon fiber-based materials as insulation. The performance of these insulation materials is obviously directly related to their thermal conductivity, which should be minimized. In addition, as inductive heating is often used in the PVT process, the electrical conductivity of the insulation is also of great importance. This will dictate their coupling with the magnetic field, i.e. the power that is injected in the insulation, to the detriment of the crucible. However, very few studies can be found in the literature regarding the evaluation of electrical conductivity of carbon fibre-based insulation. The difficulty is inherent to the fibrous nature of the materials, since it renders the standard contact method (e.g. 4-probes method) difficult to apply. Although a non-contact method (eddy current based) is feasible, it can only be applied to standard geometries whereas insulation sets in application regularly have non-standard design. In addition, it cannot be easily applied at high temperature.

In this work, we present a methodology based on a dialogue between experiment and modelling that enables determination of the apparent electrical conductivity of any carbon fiber-based insulation. For the experimental part, we placed the insulation inside a coil that represented an RLC circuit, with known value of capacitance C. In our case, the RLC circuit was directly that which was used for inductive heating of our lab-scale PVT furnace. Then we probed the RLC circuit by applying a short voltage pulse and monitored its attenuation in the RLC circuit. After data processing, this gave the value of the resonance frequency, the inductance L and the resistance R. Part of the resistance is associated to the insulation placed into the coil. Then, we used a fitting procedure that relies on finite element modelling which allowed us to retrieve an apparent electrical conductivity from the measured R. With this method, the apparent electrical conductivity was determined at room temperature for insulations with varying properties (heat treatment, fiber nature, etc.) and geometries. Methodological developments are underway to assess this apparent electrical conductivity at high temperatures (~2000°C), and some initial results will be presented. From the apparent electrical conductivity values extracted, the efficiency of the inductive heating (power injected in crucible vs. insulation) for any furnace geometry can be assessed with modelling. Some examples will be discussed. Then, when a compromise exists between thermal and electrical conductivity, these simulations – coupled with heat exchanges modelling - can be used to make the wisest choice of insulation to minimize the power consumption required to reach the desired temperature in the growth chamber.

ABSTRACT. In order to realize an energy-saving society, the social implementation of SiC semiconductor devices is progressing. The issue with the social implementation of SiC is the cost, and cost reduction is also required for the CMP process. Accordingly, the CMP slurry is moving toward increasing the oxidizer concentration to lower the CoO.

One method of formulating a high oxidizer concentration is to use sodium permanganate (SPM), which has a high water solubility. However, from our past studies, it has been found that the ignition risk increases when highly soluble sodium permanganate’s concentration increases. For example, when a cellulose such as Kimwipe contacts to slurry including high concentrated sodium permanganate, the temperature of Kimwipe becomes hotter and eventually ignites. On the other hand, when potassium permanganate applied, it does not ignite due to its solubility is relatively low, and meaning it is impossible to further improve removal rate.

After through research into how to achieve both high RR and high ignition resistance, we succeeded in developing a new technologies regarding Additive A and Additive B.

Using this technology, we were able to develop a new slurry. New slurry #1 includes Additive A shows excellent RR at a higher dilution ratio as expected, and ignition is suppressed as well. Specifically, new slurry #1 shows a removal rate at 4 times dilution that is almost the same as that of our conventional product (DSC502) at 2 times dilution.

New Slurry #1 was confirmed to have low ignition potential in the laboratory, we further tested the anti-ignition potential under relatively severe conditions. When SPM or its dried solid that does not contain Additive A it is brought into contact with Kimwipe in an environment of 60℃ or 70℃, it will ignite. On the other hand, New Slurry #1 or its dried solid is prevented from igniting, even in environments of 60°C or 70℃.

We have further developed higher ignition control technology by combination using Additive A and B (-> New slurry #2).

The ignition point control technology makes it possible to further increase the oxidant concentration in the slurry while keeping the risk of ignition low, making it possible to achieve even better CoO performance.

ABSTRACT. The mass production of 8-inch wafers for power semiconductor devices using silicon carbide (SiC) is becoming more widespread. In the SiC device manufacturing process, the cleaning process is important to ensure high device yields. On the other hand, low running costs and high productivity are required. In this study, we optimize the DIW brush cleaning technology using spin scrubber. The cleaning method introduced here is to clean the bevel and the front side of a wafer simultaneously, which is capable to shorten the cleaning process. We have also evaluated the optimal brush materials for SiC wafers in terms of particle removal efficiency and damage to pattern on a wafer. The brush made of nylon achieves high particle removal efficiency while causing low damage to pattern on a wafer. In conclusion, this material can contribute significantly to the cleaning field of SiC wafers.

ABSTRACT. Micropipe defects in silicon carbide (SiC) materials are hollow tubular line defects formed during crystal growth, typically extending along the <0001> crystal growth direction. These defects significantly degrade the performance of SiC materials and their applications in semiconductor devices, leading to detrimental effects such as reduced breakdown voltage, increased leakage current, and diminished carrier mobility.[1-3] Consequently, controlling micropipe defects is critically important during the preparation of large-diameter SiC single crystals. Current characterization methods for micropipes primarily rely on various microscopy techniques: polarized transmission microscopy reveals stress variations induced by micropipes, while white-light interferometry precisely identifies their hollow core positions. In this paper, X-ray topography (XRT) is employed to systematically investigate the morphology of micropipe defects in SiC substrates and quantify their associated lattice distortion fields. The Burgers vectors of micropipes (MPs) are expressed as b ⃗_MP=±nc(n=3~10), whereas those of threading screw dislocations (TSDs) in SiC substrates are b ⃗_TSD=±mc(m=1,2).[4] When identifying MPs in SiC substrates using XRT systems, both MPs and TSDs coexist. The distinction between MPs and TSDs in XRT imaging arises from the inequality ||b ⃗_MP |>|b ⃗_TSD |. Figure 1 demonstrates the contrast between MPs and TSDs in SiC substrates under g ⃗ = 0008 diffraction conditions, where TSDs appear as small black dots while MPs manifest as large irregular dark regions. Figures 1a and 1b present XRT morphologies of double and single micropipes, respectively. In Figure 1a, two adjacent MPs (indicated by ellipses) exhibit coalescence due to mutual stress interactions, forming an extended void structure at their junction. Figure 1b reveals a singular micropipe with a central white void corresponding to its hollow core, surrounded by an extensive irregular dark region representing the lattice distortion area. This distorted region demonstrates atomic arrangements deviating from the intrinsic 4H-SiC structure, directly attributable to the strain field generated by the micropipe. The influence of micropipe area in silicon carbide (SiC) crystals on device performance is comprehensive, encompassing electrical characteristics, thermal stability, mechanical reliability, and manufacturing costs. Large-area micropipes significantly exacerbate device failure risks, particularly in high-voltage, high-temperature, and high-frequency applications. Consequently, controlling micropipe density and size represents a critical technology for enhancing the competitiveness of SiC-based devices. When characterizing micropipe areas in SiC substrates using white light interferometry (WLI) mode microscopy, micropipes exhibit diverse morphologies including elliptical and irregular configurations, as illustrated in Figure 2. By extracting major and minor axis dimensions from these morphological profiles, the corresponding micropipe areas were calculated, with results summarized in Table 1. The measurement range of micropipe dimensions in WLI predominantly falls within 5-10 μm. A synchronous statistical analysis of identical micropipes through X-ray topography (XRT) revealed that the central white spot areas corresponding to micropipes consistently approximate 10 μm. This comparative analysis demonstrates the feasibility of utilizing XRT as a direct characterization method for quantifying micropipe areas.

ABSTRACT. The impact of crystallographic defects on the performance of silicon carbide (SiC) devices is a critical concern, with the definition of so-called "killer" defects being strongly application-dependent. While photoluminescence (PL) imaging microscopy at a single wavelength band is widely used for defect detection in SiC epilayers, particularly for polytype inclusions and stacking faults [1], PL spectroscopy is often necessary to determine the subclassification of stacking faults [2]. Substrate defect characterization traditionally relies on a combination of X-ray topography (XRT) and destructive KOH etching [3]. This combination suffers from limitations in non-destructiveness, defect specificity, and efficiency, as XRT can generally detect threading screw dislocations (TSDs), threading mixed dislocations (TMDs), and basal plane dislocations (BPDs), while struggling to detect threading edge dislocations (TEDs). This work presents a novel non-destructive approach to deep defect imaging for defect detection in SiC substrates and epilayers using the MONSTR Sense KRAKEN™ Ultrafast Imaging microscope. The KRAKEN uses two unique, simultaneous channels: Transient Absorption (TA) and Polarized Linear Absorption (PLA). This instrument employs an ultrafast laser with a degenerate pump-probe configuration tuned near the SiC bandgap. We use a combination of laser-scanning and stage scanning to rapidly acquire images. The pump pulse excites carriers in the conduction band of the material, which alters the reflectivity of the probe. Due to defect-induced band structure modifications of the probe beam's reflectivity near the band edge, the TA channel exhibits high sensitivity to defects. The PLA channel uses a polarizer for defect contrast, while the TA channel uses a finite delay to obtain an effectively background-free image of defects. Fig. 1(a,b) shows an example of a background-free defect image for a polytype inclusion and a stacking fault. We demonstrate the deep imaging capabilities of our system by acquiring these images with the carbon side facing up for a 350 µm substrate and 10 µm epilayer, thus imaging these epi-defects through the 350 µm substrate. Fig. 1(c) shows a volumetric projection of a transient absorption measurement of a stacking fault. The growth along the basal plane direction can be observed along the 4-degree tilted dashed line. Using our tool, we also show the correlation of epi-defects to defects in the substrate. Fig. 1(d) shows the PLA channel for an epi-wafer over a sub-millimeter field of view. The dipole-shaped features are threading dislocations, specifically TEDs, TMDs, and micropipes [4]. Fig. 1(e) shows the TA channel for the same field-of-view as Fig. 1(d), indicating the presence of a stacking fault. The outline of the stacking fault can also be faintly seen in Fig. 1(d). The stacking fault apex is very close to a threading dislocation, highlighted by the red rectangle, indicating a potential threading dislocation to stacking fault conversion. Comparative analysis with XRT in Fig. 2 and Table 1 demonstrates the high sensitivity of our technique toward threading dislocations. In Fig. 2, we compare PLA to XRT for a 3 mm x 3mm area. Fig. 2(a) shows the PLA channel, while Fig. 2(b) shows the (0008) XRT channel for the same field of view as Fig. 2(a). The (0008) XRT is particularly sensitive to threading dislocations. The corresponding detection statistics are shown in Table 1. The PLA is sensitive to 75% of all XRT Detections, with the remaining 25% likely attributed to pure threading screw dislocations that are not detected in PLA [4]. Notably, XRT has only a 48% Sensitivity to all threading dislocations, as it misses many threading edge dislocations present in this area of the wafer. Consequently, PLA demonstrates an enhanced sensitivity of 87% to all threading dislocations. The complementary nature of PLA and XRT potentially eliminates the need for destructive KOH etching. Importantly, these threading dislocations can be imaged much deeper than the substrate, with penetration depths of a few millimeters readily achievable. Future work will focus on using additional XRT Channels and KOH etch to distinguish TSDs, TMDs, and TEDs, and further refine our automated detection algorithm using this training data. Additionally, we plan to refine our TA channel and extend our defect detection capabilities to additional defects, including BPDs. Given that the TA channel is sensitive to all PL-detectable epilayer defects, coupled with our promising results in substrate defect characterization presented in this abstract, this work highlights the progress towards a comprehensive single-tool solution for SiC defect analysis.

[1] PC Chen, WC Miao, T. Ahmed, YY Pan, CL Lin, SC Chen, HX Kuo, CY Tsui, DH Lien, Nanoscale Res. Lett. 17, 30 (2022) [2] Moonkyong Na, Wook Bahng, Hyundon Jung, Chanhyoung Oh, Donghyun Jang, Soon-Ku Hong, Materials Science in Semiconductor Processing 175, 1088247 (2024) [3] Christian Kranert, Paul Wimmer, Alexis Drouin, Christian Reimann, Jochen Friedrich, Materials Science in Semiconductor Processing 170, 107948 (2024) [4] Shunta Harada, Kenta Murayama, Journal of Crystal Growth 650, 127982 (2025)

ABSTRACT. 8-inch 4H-SiC single crystals were grown under different temperature fields and nitrogen doping conditions by physical vapor transport method. The distributions of basal plane dislocation (BPD) in 4H-SiC single crystals under different growth conditions were studied by molten KOH etching and X-ray Topography (XRT). The results indicate that the BPDs in the crystals grown under convex temperature field are distributed at the edge. In comparison, the BPD distributions in crystals grown under a concave temperature field are relatively closer to the center. Furthermore, the BPDs distributions in nitrogen-doped crystals exhibit quadratic symmetry caused by prismatic slip. In contrast, no prismatic slip-induced slip bands were observed in the undoped crystals, and the BPD distributions in the undoped crystals are consistent with the shear stress distribution caused by basal plane slip.

ABSTRACT. Chemical mechanical polishing (CMP) is an established technology renowned for its ability to achieve exceptional global planarization while preventing subsurface damage on the 4H-SiC wafer. A High-precision polished surface with atomic-scale roughness, free from scratches and subsurface damage, is essential prior to epitaxial growth. However, despite the absence of visible surface defects on wafers following the CMP process, it has been reported that scratch-like surface irregularities, characterized by locally formed rows of step bunching, occasionally emerge on wafer surfaces after epitaxial growth. Previous studies have elucidated that the formation of step bunching rows is attributable to crystal defects newly introduced in the subsurface regions of wafers during the CMP process. These defects persist post-CMP, contributing to scratch-like polishing damage that remains in the subsurface regions of wafers even after the CMP . Such defects are often undetectable using conventional optical microscopy. In recent years, numerous researchers and engineers have made significant improvements to the CMP processes, resulting in the supply of wafers with minimal such polishing damage. However, accidental polishing damage can still occur due to process anomalies, necessitating constant monitoring and control. Furthermore, as wafer sizes increase, similar issues often re-emerge, making the efficient detection and classification of polishing damage critically important. Mirror projection electron microscope (MPJ) can visualize slight potential change due to the surface morphology of the epitaxial layer and local charging of the crystal defects beneath the surface. Therefore, MPJ is recognized as one of the most powerful and promising methods for inspecting the distribution of such polishing damage over the whole wafer. In our previous studies, the relationship between the contrast formation and the distribution of crystal defects of latent polishing damage showing dark contrast in the MPJ images. However, scrach-like polishing damage showing bright contrast in MPJ images is not yet thoroughly understood. This study aims to evaluate the detailed structure of polishing-induced damage, which appears as bright contrast in MPJ images, with the ultimate goal of achieving a comprehensive classification of polishing damage. Commercially available 4-inch n-type 4H-SiC(0001) wafers with a 4°off-orientation toward the [11-20] direction after CMP process were used in this study. The surface morphologies were investigated by MPJ. Cross-sectional and Plan-view observations of polishing damage were performed using transmission electron microscopy (TEM) and Scanning TEM (STEM), respectively. Initially, scratch-like polishing damage that was locally induced in the 4H-SiC wafer during CMP was systematically characterized and classified using MPJ. Figure 1 shows MPJ images of polishing damage A and B which were found in the MPJ inspection. Based on the principles of contrast formation in MPJ images, A showing bright line contrast is polishing damage with only surface roughness. In contrast, B showing dark line contrast is believed to be polishing damage with internal crystal defects, commonly referred to as latent polishing damage. Figure 2 shows plan-view TEM images of polishing damage A and B. The plan-view TEM image of B revealed that dislocation loops were generated along the damage line as repoted before. In contrast, distinct dislocation loops were not observed in A. There was contrast like a series of spots along the damage in the TEM image. Figure 3 shows cross-sectional STEM images of polishing damage A. No distinct crystal defects were observed within the substrate in Fig. 3(a). Lattice images near the surface revealed the presence of depressions approximately 1 nm in depth. In these depressed regions, atomic arrangement irregularities were observed. Therefore, the contrast modulation observed in plan-view TEM images of A is considered to be caused by this slight strain. In conclusion, MPJ enables classification of shallow polishing damage with only surface roughness and latent polishing damage that contain crystal defect within the substrate, based on MPJ contrast analysis.

ABSTRACT. As silicon carbide technology continues to mature, higher demands are put on each of the processing steps. One area where increased monitoring is desired is during the different oxidation steps that take place during device fabrication. This is due to the wide variety of different oxides that are used. This could be a chemical vapor deposited (CVD) oxide to use as a hard mask [1], a thermal oxide to use as a gate oxide for SiC MOS devices [2], or an atomic layer deposited (ALD) oxide for special applications [3]. What further complicates the oxidation processes is that further processing might affect the properties of the final oxide. The gate oxide quality of a MOS transistor is, e.g., also dependent on the surface quality of the substrate, implying that gate oxide optimization also includes the activation anneal after ion implantation. So, if certain oxide properties are desired, a good understanding of the processing steps and their effects on the oxide are required. Hence, inline control measurements for oxide properties are needed which are quick and do not require any test structures. This study aims to investigate the influence of different processing steps on oxide characteristics. A contactless corona-based capacitance voltage (CV) (CnCV) technique has been used to characterize the oxides. The CnCV technique uses a corona spot charging device and a Kelvin probe to perform a CV measurement of the oxidized wafers. From these measurements it is possible to extract the equivalent oxide thickness (EOT), total dielectric charge (Qtot), flatband voltage (VFB), and the distribution of interface trap densities (Dit) can be calculated up to about 0.8 eV from the band edge. The CnCV technique can be used on bare oxides and does not require any test structures. This makes CnCV a strong candidate for inline process monitoring as the contactless nature and the lack of test structure manufacturing enables fast measurements and the wafers can be returned into the processing line afterwards.

For this study several 150 mm 4H-SiC epiwafers have been used with n-type net doping concentration of about 8.9*1015 cm-3, and epi thicknesses in the range of 10.8 to 12.3 µm. These epiwafers received an oxide with a target thickness between 50 nm and 60 nm, either by a low pressure CVD (LPCVD) tetraethylorthosilicate (TEOS) deposition at about 700 °C or by thermal dry oxidation at about 1300 °C. The wafers were partially subjected to different treatments such as, time coupled HF dips prior to oxidation for surface conditioning and post oxidation anneals in NO at 1300 °C. The samples were then measured on a CnCV 230 from Semilab SDI with a recipe for oxide characterization. The results of these measurements are summarized in Table 1. For the LPCVD TEOS oxide wafers (wafers 1, 2, 3 in Table 1), it is obvious that the NO anneal is significantly lowering the VFB and Dit. The post oxide layer formation NO anneal is known to reduce the Dit for the oxide in question [4]. The VFB dropped by 3.05 V and the Dit by a factor of 6. Looking at wafers 2 and 3 that both got the NO anneal they both have about 2 nm thicker EOT than wafer 1 which did not get the NO anneal. Considering the thermally oxidized wafers 4, 5 and 6 some of the same trends are present. For example, wafer 5 has 1.55 V lower VFB than wafer 4 with the only difference being that wafer 5 has gotten the NO annealing. Table 1 also shows that wafers 5 and 6 have about a 4.5-5 nm thicker EOT than wafer 4 that did not get the NO anneal. The decrease in the Dit is not as noticeable in the case of the thermally grown oxides, looking at wafer 4 and 5 that only differ regarding the NO annealing process, it is clear that the Dit is lower on wafer 5 that got the NO annealing step. Wafer 5 has a 1.3 times lower Dit compared to wafer 4 that did not get the NO annealing step. This makes it clear that the NO annealing step is lowering VFB and Dit while increasing the EOT. In the final study more processing steps, such as the activation anneal after implantation will be added to the analysis.

Another great feature of the CnCV platform used in this study is that the Kelvin probe can be used to map the surface voltage of the oxide. Such a map showing a quarter of a wafer can be seen in Figure 1. Fig.1 a) shows how the wafer looks after a CV measurement where Corona charge was deposited in the circle with a surface voltage of about -25 V and Fig. 1 b) shows the wafer after a rinse in deionized water. As experimental wafers, the wafer could not go into any tool for drying, and that’s why the drying marks are visible in Fig. 1 b). But all the charge was clearly removed from the surface of the oxide.

ABSTRACT. SiC power semiconductors are rapidly gaining market share as core devices in next-generation power electronics—electric vehicles, renewable‐energy inverters, and smart grids—thanks to their high voltage and current handling capabilities and excellent thermal properties. To meet ever more stringent demands for higher performance, tighter quality standards, and increased productivity, it is essential to improve both the quality and wafer size of SiC single-crystal substrates, underscoring the critical importance of advanced SiC material development. Although over 200 SiC polytypes are theoretically possible, 3C, 4H, 6H, and 15R-SiC are commonly observed polytypes in practice. Among these, 4H-SiC single-crystal substrates have become the industry standard for power devices because of their wide bandgap and superior charge‐transport characteristics. Each polytype’s distinct crystal structure gives rise to different electronic band structures, bandgap energies, and dopant or defect energy levels. In the early stages of R&D for SiC single-crystal growth, preventing unwanted polytype inclusion is a top priority. This challenge must be addressed through optimization of every element of the process—from source material and graphite crucible composition to reactor design. To meet these industrial needs, we led the international standardization of a polytype‐analysis method based on ultraviolet photoluminescence: by illuminating SiC single crystals with >3.2 eV UV white light and analyzing the resulting fluorescence spectra, we established and ratified an ISO standard for rapid polytype identification.[1, 2] Typically, 4H-SiC exhibits a greenish luminescence owing to donor–acceptor‐pair (DAP) luminescence.[3] The primary dopants in SiC are N, P, Al, and B: N and P produce shallow donor levels, Al yields a shallow acceptor level, while B creates a deeper acceptor level that promotes visible DAP luminescence. [4] In this study, we first used glow-discharge mass spectrometry (GDMS) to quantify N, P, Al, and B concentrations in several SiC source materials. We then grew crystals from the same sources under varied PVT conditions and characterized the samples by UV photoluminescence, Raman spectroscopy, and X-ray diffraction. Although nitrogen is intentionally doped at high levels for power devices, P, Al, and B concentrations vary with the source, leading to different luminescence behaviors. Our results show that samples grown from sources with B ≥10¹⁸ cm⁻³ exhibit strong UV DAP luminescence, whereas those with B <10¹⁷ cm⁻³ show negligible UV fluorescence regardless of crystal quality, displaying only weak peaks associated with polytype inclusions or micro defects. Notably, even low-B sources produced slightly enhanced UV emission when the growth temperature exceeded 2500 °C. These findings demonstrate that both B-dopant concentration and growth temperature jointly influence SiC DAP luminescence and that DAP‐based photoluminescence is a powerful tool for monitoring polytypes and impurities during process optimization. Moreover, our insights into trace‐element–induced color centers offer valuable criteria for selecting source materials in the manufacture of SiC substrates for power‐device applications.

References [1] ISO 21820:2021, Fine ceramics (advanced ceramics, advanced technical ceramics) — Ultraviolet photoluminescence image test method for analysing polytypes of boron- and nitrogen-doped SiC crystals. Geneva: International Organization for Standardization; 2021. [2] H.-S. Choi, S.-M. Jeong, Color Spectroscopy for Energy-Level Analysis of Single-Crystal Silicon Carbide. Crystal Growth & Design. 2022;22(4):2117–2123. doi:10.1021/acs.cgd.1c01135. [3] T. Kimoto, J. A. Cooper. Fundamentals of Silicon Carbide Technology. Hoboken, NJ: Wiley; 2014. [4] A. A. Lebedev, Semiconductors. 1999; 33: 107–130.

ABSTRACT. Silicon Carbide has gained great interest for its high thermal conductivity, high saturation velocity, and high breakdown voltage and, therefore, its suitability to fabricate high-frequency, high-power electronic devices [1, 2]. It has been applied in various fields, including transportation and communication. However, the longevity and performance of SiC devices are hindered by defects within the substrate and epitaxial material. The observation of defects and understanding of their formation mechanism is critical for the improvement of crystal quality and, therefore, better device performance and production yield [3, 4].

In this study, we report the observation of a new arrangement of defects that we name the “galaxy” defect, which was observed on wafers from the same PVT-grown 6-inch 4˚ off-axis boule. As shown in Figure 1(a), optical microscopy images show a region of a highly dense cluster of micrometer-level inclusions. The 12 wafers within the same boule containing the “Galaxy” defect were investigated with synchrotron X-ray topography in transmission geometry for (1-100), (11-20), and (1-101) reflections, which are shown in Figure 1(b-d). XRT images were also recorded in (11-28) reflection geometry for wafer numbers 13, 18, 25, and 49, with sample 13 being closest to the seed, which is shown in Figure 2. Transmission XRT images indicate the formation of dislocation clusters with stronger contrast in (1-100) and (1-101) reflection images, while the contrast is weaker in (11-20) reflection images. Grazing images from the same region show a high density of BPDs within the “galaxy” defect region, as well as a high density of deflected Frank dislocations between the “galaxy” defect region and the periphery. The density of deflected dislocations is observed to be higher in later slices compared to slice 13, where the defect is first formed and observed. A network of TED-LAGB is also observed on the (11-28) image of slices 25 and 49. SEM investigations were performed to identify the nature of the inclusions. The SEM images in Figure 1(f) show no contrast for the inclusions, which indicates that the composition of the inclusions is not significantly different from 4H-SiC. Combining the results from these investigations, we propose that the optically visible inclusions are regions where threading dislocations are decorated with dopant atoms. The dopant concentration is possibly too small for a contrast in SEM images. The high density of deflected dislocations can also be explained by the deflection of high-density threading dislocations in this region. While the TED-LAGB is possibly caused by the residual lattice mismatch from the cluster of threading dislocations. Further investigations with various other characterizing methods, such as Raman mapping and TEM, are being utilized to confirm the nature of the inclusions in the “galaxy” defect and the formation mechanism of the dislocation cluster and LAGB observed on the XRT images. These results will also be discussed in this presentation.

ABSTRACT. We demonstrated that combining laboratory XRT and birefringence imaging enables wafer-scale, non-destructive characterization of threading dislocations, allowing rapid prediction of Burgers vectors and dislocation propagation directions. These predictions were confirmed by multi-g section topography with conventional g·b analysis, showing excellent agreement. This approach significantly simplifies defect analysis and has high potential for routine industrial application, greatly enhancing the efficiency and reliability of SiC wafer inspection.

ABSTRACT. Silicon carbide (SiC) has key properties, including a wide bandgap (WBG) and high thermal conductivity, that make it an excellent material for power applications in harsh radiation environments, such as space, where heavy ions can induce radiation damage. SiC is also suitable for quantum applications that rely on the presence of color centers, which can be created using heavy-ions. Thus, it is crucial to understand the interactions of heavy-ions with the SiC crystal. The present work aims to use Photoluminescence (PL) and Raman Spectroscopy, to investigate both the Silicon Vacancy (VSi) creation and the crystal modifications induced by heavy-ions under different irradiation conditions, such as distinct energies, penetration ranges, and Linear Energy Transfer (LET).

The present study shows a thorough optical evaluation of the impact of fluence, LET, and particle range on the VSi creation and the crystal structure modifications. At low fluences, a low VSi concentration is seen and an improvement of the crystal quality (RRI > 1 and ≈ 0 total disorder) is accompanied by a compressive stress in the crystal. For higher fluences, an increase in VSi is observed together with a decrease in crystal quality (RRI < 1 and total disorder > 0). For the final contribution, the stress evaluation, RRI, total disorder, and PL measurements will be shown for all three heavy-ion irradiation regimes (keV, MeV, and GeV) to further elaborate on the heavy-ion vs. 4H-SiC interaction.

ABSTRACT. An important step in the fabrication process of modern power electronic devices is the epitaxial growth on top of a 4H-SiC substrate. This epitaxial layer strongly influences the quality of the subsequent process steps and therefore the performance of the whole device [1]. Since dislocations, stacking faults, and extrinsic point defects might be transferred from the substrate to the epitaxial layer [1, 2], the choice of substrate is vital. 4H-SiC substrates are available from many international vendors, each providing several grades of substrate quality. These grades vary in terms of defect density, resistivity, thickness variation, and bow, and other parameters, which can all influence the quality of the epitaxial layer grown on top. Minority carrier lifetime is known to be sensitive to the presence of defects, such as point defects, dislocations and stacking faults, as well as to doping and thickness variations and surface and interface recombination [3]. Hence, lifetime measurements potentially offer a nondestructive and contactless way of monitoring the quality of the grown layer. This work aims to utilize lifetime measurements as a quality control for typical 1,200 V epitaxial layers deposited on 4H-SiC substrates from international vendors. 4H-SiC substrates with a diameter of 6 inch and a 4° off-axis orientation towards [11¯2 0] from three different vendors were used for epitaxy in multiwafer planetary reactors (AIXTRON G5 WW and G10-SiC epitaxy reactors). The total thickness of the layers ranged between 10 and 14 µm, with a maximum thickness deviation across the whole wafer of 3.4 % /mean. The layers featured a n-type doping between 8×1015 and 2×1016 cm-3 and a doping deviation of up to 6.5 % /mean across the sample, which is common for typical 1,200 V epilayer stacks. A buffer layer of 1 µm thickness and doping concentration of 1×1018 cm-3 is included. The carrier lifetime of these 115 epiwafers has been determined by microwave detected photoconductivity decay (µ-PCD) measurements in a SEMILAB WT-2000, using a laser source with a wavelength of 349 nm and a raster size of 1 mm. Effective lifetime values have been simulated with TauSIM [4] for comparison to experimental data. Since the effective lifetime in the epitaxial layers exhibits a radial dependence on the location on the wafer, as depicted in Fig. 1, the values in the center of the samples were being compared, where the lifetime is maximal with no influence from edge effects. Fig. 2 sheds light on different known influencing factors on the carrier lifetime. Fig. 2 a) – c) show the carrier lifetime in the different samples as a function of the thickness and doping of the epitaxial layer and the resistivity of the substrates, respectively. However, no clear dependency on these parameters is identifiable in the given ranges. By grouping the samples into the different substrate vendors and grades, as seen in Fig. 2 d), the lifetime values can be separated into distinct regions. Over 70 of the substrates originated from the same vendor (vendor A) with the same substrate grade. They resulted in a lifetime of ~155 ns with a deviation of only around 6.7 % from the mean value, proving the uniformity of the epitaxial layer across the different wafers of the same type as well as the reliability of the measurement method. A comparison with samples from the same vendor but with different grades shows that wafers from the second grade exhibit comparable results (~165 ns), while the lifetime in samples with the third grade exhibit significantly higher values of around 350 ns. Wafers from different vendors can also be categorized in either the lower regime (vendor B with ~ 140 ns) or the higher regime (vendor C with ~ 380 ns). We will show and discuss, on the one hand, latest results of the further increasing sample pool and, on the other hand, a more profound understanding about which differences between the different substrates and their grades might produce such differences in the carrier lifetime.

ABSTRACT. Understanding the growth behavior of SiC single crystals in the physical vapor transport (PVT) process is of vital importance to produce high-quality wafers for the semiconductor power electronics industry. Among the several defects that may be created during growth polytypes and dislocations play a prominent role since they severely impair device performance. While research efforts have achieved significant success in describing defect properties and their densities with physical models, many open questions exist regarding polytype formation, the role of doping [1], or the influence of surface defects arising from threading dislocations or steps. Atomistic models offer deep insights into such processes, but also need to be carefully calibrated and benchmarked to cope with the required system sizes and time scales while still keeping a high-fidelity description of interatomic bonding.

In this talk, we present atomistic simulations of crystal growth phenomena on the SiC surface, addressing thermodynamic and kinetic phenomena of the vapor-solid interaction. Our methodologies describe bonding and the potential energy landscape based on Density Functional Theory (DFT) as well as interatomic potentials (IP)s. For the latter, we use parametrizations available from the literature as well as machine-learning potentials developed specifically for this purpose. We compare DFT and IPs concerning their elastic properties as they are relevant for stress and dislocation behavior, the Gibbs enthalpy of formation of polytypes and relevant molecular species as a function of temperature, as they determine gas partial pressures, polytype stability, and defect energetics. On this basis, we proceed to study kinetic growth phenomena. With molecular dynamics (MD) simulations employing the MEAM potential [2] and other IPs, we investigate crystallization on the surface by rapid deposition of gas species under different conditions. We focus on the thin amorphous layers created during deposition and monitor their interface to the crystalline SiC phase as well as their migration, producing different SiC polytypes.

In order to approach models with longer growth time scales, we extend our methodology with the minimum energy atomic deposition method (MEAD) [3]. This method works by direct insertion of atoms at points of minimal potential energy through efficient scanning of candidate positions and rapid relaxation of the system. It allows simulating higher film thickness compared to MD while mimicking experimental growth rates. Furthermore, it enables in-depth studies of the evolution of crystal defects (see Figure 1, left) and residual stress build-up. We present results for varying growth rates, temperature, and partial pressures that are related to different conditions that can be created experimentally with the PVT method. To benchmark the MEAD approach, we compare it with MD simulations performed in our parallel study that focuses on SiC nucleation and defect evolution on off-axis 4H-SiC substrates with surface steps. These MD simulations capture the emergence of polytypes during early deposition and the generation and propagation of dislocations. We study the influencing factors such as deposition rate, temperature, as well as the condition of the seed crystal surface, where we consider different variations such as flat surfaces with C and Si termination, steps on the surface, or threading dislocations, as shown in Figure 1 (right).

Finally, we discuss how the generated insights can be used to improve the crystal growth process.

[1] Zahra Rajabzadeh, René Hammer, Lorenz Romaner, On the impact of nitrogen and aluminum doping on silicon carbide polytype stability: Insights from first principle calculations, Journal of the American Ceramic Society, 108, e20284, (2025). [2] Kyung-Han Kang, Taihee Eun, Myong-Chul Jun, Byeong-Joo Lee, Governing factors for the formation of 4H or 6H-SiC polytype during SiC crystal growth: An atomistic computational approach, Journal of Crystal Growth, 389, 120, (2014). [3] Shivraj Karewar, Germain Clavier, Marc G.D. Geers, Olaf van der Sluis and Johan P.M. Hoefnagels, Minimum Energy Atomic Deposition: A novel, efficient atomistic simulation method for thin film growth, Surface & Coatings Technology, 494, 2, 131462 (2024).

ABSTRACT. Nitrogen-based post-oxidation annealing (NO/N2O-POA) improves field-effect mobility in 4H-SiC MOSFETs, but often causes undesirable negative shifts in flatband (VFB) or threshold voltage (VT). One approach to increase VFB/VT while maintaining the mobility is to introduce a dipole layer using a bilayer dielectric stack, as the dipole effect can lead to a positive or negative voltage shift depending on the properties of the high-k dielectric. In this work, we demonstrate the dipole effect of SiO2/Al2O3 stack deposited entirely by atomic layer deposition (ALD) on 4H-SiC. Results demonstrate that the ALD-deposited SiO₂/Al₂O₃ dual-layer stack is an effective approach to increasing the threshold voltage in SiO₂-based devices without compromising performance. Furthermore, the results confirm that the dipole does not introduce additional scattering centers at the SiC/dielectric interface compared to devices with ALD SiO₂ only.

ABSTRACT. In this paper, we investigate the static room temperature performances of a 4H-SiC CMOS NOT logic gate after several temperature ramps, which has been heated in ambient atmosphere environment. The results show that, after reaching the temperature of 673K for 30 minutes, hysteresis effects disappears, and more reproducible characteristics are obtained. After the first 673K temperature ramp, a shift of threshold logic voltage, VM, of +6.67% and a reduction of hysteresis voltage, from ΔVH = 0.2V to ΔVH = 0.15V, are observed. Moreover, a reduction of High Noise Margin, NMH, of -6.74% and an increase of Low Noise Margin, NML, of +6.95%, can be calculated. Whereas, after the second 673K temperature ramp, almost the same values of VM and NML are reached, with a variation of 0.94% and 1% with respect to the first 673K ramp, and the same value of NMH is observed. The effects of the thermal annealing can be related to electrical behaviours of individual devices. For this purpose, we analysed the transfer characteristics in linear region of a NMOSFET and a PMOSFET with W=18μm and L=6μm, before and after the first temperature ramp, respectively. We observed an increase of NMOSFET threshold voltage and a reduction of PMOSFET threshold voltage of 6.93% and 11.15%, respectively, explaining, also, the shift of the VM. Moreover, a reduction of the hysteresis of NMOSFET and PMOSFET characteristics can be observed, which agrees with the reduction of the NOT gate hysteresis. Hence, the 673K thermal annealing seems to suggest an improvement of devices and circuits performance, allowing a more stable and repeatable characteristics of the NOT logic gate.

ABSTRACT. Bipolar degradation poses a critical challenge in SiC devices, driven by the expansion of single Shockley stacking faults (1SSFs) from basal plane dislocations (BPDs). We investigated the suppression of 1SSF expansion in 4H-SiC by implanting protons from the backside (substrate side) of the epitaxial wafer. PiN diodes fabricated on implanted wafers showed effective suppression of SF expansion without degradation of I–V characteristics. Cathodoluminescence analysis confirmed the diffusion of point defects into the epitaxial layer, which likely contributed to the suppression.

ABSTRACT. This work reports enhanced high-voltage blocking capability and enlarged process window for junction termination extension (JTE) in SiC power devices using a hybrid random and channeling implantation for the p-type doping (Al), compared with conventional random implantation. A three-step hybrid implantation process has been developed to replace a nine-step random implantation, achieving a similar doping profile and equivalent breakdown voltage in the JTE while significantly increasing the fabrication productivity and reducing the cost. Moreover, TCAD studies reveal that the enhanced breakdown voltage and enlarged dose window of the JTE in SiC devices with the hybrid approach is attributed to a deeper Al distribution with reduced peak doping concentration, which effectively alleviates electric field crowding at the JTE edge.

ABSTRACT. The demands for electrical devices capable of operating at high temperatures continue to grow. In this study, the thermal stability of Silicon-cap-annealed (SiCA) ohmic contacts were investigated under 300 ℃ in air for 100 h. The results showed that SiCA electrodes exhibited stable contact resistance and electrode surface compared to Ni₂Si/SiC electrodes. These results imply that the SiCA process offers long-term stability, suppress surface degradation, and improves the reliability of electrical devices under high temperature conditions.

ABSTRACT. Silicon carbide (SiC) is a preferred material for high-temperature, high-pressure, and high-frequency applications due to its exceptional physical and chemical properties, including a wide bandgap, high hardness (Mohs 9), excellent thermal conductivity, and superior resistance to thermal deformation and corrosion. These attributes make SiC highly promising for applications in power electron devices for energy conversion and electric vehicle industries. However, the high hardness and chemical stability of SiC pose significant challenges in its processing, particularly in wafer substrate manufacturing. Conventional diamond wire sawing technology suffers from high kerf-loss and slow cutting speeds, contributing to processing costs that can exceed 50% of the total wafer production cost. To improve the efficiency and lower the production costs of SiC wafer manufacturing, laser slicing technology has emerged as a highly effective alternative. This technique employs a high-energy-density laser beam focused inside the SiC ingot to induce localized crack propagation through thermal effects. By optimizing laser scanning parameters, a modified weakened layer with a crack array distribution can be formed at the target depth. Subsequent application of mechanical stress facilitates crack interconnection, enabling wafer separation. This study introduces ultrasonic vibration as an engineering approach to enhance crack propagation in the modified layer through high-frequency vibrational energy. The integration of laser modification and ultrasonic vibration energy (Fig. 1) enables rapid ingot slicing, achieving an estimated processing time of approximately 15 minutes per 6-inch 4H-SiC wafer—significantly faster than diamond wire sawing. This research first optimized laser modification parameters via small-scale test samples, systematically investigating the effects of pulse energy and scanning speed on crack morphology and array distribution (Fig. 2). The combined impact of laser modification and ultrasonic vibration on SiC sample was then investigated, with analyses of hardness, phase transformations, and elemental composition changes in the sliced products (Fig. 3). Nanoindentation testing revealed that the hardness of the modified region decreased significantly from 44 GPa to 13 GPa, confirming that laser modification substantially reduced bond strength and material hardness. The optimized parameters were then applied in slicing tests for 6-inch 4H-SiC ingots, followed by comprehensive quality verification of the polished wafer products (Fig. 4). The results confirmed the laser and ultrasonics-assisted slicing of SiC ingot can reduce material loss, significantly lower processing costs and time, and improve surface quality and geometric consistency compared to traditional diamond wire sawing.

ABSTRACT. For minimizing power losses in 4H-SiC MOSFETs, reduction of channel resistance and on-resistance is key. By implementing a trench structure, the so-called UMOSFET has been established for high power applications. Hereby, a major factor for reducing gate leakage and increasing long-term stability is the SiC – gate oxide interface. With reduced trench sidewall roughness, the gate leakage current can be reduced and the charge to breakdown can be increased. Furthermore, sharp corners in the trench bottom lead to locally high electric fields in the gate oxide and should therefore be avoided. A common way to reduce sidewall roughness and round the corners in SiC trenches is applying a high temperature annealing step after trench etching. [1–4] This work focuses on the roughness minimization from the first step in trench etching on, which is the structuring of the oxide mask that is generally used for SiC trench etching. The oxide is etched via reactive ion etching (RIE) using a photoresist mask. In this work, it is shown that by reducing sidewall roughness in the photoresist also the sidewall roughness of the oxide mask is reduced, and therefore we claim that the SiC trench sidewall roughness is reduced as well. By combining this enhanced oxide mask with a SiC etching process creating bottom corner rounding in the trench [5], the trench geometries after etching can be optimized and therefore enable a more gentle annealing process or even make it unnecessary. For improvement of the resist sidewall roughness, a chemically amplified resist (CAR) is used and compared to a common diazonaphthoquinone-based (DNQ-based) resist in this work. Sidewall roughness of the photoresist mask and oxide mask is analyzed by atomic force microscopy (AFM) measurements and compared to scanning electron microscopy (SEM) surface image analysis introduced by Barcellona et al. [6]. As SEM images of highly isolating materials like photoresist on top of oxide show high charging effects and are therefore more difficult to prepare, only images of the oxide mask are evaluated here. Fig. 1 shows SEM surface images of oxide masks with thickness 1.5 µm etched with a CAR mask (a) and a DNQ-based resist mask (b). Comparing the sidewalls, the profile of the oxide mask in (b) reveals apparent sidewall striations while the profile of (a) seems smoother. A profile image analysis evaluation of a section of these with a section length of 1 µm is plotted in Fig. 2. The sidewall striations of the sample prepared with DNQ resist are imaged by a higher range of grayscale values. This is reflected in the standard deviation of the grayscale values which depicts the relative roughness (RR). For measurements of the root mean square average roughness (Rq) with AFM, resist and oxide masks on Si wafers are considered as these samples can be prepared less expensive. The Rq values are obtained by measuring tilted samples and calculating the surface roughness along the sidewall. A comparison of AFM measurements with RR values gained from image analysis are displayed in Table 1. A correlation can be seen as the RR value as well as the Rq value of the oxide mask prepared with DNQ resist is higher. The roughness values of resist and respective oxide mask are similar for both resist types. In order to get a reliable correlation between RR and Rq, so that also Rq values for SiC wafers can be calculated from the RR values, more data have to be analyzed. Therefore, in the following paper further analysis results comparing each step in the fabrication of SiC trenches etched with an oxide mask prepared with CAR and prepared with a DNQ resist will be shown.

ABSTRACT. Gate trench formation in silicon carbide (SiC) is one of the crucial technological steps in fabrication process of SiC-based MOSFETs. Reactive ion etching (RIE) technique is widely used for anisotropic SiC etching of high aspect ratio trenches. Biased inductively coupled plasma (ICP-RIE) is the suitable technique for anisotropic etching with the key advantage of independent control of ions and reactive species flux from plasma to the wafer and ion energy via the source power and bias power control, respectively [1]. From technological perspective, tuning the SiC etching technique for large area wafer requires the optimization of on-wafer uniformity and within sub-µm SiO2/SiC structure scale with requirement of smooth trench walls and rounded corners. SiO2 mask on top of SiC is typically etched with quite low selectivity of 2 to 6 [2]. Thus, during the etching process SiO2 mask becomes damaged, which leads to SiC trench shape deformation (bowing and microtrenching) due to complex behavior of ion trajectories on the sub-µm structure scale. Moreover, mask and trench shapes are sensitive to reactive neutrals flux, ions flux and ion energy-angular distribution functions, and the simultaneous optimization of etching process on-wafer and within sub-µm SiO2/SiC structure scale becomes difficult and expensive. In this work we present the multi-scale simulation approach for improvement of SiC gate trench etching process in the reactor scale and sub-µm SiO2/SiC structure scale considering conventional low-pressure ICP-RIE system for 150 mm wafers with typical etching conditions in SF6/O2/Ar mixture. The multi-scale is based on the combination of fluid approach for flow and plasma dynamics with chemical reactions in presence of electromagnetic fields and Particle-In-Cell Monte Carlo Collisions (PIC-MCC) method for ions and neutrals tracing in the reactor and within the sub-µm trench. A dynamic profile of the SiO2 mask and SiC trench was simulated with respect of the process conditions. The typical reactor-scale trends in SiC etching with ICP were described [3]: non-monotonic etching trend with O2 flow rate due to competing chemical processes in plasma and on the wafer, and non-linear dependence on DC bias voltage based on transition from ion bombardment controlled to the regime of F, O flux depletion. Within sub-µm SiO2/SiC structure scale it is demonstrated that the exposure of SiO2 mask to ICP-RIE results in the appearance of mask cut angle α. The specular reflection of ions from mask causes their focus to the trench corners or side walls resulting in the microtrenching or bowing effects respectively. Maintaining large SiO2 mask cut angles α > 15º helps to avoid specular reflection of ions and, thus, SiC trench deformation. The set of SF6/O2 ICP etching conditions is proposed to minimize time period, when specularly reflected ions are focused on the side walls causing SiC trench deformation. It is demonstrated, that addition of BCl3 to the mixture results in the improved SiC trench shape due to the formation of protective polymer-like coating on the trench side walls. The features of BClx interaction and protective layer formation on SiC surface are discussed.

ABSTRACT. This study investigates the electrical characteristics of test MOSFETs fabricated on non-polar faces of 4H-SiC wafers, specifically on the (1̅100) and (1̅1̅20) planes, referred to hereafter M-face and A-face, respectively. Various surface treatments were applied prior to gate oxide formation. Sample A consists of a MOSFET fabricated on the M-face surface, while Sample B has a MOSFET fabricated on the A-face surface. Both samples were fabricated on the same wafer, sharing a p-type body with an approximate doping concentration of 1×10¹⁷ cm⁻³. The MOS gate dielectric was formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) of SiO2 followed by nitric oxide (NO) annealing. Before oxide deposition, hydrogen (H2) annealing was conducted under varying conditions, including temperature, chamber pressure and H2 flow. Finally, the gate electrode was formed by CVD of Poly-Si. The primary comparison parameter is channel transconductance (S/m), derived from ID–VG characteristics at VDS = 0.1 V. Figure 1 shows Gm–Vg curves, of both sample A and B. Sample B shows the higher peak transconductance of the two samples, reflecting the crystallographic plane influence on the MOS interface. Figure 2 shows the effect of H2 surface treatment anneal temperature.[1] Sample A shows consistent transconductance across the H2 anneal temperature range, indicating resilience to thermal variation, whereas Sample B exhibits reduced transconductance at high temperature treatment, suggesting some sensitivity of the a-face interface to the treatment. Although sample B offers slightly higher transconductance, sample A demonstrates good performance with reduced sensitivity. Literature has shown that non-polar faces present unique interfacial properties—while the a-face often exhibits higher initial transconductance, the m-face may offer more robustness under high-temperature and process variations [2–3]. Figure 3 presents the influence of chamber pressure during hydrogen surface treatment, revealing negligible effects on transconductance for both samples. Figure 4 explores the role of H2 gas. Increased H2 gas flow improves transconductance at low gate oxide electric fields during operation, especially for Sample B, indicating more effective surface passivation under higher hydrogen availability. In conclusion, both non-polar orientations studied offer promising performance for SiC MOSFETs, but their behavior under surface treatments differs. A-face device delivers higher peak transconductance but is more sensitive to the surface treatment conditions. M-face devices show relatively stable behavior across a range of process variables, making it a reliable candidate for robust fabrication. These findings underscore the importance of optimizing process conditions based on surface orientation to fully leverage the performance potential of non-polar 4H-SiC MOSFETs.

ABSTRACT. The reduction of the on-state resistance (RDS(on)) of silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFET) remains a major driver for research and development. State-of-the-art SiC trench MOSFETs (UMOS) allow for a significant reduction in RDS(on) by increasing the channel width per area and reducing internal series resistance. Consequently, channel resistance comes more into focus, and the low channel mobility remains a limiting factor for these devices. High channel resistance is mainly caused by the high density of interface traps (Dit) present at the silicon oxide/SiC interface. Sophisticated optimization processes have been developed to reduce these interface traps. These include pre-oxidation etching in hydrogen atmosphere [1], high temperature oxidation, post oxidation annealing in N2 and NO [2,3], as well as the use of chemical vapor deposition (CVD) [1,2], low pressure CVD [3], and low temperature oxidation of polycrystalline silicon [2]. Most of the processes have only been evaluated on planar MOS capacitors (MOSCaps) as the measurement and evaluation of Dit the for the UMOS relevant trench sidewall is a challenge. We present a method for the evaluation of the trench sidewall capacitance which expands on the method reported by Guo et al [4]. The capacitance of a trench MOS capacitor is simplified to consist of three parallel capacitors the capacitance on the top of the trench Cm, the trench side wall Cs and the trench bottom Cb (Fig. 1d). The total capacitance C is the sum of these three contributions: C(V)=A_m*C_m(V)+A_s*C_s(V)+A_b*C_b(V) Here, Am, As and Ab, represent the effective areas of the trench top, sidewall, and bottom, respectively. It is possible to extend this model by adding additional terms in case of significant corner rounding at the trench top and bottom, if needed. The areas are taken from the mask layout and wafer-level trench depth is measured by structured illumination microscopy (Fig. 1c) which is verified by focused-ion-beam cross-section SEM measurements (Fig. 1b). The knowledge about the effective areas allows for determination of the different capacitances by solving a linear system of equations. At least three different trench MOSCap designs with different area ratios are needed for this. We expand on the method of Guo et al. by evaluating C(V) measurements of fourteen different devices (Fig. 2a) . Because of process variation, it is beneficial to increase the accuracy of the estimation by forming an overdetermined system of equations which is then solved by fitting a least-squares solution to the linear matrix equation. This yields a per-area capacitance for the trench mesa, trench sidewall, and trench bottom. Fig 2b indicates that the extracted areal capacitance of the trench top and trench bottom correspond well to each other while the trench sidewall shows a different behavior. These areal capacitances can be multiplied by the respective areas to determine the contribution of each partial capacitance. This is illustrated in Fig. 2e for the trench sidewall capacitance of some of the devices. To evaluate the accuracy of the method, two different gate oxides are fabricated and will be used to evaluate the proposed method. The process flow for the MOSCap devices uses the major building blocks from a UMOSFET process flow and is illustrated in Fig. 1a. The gate oxide is formed by either deposition and subsequent low temperature oxidation of undoped polysilicon or by first performing a sacrificial oxidation and then depositing LPCVD TEOS oxide which is densified at 900 °C. For each of the gate oxides one wafer is annealed at 1300 °C in NO atmosphere while another wafer is processed without the annealing. Fig. 2c and 2d show C(V) characteristics of planar and trench MOSCaps with the different gate oxides. The variance of the measurements is smaller for the TEOS wafer. Fig. 2f shows the corresponding wafer map of the oxide capacitance of the trenched MOSCap indicating not only an influence of the trench depth (cf. Fig. 1c), but also other process variations. For both gate oxides the trench MOSCaps show several steps related to different flatband voltages indicating a system of parallel capacitors. Fig. 2g shows an exemplary Dit evaluation performed on a planar MOSCap of the polysilicon oxidation gate oxide. The observed Dit at 0.2 is close to results reported by Kobayashi et al. for a similar approach [2]. The accuracy of this method for trench MOSCaps will be discussed in detail in the full paper as well as TZDB and TDDB reliability data that confirm the trench oxide quality of our previous work [3]. [1] T Keita et al. Appl. Phys. Express. 13 121002 (2020). [2] T Kobayashi et al. Appl. Phys. Express 13 091003 (2020). [3] MW Lim et al. MSF. 1004, 535–40 (2020). [4] Z. Guo et al. IEEE Trans. Electron Devices, vol. 68, no. 6, pp. 2879-2885 (2021).

ABSTRACT. SiC as wide band gab semiconductor is one of the key materials for enhancing the properties for high power electronics to higher performance and better energy efficiency, which is crucial for applications as renewable energy generation and electric driven mobility. With its wide band gab and unique material properties, SiC can improve the thermal load and the high voltage performance of the manufactured devices significantly compared to similar electronics made from Si. The compound semiconductor SiC has the benefit that many processing steps can be adopted from existing Si wafer processing, but some additional material specific processing steps arise. After deposition of metal to SiC, a Schottky contact is formed, which needs to be changed to an ohmic contact to ensure good device performance. The ohmic contact is formed by material phase modification (NiSi phases), which can be performed in a thermal process like rapid thermal annealing at high temperatures. But after thinning the wafer backside, methods can be applied only which offer localized material treatment and have no impact on the already processed frontside. UV laser annealing for Ohmic contact formation has been proven successful for this production step. The rising demand for SiC electronics lead to the need for a high throughput laser annealing machine with reasonable footprint, high availability, and low cost of ownership in manufacturing. Several different laser-based methods have been developed. Excimer laser-based solutions provide a reasonable process quality, but at the expense of high running and maintenance cost and medium uptime. UV solid state lasers are beneficial as they provide lower running cost, longer lifetimes, and higher availability. Several production tools are based on a combination of a medium power UV DPSS single mode laser and galvo scanner-based optics systems, which can cover the process with medium homogeneity, but at the expense of low throughput of < 10 WPH for 200mm wafers. The presented laser annealing solution can significantly enhance both the throughput and the material quality while maintaining the benefits of the superior reliability, reasonable footprint and low running cost. A high-power UV DPSS laser is coupled to a specialized optical engine, which provides a highly homogeneous laser intensity distribution on the wafer. The wafer is scanned below the laser beam, which ensures constant process quality across the wafer and makes the machine flexible for different wafer sizes. The specialized laser beam shape allows for the use of a significant higher amount of the available UV photons for the process. The steep beam edges enable the ability to reduce the beam overlap while maintaining and even enhancing the process quality. The beam size can be adjusted in length and width for optimum usage of the available laser power for throughput. The formation of the ohmic contact is demonstrated by sheet resistance measurements. The sample surface quality (measured by an optical microscope) and material phase composition (measured by SEM and XRD) are examined as a function of scan overlap and energy density. The electrical properties were examined and the experimental depth of focus is determined found to be superior to alternative solutions. The adjustable pulse length allows precise control of the process parameters for optimum process results and low thermal budget on the wafer. The fully automated machine solution integrates wafer handling and online-metrology for process control. Due to the high-power UV laser, a productivity of >=20 WPH for 200mm wafers is demonstrated. Besides SiC ohmic contact formation, the versatile laser machine platform can also be used for Si/SiC dopant activation and other semiconductor applications.

ABSTRACT. 4H- SiC wafers were processed in thermal oxidation furnace and impact of processing temperature up to 1500 °C, pressure and different gaseous ambient at oxide thickness distribution was investigated. Beside impact of thermal distribution within oxidation furnace, an additional effect on oxide thickness distribution has been observed, due to promotion of oxidation rate in the center of the wafer. Within this study we have examined which influence processing parameters have on described effect, specific for SiC oxidation.

ABSTRACT. While interface nitridation using NO annealing is a standard method to enhance the field-effect mobility (μFE) of SiC MOSFETs, it introduces electron or hole oxide traps near the SiO2/SiC interfaces, which can lead to reliability issues. In this study, we propose a 2-step annealing process in H2/Ar gas mixtures (2-step H2/Ar) to improve the performance of SiC MOS devices without requiring interface nitridation. In the proposed approach, diluted hydrogen (3%-H2/Ar) annealing was performed before and after deposition of SiO2 dielectric, aiming to remove SiC surface defects and reduce SiO2/SiC interface defects. The proposed method achieved a substantially low interface state density (3.2×10^11 eV^-1cm^-2 at Ec-E=0.2 eV) and a high μFE (17.2 cm^2V^-1s^-1). These results highlight the potential of the 2-step H2/Ar process as an effective alternative to traditional nitridation methods for fabricating high-performance and reliable SiC MOS devices.

ABSTRACT. Threshold voltage VTH is one of the critical parameters for MOSFET operations. In this study, we attempt to understand and model the temperature variation in VTH for 4H-SiC n-channel MOSFETs on Si-face. Measurement results for lateral long-channel SiC MOSFETs are compared with Sentaurus simulation and a simple model from the classic VTH definition with interface charges included. It is found that the simple model predicts the temperature variation reasonably well within a temperature range from 83 to 473 K.

ABSTRACT. Despite their revolutionizing characteristics, SiC MOSFETs exhibit unique challenges, particularly concerning their reverse conduction and gate oxide behavior. A lesser-explored phenomenon is the dynamic variation of the forward and reverse conduction behavior, particularly in the subthreshold region. This study discusses the underlying mechanisms of these variations, their root causes, and their effects on device characteristics. Previous studies have examined the influence of gate voltage on the reverse conduction properties of SiC MOSFETs, particularly partial conduction at the channel region during depletion – before full accumulation [1]. By using the body diode forward voltage (Vf) as a temperature-sensitive electrical parameter (TSEP), it has been observed that the voltage behavior is strongly time-dependent. These changes in the conduction behavior lead to inaccuracies in junction temperature estimation, potentially causing over- or under-stress conditions during reliability tests like power cycling [2-3]. However, the existing studies have not explained the responsible mechanism behind the dynamic Vf and its correlation to dynamic channel/oxide characteristics, which will be addressed in this study. To systematically analyze the dynamic channel behavior, SiC MOSFETs underwent controlled gate bias preconditioning – both in strong inversion (+15VGS) and strong accumulation (-15VGS) – before being subjected to the subthreshold region. Monitoring the voltage drop from drain to source (VDS) in this condition while driving a reverse conduction current of 10mA from source to drain, a drift in the VDS with a long recovery time (τ≈160 s) as depicted in Fig. 1, was observed. The polarity of the drift depended on the preconditioning voltage, exhibiting an inverted settling behavior. The direction of drift was dependent on the preconditioning voltage. Positive preconditioning enhanced conduction, while negative preconditioning suppressed it. Despite these initial differences, the conduction levels ultimately converged to a common steady-state value. This behavior can be as well observed during a measurement in forward conduction with a current from drain to source as seen in Fig. 2. Further analysis involved switching the gate voltage between -10V and +10V post-preconditioning while monitoring ΔVDS (temporal variation of VDS) in comparison to the gate capacitance revealed that dynamic effects are most pronounced during channel depletion and weak inversion, correlating with gate capacitance profiles. Kang et al. reported that this dynamic behavior can be explained by the presence of deep oxide traps with long tunneling time constants [4]. In MOS-capacitor structures, the release of trapped charges (either positive or negative) can take place over extended periods, effectively shifting the flat-band voltage (Vfb). After a positive preconditioning, the oxide gradually releases holes, leading to a decreased channel depletion. Conversely, after a negative preconditioning, negative charges are released, increasing the channel depletion. Fig. 1 illustrates the presence of both deep positive and negative oxide traps. Deep traps located far from the SiC/SiO interface, generally have larger time constants compared to near interface trap locations, making them harder to detect during rapid measurements. The tunneling probability of deep traps appears to dominate the overall time constant of the observed dynamic effect, aligning with the measurements reported in [4]. The switching trap behavior dependent on the preconditioning voltage shows similar behavior with the observation of dipole oxygen vacancies e.g. E’γ4 states [5]. We were able to exclude alternative explanations, such as self-heating effects or deep level bulk crystal defects. In the subthreshold region, variations in flat-band conditions significantly influence the depletion region and, consequently, conduction.(Fig. 3 right) However, for gate voltages exceeding the threshold voltage (Vth), the channel enters strong inversion, minimizing the sensitivity of Vfb shifts on conduction. Similarly, for large negative gate voltages, the channel becomes highly depleted and the pn-junction is carrying the main reverse current of the device, rendering trap dynamics inconsequential in that regime. (Fig. 3 left) These findings demonstrate that the conduction properties of SiC MOSFETs can exhibit significant time-dependent drift due to deep oxide traps, particularly in the subthreshold region. A deep understanding of these mechanisms is essential for accurately using the forward voltage (Vf) as a temperature-sensitive electrical parameter and for preventing inappropriate device stress during long-term reliability testing.

ABSTRACT. In this work, for radiation hardened image sensor, SiC CMOS active pixel sensors (APS) with embedded UV photodiode was suggested and demonstrated. In our previous study on the SiC CMOS image sensor, after high gamma-ray radiation of 2 MGy, the radiation effect on the device was mainly caused at the surface of SiC photodiode. In this work, we introduced an embedded photodiode in 4H-SiC CMOS APS for preventing radiation effects at the interface. And we investigated 5 MGy gamma-ray radiation effects on the four Transistor Active Pixel Sensors (4T-APS) with the non-embedded PD and the embedded PD. The results confirm that the embedded PD is effective in reducing the reduction of quantum efficiency due to gamma-ray irradiation.

ABSTRACT. A power cycling test (PCT) is a representative method for assessing the thermal reliability and electrical degradation of power semiconductor devices under repeated thermal load [1]. In SiC MOSFETs, power cycling typically results in threshold voltage variation, conduction degradation, and increased leakage, accompanied by packaging-related failures [2]. While the thermal reliability of conventional SiC MOSFETs has been widely studied, limited attention has been given to the degradation behavior of devices with integrated Schottky barrier diodes (SBDs) under power cycling conditions [1-2]. During PCT, the integrated SBDs may undergo characteristic degradation, which can affect their electrical behavior and lead to inaccurate estimation of junction temperature through the temperature sensitive electrical parameter (TSEP) [3]. In this study, we present a comprehensive analysis of the degradation in electrical characteristics of SiC MOSFETs with integrated SBDs subjected to different power cycling counts. Experimental results obtained from device measurements are provided to clearly illustrate the progression of degradation and performance variation with increasing power cycling. Figure 1 presents the schematic diagram of the PCT setup and the corresponding current and junction temperature waveforms during a single cycle. Table 1 summarizes the operating conditions applied during the PCT in forward MOSFET mode. Figure 2 compares the changes in on-resistance (Ron) for conventional MOSFETs and MOSFETs with integrated SBDs over the number of cycles. It is evident that MOSFETs with integrated SBD undergo more rapid degradation compared to conventional MOSFETs. Additionally, distinct failure characteristics, different from those of conventional MOSFETs, were observed in the integrated SiC SBD MOSFETs. PCTs were systematically carried out at various cycle intervals, followed by detailed evaluations after PCT to perform a comprehensive analysis of device characteristics, particularly during the plateau region of integrated SBD devices. Figure 3 illustrates the forward voltage (VF) variations according to the number of cycles. VF is a critical parameter for accurate estimation of junction temperature. The increase in VF with prolonged cycling leads to inaccurate estimation of junction temperature. Figure 4 presents the Ron according to each cycle. Degradation becomes more pronounced with increasing number of cycles. Figure 5 shows the threshold voltage changes over cycling duration. It indicates that electron trapping in the gate oxide layer, resulting from continuous cycling, leads to shifts in the threshold voltage. Figure 6 shows the degradation of breakdown characteristics with increasing number of cycles, highlighting the detrimental effects of power cycling on the device’s reliability. Based on the experiment, it was confirmed that hysteresis in electrical characteristics occurs during the PCT of the embedded SBD device. This phenomenon is attributed to over-cycling caused by an underestimated junction temperature due to increased VF. Further analysis will be conducted to investigate this behavior in more detail.

ABSTRACT. The high breakdown field and excellent thermal conductivity of Silicon carbide (SiC) have enabled its widespread use in power devices [1]. However, the intrinsic trade-off between breakdown voltage (BV) and specific on-resistance (Ron,sp) remains a major challenge in achieving high voltage tolerance alongside high current density, fast switching, and low power loss. By employing charge compensation effect, superjunction (SJ) technology breaks the conventional BV~Ron,sp trade-off, allowing for higher drift doping concentrations under high breakdown conditions and thus offering significant potential for low-loss, high-voltage device operation [2]. However, the charge balance in SJ devices, realized by periodically alternating heavily doped N-pillars and P-pillars, demands highly precise process control, significantly increasing fabrication complexity, especially in the termination region [2]. Notably, studies on SiC SJ terminations remain limited, and most using uniform P-pillar distributions, with few analyzing the impact of P-pillar distribution on termination performance [2-4]. In this work, the impact of P-pillar distribution on the performance of JTE-based 4H-SiC SJ termination structures is evaluated by TCAD simulations. Figs. 1(c) ~ 1(e) illustrate three termination designs (D1–D3) with different P-pillar profiles, and the top-view layout is shown in Fig. 1(a). The corresponding breakdown voltages, shown in Fig. 1(b), all exceed 1700  V, satisfying the 1200  V voltage device requirement. The electric field distribution at 1500 V is shown in Fig. 2(a). D2 exhibits higher P-pillar utilization efficiency, with the P-pillars near complete depletion at the edge of the termination due to the reduced spacing between them. Fig. 3 further analyzes the electric field distribution along different cutlines (C1~C3). D2 exhibits significant electric field peaks near the thermination surface at C1 and C2, exceeding the bulk field levels, and a sharp field drop at the edge (C3), potentially compromising the long-term reliability of the device. D1 shows low electric field peaks at C1 and C2, indicating insufficient voltage sharing across the termination. By comparison, D3 demonstrates a highly uniform field profile, indicating improved prospects for long-term device stability. The reliance of SJ structures on precise charge balance makes them highly sensitive to process variation, posing a major challenge to device fabrication. Fig. 4 shows the impact of P-pillar dose errors on termination performance. It is observed that D3 maintains 1200 V blocking capability with an error window exceeding ±13 %, showing a clear advantage, especially under P-rich conditions. The improved robustness is attributed to the widened P-pillar spacing at the edge, which reduces the effect of charge imbalance on termination performance. The impact of oxide charge cannot be ignored in the manufacturing of SiC devices. Fig. 5 illustrates the sensitivity of termination blocking capability to oxide charge density (NOX). For positive oxide charge, all three structures exhibit nearly identical blocking performance, while D3 shows a broader blocking range under negative oxide charge. The breakdown current distribution at a negative NOX of 5 × 10¹² cm⁻² is shown in Fig. 2(b). The breakdown location of D3 shifts inward compared to D1 and D2, indicating its potential to withstand higher negative oxide charge density. The impact of JTE concentration variation on termination blocking capability was investigated in Fig. 6, considering the dose sensitivity of JTE structures. D2 and D3 exhibit low sensitivity to JTE dose errors within ±15 %, indicating improved process tolerance by reducing implantation accuracy requirements. In conclusion, the proposed D3 structure demonstrates high process tolerance, significantly reducing manufacturing complexity. Further optimization will refine the D3 design for enhanced termination performance, and focusing on the influence of P-pillar count and spacing. [1] M. Buffolo et al., J. IEEE Trans. Electron Devices. 71.3 (2024). [2] Masuda et al., C. IEEE Intl. Symp. Power (ISPSD). (2020). [3] Wang, Ruidi, et al., J. IEEE Trans. Electron Devices. 43.7 (2022). [4] Kang, Haobo, et al., J. Science China Information Sciences. 68.4 (2025).

ABSTRACT. In the latest generation of silicon carbide (4H-SiC) metal oxide semiconductor field effect transistors (MOSFETs), a reduction of the ON-resistance (RON) and an increase ot the maximum operating current is expected, through the reduction of cell pitch and optimized thermal activation of the implanted regions. [1]. In 4H-SiC MOSFETs, ion implantation is typically used to introduce dopant species (Phosphorus for n-type and Aluminum for p-type) into specific regions of the semiconductor material, followed by high-temperature annealing to electrically activate the dopants. [2,3]. Given the discrepancies between designed and actual properties, to understand the real device performance, both the active doping concentration (or the material resistivity) and the real device geometry (e.g. size of the implanted region, junction depths, etc.) must be accurately monitored at the nanoscale. In this context, due to the limitation of the chemical characterization techniques evaluating active doping profile in the implanted region of the semiconductor, two dimensional (2D) electrical scanning probe techniques (SPM), attracted the scientific community to obtain reliable insights on the device physics. However the most commonly employed SPM techniques for carrier profiling, such as scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM), present some limitations in the quantification of the spatial distribution of the active dopants concentration and local resistivity in the region underneath the tip [4], due to several factors, including the non-ohmic contact between the sample and the probe [5]. On the other hand, scanning microwave impedance microscopy (sMIS) is emerging as a powerful technique to overcome these limitations related to the tip/sample contact and it enables the linear feedback between its signal and the active doping concentration (on both p- and n-type materials) [6]. Scanning Microwave Impedance Microscopy (sMIM) uses a sharp conductive tip designed to measure the reflected microwave signals coming from the sample after an appropriate stimulation (Fig.1). A microwave signal is applied to the tip, typically in the frequency range of gigahertz (GHz). The signal interacts with the sample surface, and depending on the electrical properties of the material (such as conductivity, permittivity, and dielectric properties), the microwave signal is either reflected, transmitted, or absorbed [7]. The reflected microwave signal is analyzed to extract information about both the resistive (real) and reactive (imaginary) components, which correspond to the material’s ability to conduct electricity and store energy, respectively. This results in a 2D map of the local impedance properties, which can be used to visualize and characterize fine-scale features in the sample. In particular, the impedance measured under the tip has two components where the imaginary part Im(Z)=sMIM-C is proportional to (ωC)-1. Hence, in a tip/semiconductor Schottky contact condition – like in most of the wide band gap semiconductors – this can be associated to the local active doping concentration (∝C-2). In this paper, sMIM analysis has been performed and compared to TCAD simulations on the channel region of a commercial vertical 4H-SiC power MOSFET, with the aim to determine both the low and high doping the n-type and p-type distribution in real device. Fig. 2 shows the sMIM map collected using wave-guide/antenna TiW coated (sMIM 150) tips on a MOSFET device. As can be noticed, the sMIM image is able to detect the carrier variations in the different regions of the device (source, drift, JFET and p+ ohmic contacts). On the other hand, by adding a DC voltage ramp on each pixel, the sMIM is capable to collect a “data-cube”, where dC/dV signal per pixel can discriminate between p- and n-type semiconductor materials. Fig. 3 reports the sMIM-C signal converted to doping concentration according to the following equation: . Fig.4 shows the local punctual active doping levels determined in the p+ ohmic contact, on the body, in the source and in the drift regions. The data-cube acquired by over imposing a DC voltage ramp (from –10 to +10 V) it is possible to monitor the variation of the carrier concentration underneath the sMIM probe. Fig. 5a shows the sMIM-C signal across the JFET region (as schematically shown in the inset) at different DC bias values. These curves were compared to the carrier concentration simulated to a TCAD model developed on the data estimated from the sMIM measurement itself. Fig. 5b shows the TCAD simulated carrier concentration estimated by varying the gate bias in a simulated device. The comparison between the experimental data (Fig. 5a) and the TCAD simulated (Fig. 5b) gives a first approximation on the MOSFET device physics with no information on the real device design. Finally, the sMIM-C can quantify the accumulation charge in the channel region (not shown here). Even though this aspect deserves further investigation, sMIM is promising for the investigation of shrunk latest MOSFETs generation in terms of lateral resolution. This work is supported by Horizon EU AdvanSiC Project (grant agreement n. 101075709)

ABSTRACT. This work reports, for the first time, the experimental characterization of a 3.3 kV SiC MOSFET with a Quasi-Planar Trench (QPT) structure, developed alongside a planar reference device on the same wafer. Static forward characteristics were measured at both room and high temperatures. The QPT design demonstrated improved control of short-channel effects and breakdown voltages above 3 kV. A detailed analysis of the device’s on-resistance (RON) was carried out using 3D TCAD simulations, focusing on the influence of gate oxide thickness along the trench. The study confirms the feasibility of the QPT approach and provides insights into key design parameters.

ABSTRACT. SiC Power MOSFETs are advanced power semiconductor devices that enable highly efficient, high-power electronics applications due to their wide bandgap characteristics [1, 2]. Recent advancements have aimed at minimizing the on-resistance (Rds,on) to reduce conduction losses while considering trade-offs among key design parameters, as discussed in our previous reports [3, 4]. This paper will focus on the P-body effect formed by ion-implantation, which impacts both static characteristics, including body-diode reverse recovery, short circuit withstand time (Tscwt), and switching energies in 1.2 kV 4H-SiC Power MOSFETs. Figure 1 shows a simplified cross-sectional view of the 1.2 kV SiC Power MOSFET. P-well doping concentration was varied at two levels to investigate the Pwell doping effect as a P-body (High PW and Low PW). Figure 2 (a) and (b) show the drain current (Id) and calculated field-effect mobility (μFE) versus gate voltage (Vg) and Trap density (Nit) measured using charge pumping (CP) method measured on Lateral SiC MOSFETs, respectively, revealing the impact of P-well doping on MOSFET channel properties. High PW exhibits a slightly higher threshold voltage (Vth), 80 mV higher than Low PW, while μFE is about 10% lower. Additionally, Nit is approximately 22% greater in High PW samples. Figure 3 presents the static characteristics of the 1.2 kV 4H-SiC Power MOSFET at 25 °C and 175 °C. Figures 3(a) and (b) show the normalized Rds,on versus Vth and breakdown voltage (BVdss) versus Rds,on, respectively. The High PW shows higher Vth, Rds,on, and BVdss compared to Low PW, consistent with Fig. 2. Additionally, the increase rate in Rds,on at 175 °C is less pronounced than at 25 °C as P-well doping increases. Figure 4 presents the measured normalized parasitic capacitance plots (Ciss, Coss, and Crss) for both configurations, showing that Ciss and Crss for High PW are approximately 5.5% higher and 33% lower than those for Low PW, respectively, attributed to higher PW doping levels, which also explains the higher BVdss shown in Fig. 3(b). Figure 5 represents the switching waveforms from the double pulse test (DPT) for comparing the switching characteristics of MOSFETs with High PW and Low PW during Turn On (Fig. 5(a)) and Turn Off (Fig. 5(b)). Figure 6 presents the reverse recovery characteristics, comparing the body diode performance for both samples. The normalized switching parameters, including dI/dt, switching energy losses (Eon and Eoff), and dIr/dt, are summarized in Table 1. The High PW shows lower dI/dt during Turn On and higher Eon compared to Low PW, while exhibiting higher dI/dt during Turn Off and lower Eoff. These behaviors are attributed to reduced channel mobility from heavier P-well doping. For reverse recovery, High PW demonstrates higher dIr/dt and reverse recovery current (Irr), but lower reverse recovery charge (Qrr) than Low PW. The heavily doped P-well contributes to a lower softness factor in body diode performance, albeit with a reduced Qrr. Additionally, the High PW configuration shows a higher body diode forward votlage drop (Vsd) when the gate is fully turned off. Figure 7 presents a comparison of short-circuit current waveforms at a Vds of 800 V. The High PW exhibited a smaller peak drain current. The reduction in peak drain current during short-circuit events correspondingly improved Tscwt with heavily doped P-well. These results indicate that the channel mobility, along with the straggle associated with P-well implantation due to the heavier P-well doping, contributes to the increased Tscwt. In conclusion, this study demonstrates that variations in P-well doping significantly influence the electrical characteristics of the 1.2 kV SiC Power MOSFET. The High PW, characterized by increased doping levels, results in higher Vth, Rds,on, and BVdss, while also revealing a notable impact on switching behavior and body diode performance. Exhibiting lower channel mobility, the High PW improves Tscwt by reducing peak drain current during the short circuit event. Overall, the findings underscore the critical role of P-well doping in optimizing MOSFET performance for high-voltage applications.

ABSTRACT. The tunneling field-effect transistor (TFET) has been historically discussed as a direct competitor to the metal oxide semiconductor field-effect transistor (MOSFET) in integrated circuits due to the theoretical superiority of the TFET in terms of the fundamental limit in subthreshold swing and therefore the necessary supply voltage and finally the efficiency [1]. TFETs have not yet succeeded in delivering on those promises. In power electronic devices other metrics are of interest. Here, static loss in terms of the on-state resistance R_DS,on and dynamic switching loss in terms of the switching energy at a certain conduction current E_dyn(ID), and finally device unit cost govern the relevance of a device. The TFET device concept, as shown in Fig. 1 a), can be adapted to high-voltage operation by introducing a lightly n-type doped drift zone instead of the intrinsic region of the pin-diode structure and shortening the gate to just form the channel on the source-side junction, as shown in Fig. 1 b). Compared to the equivalent laterally diffused MOSFET (LDMOS) shown in Fig. 1 e), the adapted TFET for power applications (Power-TFET) has a simpler device structure, which addresses the unit cost per device from a production standpoint. In addition, the convenience of the free-wheeling diode is preserved. Fig. 1 b) and e) show the comparison of the R_DS,on of LDMOS and Power-TFET. Assuming equivalent device geometry, the R_DS,on only differs with respect to the tunneling resistance R_tunnel or the channel resistance R_ch. If R_tunnel matches R_ch, the R_DS,on is equal. Smaller capacitances improve upon the dynamic loss since less charge must be transferred onto the capacitor. Fig. 1 c) and f) illustrate how the simpler structure of the Power-TFET omits the gate-body capacitor, where the inversion channel in the LDMOS would be formed. Additionally, the Power-TFET uses an accumulation channel for switching, which relies on the majority carriers already present in the drift zone, which should improve the transient characteristics. The first Power-TFET device was fabricated alongside the equivalent LDMOS on the 2 μm high-temperature 4H-SiC CMOS platform provided by Fraunhofer IISB. The fabrication process of the devices is described by May et al. in [2]. A comparison of the static transfer characteristics is shown in Fig. 2. The LDMOS shows the exponential subthreshold behavior expected from thermionic emission, whereas the Power-TFET shows the rather rounded behavior known from the tunneling junction, also displayed in [1]. Fig. 3 shows the output characteristics of the devices normalized on the gate width and appropriately scaled axes for direct comparison. At low V_DS, the Power-TFET shows the characteristic Zener tunneling breakdown up to a voltage of 13 V, where it saturates comparable to the LDMOS. Breakdown voltages of the LDMOS and the Power-TFET, shown in Fig. 4, are comparable due to the same geometry of each drift region with a length of 12 μm and RESURF implantations to avoid surface breakdown. It is visible from Fig. 2 that the on-state current of the Power-TFET is 5.5 orders of magnitude lower than the on-state current through the LDMOS, comparable to the first Si TFET [3]. This shortcoming of TFETs is well known in literature and further enhanced by the large band gap of 4H-SiC. Multiple solutions have been proposed on various material systems, such as the introduction of heterostructures for reduced barrier height and shorter tunneling distances [4, 5]. Those devices can match the on-current of the equivalent MOSFET but increase the device complexity. Focusing on wide-bandgap semiconductors the free-wheeling pin-diode structure is not satisfactory due to its high built-in voltage and resulting static loss. Junction barrier Schottky (JBS) diodes are commonly used in those applications. The switchable junction would then be a gated Schottky contact (Schottky Power-TFET). At such contacts, the barrier height and, therefore, the current carrying capability can be selected by material combination at the metal-semiconductor interface. Simulations shown in Fig. 5 of such a Schottky Power-TFET with contact potential of ɸ_M-HL = 0.6 V suggest comparable on-current to the LDMOS.

ABSTRACT. In power device fabrication, forming low-resistance ohmic contacts is crucial for the performance and energy efficiency of devices. Achieving such contacts on 4H-SiC is more challenging than on silicon, primarily due to SiC's wide bandgap and high chemical inertness. Transfer Length Method (TLM) test structures are widely used for extracting the specific contact resistivity (ρc) between metal and semiconductor layers, together with the sheet resistance of electrically isolated doped layers [1]. However, the accuracy of the extracted parameters is strongly influenced by the design of the TLM test structure, the measurement procedure, and the proper interpretation of measurement data [2]. Contact implantation and the consumption of SiC material during the contact formation process modify the semiconductor layer beneath the contact. This results in a sheet resistance below the contact (RSK) that deviates from the sheet resistance between the contacts (RSH). In standard TLM evaluation, it is assumed that the difference between the sheet resistances RSH and RSK is negligible. Therefore, the analysis is simplified to determining resistances between two contacts (C1 and C2) at varying distances (di), allowing the determination of the so-called contact front resistance (RCF) and transfer length (LT). LT is the distance beneath the contact, where the potential difference drops to 1/e of its peak [1]. The contact length (L) should ideally be in the range of the transfer length (LT) to accurately determine RCF and RCE [1]. For a more accurate analysis of contact resistivity, the assumption that RSK equals RSH should be reconsidered. To differentiate RSH from RSK, the contact end resistance (RCE) must also be determined [3]. The third contact (C3), which is not subjected to current flow, functions as a voltage probe to determine RCE (as schematically illustrated in the cross-section in Fig. 1). This study performs a simulation analysis to investigate the influence of the contact length (L) and the sheet resistances (RSK and RSH) on RCF and RCE for different contact spacings (di). We simulate the TLM structure as a three-contact configuration (Fig. 1) and modify the sheet resistance beneath the contact (RSK) by adjusting the local net doping concentration. For simulating a standard TLM measurement, the contact spacing di is varied, and the current-voltage (IV) characteristics between C1 and C2 are simulated. Then RCF is obtained from a linear fit of resistances between C1 and C2 as a function of di. Fig. 2 (left) shows the current (I1) through C1 as a function of the applied voltage (VCF) between C1 and C2. Fig. 2 (right) shows the current (I1) in dependence of the measured voltage (VCE) between C2 and C3, which is used to determine RCE. The standard TLM analysis is shown in Fig. 3 for different contact lengths with RSK equal RSH. Fig. 4 shows the TLM analysis for different RSK and RSH with the same contact length. The TLM structure is modeled in 2D with a simulation depth of 1 μm in TCAD [4]. The structure consists of a p-type layer featuring implantation beneath the contacts on top of an n-type substrate. The implantation beneath the contacts is used to influence RSK. Fig. 5 shows the influence of L on RCF and RCE. If L is much larger than LT, the potential difference and thus the resistance approach zero. This makes the correct extraction of RCE unfeasible due to measurement limitations [1]. Conversely, when L is short, RCE becomes sensitive to manufacturing variations in L. Fig. 6 shows the current density beneath C2 for L larger than LT. The goal of this simulative investigation is to quantify the impact of contact length (L) on RCF and RCE, from which ρc, and the sheet resistances (RSH and RSK) can be determined. The findings provide a deeper understanding of the TLM technique's robustness when applied to 4H-SiC. This offers valuable guidelines for optimizing TLM test structures to ensure accurate characterization of ohmic contacts. The final paper will discuss additional factors, such as doping levels and implantation depths beneath the contact. Additionally, we will identify under which conditions our simulation diverges from established analytical equations and analyze potential inaccuracies of the standard TLM procedure.

ABSTRACT. The rapid development of Silicon Carbide (SiC) power MOSFETs technologies fueled by the increasing demand of electric traction poses new reliability and robustness challenges [1-2]. The components must be able to withstand extreme temperature, humidity and possible contaminants rendered much more stressfull by the high currents and fields experienced by the devices. One of the key parameters in ensuring the ruggedness of an electric traction power train is the ability to respond timely to short circuit events. Having higher time to fail (ttf) in the devices ensure that the external detection circuit can respond appropriately before destruction. In this work we study how to simulate short circuit (SC) events with the help of technical computer-aided-design (TCAD) tools, in particular the synopsys suite, and study the dependence on the simulation parameters and models on the physics of the device identifying two different failures mechanisms. To simulate the SC event the device is brought to its operating voltage with the gate completely turned off, then a square pulse of 18 V of amplitude is sent to the gate allowing the current to flow through the device for a set amount of time. The two most important parameters in modelling the behaviour of a device are the time to fail and the energy dissipated during the SC event. Using the default models and parameters is possible to induce device failure and thermal runaway but the ttf is much larger than what is expected from experimental results. One of the possible ways to modify the response is to align the SiC lattice thermal conductivity. Using available data[3] is possible to test different models present in the suite or to introduce new ones entirely. The results show that having higher temperatures in the SiC epi layer lowers the current flowing through the device due to the increased resistance. The thermal runaway is still induced at very large ttf and the energy dissipation is misaligned. Another important parameter that can trigger failure is the carrier lifetime. This value determines the amount of electron-holes production during the event and has a key role in the rapid surge of current typical of SC failures. The carrier lifetime in SiC is calculated using the Scharfetter relation for the concentration dependent part while the thermal part is modelled by a power law with an exponent that is purely phenomenological and process dependent. The default value comes from a low temperature multi-phonon approximation that predicts a positive one, i.e. carriers have longer time with increasing temperatures [4]. In literature it is often found that for higher temperature the approximation fails and the power law is reversed requiring negative exponents [5] and a lowering of the max value for lifetime. The change in the recombination model has an important impact on the physics of the device allowing for early failures aligned with the experimental tests. Maximum dopant life and the power law exponent are used to tune the ttf to the experimental values but can be used to modulate the failure energy. It is interesting to look at the failure mechanism predicted by the simulation. The program predicts a surge in current due to the extreme temperature inducing electron-hole recombination near the body junction. Electron-hole production and recombination increase the temperature itself in a self-heating loop. Finally, the combination of large fields currents and temperature induces a sizeable current through the gate oxide as well. This self-sustained phenomenon cannot be turned off by closing the channel once a certain critical temperature is reached and it leads to the device destruction.

[1] D. Cimmino et al., Electronics 2020, 9, 1884; doi:10.3390/electronics9111884 [2] J. Leppannen et al., Microelectronics Reliability 123 114207 (2021) [3] Rusheng Wei et al., Journal of Applied Physics, (2013). [4] A. Schenk, Solid-State Electronics, vol. 35, no. 11, pp. 1585–1596, (1992) [5] Kakarla, Bhagyalakshmi et al., in 2020 32nd ISPSD, pp. 234-237, (2020)

ABSTRACT. Despite continued improvements in 4H-SiC material quality and device processing, bipolar degradation remains a persistent reliability challenge in SiC power devices, particularly under body-diode or bipolar operating modes. This degradation is driven by recombination-enhanced defect propagation and stacking fault (SF) expansion originating from basal plane dislocations (BPDs). In this work, we investigate a scalable screening method based on surge current pulse stress. This is an alternative to conventional DC-based high-temperature tests which typically require extended durations and fail to replicate realistic transient operating conditions [1,2]. Three batches of commercially available 1200V TO-247-packaged SiC MOSFETs (sample set A, B, and C) were evaluated under identical surge current time pulse conditions but different amplitude (400 A for sample set A and C; 190 A for the sample set B). Due to the different die areas, the following current densities resulted, respectively: ~2597 A/cm² for sample set A, ~3795 A/cm² for sample set B, ~2941 A/cm² for sample set C. Sample set A, operating at the lowest current density of ~2597 A/cm², exhibited excellent stability across all measured parameters, including RDS(on), threshold voltage (Vth), 3rd quadrant characteristics, and output curves, with no failures and deviations below 3.2% with up to 200,000 current pulses. UVPL imaging confirmed the absence of any stacking fault. In contrast, sample set B exhibited severe degradation already after 25,000 pulses. After 50,000 pulses RDS(on) increased by up to 37%, Vth shifted by as much as –9%, and output current dropped by over 10%, with 30% of the devices failing entirely. Fig. 1a-c depicts the emergence and growth of stacking faults under this stress condition: starting from none in the reference state to widespread propagation after 50,000 pulses. The 3rd quadrant characteristics shown in Fig. 1d complement the optical findings: A gradual deviation in reverse conduction behavior is revealed beginning starting from 20,000 pulses. This electrical shift aligns closely with the onset of optically visible stacking fault expansion, and becomes more pronounced at 50,000 pulses, confirming the correlation between structural degradation and reverse conduction degradation under repetitive bipolar stress. Sample set C, which was tested with the same current as sample set A but having a smaller die area, showed moderate degradation after 100,000 pulses. Devices in this group experienced RDS(on) shifts between 3.5% and 15%, a change in Vth changes below 2.5%, and one device completely failed. Fig. 2 compares two such devices, showing a clear correlation between SF visibility in PL and electrical degradation severity. These results are in line with studies, which demonstrate that minority carrier injection and high current densities can activate stacking faults via recombination-enhanced defect propagation in the substrate beneath the buffer layer; particularly in material with high BPD content [1,3]. The degradation patterns seen in sample sets B and C align well with earlier findings from body diodes and p-i-n structures [2,4]. Meanwhile, the relatively small but measurable Vth shifts across all samples point towards bias temperature instability mechanisms involving near-interface oxide traps and charge redistribution, as described by Lelis et al. [5]. The critical insight is that even with identical normalized stress levels (N = J/Jnom ~ 3.3), devices with smaller die areas suffer disproportionately higher degradation due to elevated absolute current density. This reinforces the importance of die and buffer layer design as well as epitaxial quality control in SiC device development. The surge current screening method presented in this work provides a scalable and time-efficient means to evaluate reliability limits and to flag device designs that are vulnerable to degradation under mission-profile-relevant stress conditions.

ABSTRACT. Silicon Carbide (SiC), a wide bandgap material, offers a higher critical electric field than conventional silicon, allowing comparable static performance to be achieved in a smaller device area. As a result, SiC-based unipolar devices, such as MOSFET, exhibit lower capacitance in a more compact form. This feature allows SiC MOSFETs to achieve one of their key advantages: high-speed switching performance, which is critically important in system design. However, such high-speed switching also makes the devices more sensitive to minor variations and noise in dynamic characteristics, emphasizing the necessity for precise device characterization and design optimization [1]. In particular, SiC MOSFETs exhibit asymmetric switching behavior between turn-on and turn-off conditions. This asymmetry should be carefully considered in the design of parallel applications, soft-switching circuits, and system-level control methods [2], [3]. This study investigates the asymmetric dynamic behavior of SiC MOSFETs using Double Pulse Test (DPT). The test setup includes a custom-fabricated PCB and a Schottky diode used as a free-wheeling diode, as illustrated in Fig. 1. We conducted switching tests on commercial 1200V SiC MOSFETs with on-resistances of 40mΩ, 160mΩ, and 350mΩ under their respective rated current conditions. The rise time (Tr) and fall time (Tf), which represent the duration for the drain voltage to transition from 10% to 90%, were measured during the turn-on and turn-off events. Energy losses were also calculated and analyzed. As shown in Fig. 2, distinct differences between the turn-on (Fig. 2 (a)) and turn-off (Fig. 2 (b)) behaviors were observed. As current increased, the Tr decreased, while the Tf tended to increase. This difference was particularly significant in the Tr. It is believed to result from the distinct charging and discharging behaviors of the gate-to-drain capacitance (CGD) within the Miller region during the turn-on and turn-off transition. Among the two, the turn-off is more sensitive to variations in current, leading to a more noticeable change in switching behavior. This behavior was hypothesized to be influenced by both the CGD and gate-to-drain current (IGD) parameters, and further analysis was conducted to identify the dominant factor. Additionally, as the device's on-resistance increased, the CGD tended to decrease, leading to shorter rise and fall times under the same current conditions. Furthermore, as shown in Fig. 3, energy losses during the turn-on (Eon, Fig. 3 (a)) and turn-off (Eoff, Fig. 3 (b)) were evaluated with respect to increasing current. Energy loss during the turn-on increased significantly with current, whereas the increase during the turn-off was relatively minor. The phenomenon of faster switching speeds under higher current during the turn-off is considered to be one of the contributing factors to this behavior. This interpretation aligns with the switching speed trends observed in Fig. 2. In conclusion, this study analyzed the asymmetry in the turn-on and turn-off switching behavior of SiC MOSFETs through quantitative comparison of rise and fall times. The findings provide valuable insight into how such characteristics impact system-level design and are expected to serve as a useful reference for SiC MOSFET-based power system applications.

ABSTRACT. A representative wide bandgap semiconductor, silicon carbide (SiC) is a strong candidate material to substitute the silicon (Si)-based power device applications [1, 2]. Since an energy bandgap of 4H-SiC is three times higher than Si, this material has an order of magnitude higher critical electric field than Si. Additionally, thermal conductivity of 4H-SiC is also better than Si. These advantages have made 4H-SiC the most successfully commercialized material in the power semiconductor industry [3–5].

A specific-on-resistance calculated by multiplication of on-resistance and active area is the most widely used performance index in power semiconductor devices. In silicon carbide-based power MOSFETs, electron carrier mobility is very low in the inversion channel region compared with silicon devices. This low electron mobility increases the channel resistance of the SiC MOSFETs which results in the portion of channel resistance is more than half in total device resistance. To reduce the specific-on-resistance of SiC planar MOSFET, it is necessarily required the shrink of the cell pitch. However, the cell pitch reduction involves some unwanted side effects. For example, if the JFET width is reduced the JFET resistance will be increased. For this reason, optimization of the unit cell design is important for compromising the balance of device performances.

In this paper, we show an improved specific-on-resistance of the new device structure with an optimized cell pitch and design parameters. Figure 1 shows the conventional and new active cell structure of our first generation (Gen1) and new generation (Gen2) 1200V SiC MOSFETs. Although the new structure has a narrow JFET region, the specific-on-resistance is smaller than conventional structure by applying an entirely increased JFET doping concentration with an advanced implantation technology. The smaller gate-drain capacitance of the new design results from the narrow JFET structure which makes it possible to have a dramatically reduced on/off switching loss characteristics as shown in Fig. 2. In addition, the narrow JFET region can limit the maximum drain current under short-circuit situation as shown in Fig. 3 which results in the improvement of a short-circuit capability of the new device.

ABSTRACT. High temperature operation of integrated circuits has been requested for electronics. 4H-SiC integrated circuits are expected to be a MOSFET operable in high temperature environments. However, despite the potential of 4H-SiC, at the high temperature, degradation and breakdown are induced in metal wires and gate electrodes. In this study, 4H-SiC n/p MOSFETs with Pt/Ti and Pt/TiN wires were investigated for high-temperature integrated circuits. The results show the superiority of Pt interconnections with Ti and TiN in the adhesion layer under 500°C environment.

ABSTRACT. Repetitive peak surge current (IF,RM) is a practically important parameter for SiC Schottky diodes, as it ensures reliable and robust circuit designs. However, there is no established method and criterion for this imperative parameter. Manufacturers predominantly provide the non-repetitive surge current value (IF,SM) in datasheets, which is generally determined from derated measured peak currents that cause diode failures [1-3]. Consequently, it is assumed that IF,SM enables diodes from various manufacturers with different structural designs to be compared in terms of their repetitive surge current performance. In this paper, we will demonstrate the need for a consistent criterion and a method to determine IF,RM by analyzing repetitive surge currents in representative commercially available SiC Schottky diodes. The analysis is based on a recently proposed method and criterion for the repetitive peak surge current in SiC Schottky diodes that ensures the junction temperature (Tj) does not exceed the maximum rating, which is 175°C for commercially available devices [4]. Figure 1 illustrates this method by mapping the surge current measurements (loops) to the isothermal I-V characteristics measured at 175°C. The analysis in this paper will show that the IF,RM values obtained by the newly proposed method are consistent with most values stated in datasheets, which means that this method can be used to determine IF,RM values when they are not stated. An example of the analysis that will be provided in the paper is illustrated by the data shown in Tables I and II. Table I shows that derated IF,SM values (the column labelled as “0.7 IF,SM” in Table I) are not in a good correlation with the stated IF,RM values. This in turn signifies that IF,SM is not an adequate indication for IF,RM when it is not stated in datasheets (vendor B). Table II shows that the newly proposed criterion, which measures the peak surge current (I_peak) for Tj=175°C and the case temperature Tc=25°C, is in good agreement with most IF,RM values stated in manufacturers datasheets when it is derated to 90% (0.9I_peak). Table II also shows that, in the case of Vendor A, the datasheet IF,RM value for one 1200V diode is slightly overrated, whereas the datasheet values for two 650V diodes are underrated. In conclusion, the analysis in the paper will demonstrate the significance of implementing the newly proposed method and criterion for repetitive surge current in commercial SiC Schottky diodes.

[1] X. Huang, G. Wang, M. C. Lee, and A. Q. Huang, In Proc. IEEE Energy Convers. Congr. Expo. 2245-2248 (2012). [2] S. Palanisamy, J. Kowalsky, J. Lutz, T. Basler, R. Rupp, and J. Moazzami-Fallah, In Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD). 367-370 (2018). [3] J. Wu, N. Ren, H. Wang, and K. Sheng, IEEE J. Emerg. Sel. Top. Power Electron. 7(3), 1496-1504 (2019). [4] J. Damcevska, S. Dimitrijev, D. Haasmann, and P. Tanner, IEEE Trans. Power Electron. Revised manuscript submitted for publication.

ABSTRACT. Reliability is an essential aspect of the development of power electronics devices. To guarantee a target lifetime spanning decades, the environmental robustness of devices must be validated through accelerated stress tests. A combination of factors that have been identified as critical include humidity, high temperature and electric field. A test that stress power devices with these factors is High Voltage-High Humidity High Temperature Reverse Bias (HV-H3TRB), with 85°C, 85% of Relative Humidity and 80% of breakdown voltage. Several mechanisms could occur in these conditions, such as ion migration, dendrites, corrosion, bubbles formation and silicon carbide (SiC) degradation due to oxidation [1]. Because the temperatures during HV-H3TRB are substantially lower than typically necessary to thermal oxidize silicon carbide, oxidation is due to electrochemical reactions that can depend on different pH-environments [2-4]. In this work, the degradation of silicon carbide that occurs during the HV-H3TRB test due to oxidation reaction is investigated (Fig. 1). The aim of this work is to better understand the underlying mechanism of silicon carbide oxidation occurring under humid conditions. The first part of the experiment consists of verifying that anodic oxidation occurs using a 4H-SiC sample as anode in an electrochemical system in the presence of different electrolytes. In particular, rectangular pieces of 10×15 mm2 of n-type 4H-SiC, usually employed in microelectronics, were used. Each piece before any experiment was degreased by sonicating in acetone for 4 minutes. To perform anodic polarization curve, a three-electrode electrochemical system was built with 4H-SiC sample as working electrode (anode), a platinum mesh as counter electrode (cathode) and a saturated calomel electrode (SCE) as reference electrode. To study the environment effect three different electrolytic solutions have been chosen: Sodium Chloride (NaCl), Hydrochloric acid (HCl) and potassium Hydroxide (KOH). In Fig. 2, an anodic polarization curve obtained from each of three solutions is shown. The region where the current density of each curve growth is called active region, corresponding when the oxidation reaction occurs. The behavior of the curves is similar in all the solutions, all of them show an active region, though there is an evident shift in voltage range, especially for KOH solution. The tested samples in the three environment conditions were analyzed at SEM. Fig 3 shows the morphological features of the samples, and it is possible to deduce that 4H-SiC exposed to NaCl and HCl exhibits the growth of an oxide, whereas the surface of the sample exposed in KOH has a different type of coverage. From the results obtained, neutral solutions appear to favor the oxidation of 4H-SiC. To confirm the oxide formation, XPS analysis will be carried out. Furthermore, the experiment will be extended to include more structured samples, in particular samples with different passivation layers deposited on the 4H-SiC surface, with the goal to study the ability of different passivation layers to prevent the anodic oxidation phenomenon.

[1] Hoffmann, Felix, et al. "A novel degradation mechanism of SiC power devices under electro-chemical stress." 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2024. [2] Kimoto, Tsunenobu, and James A. Cooper. Fundamentals of silicon carbide technology: growth, characterization, devices and applications. John Wiley & Sons, 2014. [3] Ebihara, Kohei, et al. "Durable Edge Termination Design of SiC SBD Against Humidity." 202436th International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2024. [4] Chen, Zhaojie, and Yonghua Zhao. "Investigation into electrochemical oxidation behavior of 4H-SiC with varying anodizing conditions." Electrochemistry Communications 109 (2019): 10660

ABSTRACT. Silicon carbide (SiC), known for its wide bandgap, exhibits excellent thermal conductivity, high electron saturation velocity, and a strong breakdown electric field. These properties make it a promising material for high-power and high-frequency applications, particularly where high voltage operation is required [1,2]. In this study, we investigate how variations in the JFET region design affect the electric field (E-field) stress on the gate oxide located beneath the gate poly in 1700 V planar-type SiC MOSFETs. Devices were fabricated with three different cell pitches (A < B < C), but the only variation was the JFET width; all other structural parameters such as P-well depth & width, channel length, and oxide thickness were kept constant in Fig. 1. The cell pitch increased proportionally with the JFET width. As the JFET region becomes wider, the vertical E-field applied to the gate oxide during high-temperature reverse bias (HTRB) testing increases, raising the risk of oxide breakdown. [3] Experimental results from multiple wafer lots of planar-type 4H-SiC MOSFETs show a clear correlation between wider JFET regions and higher failure rates under HTRB conditions. TCAD simulations confirm this trend, showing E-field peaks of 2.93 MV/cm (A), 3.69 MV/cm (B), and 4.35 MV/cm (C) when a drain voltage of 1700 V is applied, matching the rated breakdown voltage (BV). This increase in localized field stress significantly enhances the risk of time-dependent dielectric breakdown (TDDB), particularly under prolonged high-voltage and high-temperature conditions. [4] To evaluate this effect experimentally, we performed HTRB tests(175℃, Vds = 1700V) using actual 1700 V-rated planar SiC MOSFETs. A total of 80 samples per condition were tested. Devices with the widest JFET (C) exhibited 5 failures within 168 hours, and testing was halted early due to severe burn damage. Medium-width devices (B) had 2 failures at 168 hours and an additional 2 failures by 500 hours in Fig. 2. In contrast, narrowest JFET devices (A) completed the full 1000-hour test with no failures. The results show a strong correlation between peak E-field and oxide reliability, indicating that a field level below 3 MV/m is a practical design guideline for TDDB prevention. [5] These findings highlight the importance of managing electric field distribution in the JFET region, as structural differences can lead to reliability issues under prolonged high-voltage stress, as verified in 1700 V-class SiC MOSFETs. Since the JFET width is defined by P-well geometry, ongoing layout optimization focuses on adjusting both the depth and lateral width of the P-well to strike a balance between oxide robustness and overall device performance. Although narrowing the JFET width from C to A increases Rds(on) by approximately 4% in total (2% per step), this moderate increase is considered acceptable to ensure gate oxide stability in 1700 V-class SiC MOSFETs. [6]

ABSTRACT. Silicon carbide (SiC) power semiconductors have emerged as a transformative technology in the field of power electronics, particularly for high-voltage and high-current applications. One of the most defining characteristics of SiC is its critical electric breakdown field strength, which is approximately ten times greater than that of conventional silicon (Si). This unique property enables SiC devices to be fabricated with much thinner drift layers or at higher doping concentrations without compromising breakdown performance. Consequently, SiC-based power devices exhibit several advantageous features: high breakdown voltage, low on-resistance, and substantially lower parasitic capacitance. These characteristics collectively allow SiC devices to switch significantly faster and with much lower switching losses compared to their silicon counterparts. Despite these advantages, applying SiC devices in practical power electronic systems introduces new challenges. Specifically, the rapid switching transitions—though desirable from an efficiency standpoint—can excite parasitic components in the circuit layout, particularly parasitic inductances originating from the device packaging and busbar structure. These parasitic elements can cause severe voltage overshoot and oscillation during switching events, posing risks to system-level reliability and device lifetime [1]. Such electrical stress must be carefully managed to fully exploit the performance potential of SiC power modules. Among the various mitigation techniques, the implementation of a snubber circuit has proven to be one of the most effective solutions. Typically composed of a resistor (Rsnubber) and a capacitor (Csnubber) connected in series, the snubber circuit is designed to absorb transient energy and smooth voltage transitions. However, the benefits of a snubber circuit are highly sensitive to its component values. An improperly tuned snubber may reduce overshoot but worsen oscillations or increase losses. Therefore, the design of a snubber circuit must consider a balanced trade-off between voltage suppression, damping, and settling time, which requires both simulation and experimental validation [2]. In this study, we present a comprehensive approach to the design and optimization of snubber circuits for a 1200V/120A SiC MOSFET half-bridge power module. To realistically capture switching behavior, it is critical to account for parasitic inductances inherent to the physical structure of the module and its packaging [3]. These parasitic values were accurately extracted using ANSYS Q3D electromagnetic simulation software from a 3D model of the power module. Fig. 1 shows the modeled geometry used for inductance extraction. With these parasitic values incorporated, LTSpice was used to perform switching simulations under double pulse test (DPT) conditions. The simulation model, as shown in Fig. 2, includes varying combinations of Rsnubber and Csnubber. In this figure, the red lines highlight the current path during turn-off overshoot events, while the blue lines indicate the snubber path. Simulation results reveal that increasing the value of Csnubber generally reduces voltage overshoot, while increasing Rsnubber effectively suppresses oscillation amplitude and shortens the settling time. However, the relationship between the snubber parameters and switching characteristics is not strictly linear. A particularly notable observation is the behavioral transition near Rsnubber ≈ 0.5Ω, where system response changes more dramatically—a nonlinear threshold effect shown in Fig. 3. To validate the simulation results, a series of DPT-based experiments was conducted using nine different snubber configurations. These involved three values of Rsnubber (0.01Ω, 0.47Ω, 10Ω) and three values of Csnubber (10nF, 100nF, 10μF), forming a full factorial test matrix. The measured waveforms, as shown in Fig. 4, were analyzed to extract overshoot voltage and settling time under each condition. The experimental setup mirrors the simulation scenario to ensure consistency. The results demonstrate excellent agreement between simulation and experimental data: the maximum overshoot error was only 2.17%, while the maximum difference in settling time was 16.66%. Importantly, a similar nonlinear threshold was observed experimentally. As visualized in Fig. 5, when Rsnubber < 0.47Ω, increasing Csnubber consistently reduced overshoot. However, for Rsnubber > 0.47Ω, increasing Csnubber had a diminished effect, suggesting a saturation point in snubber effectiveness. These findings underscore the importance of holistic snubber circuit design that takes into account both linear and nonlinear behaviors of switching characteristics. The results confirm that switching transients in SiC-based power modules—particularly voltage overshoot and settling time—can be finely controlled through appropriate selection of snubber components. Furthermore, the close alignment between simulated and experimental data supports the reliability of the proposed methodology. This work contributes a practical and validated design approach for engineers and researchers aiming to build high-performance, high-reliability SiC-based power electronic systems for next-generation applications.

[1] H. Lee, V. Smet, and R. Tummala, J. Mater. & Device 8, 239 (2019). [2] D. Aggeler, et al., J. Appl. Phys. 28, 4074 (2012). [3] F. Hou, et al., Power Semiconductor, PRESS (2019), p. 223.

ABSTRACT. 4H-SiC MOSFETs are widely utilized in high-voltage and high-frequency power conversion systems due to their excellent switching performance, wide bandgap, and superior thermal conductivity[1]. In particular, they are considered promising candidates for spaceborne power electronics, where both high power density and radiation hardness are critically required. Under such harsh environments, system reliability is strongly influenced by electromagnetic interference (EMI) and radiation-induced instability during fast switching. The switching behavior of SiC MOSFETs varies significantly depending on the package. The conventional TO-247-3L package suffers from gate voltage oscillation and increased switching losses due to the common source inductance. In contrast, the TO-247-4L package adopts a Kelvin source configuration that separates the gate drive loop from the power loop, which is suggested to mitigate gate ringing and enhance dynamic performance[2]. This study investigates the package-dependent switching behavior of SiC MOSFETs under gamma-ray irradiation with a focus on total ionizing dose (TID) effects. The evaluation is conducted on commercial 1200 V 4H-SiC MOSFETs packaged in TO-247-3L and TO-247-4L. Devices are irradiated with gamma-rays at total ionizing doses (TID) of 0 krad (non-irradiation), 100 krad, and 500 krad. After irradiation, turn-on and turn-off switching characteristics are evaluated using the double pulse test (DPT). The experimental setup, illustrated in fig. 1, incorporates custom PCB layouts that isolate gate drive loops, enabling a controlled comparison of inductive switching behavior across package types. To precisely investigate the internal device physics and analyze radiation-induced degradation mechanisms, a five-contact TCAD mixed-mode simulation (device and circuit) is employed. In this configuration, the gate terminal is divided into gate-to-source (VGS) and gate-to-drain (VGD) nodes, while the source terminal is partitioned into n+ (channel current) and p+ (displacement current) regions. This allows detailed separation of current components during transient switching operation. Among various radiation-induced parameter shifts, the threshold voltage (Vth) shift is known to have the most direct influence on switching behavior, as it modulates both channel formation and current drivability[3]. To accurately model the ionizing dose effect, the simulation incorporates experimentally validated Vth variations for each TID level, enabling direct correlation with dynamic performance changes. Measured turn-on and turn-off waveforms are presented in fig. 2 and fig. 3, while the corresponding simulation results are shown in fig. 4 and fig. 5, respectively. By comparing the experimental and simulated waveforms, the study quantitatively evaluates the influence of gamma-ray irradiation and package-induced parasitic elements on gate ringing and switching energy loss. In addition, the simulation enables detailed observation of internal current flow and charge redistribution, which are difficult to access through measurement alone.

ABSTRACT. The reliability of SiC MOSFETs is critical aspect for extensive utilization in diverse system applications. The degradation mechanisms and weaknesses of the gate oxide have been demonstrated through dynamic gate stress test (DGS) in both planar and trench devices [1-5]. Furthermore, the application of high drain-source (VDS) bias may induce additional threshold voltage drifts [1-3]. This paper evaluates 1.2 kV SiC MOSFETs in TO247-4L package for prolonged switching in a modified H-bridge inverter. This pioneering work explores the combined effects of VGS, VDS bias, load current (IL), temperature and different dv/dts, representing realistic operating conditions.

ABSTRACT. This study investigates the mechanisms of single event leakage current effect (SELC) and single event burnout (SEB) during heavy-ion irradiation in SiC power diodes. Using Technology Computer-Aided Design (TCAD) simulations, the role of applied bias and incident heavy-ion was analyzed. Pre- and post-irradiation characterizations with deep level transient spectroscopy (DLTS) and minority carrier transient spectroscopy (MCTS) were performed to correlate defects with SELC degradation. Two diode structures, Junction Barrier Schottky (JBS) and Merged PiN Schottky (MPS), were irradiated with gold ions at the UNIversal Linear ACcelerator (UNILAC). SELC was observed at specific reverse biases, while SEB was associated with exponential leakage current increase and physical damage. TCAD simulations revealed that SEB occurs when the electric field reaches the critical value for 4H-SiC. Further investigations with photoluminescence (PL) and Energy Dispersive X-ray Spectroscopy (EDX) are planned to explore material composition and defect states.

ABSTRACT. This work presents a low-inductance SiC MOSFET power module packaging design employing a two-layer PCB structure with an integrated shielding layer to mitigate parasitic effects common in high-speed switching applications. Conventional interconnects, such as wire bonds and copper frames, contribute significantly to parasitic inductance, which degrades switching performance, increases EMI, and compromises system reliability. To address these issues, the proposed packaging replaces the interconnection with a two layer PCB, where the top copper layer serves as an electromagnetic shield. Finite element simulations in ANSYS Q3D and switching simulations in LTSpice demonstrate that this design reduces total loop inductance by 10%, lowers voltage overshoot during turn-off by 10%, from 98 V to 88 V, and reduces the switching energy loss from 400μJ to 370μJ. The final paper will extend the design to multi-chip configurations and experimentally validate the performance using double-pulse testing.

ABSTRACT. To address the growing demands for efficiency and power density in power electronics systems, silicon carbide （SiC） power modules are increasingly replacing traditional silicon-based solutions due to their superior electrical and thermal performance. While SiC modules enable higher packaging density and output power compared to conventional devices, the resulting high heat flux density poses significant challenges for thermal management and the thermal stability of packaging materials. Particularly in high-power, high-temperature operating environments, the packaging system must exhibit excellent thermal performance and long-term reliability to ensure stable operation.

This study focuses on automotive applications, presenting an innovative compact 6-in-1 SiC power module with an enhanced double-side cooling structure, eliminating the need for a direct bonded copper （DBC） substrate. By replacing the traditional DBC with a custom copper lead frame, the module achieves a significant reduction in both thickness and weight. The integration of six high-power SiC devices in a single module optimizes current distribution and effectively suppresses parasitic inductance, making it particularly suitable for high-voltage inverters, DC-DC converters, and onboard charging systems in electric vehicles （EVs） and hybrid electric vehicles （HEVs）. The double-side cooling design enables simultaneous heat dissipation from both the top and bottom of the devices, reducing thermal resistance by up to 40% while mitigating localized hot spots and improving temperature uniformity. High-reliability packaging materials, including epoxy molding compound （EMC）, sintered silver die-attach （DA） material, and preformed solder, ensure stable operation under high-temperature conditions.

The finalized module, occupying a compact footprint of 75mm ×50mm and with a total thickness of 1.68mm, incorporates six SiC devices, a customized copper lead frame （LF）, six source connection clips, six gate connection clips, and twelve copper blocks for electrical interconnection and mechanical reinforcement. Figure 1 presents a schematic cross-sectional view （not to scale） of the structure and an isometric view of solid model for the proposed module. The development process encompasses four key phases including design optimization, advanced packaging process development, comprehensive electrical and thermal performance evaluation, and reliability validation. Firstly, thermal, electrical, and mechanical simulations are conducted to guide material selection and structural refinement. Subsequently, process development and optimization efforts are carried out, with the final manufacturing flow summarized in Figure 2. Key process steps include SiC die attachment, copper block/post placement, copper clip bonding, molding encapsulation, grinding, and mechanical milling. Representative optical images of the completed 6-in-1 module are shown in Figure 3. Following fabrication and assembly, extensive performance characterization and reliability assessments are conducted. Failure analysis is performed on any samples exhibiting performance degradation. Key experimental results are summarized in Figure 4, and the test results demonstrate outstanding performance: the module exhibits a thermal resistance as low as 0.106°C/W, a power loop inductance of 10.38nH, and leakage parameters that meet industry standards. Under junction temperature fluctuations (ΔTj) of 150°C, the module successfully passed 50,000 power cycling tests, indicating its exceptional thermal reliability and structural stability.

Acknowledgement: This work was supported by the Science and Engineering. Research Council of A*STAR (Agency for Science, Technology and Research) Singapore, under Grant No. A20H9a0242.

Reference: [1] I. H. Ji, et, al, Proceedings of 2023 IEEE International Reliability Physics Symposium （IRPS）, [2] F. Sommer, et, al, Proceedings of the 2022 International Power Electronics, p.1390. [3] L. C. Wai, et, al, Proceedings of 2022 IEEE 72nd Electronic Components and Technology Conference （ECTC）, p.2211

ABSTRACT. SiC MOSFET technology (1200 V class) is continuously progressing towards higher performance driven by the massive growth potential of electric vehicle (EV) and urban air mobility (UAM) markets. Several suppliers have announced their fourth-generation chips claiming lower on-state resistances, faster switching speeds as well as more stable switching transients compared to previous generations. With respect to chip performance the latest generation of 1200 V SiC MOSFETs reach current levels up to around 120 - 150 A per chip. Consequently, for typical passenger EV or UAM applications power modules comprising three to four devices in parallel are targeted. For such power modules with multiple chips per switch position, the switching performances and the electromagnetics of the packaging (e.g. stray inductance, gate inductances, mutual coupling) determine the oscillations, losses and over/undershoots, and even the chip failures in case of a suboptimal design. Thus, a thorough investigation of parallel SiC chips operation is essential to facilitate the developments towards the ever-increasing demand for higher power density in EV and UAM applications. In this study, 1200 V automotive SiC MOSFETs from four different suppliers have been investigated, namely Device 1 to 4, which all belong to the latest available generations of the chips at the time of writing this article (fourth gen for devices 1 to 3 and second gen for device 4). To evaluate the switching performances in parallel, four chips per switch position were assembled on a ceramic substrate in a half bridge configuration, and three variants (without Rg-sub and with Rg-sub of 3 Ω and 5 Ω) were prepared (Fig. 1). The switching characterizations were done using a double pulse tester setup at 400 A and 800 V, and a gate driver unit with adjustable gate resistance, which allowed tuning the voltage transient rate (dV/dt). Device 4 had the fastest turn off and Device 1 had fastest turn on at room temperature, however Device 3 had the slowest current transient rate (dI/dt) at both turn off and turn on (Fig. 2). At 150 °C, Device 4 showed the fastest switching at turn off and Device 2 was the fastest during turn-on transients (Fig. 3). The switching losses were consistent with the switching speeds, i.e. Device 3 had the highest losses in both turn on and turn off transients (Fig. 4). Device 3 failed at 150 °C, all other devices were able to switch even without the Rg-sub. The analysis of results showed that the diode turn-off transient was the most critical for Device 3, as it generated high frequency oscillations with high amplitudes on the gate voltage of the device, which was supposed to be turned off (Fig. 5a). Such highly negative voltage peaks can significantly stress the gate insulator and damage the device or highly reduce its reliability. In Device 2, such oscillations had much lower frequency and lower amplitude, and the peak negative voltages barely exceeded the recommended operating gate voltage range (Fig. 5b). Nevertheless, the oscillations still existed but it should be noted that the parallel operation of the devices highly depends on the packaging design and electromagnetic parameters of the package. However, in this experiment the devices were benchmarked in the same conditions, with Device 1 and 2 showing the best performances overall. The assembly configuration and substrate were designed to do a comparison of the chips in the same platform, and the layout can be further optimized to improve the switching quality. Nevertheless, Device 3 performance revealed that it was the most sensitive to imperfections. The comparison of Device 2 (4th gen) and its predecessor (3rd gen) from the same supplier shows an improvement in the switching speed in the 4th generation (Fig. 6a), which also results in improved switching losses in both turn-on and turn-off transients (Fig. 6b and c respectively).

ABSTRACT. This study addresses the critical issue of recycling waste light bulbs, which are the least recycled e-waste products globally, with a recycling rate of merely 5%. [1] Traditional recycling methods for lighting products are limited to recovering metals from LED chips and PCB, particularly from larger-sized lighting, leaving small bulbs–composed of polymers, glass, and metal–destined for landfills and contributing to significant environmental issues such as microplastic pollution and soil contamination. We introduce a problem-solving thermal transformation process of enclosures of waste bulbs into multiphasic SiC nanopowder for energy storage. Collected post-consumer light bulbs were segmented by components for characterization as shown in Fig. 1. The polymeric diffuser of waste LED bulbs (LED-PD) was used as a source of carbon and the glass diffuser from incandescent bulbs (I-GD) as a source of silicon. LED-PD was identified as polycarbonate via Fourier Transform Infrared Spectroscopy (FTIR), and Carbon, Hydrogen, Nitrogen, and Sulfur (CHNS) analysis showed a carbon content of 75.61%, making it an excellent carbon source. Similarly, X-ray Fluorescence (XRF) analysis of I-GD revealed a SiO₂ content of 71.70%, providing a sufficient silicon source for SiC synthesis. Key synthesis parameters were optimized to maximize purity and yield. The sizes of LED-PD were compared between 0.5 mm and 2 mm, and the comparison of the mixing ratios ranged from an I-GD-to-LED-PD ratio of 1:1 to 1:4. The reaction temperature varied between 750°C and 1550°C, which are relatively lower than the 1700–2500°C range used in the conventional synthesis method. [2] By mixing larger-sized LED-PD particles with fine I-GD powder, and tuning other synthesis conditions, 95%-pure SiC compound containing both β-SiC (46.2%) and α-SiC (48.6%) phases was synthesized at 1550°C, confirmed by FTIR and XRD with Rietveld analysis shown in Fig. 2. The obtained SiC containing multiple polytypes is associated with the increased number of phase interfaces, which subsequently contributes to superior Li-ion diffusion compared to single-phasic SiC anode. [3,4] Raman spectra of dispersed spots of the SiC powder demonstrate how uniformly the different phases are distributed. FIB-SEM and TEM images with EDS analysis show that the synthesized SiC has two distinct morphologies shown in Fig. 3, with a superior surface area identified by Brunauer–Emmett–Teller (BET) analysis. TGA and DSC analyses validate the thermal stability of synthesized SiC up to 800°C, additionally supported by the results of high-temperature XRD, and this temperature is high enough to ensure thermal endurance for battery applications. Fixed carbon with an approximate content of 4% was observed by the XRD peak around 26° in the SiC after oxidation. The presence of fixed carbon and closed pores can lead to enhanced electrical conductivity and Li+ storage capacity. [5] Based on the excellent characterization results, the as-synthesized SiC was further applied as the anode in a lithium-ion battery, and the anode exhibited superior cycling stability and enhanced performance. Thus, this problem-solving method may not only open a new era of recycling technology of waste bulbs but also introduce a novel approach to high-value silicon carbide production.

[1] UNITAR, ITU, Global E-Waste Monitor 2024, United Nations University, Germany (2024). [2] S. E. Saddow and A. Agarwal, Advances in Silicon Carbide Processing and Applications, Artech House, (2004), p129. [3] Wang, S., Cai, Z., Cao, R., Ma, Z., Wu, Q., Moin, M., ... & Wen, C. Facile synthesis of multi-phase (Si+ SiO2)@ C anode materials for lithium-ion batteries. Dalton Transactions, 53(9), (2024). [4] Kwon, D., Choi, S., Wang, G., & Park, S. Germanium-based multiphase material as a high-capacity and cycle-stable anode for lithium-ion batteries. RSC Advances, 6(92), (2016). [5] Tang, Z., Zhang, R., Wang, H., Zhou, S., Pan, Z., Huang, Y., ... & Shao, M. Revealing the closed pore formation of waste wood-derived hard carbon for advanced sodium-ion battery. Nature Communications, 14(1), 6024, (2023).

ABSTRACT. Silicon Carbide (SiC) semiconductor devices offer distinct advantages for power electronics, including high breakdown voltage, superior thermal stability, and excellent power efficiency, making them ideal for demanding applications such as electric vehicles, renewable energy systems, aerospace, and smart grid technologies. Diamond, on the other hand, possesses exceptional thermal conductivity exceeding 2000 W/(m·K), significantly outperforming conventional semiconductor materials and making it highly attractive for advanced thermal management solutions. Effective heat dissipation is crucial for SiC power devices, as efficient thermal management directly impacts device reliability, performance, and lifespan. Incorporating diamond layers into SiC provides a promising solution due to diamond’s superior thermal conduction capabilities, thereby enabling efficient heat removal under extreme operating conditions. Previous studies on diamond integration with semiconductor substrates have primarily faced challenges associated with plasma-induced substrate damage, uneven nucleation, and inadequate management of thermal interfaces. Such limitations have hindered the widespread adoption of diamond as a thermal management solution in semiconductor devices. In this study, we aim to enhance the heat dissipation capability of SiC substrates by utilizing high-thermal-conductivity diamond layers. Our approach involves depositing diamond films using Microwave Plasma Chemical Vapor Deposition (MPCVD), while addressing a critical challenge—plasma-induced damage to the SiC substrate. To mitigate this, we employ Atomic Layer Deposition (ALD)-grown oxide layers (e.g., Al₂O₃, HfO₂) as protective interlayers that serve as effective passivation during the MPCVD process. Following diamond growth, the films are separated from the oxide buffer via a self-separation technique driven by interfacial stress, and subsequently reattached to the backside of the SiC substrate. This approach allows the integration of free-standing diamond layers for advanced thermal extraction, significantly improving the thermal performance of SiC-based power devices. This study differentiates itself by focusing on substrate-level thermal enhancement, rather than on-chip device packaging alone. By combining ALD oxide passivation, free-standing diamond transfer, and re-bonding strategies, we propose a practical, scalable solution to extend the operational boundaries of next-generation high-power SiC electronics.

ABSTRACT. Currently SiC crystal is widely used in electric vehicle (EV) related electronic applications. Typically, operational voltages of these power devices are in the range of 0.6-1.5kV, where typically 6µm-15µm epitaxial layers are used. However, to block high voltage (>5kV), much thicker epitaxy (>50µm) is required. Thick SiC epitaxy is extremely challenging due to severe surface degradation by formation of larger morphological and extended defects, as well as various complex dislocations (HLA, BPD pileup, etc.). In this research, we study epitaxy in the range of 60-200µm on 150 mm 4H-SiC wafers in a comparative manner for surface, defectivity, wafer shape, etc.