ABSTRACT. Silicon carbide (SiC) based high-voltage power devices require thick voltage blocking layers (epilayers) with low doping concentrations. SiC epi-wafers with thick epilayers are prone to basal plane dislocations (BPDs), which form around triangular defects (3C-SiC inclusions) and 3C defects near the wafer edge, caused by lattice mismatch and thermal stress acting as driving forces. Propagations of some BPDs from the wafer edge toward the center, which reduces the effective area of the wafer and the device yield, hence the crucial need to suppress BPD formation. The authors previously revealed that two types of BPDs with different Burgers vectors were generated during the epitaxial growth process [1]. One has a dislocation segment along the [1¯100] direction with an extra half-plane above the dislocation core (Type-A), and the other has a dislocation with opposite Burgers vector (Type-B). The former can mitigate compressive stress accumulated in the epilayer, and the latter can mitigate tensile stress around the triangular defects and in the substrate. In more detail, BPDs in SiC are classified into six types with equivalent Burgers vector of 1/3<11¯20> as shown in Fig. 1. In this study, gꞏb analysis was performed to confirm the existence and behavior of all types of BPDs with different Burgers vectors. An epi-wafer 150 mm in diameter and with an n− epilayer thickness of 200 μm (Nd−Na=~2×1014 cm−3) was used. The n+ substrate (Nd−Na=~5×1018 cm−3) was thinned down to ~3 μm. Prior to the gꞏb analysis, the observed BPDs were classified into two types, A and B, based on the dislocation contrast on the (¯1¯128) reflection image. Synchrotron x-ray topography images of g=10¯10, 01¯10, and ¯1100 under transmission geometry were obtained then analyzed to determine their Burgers vectors. Figure 2 shows synchrotron x-ray topography images around a triangular defect where Type-B BPDs are formed. For the two topography images in the (10¯10) and (01¯10) reflections, the BPDs propagating to the right/left side of the triangular defect disappear in one of the two images. From the contrast invisibility criterion: gꞏb=0, they are BPDs with a Burgers vector of either 1/3[¯2110] or 1/3[1¯210] when the dislocation direction is defined in a counterclockwise direction of the half-loop. The BPD half-loops propagated toward the [¯1¯120] direction which form interfacial dislocations at the epilayer/substrate (epi/sub) interface exhibit contrast on both reflection images, thus their Burgers vector is 1/3[¯1¯120]. Configurations of Type-B BPDs with differing Burgers vectors around a triangular defect are schematically shown in Fig. 2(c). BPDs with a Burgers vector of 1/3[¯2110] or 1/3[1¯210] propagated in a direction 60° or 120° from the step-flow, while BPDs with a Burgers vector of 1/3[¯1¯120] propagated toward the [¯1¯120] direction. These observation results suggest the propagation direction of the BPD half-loops is parallel to their Burgers vectors. The same analysis was also performed for Type-A BPDs as shown in Fig. 3. Here, the images of three g vectors in the same field of view for BPDs with different Burgers vectors are shown. In the images of the upper row, the contrast of dislocations in a vertical direction indicated by the arrows disappear in the (¯1100) reflection image, which means the Burgers vector is 1/3[11¯20]. The lower side of the BPD contrast disappears because the BPD has propagated beyond the epi/sub interface into the interior of the substrate. The images in the middle row show the BPDs propagating from the triangular defect toward the right. The dislocation contrast in the (01¯10) and (¯1100) reflection images indicated by the arrows disappear in the (10¯10) reflection image, which means the Burgers vector is 1/3[¯12¯10]. The BPDs shown in the images of the bottom row appear on the left side of the triangular defect. The contrast in the (10¯10) and (¯1100) reflection images disappear in the (01¯10) reflection, thus the Burgers vector is 1/3[2¯1¯10]. Figure 4 schematically shows how Type-A BPDs propagate around a triangular defect. Type-A BPDs propagate anti-parallel to their Burgers vectors when the dislocation direction is defined as the counterclockwise direction of the half-loop. BPDs with Burgers vectors of 1/3[¯12¯10] and 1/3[2¯1¯10] form only on either the right or left side of the triangular defect, respectively. These types are detrimental in that they reduce the effective area of the wafer by propagating toward the wafer center. The tensile stress around the triangular defect and in the substrate is considered as the driving force for Type-A BPDs to expand, thus the BPDs tend to propagate not toward the epilayer surface but toward the interior of the substrate where tensile stress is applied due to the lattice mismatch between the n− epilayer and n+ substrate.

ABSTRACT. One of the main applications for SiC is connected to the realization of radiation detectors. 4H-SiC is a wide band gap semiconductor with a band gap almost a factor 3 higher than Si. This property produces both a lower leakage current and a high radiation hardness. To realize these devices, we need generally thick epitaxial layer with good crystal quality and reasonable cost. To decrease the cost of the epitaxy it is necessary to realize a process with high growth rate. This kind of process was not possible in the past because trying to increase the growth rate, we must increase the Si/H2 ratio and, at some point, we have the formation of silicon precipitates in the gas phase. In 2004 we have realized a new process with the introduction of chloride that gives the opportunity to avoid this precipitation and increase the growth rate to more than 100 micron/hour. In this work we have studied the properties of different 100 and 250 m epitaxial wafers grown specifically for the realization of radiation detectors for different applications (X-Ray, neutrons, high energy particles, …). All the wafers have been grown in collaboration with ASM® in their reactors (PE1O6™, PE1O8™ and PE2O8™) using the same chloride chemistry and processes.

ABSTRACT. Currently SiC crystal is widely used in electric vehicle (EV) related electronic applications. Typically, operational voltages of these power devices are in the range of 0.6-1.5kV, where typically 6µm-15µm epitaxial layers are used. However, to block high voltage (>5kV), much thicker epitaxy (>50µm) is required. Thick SiC epitaxy is extremely challenging due to severe surface degradation by formation of larger morphological and extended defects, as well as various complex dislocations (HLA, BPD pileup, etc.). In this research, we study epitaxy in the range of 60-200µm on 150 mm 4H-SiC wafers in a comparative manner for surface, defectivity, wafer shape, etc.

ABSTRACT. For the success of bipolar SiC high power devices, SiC epitaxial layers need to be free of basal plane dislocations (BPDs) as they source Shockley-type stacking faults in the presence of an electron-hole plasma and cause forward voltage drifts, leading to device failure [1]. Research has been conducted over the years to mitigate the expansion of BPDs propagating from the substrate into the epitaxial device layers [2-5]. While these ex-situ and in-situ processes have been extremely successful, limiting the ~ 200 – 1000 BPD/cm2 in the substrate from penetrating into the epitaxial layers, the issue remains that under high current densities (> 1000 A/cm2), the injected carrier concentration is sufficiently high to expand the BPDs from the substrate into the epitaxial layer, thus becoming device killers [6]. We developed an in-situ growth process that incorporates a H2 etch prior to the growth of the buffer layer to convert BPDs to electrically benign threading edge dislocations, followed by a growth interrupt between the buffer layer and the drift layer, which significantly quenches the buffer layer lifetime, preventing BPDs from expanding into the drift layer during high current densities. Note the drift layer carrier lifetime is not reduced. Using this process, we successfully demonstrated the prevention of BPD expansion at current densities up to 12 kA/cm2 [7]. Here we incorporate the novel growth technique to commercially grown, full 150 mm wafers, and investigate its robustness, demonstrating a lab-to-fab transition, its manufacturability and ultimate impact of the novel defect mitigation process. Two lots of ten – 150 mm epitaxial wafers were grown with a highly doped buffer layer and a 35 µm thick active layer, n-type at 2 x 1015 cm-2. Half of each lot was grown with and without the BPD mitigation process described above. Fig. 1 provides the growth schedule of the BPD mitigation process. X-ray topography was performed on the substrates prior to growth, and ultraviolet photoluminescence (UVPL) was conducted after growth to measure defects in the epilayer. Machine learning was used to determine the densities of BPDs, threading screw/mixed (TSD/TMD) dislocations, inclusions and in-grown stacking faults (IGSF) for each wafer. A third lot with 60 µm epilayers will also be presented. The first lot was fully characterized via UVPL and the average BPD free region (5 x 5 mm2) for both with and without the BPD mitigation process was 77%, meeting our target of 75% BPD free region. Zero BPDs propagated from the substrates to epilayers, rather the BPDs were created during epitaxial growth from downfall related inclusions. Fig. 2 is a UVPL image of the wafer grown using the BPD mitigation growth process with BPD free area of 84%. The first lot of wafers resulted in very low average TSD/TMD densities of 173 cm-2. Inclusions were minimal at 0.3 cm-2 and an average of 84 IGSF per wafer. Fig. 3 shows the BPD and TSD/TMD count and density maps, respectively, for the wafer with the lowest (top) and highest (bottom) defectivity in the lot using the BPD mitigation process. The second lot results will be presented, and preliminary characterization indicate the defectivity is lower along with a tighter range of densities compared to the first lot. Finally, 3.3kV PiN diodes and MOSFETs with current rating up to 50A are being fabricated. These devices will be tested at various current densities including surge conditions to directly evaluate the robustness of the interrupted growth BPD mitigation technique.

[1] J.P. Bergman, et. al., Mater. Sci. Forum Vol. 353-356, 299 (2001). [2] N.A. Mahadik et.al., Mater Sci Forum 858, 233 (2016). [3] R. E. Stahlbush, et. al., Appl. Phys. Lett. 94, 041916 (2009). [4] M. Kato, et. al., Sci. Rep., 12, 18790 (2022). [5] M. Kato, et. al., Japanese J. Appl. Phys., 63, 020804 (2024). [6] N.A. Mahadik, et. al., Appl. Phys. Lett., 100, 042102 (2012). [7] R. Myers-Ward, et. al., “Basal Plane Dislocation Mitigation via Annealing and Growth Interrupts,” ICSCRM, Sept. 20, 2024.

ABSTRACT. Silicon carbide (SiC), a key wide bandgap semiconductor for power electronics and quantum applications, would benefit from a scalable SiC-On-Insulator (SiCOI) platform for integrated nano-photonics [1]. Current methods like mechanical polishing with etching are not scalable. Remote epitaxy (RE) using a 2D material intermediary like graphene [2] offers a potential solution for transferable SiC films (Fig. 1) but faces challenges with SiC's complex polytypes, high growth temperatures, and reactive gas chemistry. This study investigates SiC RE intricacies, utilizing a hot wall CVD system for graphene and SiC growth. Characterization via optical microscopy (OM), Raman spectroscopy, electron backscatter diffraction (EBSD), and transmission electron microscopy (TEM) assessed graphene and SiC layer properties.

RE relies on atomic force penetration through the 2D layer for substrate information transfer [2]. For SiC, this must include stacking information for polytype replication, necessitating a step-flow mechanism rather than island growth common in III-V RE.

Following successful graphene growth on off-axis substrates (Fig. 2a)—a modification from typical on-axis growth—systematic SiC RE experiments (Table 1) commenced. A primary challenge was preserving the graphene layer while enabling SiC epitaxy. Initial tests showed graphene preservation under H2 was limited to 1300 ℃, far below SiC's optimal epitaxy temperature (>1550℃), prompting the use of Ar as the main carrier gas. Subsequent experiments revealed extreme difficulty in this endeavor: high precursor flow rates led to graphitic islands but preserved graphene, whereas extremely low rates removed graphene without SiC growth (Fig. 3a-b). Reducing temperature with moderately low flow rates initiated SiC growth but sacrificed the graphene (Fig. 3c-e). An increased C/Si ratio at the same temperature preserved graphene and initiated SiC growth, but again with surface graphitic islands (Fig. 3f-g). One process, involving a slight temperature increase and high C/Si ratio, initially suggested successful RE with preserved graphene and epitaxial SiC via Raman and EBSD (Fig. 3h). However, crucial TEM analysis revealed the graphene signal originated from graphene formed on top of the SiC, with no SiC/graphene/SiC interface, indicating graphene removal before or during SiC growth. Further investigation into graphene stability showed it could not be preserved at growth temperature with silane in Ar, but could with propane in Ar. Despite this, attempts to preserve graphene by early propane introduction or by adding H2 to Ar (testing ratios of 0.013 and 0.25) failed to yield the desired SiC/graphene/SiC interface, even when Raman or EBSD indicated SiC presence or graphene preservation (Fig. 4).

We conclude that SiC RE, especially on off-axis c-plane substrates, presents unique challenges. Potential solutions include using alternative substrates (e.g., a-plane, where graphene was successfully grown, Fig. 1b), lower growth temperatures with H2, or different precursors like MTS. Current work focuses on low-temperature SiC epitaxy on graphene on a-plane substrates.

ABSTRACT. Solution growth of SiC has been explored for many years, with the aim of producing high-quality single crystals [1,2]. The recent production of a large-diameter 4H-SiC “ingot” obtained by top-seeding solution growth (TSSG) has proved to be a real tour de force and could establish itself as a relevant alternative crystal growth process to physical vapor transport (PVT). However, its implementation is fairly complex due to the difficulties involved in controlling the fluid dynamics at high temperature in order to obtain a stable growth front over the long term [3]. The Travelling Solvent Method (TSM) is an interesting approach to simplifying the process [4–7], but has never been widely developed. An isothermal variant, called ‘metastable solvent epitaxy’, has been proposed by Kaneko et al. [8], but the nature of the driving force in this apparently simplest configuration is still unclear. In this work, we aim to identify the exact nature of the driving force for growth. The experiments were carried out in a high-temperature graphite induction furnace, designed to ensure isothermal conditions in the treatment zone. The samples consisted of a sandwich composed of a single-crystal seed of 4H- or 3C-SiC (top), a polycrystalline wafer of 3C-SiC as a source (bottom) and a piece of molten silicon in between. These stacks were heat treated at 1900°C in argon for 1 hour. A systematic measurement of the growth rate as a function of different parameters have been carried out. The main parameters investigated were i) the nature of the polytype (source and seed substrate), ii) the thickness of the liquid Si solvent film and iii) the microstructure of the polycrystalline SiC source material (grain size, texture and orientation, nature of grain boundaries …). Samples were then observed in cross-section by a combination of Scanning Electron Microscopy (SEM), Electron Back Scattered Diffraction (EBSD) imaging and Raman spectrometry. An example of a 4H-SiC epilayer growth rate as a function of liquid Si solvent thickness, all the other parameters being constant, is given in Fig. 1. The inverse dependence of the growth rate on the thickness of the liquid film demonstrated a purely diffusive transport regime. The polycrystalline source, observed after dissolution, shows that its microstructure is a key factor determining the growth rate (Fig. 2). Using large grains (>10 μm), preferential dissolution is observed along the grain boundaries, without passing through the crystalline twins. Using a polycrystalline source of 3C-SiC with a smaller grain size increases the growth rate by a factor of three when the width of the liquid Si is greater than 80 μm. Using a (100)-oriented 3C-SiC seed gave slightly different results. Firstly, this orientation is prone to facet formation, favoring the development of (111) facets, which makes it more difficult to maintain a stable and smooth interface as in the case of 4H-SiC. Secondly, the microstructure of the polycrystalline 3C-SiC source has a much weaker effect. Overall, we show that at first order, the polytype difference is not the driving force that produces epitaxial layer growth under isothermal conditions. The higher chemical potential at the polycrystalline source comes from the energy of the grain boundaries. In addition to a qualitative discussion, a quantitative determination of the driving force will be carried out, shedding new light on the basic thermodynamics of SiC growth.

ABSTRACT. An accurate energy distribution of interface state density near the valence band edge was obtained for the nitrided SiC/SiO2 interface by the conductance method. In addition, the conductance method revealed that the surface potential fluctuation near the valence band edge is significantly smaller than that near the conduction band edge, which would be one of the reasons for the relatively high mobility in SiC p-channel MOSFETs.

ABSTRACT. SiC MOSFETs fabricated on nonpolar faces such as (11-20) and (1-100) exhibit higher free electron mobility than those fabricated on the polar (0001) face. However, the physical origin of the enhanced mobility and the electron scattering mechanism in nonpolar MOS channels remain unclear. In this study, we investigated the electron scattering mechanism in (0001) and (11-20) MOSFETs through experimental measurements and theoretical calculations of free electron mobility. It was found that the higher free electron mobility in (11-20) MOSFETs is primarily attributed to the reduced Coulomb and surface roughness scattering, resulting from a lower trapped electron density and a weaker electric field near the (11-20) MOS interface.

ABSTRACT. In pursuit of lower on-resistance and higher channel mobility, trench MOSFETs have been developed within the past few years [1-3]. Continuous switching of SiC MOSFETs during their operational lifetime (e.g., ~1011 cycles in automotive applications) leads to threshold voltage shift ΔVth due to bias temperature instability (BTI) and gate switching instability (GSI) phenomena. While the former is well-investigated, the latter presents a more recently reported [4] degradation mechanism primarily driven by the number of the switching cycles [5-6]. In this work, for the first time, we apply charge pumping (CP) to shed light on the underlying physics of GSI in trench SiC MOSFET devices. Vertical trench n-channel MOSFET test structures used in this work (Fig. 1) were fabricated with only one active trench sidewall coinciding with either anti-m, m, anti-a or a crystal plane (the last two trench configurations are, in fact, 4° off from the corresponding crystal plane due to standard 4° miscut of SiC wafers). All measurements were performed at wafer level at room temperature, each device had four contacts: drain at the backside of the wafer, source, gate and a separate p-body contact at the wafer surface at which the CP current is measured. The gate oxide was a deposited 50 nm layer of SiO2 with subsequent NO anneal. We used the following equipment: Cascade microchamber attoguard Summit 11201B manual probe station and parameter analyzer Keithley S4200-SCS equipped with a 4245-PMU card, two 4225-RPMs and a 4200-PA preamplifier. It is important to realize that a vertical n-channel MOSFET is a superposition of a PMOS (the ‘n-epi’ part in Fig. 1, purple crosses) and an NMOS (the ‘channel’ part, Fig. 1, yellow crosses) transistor, each of them giving separate contributions to the overall CP curve (and with ‘epi’ signal showing up at lower Vbase than the ‘channel’ one due to the lower threshold Vth and flatband Vfb voltages for the PMOS). Fig. 2 shows an example of the CP signal at the separate body contact of a device with m trench orientation (f=500 kHz, ΔVa=10 V, duty cycle 50%, trise=tfall=100 ns) in three different measurement configurations: with both source (S) and drain (D) grounded (blue curve), floating S and grounded D (orange line), grounded S and floating D (yellow curve). At ΔVa=10 V, the channel is open, and electrons for recombination can come both from grounded S and D (Fig. 2, blue curve). Floating S does not make a difference for the CP current (the blue and orange curves in Fig. 2 coincide with each other), because the electrons are still supplied from D since the ‘epi’ (PMOS) is open. On the other hand, floating D affects the CP signal, leaving behind only one peak (shown in yellow in Fig. 2) and making the rest of the signal disappear. In this case, electrons for recombination come from S only, revealing that the yellow contribution to the CP signal corresponds only to the ‘channel’ (NMOS) part of the SiC/SiO2 interface. Hence the purple curve in Fig. 2 calculated as the difference between the blue and the yellow ones must come from the defects at the interface between SiC n-epi and SiO2 (PMOS). At low pulse amplitudes (e.g., ΔVa=4 V) and closed channel, the CP signal measured with floating D almost completely vanishes (not shown), confirming our hypothesis that ‘epi’ defects need electrons coming from D for the recombination to happen. Next, we carried out GSI experiments (Vg=−5/+18 V with a switching frequency of 250 kHz for up to 1e11 cycles) to see how this type of stress affects the CP signal. An example of the ultra-fast measurement of ΔVth recovery after a GSI stress is shown in Fig. 3: there, only a quasi-permanent ΔVth is clearly observed, without any visible creation of the new fast states. On the contrary, in CP (f=10 kHz, ΔVa=10 V, duty cycle 50%, trise=tfall=100 ns), the overall CP curves before and after GSI (Fig. 4, solid lines) do not shift to the right, which would prove the presence of the quasi-permanent ΔVth. However, decomposing the CP signal into the ‘channel’ and ‘epi’ parts (as outlined in Fig. 2) shows that the quasi-permanent ΔVth (from Fig. 3) is in fact hidden in the CP signal. Moreover, for Vbase>−6 V, the falling edge of the overall post-GSI CP curve together with its ‘channel’ part is also affected by the creation of acceptor states. Thus, charge pumping clearly highlights two effects taking place during GSI: a quasi-permanent Vth shift (fixed negative charge build-up) along with the creation of new acceptor states at the interface. A more detailed investigation including the effects of GSI stress on different crystal planes (m, anti-m, a, anti-a) will be provided in the full paper.

[1] P. Sharmila, G. Supraja, D. Haripriya et al., Micro and Nanostructures 202, 208126 (2025). [2] R. Siemieniec, D. Peters, R. Esteve, W. Bergner, D. Kück et al., in Proceedings of the 19th European Conference on Power Electronics and Applications (2017). [3] C. Langpoklakpam, A.-C. Liu, K.-H. Chu et al., Crystals 12, 245 (2022). [4] AN2018-09 – Guidelines for CoolSiC™ MOSFET gate drive voltage window, 2019-05-064, Infineon Technologies AG, 2018. [5] M. W. Feil, K. Waschneck, H. Reisinger et al., IEEE Transactions on Electron Devices 71 (7), 4210 (2024). [6] T. Grasser, M. Feil, K. Waschneck et el., IEEE Transactions on Electron Devices 71 (7), 4128 (2024).

ABSTRACT. Silicon carbide (4H-SiC) is among the most prominent semiconducting materials for high-power, high temperature applications. SiC metal-oxide-field effect transistors (MOSFETs) are increasingly utilized in high-frequency switching applications due to their low losses, which enhance efficiency in power electronics. Despite advances in device fabrication, their performance is limited by thermal-oxidation-induced defects near the SiC-SiO2 interface - impacting carrier transport and resulting in high channel resistance. Post-oxidation annealing (POA) in nitric oxide (NO) at high temperatures is reportedly the most effective process to reduce the density of interface states (Dit). However, POA in NO environment also creates hole traps in the oxide [2] and leads to unintentional doping of n-type SiC near the SiC-SiO2 interface. Previous studies have focused on n-type thermal oxidation, but the channel is in fact formed on a p-type doped layer. Thus, understanding the impact of NO annealing for p-type samples is crucial. In this work, we have studied the impact of NO annealing on the near-surface <200 nm region of p-type 4H-SiC by low-energy muon spin-rotation spectroscopy (LE- μSR).

The LE-μSR results provide new insights about the electrical activation resulting from the POA at high temperatures. Further, the carrier concentration is changed not only near the interface, where N concentration should be maximum, but is of the same order as the p-type doping concentration at a depth of approximately 75 nm below the interface - which is likely to impact the channel region in a MOSFET.

In the final contribution, the LE-μSR results will be complimented with Dit and fixed oxide charge measurements at the SiC/SiO2 interface. Technology Computer Aided Design (TCAD) simulations implementing the carrier density profiles extracted by LE-μSR and Dit measurements will be presented to put the experimental results into perspective with the capacitance-voltage output characteristics.

ABSTRACT. As the power density of the latest 4H-silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) increases, a challenge for device designers is to adequately protect the gate oxide during short circuit events to maximise their withstand time. One approach proposed in simulation [1] is the incorporation of ferroelectric dielectric materials such as doped hafnium oxide (HfO2) into the gate oxide. The HfO2/SiO2 gate stack has a Curie temperature [1] below room temperature, meaning that as the temperature rises during a short circuit event, the dielectric constant of the HfO2 layer reduces. This was shown in [1] to reduce the current peak and maximum temperature during a fault imposed on a 1.2kV MOSFET, so extending its withstand time. The aim of this study is to analyse the electrical and material responses of doped-HfO2/SiO2/4H-SiC MOS capacitors (MOSCAPs) at temperatures ranging from 25℃ to 250℃. The investigation has been conducted on 21 fabricated planar MOSCAP chips. On a 4H-SiC epi-wafer with a 10 μm, 1×1016 cm-3 drift region, all MOSCAPS comprised of a 6 nm layer of SiO2, then 30 nm of HfO2 both deposited via ALD, as verified in Fig. 1a and 1b. Si or Al dopants were periodically introduced by depositing a single monolayer between n layers of HfO2. As such the following matrix of processing steps are explored herein: 1) Undoped HfO2 annealed in N2 at 900℃, 1000℃, or 1100℃. 2) Al-doped HfO2 (ratios 1:9, 1:19, or 1:29) annealed in N2 at 900℃, 1000℃, or 1100℃. 3) Si-doped HfO2 (ratios 1:4, 1:9, or 1:24) annealed in N2 at 900℃, 1000℃, or 1100℃. Fig. 2 shows normalised 1 MHz C-V sweeps of a MOSCAP (Al-doped 1:19, annealed at 1100℃ in N₂), all referenced to the 25℃ accumulation capacitance. The accumulation capacitance at +10V decreased by 15% over the temperature range from 25℃ to 250℃, aligning with Landau’s ferroelectric capacitance theory [2]. Fig. 3 shows this data summarised alongside the 1:14 Si doped and 1:29 Al doped samples, showing only the capacitance in accumulation. Fig. 4. Shows SEM images of the surface of an unannealed and an N2 1100℃ annealed HfO2 layer. Grazing incidence X-ray diffraction (GIXRD) results of the Al-doping, Si-doping, or no doping, in Fig. 5., are like that of [3], leading to the monoclinic phase of paraelectric HfO2. This is the ideal crystal phase for decreasing the HfO2 dielectric constant. The measured capacitance is normalised, and the temperature-dependent decline is used to extract an empirical model for the SiO₂ dielectric constant shown in Fig. 6. This model is implemented in TCAD for a 750 V double-trench (DT) MOSFET with a 50 nm gate oxide and short-circuit withstand time (SCWT) of 11 μs, first simulated in [4]. Fig. 7 shows a simulated 13 μs SC pulse with and without the temperature-dependent dielectric. The standard oxide fails to turn off safely, while the ferroelectric-like dielectric reduces peak current [4] and enables safe turn-off. The lower saturation current, due to reduced gate capacitance, results in less self-heating and longer SCWT by 2 μs as shown in Fig. 8. For the final submission, a full set of electrical reliability data for all the doped gate-stack MOSCAP chips will be further analysed – including density of interface traps (Dit) at 25℃, flatband voltage and hysteresis data at varying chuck temperatures. Results obtained from material analysis techniques, such as GIXRD, will be used to investigate correlations between HfO₂ crystallisation phases in the gate stack, against changes in accumulation capacitance, and all electrical reliability data.

ABSTRACT. Interface nitridation with nitric oxide (NO) is widely used to improve the channel mobility in 4H-SiC MOSFETs. Moreover, other nitridation methods using nitrogen-containing plasma also successfully reduce the SiC/SiO2 interface states. However, the mechanism of interface/surface passivation is still unclear. In this study, we investigated effects of nitrogen-plasma treatment on the SiC surface. It was revealed that nitrogen-plasma treatment effectively introduces nitrogen atoms into SiC and forms Si-N bonds at the surface, but the treatment itself causes generation of various point defects.

ABSTRACT. Silicon carbide (SiC) is a wide gap semiconductor that is being rapidly adopted in power electronic applications due to its high critical electric field, high thermal conductivity, the availability of high-quality large area substrates, and maturing fabrication technology. However, SiC MOSFETs exhibit poor performance due to a high density of interface states, leading to low channel mobility (<5% of bulk mobility). To mitigate this, various studies have explored using deposited gate oxide processes such as ALD [1], CVD Si [2, 3], PECVD [4, 5] to avoid thermal decomposition of the substrate. In this study, we use Applied Materials™ Centura™ DPN (Decoupled Plasma Nitridation) in conjunction with Applied Materials™ Picosun™ P300B ALD to form SiO2-based gate oxide. DPN is a remote plasma process, capable of directly nitriding the SiC surface within a few tens of seconds, and is therefore particularly suitable for high-volume manufacturing. Optimization of the DPN parameters allows the introduction of a tunable concentration of [N] – as high as ~1.5E21/cm3 – sharply at the interface SiC/SiO2, making the traditionally hours-long and expensive NO or N2O post-deposition nitridation process unnecessary. The MOSFETs formed by this process show a 1.5X enhancement in the peak channel mobility compared to standard MOSFETs prepared by thermal oxidation and NO annealing. The MOSFET templates consist of an n-type 4H-SiC substrate with a 9.0E15 cm-3 n-type epilayer with ion implanted p-body regions having a surface Al concentration of 1.6E16 cm⁻3. The source and drain regions consist of highly doped n+ regions implanted with nitrogen. Before forming the gate oxide, the substrates were first RCA cleaned and subjected to H2 etching in a hot walled CVD furnace (1300°C, 900 mbar, 10 slm H2) for 6 min. During the final 3 minutes of this anneal, a 5% SiH4/H2 mixture was added at a flow rate of 100 sccm. This last silane step was critical to minimize and passivate the interface defects [3, 4]. Subsequently the samples were subjected to the DPN process with a N2 remote plasma to incorporate nitrogen on the SiC surface, which is critical to achieving a NO-free process. Silicon dioxide was then deposited with an Applied Picosun P300B ALD system, and densified by annealing in a N2 ambient at 1200°C for 30 min. The final MOSFETs were formed with doped polysilicon gates, annealed Ni source / drain contacts, and Al top metal pads for electrical measurements. The gate oxide thickness was about 48 nm, while the channel length and width were 140 μm and 110 μm respectively. The transfer characteristics of a typical MOSFET fabricated in this manner are shown in Fig 1a. The device shows a sharp increase in drain current with a positive threshold voltage (Vth ~ 1 V) in comparison to the control sample (thermally grown NO annealed device with tox = 50 nm). The field effect mobility (Fig. 1b) of a SiH4 & DPN® treated device shows a significant improvement (~38 cm2 /Vs) as compared to thermal oxide+NO annealed control sample (~25 cm2/Vs). This increase in mobility (~ 1.5X), lower threshold voltage, and sharper turn-on characteristics can be attributed to a reduction of the interface state density. Finally, the high frequency CV (100 kHz / dark conditions) characteristics are shown for the SiH4 & DPN treated ALD MOSCAPs (Fig 2a). The CV data shows minimal hysteresis, and the overall shift of the curve towards lower voltages in comparison thermal oxide+NO anneal control sample signifies a reduction in negative interface charges (interface + fixed charge), which is consistent with the higher mobility in noted in Fig 1b. Finally, a transmission electron microscopy (TEM) crosss-section image and EELS map across the interface is shown in Fig 2b. The image shows N2 is preferentially incorporated at the interface during the DPN treatment. In summary, we have demonstrated a gate oxide process that reduces the interface defect density to yield a 1.5X improvement in peak channel mobility while maintaining a small positive threshold voltage. The effectiveness of the DPN process in nitriding the SiC surface in a very short time enables a high-throughput fabrication process, and is therefore particularly suitable for high-volume-manufacturing of SiC devices. The authors would like to thank support from the Margot A. and Carl J. Johnson Foundation for financial support. This work was done in part at the Birck Nanotechnology Center, Purdue University. We also acknowledge the assistance from Clas-SiC Wafer Fab.

[1] R. Ramamurthy et. al., IEEE 5th WiPDA, pp 242-245 (2017) [2] T. Kobayashi et. al., Appl. Phys. Express, vol. 13, pp 091003 (2020) [3] K. Ramadoss et. al., ICSCRM (2024) [4] K. Tachiki et. al., Appl. Phys. Express, vol. 14, pp 031001 (2021) [5] M. Yakut et. al., Solid State Phenomena, vol. 359, pp 157-162 (2024)

ABSTRACT. To ensure continuous improvement of SiC power MOSFET performance in a massively growing market, innovative approaches for further RDS,on×A reduction are required. Among the potential design elements to reduce the FET’s resistivity, MOS channel engineering remains a foremost pathway. Up to now, pushing the defect density at the SiO2/4H-SiC transition towards a more ideal interface is still a major obstacle. In the recent years, deposited SiO2 gate dielectrics were increasingly studied by the community to substitute thermal oxides for SiC MOSFET applications. Along with that, process development for surface pretreatment before the gate insulator deposition gained growing scientific interest. Especially H2-based high-temperature surface conditioning revealed a remarkable increase in channel mobility, while the underlying physical mechanisms are still under investigation [1]. Furthermore, an additional annealing in N2 atmosphere was shown to create an ultrathin, dangling-bond free silicon oxynitride film on the 4H-SiC (0001) surface in a self-limiting manner [2], which potentially serves as an ideal starting point for subsequent SiO2 deposition. However, according to our knowledge, the potential of such a process has not been published yet on SiC MOSFET devices. In this work, we study the impact of high-temperature H2- and N2-based surface conditioning processes on the channel properties of lateral 4H-SiC MOSFETs. The schematic device as well as the detailed fabrication flow of the investigated gate formation are shown in Fig. 1. Except the respective pretreatment, all wafers underwent the same manufacturing sequence. Fig. 2 a) and b) show the transfer characteristics of seven exemplary MOSFET devices per wafer on a linear and logarithmic scale at room temperature. As compared to the reference wafer (SiO2), especially the wafers processed with N2-containing pretreatments (N2-SiO2, H2/N2-SiO2) reveal a significant increase in curve steepness as well as a reduced sub-threshold hysteresis. Similar measurements were conducted up to 175 °C to extract the field-effect mobility µFE values over a broad temperature range (Fig. 2 c)). When comparing all four wafers, two groups with a different temperature coefficient (TC) of µFE are elucidated. The wafers with N2-containing pretreatments exhibit a more than two times improved µFE at room temperature with gradually µFE decrease with increasing temperature. This behavior is in contrast to the SiO2 and H2-SiO2 wafers and can be attributed to a significantly diminished defect density at the SiO2/4H-SiC interface by N2. Consequently, the µFE trend takes over the negative TC of phonon scattering instead of the positive TC of Coulomb scattering. Similar behavior is typically only reported on non-polar surfaces like (11-20) or (0-33-8), where the interface quality is inherently much better [1,3]. Interestingly, in our experiments, the H2 pretreatment (H2-SiO2) shows just minor improvements of channel properties. To study whether the thermal pretreatment processes impact the breakdown behavior of the SiO2 gate dielectrics, time-zero (TZDB) and time-dependent dielectric breakdown (TDDB) measurements were performed. Again, the N2-SiO2 and H2/N2-SiO2 wafers show a slightly different behavior in Fig. 3 a) with an earlier increase of the Fowler-Nordheim (FN) tunneling current and a slightly different curve shape. Despite the significantly higher FN current at the chosen electric field stress, the TDDB measurements in Fig. 3 b) result in similar dielectric lifetimes when comparing the SiO2 reference with the N2-SiO2 wafer. Overall, the electrical results show a distinct difference when having N2 in the annealing atmosphere. To better understand the physical mechanisms of the investigated surface treatments, XPS analysis was carried out on additional, bare 4H-SiC wafers, which underwent the same annealing processes. As depicted in Fig. 3 c), all annealing processes decrease the C concentration on the surface by forming oxides and oxynitrides. Especially the oxynitrides, formed by N2-containing surface conditioning, lead to superior MOSFET performance while maintaining the transistor’s reliability. Our experimental results are in excellent agreement with the published theoretical predictions regarding epitaxial oxynitride film formation by N2-containing surface treatment of 4H-SiC [2].

[1] K. Mikami et al., IEEE Transactions on Electron Devices 71 (1), 931-934 (2024). [2] H. Tochihara and T. Shirasawa, Progress in Surface Science 86 (11-12), 295-327 (2011). [3] T. Hiyoshi et al., Materials Science Forum. 740-742, 506-509 (2013).

ABSTRACT. 4H-silicon carbide (SiC) has emerged as a leading semiconductor material for power electronics, given its remarkable properties, which include a wide bandgap (~3.26 eV), high critical breakdown electric field (~3 MV/cm), and superior thermal conductivity. Despite these advantages, the further uptake of SiC MOSFETs is hampered by a high density of interface states (DIT) at the SiO2/SiC interface, particularly near the conduction band edge [1-2]. These interface states primarily arise from residual carbon clusters, silicon suboxide phases, and unpassivated dangling bonds formed during conventional thermal oxidation processes [3-4], leading to charge trapping and reduced electron mobility, thus limiting device reliability and efficiency [1-2]. To address these limitations, alternative dielectric deposition techniques such as chemical vapour deposition (CVD) and atomic layer deposition (ALD) have been explored. ALD offers excellent control over dielectric thickness, uniformity, and composition. Post-deposition annealing (PDA) processes are often employed to further enhance dielectric quality and effectively reduce interface trap densities, demonstrating significant improvements in electrical performance and reliability [2, 5]. Prior studies indicate that nitrogen and hydrogen plasma treatments effectively reduce interface trap densities and enhance channel mobility through nitrogen incorporation without additional oxidation and by passivating interface states, respectively [6-7]. In this study, the effects of hydrogen (H2), nitrogen (N2), and mixtures of these gases in plasma pretreatments applied to SiC surfaces prior to SiO2 deposition were systematically investigated, all performed within the same ALD chamber. Plasma pretreatment conditions varied across pure N₂, 25% H2, 50% H₂, 75% H2, and pure H2 (100%). Following deposition, samples underwent PDA at 1100°C in either pure nitrogen or forming gas (FG) to further passivate interface defects, as shown in [5]. A control group, fabricated without plasma treatment and subjected only to PDA, was included for comparison. A summary of the fabrication matrix is listed in Table 1. SiC metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated using standard lithography, sputtering, and metal lift-off techniques to pattern Al dots on the oxide layers. Figure 1 illustrates the fabrication process. Electrical characterisation, including capacitance–voltage (C–V) and current–voltage (I–V) measurements, was performed to evaluate improvements in interface quality and stability. The combined effects of plasma pretreatment and PDA are shown to enhance key performance indicators such as interface state density, flatband voltage, and dielectric strength, with plasma-treated samples demonstrating significant improvement over the control. These findings highlight the potential of in-situ plasma treatment as an effective surface conditioning method to improve the quality and reliability of SiO2/SiC interfaces. Further results on channel mobility extracted from lateral MOSFET structures will be discussed in the full paper.

[1] P. Fiorenza, F. Giannazzo, and F. Roccaforte, “Characterization of SiO2/4H-SiC interfaces in 4H-SiC MOSFETs: A review,” 2019, MDPI AG. doi: 10.3390/en12122310. [2] T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology. Wiley, 2014. doi: 10.1002/9781118313534. [3] K. Zekentes and K. Vasilevskiy, “Advancing Silicon Carbide Electronics Technology II Core Technologies of Silicon Carbide Device Processing,” 2020. [Online]. Available: http://www.mrforum.com [4] S. T. Pantelides et al., “Si/SiO2 and SiC/SiO2 Interfaces for MOSFETs – Challenges and Advances,” Materials Science Forum, vol. 527–529, pp. 935–948, Oct. 2006, doi: 10.4028/www.scientific.net/msf.527-529.935. [5] A. B. Renz et al., “Development of high-quality gate oxide on 4H-SiC using atomic layer deposition,” in Materials Science Forum, Trans Tech Publications Ltd, 2020, pp. 547–553. doi: 10.4028/www.scientific.net/MSF.1004.547. [6] H. Yoshioka, M. Yamazaki, and S. Harada, “Reduction of interface states by hydrogen treatment at the aluminum oxide/4H-SiC Si-face interface,” AIP Adv, vol. 6, no. 10, Oct. 2016, doi: 10.1063/1.4966041. [7] X. Zhu et al., “The effect of nitrogen plasma anneals on interface trap density and channel mobility for 4H-SiC MOS devices,” Solid State Electron, vol. 57, no. 1, pp. 76–79, Mar. 2011, doi: 10.1016/j.sse.2010.12.002.

ABSTRACT. As previously reported, high-temperature annealing under very low oxygen partial pressure (Po2) leads to the precipitation of carbon-related defects, including C–C bonds, which is detectable by attenuated total reflection Fourier-transform infrared spectroscopy (ATR-FTIR). These defects are almost completely suppressed by introducing a slight amount of oxygen (Po2 ≈ a few Pa), indicating their instability under high-Po2 conditions. However, it is well known that interface traps in SiC MOS structures are mainly caused by defects formed as byproducts of thermal oxidation under high-Po2 conditions. To elucidate their connection, we performed Ar annealing after thermal oxidation and found that prior oxidation significantly enhances C–C defect formation during subsequent Ar annealing. Furthermore, this anomalous enhancement was effectively suppressed by introducing hydrogen annealing after oxidation.

ABSTRACT. Silicon carbide (SiC) vertical power MOSFETs offer efficient switching, thanks to their wide-band gap leading to lower on-resistance at a similar operating voltage as compared to their silicon counterparts. Therefore, ensuring excellent reliability has become a primary focus for SiC-based devices. Although gate oxide intrinsic reliability has shown great improvements over the years, there has not been much discussion about extrinsic reliability until recently. This paper addresses gate oxide reliability across all three phases of the bathtub curve. It also demonstrates enhanced gate oxide reliability obtained through highly optimized screening in both 150 mm and 200 mm wafer fabrication/process technologies.

ABSTRACT. In SiC MOSFETs, threshold voltage drift occurs under bipolar AC gate switching, where the MOSFET repeatedly switches between accumulation and inversion states. To explain the mechanism of this phenomenon, the photon-assisted electron injection model is proposed, in which photons generated by electron-hole recombination at traps near the SiC/SiO2 interface under bipolar AC gate voltage excite channel electrons and inject them into SiO2. To verify the mechanism, luminescence was observed from the chip backside under various conditions. By varying the negative gate-off voltage, temperature, and duty ratio, we found that the luminescence intensity above 2.7 eV - which exceeds the conduction band offset - showed a positive correlation with the threshold voltage drift. Furthermore, irradiating the inversion layer with higher-energy monochromatic light increased the quantum yield of the gate leakage current. These results support the photon-assisted electron injection model.

ABSTRACT. The results of a high-voltage reliability study for a 3.3kV high-k (HK) SiC MOSFET are reported. Performed tests are High Temperature Reverse Bias (HTRB), High Voltage-High Temperature-High Humidity Reverse Bias (HV-H3TRB). We compare the Hitachi Energy 3.3kV HK SiC device versus a commercial 3.3kV SiC device, with SiO2 as gate dielectric, showing the superior performances of the HK device. Differences are found in blocking behavior, in subthreshold slope and in gate current after both stress tests. Through a post-stress test characterization, we attribute this difference to the contribution of different aging mechanisms occurring during HV stress tests. Finally, robustness against Single Event Burnout (SEB) is demonstrated through a validated cosmic ray test setup, where DUTs are irradiated with high-energy protons.

ABSTRACT. The pursuit of higher system efficiency and power density in power electronics paves the way for increased use of wide bandgap semiconductor devices such as silicon carbide MOSFETs, due to their lower conduction and switching losses compared to silicon. To ensure robust operation in electric drives and traction inverters, SiC MOSFETs are switched bipolarly to prevent parasitic turn-on. Recently, it has been shown that bias temperature instability and gate-switching instability in bipolar-switched applications must be considered a reliability concern for SiC MOSFETs. While gate-switching stress tests usually focus on critically damped conditions regardless of rise and fall times, real-world applications may involve overshoots and a wide range of gate-voltage slopes depending on the converter design. It is shown that the peak voltage, even if applied for only a few nanoseconds, has a dominating influence on gate switching instability. Furthermore, it is shown that higher gate-voltage slopes lead to higher gate switching instability, but are not a dominating factor.

ABSTRACT. 4H-SiC is recognized as one of the most suitable semiconductor materials for high-power and highfrequency devices due to its superior physical properties. Among all 4H-SiC-based devices, insulated gate bipolar transistors (IGBTs) are desirable for the ultra-high-voltage/current application [1]. In principle, nchannel IGBTs are preferred over p-channel IGBTs due to faster switching speed, but the development of the former is hampered due to the lack of high-quality P-type SiC substrates with low resistivity [2]. As a promising method to produce high-quality P-type SiC crystals, the solution growth has been studied over decades and substrates with 1.7 inches in diameter have been exhibited [3, 4]. However, challenges such as polycrystals, cracking, solvent inclusions, and doping uniformity still hinder the further development of larger-sized P-type substrates fabricated from solution growth. In this study, we present a novel configuration of the growth system which can greatly decrease the radial temperature gradient on the growth front and avoid local cracking due to large thermal stress. Consequently, 6-inch P-type 4H-SiC substrates with high crystal quality and low resistivity are fabricated and characterized, for the first time as far as we know. A traditional SiC solution growth system is presented on the left side in Fig. 1 (a), where the graphite crucible plays the roles both as carbon source and heat source inducted by the coil. To grow larger scale crystal, the diameter of the crucible has to be correspondingly increased, which makes it more difficult for the inducted heat on the graphite wall to be transported to the center. As a result, larger diameter crystals have more defects and are more easily to crack due to larger radial temperature gradient. To solve this issue, we propose an improved structure with a circular arc-shaped radiation shield (shown in Fig. 1 (a) right), the circle center of which locates at the junction of the shaft and seed holder. This shield can reflect the radiation from any direction to the center of the seed holder, compensating for the low local temperature. Compared with the original structure, the improved case shows very uniform temperature distribution and the radial temperature gradient is more than one magnitude lower (Fig. 1 (b)). Based on the improved thermal field, the 6-inch P-type substrates are successfully fabricated (Fig. 2 (a)). The substrates show a deep blue color under the strong white light, representing a heavy doping of Al. The corresponding resistivity is shown in Fig. 2 (b), with the average of 123 mΩ·cm and uniformity of ~4%, which is the lowest value of P-type SiC substrates to the best of our knowledge [5]. Besides the electrical property, the substrates also show good crystallinity with 4H polytype area of 100% and average full width at half maximum of ~16 arc sec. Moreover, owing to the merit of solution growth [6], very large amount of threading screw dislocations (TSDs) are converted into basal plane. Beyond our expectation, most of the macrosteps achieving TSD conversion are lower than 1 um, lower than the required minimum step height (~3 um) reported in literatures [7]. As a result, the TSD density measured by X-ray Topography (XRT) is only 12 cm-2, more than one magnitude lower than that of the current commercial N-type substrates.

ABSTRACT. Top-Seeded Solution Growth (TSSG) method is promising for growing high-quality, large-size bulk silicon carbide (SiC) crystals and is being applied in mass production. The main advantages of solution growth are defect reduction by TSD (threading screw dislocation) conversion and larger diameter growth [1, 2] under controllable step growth. Experimental and numerical studies have validated that, the solution flow direction antiparallel to the step flow direction [3, 4] is favorable to stabilize step growth. According to the axisymmetric hot-zone of TSSG-Si furnace, the switching flow, characterized by periodic transitions between inward and outward flow under the seed crystal, is a compromise method to improve crystal morphology. However, the unidirectional solution flow antiparallel to the step flow is supposed to be the ideal growth condition for high growth rate and defect-free SiC crystal. Although axisymmetric 2D simulation is the standard method for optimizing hot-zone and process parameters, it constrains the scope of optimal thermal field designs and reasonable flow control. It is particularly challenging to realize the unidirectional solution flow design using only rotations of the crucible and seed crystal due to the singularity in rotational center and the asymmetric step flow direction. Conversely, 3D modeling of SiC solution growth has the potential to offer insights into asymmetric seed crystal settings and unidirectional solution flow. We present the 3D modeling results for our TSSG-Si growth, and specially designed asymmetric hot-zone designs for the realization of unidirectional solution flow. First, 3D global simulations for the conventional axisymmetric hot-zone [Fig.1 (a)] were conducted for the inward and outward flow conditions. The results of the inward flow simulation revealed axisymmetric temperature and flow structures, a consequence of the crucible rotation effect. However, the suppression caused by the rotation of the crucible led to the dominance of circular flow over the solution flow, resulting in high but inhomogeneous growth rate, as shown in Fig. 1 (b). Conversely, for outward flow, the circumferential flow generated by crystal rotation affected only a limited region. Consequently, the carbon in solution exhibited full mixing, as indicated by a lower but homogenous growth rate, as shown in Fig. 1 (c). Second, we proposed the multi-seed design with four off-axis seeds and fast crucible rotation. The off-axis seeds could not only experience the unidirectional solution flow due to the fast crucible rotation [Fig. 2(a)], but also reduce the growing cost by the higher yield. Third, we invented the solution growth with horizontal coil for the active flow control by Lorentz force. In this configuration, the SiC ingot could be grown under unidirectional solution flow without the rotations of crucible and seed [Fig. 2 (b)], which simplified the TSSG-SiC growth. The TSSG-SiC process is characterized by the unidirectional step-flow growth and the convection-dominated carbon transport. The crucible rotation and Lorentz force could be suitable driving forces to realize the unidirectional solution flow antiparallel to the step flow in an active and efficient manner. The presented asymmetric results and insights must be derived from 3D modeling of solution growth. For this developing process, we must think outside the box of the vertical axis-symmetric growth, and achieve the cost-effective mass production of TSSG-SiC crystal by 3D asymmetric modeling.

ABSTRACT. Reduction of basal plane dislocations (BPDs) of SiC substrates that cause forward-current degradation in bipolar devices or MOSFETs [1] is crucial for advancing the reliability of SiC devices. Although 8-inch substrates have entered the SiC substrate market, their high BPD densities compared to those of 6-inch substrates hinder widespread adoption. To date, we have developed a novel method to grow 6-inch 4H-SiC crystals with low BPD densities using our ceramic processing technology [2-3]. In this study, we have applied this crystal growth method to 8-inch SiC substrates and evaluated their material properties. Fig. 1 shows a schematic of our crystal growth process. SiC powder mixed with additives that form a liquid phase upon heating and facilitate crystal growth, along with an 8-inch SiC substrate (seed crystal), are placed in a graphite crucible. The crucibles are subjected to heat treatment at temperatures exceeding 2000 °C in a mixed argon-nitrogen atmosphere, utilizing a furnace equipped with graphite heaters. Through this process, 4H-SiC single crystals with a thickness of ~100 – 200 μm are grown onto the seed crystals. A large benefit of this process is its capacity to handle multiple substrates simultaneously, resulting in enhanced productivity and reduced costs. To estimate the global BPD density of 8-inch substrates, X-ray topography (XRT) was performed on the seed crystals and grown crystals. The XRT images were divided into a 10 mm × 10 mm grid, and the BPD densities at each grid were calculated and mapped by image processing software. As shown in Fig. 2 (a) and (b), BPD densities in the grown crystal are lower than those in the seed crystal over the whole substrate area. To compare the BPD densities and BPD reduction rates between 6-inch and 8-inch substrates, their values are summarized in Table Ⅰ. The data for the 6-inch samples represent typical values obtained in our previous experiments. Despite the high BPD densities in the seed crystals of the 8-inch substrates compared to those of the 6-inch substrates, the BPD reduction rate was not markedly different. To further understand the behavior of BPDs, the sectional XRT images were obtained as shown in Fig. 3 (a)-(c). The string-like contrasts that represent BPDs gradually decreased as the crystal growth proceeded. We have already observed similar behavior in 6-inch substrates [3], suggesting that the reduction behavior of BPDs is consistent between 6-inch and 8-inch substrates. The typical properties of 8-inch SiC substrates (seed crystals) and grown crystals are summarized in Table Ⅱ. The grown crystals have low BPD densities while maintaining the seed crystals’ polytype, off-angle, and resistivity. These results indicate that our crystal growth method has a potential to contribute to expanding the use of 8-inch substrates with relatively high BPD densities, eventually leading to a reduction in the total cost of devices.

ABSTRACT. Photoelectrical detection of magnetic resonance (PDMR) is a promising method for spin readout of defects in the device-compatible material SiC. So far, it has only been demonstrated for nitrogen-vacancy centers in diamond and silicon vacancies in 4H-SiC. In this study, we demonstrate room-temperature PDMR of an ensemble of divacancy-related defects in 4H-SiC. We compare PDMR with conventional optically detected magnetic resonance and further investigate the spin structure of these defects using coherent PDMR techniques.

ABSTRACT. The neutral axial (hh) divacancy defect (PL1) in 4H-silicon carbide (SiC) is one of the most prominent candidates for functioning as room-temperature quantum bits (qubits) with near-telecommunication-wavelength emission. Nonetheless, the pivotal role of electron-phonon coupling in the spin-polarization loop remains unrevealed. In this work, we theoretically investigate the microscopic magneto-optical properties and spin-dependent optical loops utilizing first-principles calculations. First, we quantitatively demonstrate the electronic level structure, assisted by symmetry analysis. Moreover, the fine interactions, including spin-orbit coupling (SOC) and zero field splitting (ZFS), are fully characterized to provide versatile qubit functional parameters. Subsequently, we explore the electron-phonon coupling, encompassing dynamics and pseudo-Jahn-Teller (DJT and PJT) effects in the intersystem crossing (ISC) transition. To quantify these features, the Vienna Ab initio Simulation Package (vasp 5.4.1) code in the framework of density functional theory (DFT) with the Heyd-Scuzeria-Ernzerhof (HSE) hybrid functional was employed for implementing all atomistic simulations. A PL1 center was embedded in a 576-atom 4H-SiC supercell (6×6×2) with a gamma-point sampling of the Brillouin zone. The cutoff energy was set as 420 eV. The atomic configurations were relaxed with the total energy and force thresholds of 1E-4 eV and 0.01 eV/A. The excited states were determined using the delta-SCF method. Finally, the projector-augmented-wave method implemented by Martijn Marsman and the noncollinear approach were employed for the ZFS and SOC calculations, respectively. After having the basic magneto-optical quantities in our hand, we analyze the photoluminescence lifetime based on the major transition rates in the optical spin-polarization loop. We detail the threshold of the optically detected magnetic resonance (ODMR) contrast C=(τ_±-τ_0)/τ_0 =(r_0-r_±)/r_±, where the τ0 (τ±) is the optical lifetime of the with ms = 0 (± 1), and r0 (r±) is the corresponding transition rate from the excited state with ms = 0 (± 1), following the relationship of τ0 (τ±) = 1/r0 (r±). In this work, we consider the ideal case and assume that there is only a non-radiative ISC transition from the with ms = ± 1 to the singlet state, i.e., r± = r0 + r_ISC. The final low-temperature contrast agrees well with the experimental data of about -10% which is naturally a smaller absolute value due to imperfections in the experiments that is not covered by our theory. We further demonstrate that strain is an effective control parameter for significantly enhancing readout contrast. By a comprehensively considering the strain effect on both the radiative transition (parameters including ZPL, transition dipole moment) and the ISC transition (parameters including transverse SOC, energy gap between the triplet excited state and singlet ground state), we find that the axial strain (zz) without distorting the geometry and while maintaining total symmetry, can dramatically modulate the ODMR contrast. When a compressive strain reaches -2%, the contrast will increase by 59% from the zero-strain case. This demonstration will benefit further optimization of qubit operation.

ABSTRACT. 4H-silicon carbide (SiC) has recently emerged as a promising platform to host point defects with possible applications in quantum technologies, such as distributed quantum computing or sensing. Two well-studied color centers in 4H-SiC are the silicon vacancy (VSi) and divacancies (PL1-4 centers). Those color centers have already shown to comprise desirable properties in this regard, such as nearly- lifetime-limited optical linewidths, photon indistinguishability and spin coherence times on the order of ms at cryogenic temperatures [1]. However, the typically detected spin signal contrast of those color centers under off-resonant laser excitation is less than 5 % while the count rates are quite low with ∼ 15 kilo counts per second (kcps) in unstructured bulk samples for the VSi & ~ 30 kcps for the PL1-4 centers [2]. High contrast spin readout based on resonant laser excitation is only possible at cryogenic temperatures below 20 K. This limits their applications in fields of quantum sensing where a high spin contrast as well as a high photon count rate is required. Recently, modified divacancies (PL5-7 centers) have drawn considerable attention with a high readout contrast of about 30% and a high photon count rate at room temperature [3], making them competitive with the nitrogen-vacancy centers in diamond [4] and suitable for applications in magnetic field sensing at room temperature, but in the industry compatible platform SiC. Nevertheless, as the defects are relatively new, their theoretical properties are unexplored, and their production is not yet deterministically possible. Lately, there have been some attempts to explain the origin of the PL5 and PL6 centers. The original idea that these centers are divacancies near stacking faults has shifted towards that these color centers are a divacancy with nearby carbon antisites [5,6]. Here, we report on recent updates of our work including the generation of single PL6 centers through ion irradiation and subsequent high temperature annealing, the investigation of their spin properties via optically detected magnetic resonance (ODMR) and pulsed measurements at room temperature (Fig 1, [7]). In the process, we consider both the properties of the ground state and the excited state to further gain knowledge about those color centers. We demonstrate the coupling of a single PL6 center to a nearby nuclear spin and a high degree of control over it with a fidelity of ~ 90 %, relevant for the use of nuclear spins as quantum memory [7]. Finally, we show the first attempts how these defects can be implemented into nanostructures to optimize the photon collection efficiency (Fig. 2). [1]: Babin, C. et al., Nat. Mater. 21, 67-73 (2022) [2]: Chen, Y.-C. et al., Nano Letters19 (4), 2377-2383 (2019) [3]: Li, Q. et al., Natl. Sci. Rev. 9, nwab122 (2022) [4]: Jelezko, F., Wrachtrup, J., Phys. Stat. Solidi. A 13, 3207 – 3225 (2006) [5]: Zhao, X. et al., arXiv:2503.14170 (2025) [6]: Chen, Y. et al., arXiv:2504.07558 (2025) [7]: R. Wörnle et al., In preparation (2025)

ABSTRACT. Silicon carbide’s exceptional physical and electronic properties drive its broad applications ranging from high-power electronics to emerging quantum sensing technologies [1]. All-electrical SiC magnetometers exploit near-zero-field magnetoresistance (NZFMR), a quantum phenomenon in which minute magnetic fields influence spin-dependent recombination currents via spin-correlation mechanisms in a diode [2]. While opening new sensing possibilities, such as magnetometry up to 500 °C [3], solid-state SiC magnetometers need to have a high sensitivity to realize their full potential. Currently, state-of-the-art all-electric devices have a sensitivity of 440 nT/√Hz [4], which can be improved to 30 nT/√Hz with above-bandgap optical pumping [5]. In this work, we propose to boost NZFMR sensitivity in SiC diodes by irradiating commercially available (COTS) SiC devices to increase the spin-center density, avoiding the cost, hazards, and supply constraints associated with isotopic purification based on silane gas, and thereby offering a scalable, deployment-ready solution. Fig. 1 depicts the NZFMR signal from a COTS SiC JFET measured with an in-house lock-in amplification setup [3]. Static field offsets of -0.3, 0, and +0.3 mT translate the NZFMR peak-dip feature laterally, providing a correspondence between magnetic bias and electrical response. This demonstrates that COTS SiC electronics can operate as quantum-enabled magnetometers. The minimum detectable field [eta] was estimated using the relation [eta] = [sqrt{S_I}/G] , where S_I is current noise power spectral density and G expresses the device’s responsivity. While forward biasing the SiC JFET at voltage of 2.4 V, we recorded over 2000 concatenated external magnetic field ramps and then subtracted the mean waveform to isolate stochastic dark-current fluctuations. We then computed the single-sided power spectral density via a normalized FFT, which contains a 1/f noise region below 0.01 Hz followed by a 27.6 pA/√Hz white-noise plateau that abruptly rolls off above 1.6 Hz due to the low-pass filter setting used for the lock-in, as shown in Fig. 2. The peaks appearing at 0.1 Hz harmonics reflects residual periodic components from the 10s field ramp. By analyzing the experimental NZFMR line-shape of Fig. 3, we extrapolated a small-signal responsivity of approximately 20 nA/mT, which sets the sensitivity of the investigated COTS device to 1.35 µT/√Hz. This value, indicated by a black circle in Fig. 4, sets the baseline of our irradiation analysis. Fig. 4 displays the COTS SiC JFET sensitivity by increasing the spin-center density . To generate this projection, we solved a master equation for the SiC defect manifold, producing . Using the derivative and an SRD recombination current model, we extrapolated the defect density by fitting the NZFMR signal (see Fig. 3). Our model predicts a monotonic improvement, i.e. [eta] \prop [rho]^-1(see Fig. 4, red line). Raising to [rho] to \approx 10^13 cm3 – readily achievable with moderate ion implantation dosages and fluences, currently under investigation – could drive the baseline below 10 nT/√Hz. Preliminary results corroborate defect formation through irradiation. The SEM image in Fig. 4 shows formation of dark vacancy clusters in a COTS SiC JFET after being irradiated by a 30 keV Ga+ beam (9.3 nA, 5 min), grounding the base for our ongoing characterization. Our results trace a fabrication-compatible roadmap from the raw µT/√Hz baseline of an off-the-shelf diode to sub-nT/√Hz performance, suggesting that spin defect engineering—not optics or isotopically purified material—offers an attractive approach to boosting spin-defect quantum magnetometry in SiC devices. This work is supported by NASA contract number 80NSSC23CA145. We acknowledge helpful conversations with M. E. Flatté, P. M. Lenahan, and C. Cochrane. [1] M. Bakowski, IEEJ Trans. Ind. Appl. 126.4 (2006); F. W. Koehl, et al, Nature 479, 84-87 (2011). [2] C. J. Cochrane and P. M. Lenahan. J. Appl. Phys. 112 (2012) & Appl. Phys. Lett. 103 (2013). [3] F. Sgrignuoli, et al. arXiv:2411.15196 (2024), submitted to ICSCRM 24 proceeding. [4] C. J. Cochrane et al. Sci. Rep 6, 37077, (2016). [5] Lew, CT-K., et al. Appl. Phys. Lett. 122 (2023).

ABSTRACT. High-resolution nanoscale nuclear magnetic resonance (NMR) spectroscopy has been proposed for measuring chemical structure and dynamics at the single molecule level. The nanoscale sensing volume of a single solid-state defect provides spatial discrimination, while sensing techniques such as Quantum Heterodyne [1] and Synchronised Readout [2] allow this measurement to be made with millihertz spectral resolution. This technique has so far been demonstrated using nitrogen vacancy centres in diamond. However, to bring this technique to a commercial device for widespread use, it is advantageous to develop it in a CMOS compatible material like SiC. In this work, we demonstrate this technique by sensing an artificial test signal using a single defect in SiC. The k-site silicon vacancy defect (V2) is an attractive candidate for nanoscale sensing because they have demonstrated room temperature operation and a long coherence time [3]. We implanted these defects using 15N+ irradiation with an energy of 2.5 keV, resulting in defects with a mean depth of 6.4 nm and displaying a spin echo coherence time of approximately 1.8 us. This coherence time would limit the spectral resolution of spin echo sensing to be greater than 500 kHz, so we surpass this limit by applying the Synchronised Readout technique [2]. Synchronised Readout works by applying repeated sensing measurements. The steps of quantum sensor initialisation, RF pulse sequence, and sensor readout are contained within a unit that is repeated at a regular interval. These repeated measurements under-sample the oscillating magnetic field of interest, resulting in a low frequency alias that can be used to recover the original signal. The length of time over which these measurements are taken determine the spectral resolution, and it is ultimately limited by clock stability of the measurement hardware. Successive traces of these measurements may be coherently averaged if they are locked to an initialisation pulse or phase reference. We use our single V2 defect to sense a test signal at ~3.3 MHz with a spectral resolution of ~333 mHz, with coherent averaging over 10 hours. By repeating this measurement at a range of test signal voltages, we calibrated the magnetic field strength seen by the sensor and used this information to estimate a measurement sensitivity of 358 uT/sqrt(Hz). We then make a comparison with theory [4] and find the primary limitation to be optical collection efficiency of our confocal microscope. We estimate that our sensor could detect 5.26 million 1H spins over 1 second of integration [5]. Finally, with a number of realistic improvements, we propose a path to achieve single-spin sensitivity with V2 defects. Further developing quantum sensing in a CMOS compatible material like SiC, with a goal of utilising existing CMOS industry infrastructure, may provide a pathway to creating on-chip quantum sensors at large scale and low cost. This could lead to new enabling technologies that make NMR sensing widely accessible to chemists, biologists, and medical scientists alike, with nanoscale sensing unlocking new discoveries in molecular dynamics at the single-molecule level.

[1] S. Schmitt et al., Science 356, 832–837 (2017). [2] D. R. Glenn et al., Nature 555, 351–354 (2018). [3] M. Widmann et al., Nat. Mater. 14, 164-168 (2015). [4] J. F. Barry et al., Rev. Mod. Phys. 92, 015004 (2020). [5] I. Lovchinsky et al., Science 351, 836–841 (2016).