ICSCRM 2023: INTERNATIONAL CONFERENCE ON SILICON CARBIDE AND RELATED MATERIAL 2023
PROGRAM FOR FRIDAY, SEPTEMBER 22ND
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08:30-10:30 Session 26A: Devices 5: High performance SiC MOSFETs concepts
08:30
Low on-resistance (< 0.7 mΩcm2) 4H-SiC vertical FinFETs with increased threshold voltage by using p-type poly-Si gate (invited paper)
09:00
SiC GAA MOSFET concept for high power electronics performance evaluation through advanced TCAD simulations
09:20
SiC n-channel MOSFETs fabricated on a high-purity semi-insulating substrate
09:40
Experimental Demonstration and Analysis of 3.3kV 4H-SiC Common-Drain Bidirectional Charge-Balanced Power MOSFETs
10:00
Reverse recovery characteristics of 1.2kV SiC-Superjunction-MOSFETs
08:30-10:30 Session 26B: Defects 4: Novel defect characterization techniques
Location: Ulisse
08:30
Depth profiles of deep levels in the whole band gap generated by reactive ion etching near the surface of 4H-SiC (invited paper)
09:00
Emission of Trapped Electrons from the SiC/SiO2-Interface via Photon-Irradiance at Cryogenic Temperatures
09:20
Direct observation of charge density manipulation in 4H-SiC MOS capacitors using low-energy muon spin spectroscopy
09:40
Temperature Dependent Permittivity of (0001) and (11-20) 4H-Silicon Carbide Measured by Electrical Impedance Spectroscopy
10:00
Atom probe tomography characterization of SiO2/4H-SiC interface
11:00-12:30 Session 27A: Devices 6: Gate dielectric engineering
11:00
Suppression of subthreshold drain leakage via implementation of high-κ dielectrics for advanced SiC power MOSFETs
PRESENTER: Sami Bolat
11:20
High Mobility 4H-SiC p-MOSFET via ultrathin ALD B2O3 interlayer between SiC and SiO2
11:40
Modelling-augmented failure diagnostics in planar SiC MOS devices using TDDB measurements
12:00
Extraction of SiO2/4H-SiC interface trap charge by TCAD simulation
11:00-12:30 Session 27B: Material 4: Emerging growth technologies
Location: Ulisse
11:00
Geometrical modification of the starting surface for three-dimensional epitaxy of low defect 3C-SiC
11:20
Novel Graphene and SiC Epitaxy to Enable Film Transfer
11:40
Epitaxial growth of GaN and 4H-SiC layers on 4H-SiC vicinal off angle substrates for GaN/SiC hybrid devices
12:00
Demonstration of SiC-on-insulator substrate with Smart Cut™ technology for photonic applications
14:00-14:40 Session 28: Plenary III
14:00
Next step in SiC technology

ABSTRACT. Since the commercialization of the first SiC SBD in the early 2000s and the first SiC MOSFET in early 2010, many researchers have made an effort to improve SiC Diode and MOSFET performance continuously. And the growth of electric vehicles in early of 2020s became a catalyst for the popularization of SiC power semicondutors. Even though early SiC products had several challenges in device quality and manufacturability, these issues have been resolved rapidly. As a result, SiC device is becoming the strong competitor of Si IGBTs, MOSFETs & FRDs in the power semiconductor market for voltage ratings above 650V. Many reseachers is considering  how to cost-effectively replace Si with SiC.

Two key drivers can be dicussed. One is manufacturing of SiC power semiconductors to use 200mm SiC wafers and other is FoM(Figure of Merit) improvement of SiC Diode and MOSFETs.

 SiC power semiconductor manufacturing is largely based on 150 mm substrates so far and an impressive achievement in the device performance was made. But 200mm substrates to allow cost reduction is inevitable now. onsemi has made large investments in Bucheon, Korea to satisfy these needs. An update in 200mm SiC MOSFET manufacturing is discussed in the presentation.

Many manufacturers in SiC power semiconductors have made an effort to improve FoM (Figure of Merit) of their Diodes and MOSFETs. onsemi’s latest technology has focused on this.

onsemi is investigating new diode technology of JFET diode structure to emphasize lowest total capacitive charge(Qc), which has big benefit to reduce switching loss in diode application.

In the presentation of onsemi’s effort on SiC, trench MOSFET technology which is optimized in EV application is discussed. This technology ensures long-term performance by minimizing electric field in the trench bottom with the new deep P structure and lowest Rsp with narrow cell pitch design.

In the road to go to trench technology, new planar MOSFET technology will be discussed, which is optimized in EV application as well. onsemi has focused on low Rsp value and immunity on parasitic turn-on with planar technology.

These three technologies will be discussed in the presentation.