ABSTRACT. We demonstrate a two-dimensional(2D) MoS2/WSe2 Core-Shell junctionless FET (CS-JL FET) fabricated on a silicon-on-insulator platform. This work reports the first experimental demonstration of 2D semiconductor CS-JL FET and elucidates its operating mechanism through simulation. Through van der Waals stacking of core and shell, this architecture is experimentally implemented and offers significant gain in on-state current and transconductance peak compared to MoS2 JL FET. Simulation indicates a wide threshold voltage tunability by adjusting core-shell doping configuration, offering a manufacturable route to mitigate the on-state current-threshold voltage trade-off in 2D JL FET. This work establishes vertical heterojunction engineering as a viable strategy for logic transistor scaling beyond silicon.

ABSTRACT. This work demonstrates the advantages of a novel channel-last (CL) integration of MoS₂ in stacked-channel transistors using calibrated TCAD simulations. The CL approach enhances electrostatic doping in the source/drain regions, significantly increasing electron concentration. Both with and without chemical doping of the MoS₂ film, our CL integration achieves superior ION/IOFF performance compared to conventional channel-first (CF) integration.

ABSTRACT. We employ ab-initio quantum transport simulations to explore the operation and design of Dirac-source FETs (DSFETs) based on van der Waals heterojunctions (vdW-HJs) formed between graphene (Gr) as the source material and different channel materials. We first present methodological guidelines for ab-initio modeling of DSFETs. We then compare the transfer characteristics of several vdW DSFETs: n-type graphene–molybdenum disulfide (Gr/MoS2), p-type graphene–hydrogenated graphene (Gr/HGr), and n-type graphene–fluorinated graphene (Gr/FGr). Our simulation results indicate that the Gr/FGr DSFET exhibits a reliable sub 60mV/dec operation and an ON-state current approximately 2x and 60x larger than those of the Gr/MoS2 and Gr/HGr DSFETs, respectively. In particular, using DFT-projected orbitals at the vdW heterojunction, we analyze the orbital contributions to interlayer tunneling and the resulting ON-state current.

ABSTRACT. The strong dependence of the electronic and dielectric properties of two-dimensional (2D) semiconductors on the number of layers makes their accurate representation in conventional TCAD simulations challenging. In this work, we investigate the MoS2/SiO2 heterostructure using density functional theory in order to extract effective parameters suitable for TCAD modeling. The system is described as a fully layered structure, allowing the explicit inclusion of the interfacial gap between MoS2 and the substrate. By analyzing the induced electron density under an applied electric field, the dielectric constants and effective thicknesses of the layers are determined. The results show that the MoS2/SiO2 interface can be modeled using alternative insulating layers, enabling the implementation of a physically accurate layered model in Sentaurus TCAD.

ABSTRACT. Abstract — This paper presents a comparative study of Forksheet and Nanosheet transistors with different dimensions, focusing on electrostatic integrity from room up to 150 oC. Using 3D TCAD simulations calibrated with experimental n-type forksheet data, it was investigated the impact of sheet height (HS) and gate oxide thickness (XOX). The results reveal a fundamental trade-off: while Nanosheets offer superior transconductance (gm) due to their quadruple-gate structure, Forksheets demonstrate better short-channel control (lower SS and DIBL) at scaled dimensions (HS = 5 nm) by mitigating corner effects through their dielectric wall. Additionally, the Forksheet architecture provides 10-16% lower gate capacitance (Cgg), establishing it as a promising candidate for high-density, energy-efficient applications under thermal stress.

ABSTRACT. This work presents, for the first time, the evaluation of an experimentally characterized forksheet transistor through its application in a low-dropout (LDO) linear regulator, assessing its suitability for analog power management circuits. The LDO was implemented under three different forksheet transistor efficiencies: gm/ID of 5, 8 and 11 V⁻¹. The experimental n-type forksheet used in this work presents a sheet thickness of HFS = 7 nm, sheet width of WFS = 23 nm and a transistor channel length of LG = 70 nm. When gm/ID increases from 5 to 11 V⁻¹, the DC loop gain improves from 35 dB to 40 dB, which directly translates into an improvement in Power Supply Rejection (PSR) from −30 dB to −37 dB. All designs achieved power efficiency close to 80%, while maintaining proper load regulation and stable closed-loop operation. The results demonstrate that the forksheet transistor can be effectively employed in analog building blocks such as LDOs, reinforcing its potential for mixed-signal integrated circuits using this emerging technology.

ABSTRACT. TCAD tools have been instrumental in the design space exploration and optimisation of the MOSFET. However, with the scaling and increase in complexity of the MOSFET architecture, the computational burden and non-convergence in the conventional TCAD tools have increased. Hence, DNN-based frameworks are being actively explored to overcome these pitfalls. In this work, we enhance our DNN-based TCAD tool, which can predict electrostatics over a wide range of cross-sections (from T = 3-40 nm) and applied biases (V_G = 0-0.6 V), by developing gradient-aware and MOSFET operation-aware synthetic data generation to make the training of the DNN more efficient. This reduces the training time and data requirement by ~78% and ~72%, respectively, without compromising the accuracy. We further benchmark the DNN-based simulator by reproducing the experimental transfer characteristics published in the literature of stacked nanosheet FETs in ~0.35 sec.

ABSTRACT. Si FDSOI devices are a promising platform for spin qubit based quantum computation. Understanding their room temperature electrical behavior is essential for efficient qubit screening and reliable crygenic temperature operation. Here, we demsontrate calibration and analysis of two FDSOI spin qubit structures using 3D TCAD simulations. We have successfully reproduced the experimental behavior of spin qubits despite their gate layout complexity and also revealed new device behavior affecting performance at cryogenic temperature.

ABSTRACT. This work aims to evaluate the impact of a single dopant position inside the channel of SOI GAA nanosheet transistors on the on-current, and the role of the device's dimensions on this effect, using an in-house Monte Carlo simulator with quantum corrections implemented through the effective potential method. The simulations showed that the effect of the dopant presence on the on-current variability is more pronounced in thinner devices, with up to 39.71% of variation in the current for the nanosheet with fin width of 10 nm and fin height of 5 nm, and for narrower devices, with 30.63% of variation in the current for the nanosheet with fin width and height of 10 nm, with the dopant, in both cases, placed in the center of the cross-section at 10 nm away from the source region. Therefore, our simulations clearly indicate that short, narrow nanosheets are more prone to on-current variations than short, wide ones.

ABSTRACT. We present results in the implementation of a new in-situ doped source/drain junction that has been developed for the tuning/optimisation of a fully-depleted SOI device for RF/mmW applications. We successfully correlate standard characterisations like AC/DC and inline process control measurements with advanced RF extractions.

ABSTRACT. The continuous scaling of semiconductor devices is approaching physical and economic limits, demanding novel approaches to sustain progress in microelectronics. Back end of line (BEOL) integration of active devices addresses this challenge by exploiting the largely unused vertical volume above conventional transistor layers, instead of restricting this space to passive interconnects. Such three-dimensional architectures aim to overcome the von Neumann bottleneck, reduce energy and latency associated with data transfer, and enable more efficient use of chip area. [1,2] The reconfigurable field effect transistor (RFET), with its dopant-free concept, high functionality density, and dynamic polarity control, is ideally suited for BEOL integration, where conventional CMOS devices face challenges due to thermal and design constraints. [3,4] As a first step towards a BEOL compatible fabrication of Si channel RFETs, a low-temperature atomic layer deposition (ALD) process is used to deposit 5 nm of gate oxide instead of high-temperature thermal oxidation. An optimized SiO2 ALD process at 280 °C growth temperature utilizing BDEAS precursor and O2 plasma is used to grow SiO2 on top of the Si nanosheet channel (12×30×800 nm3). Additionally, a second batch of RFETs is fabricated using HfO₂ ALD processes at growth temperatures between 150 °C and 250 °C, employing HyALD™ as the precursor and O₂ plasma as the oxygen source. The properties of the gate oxides are compared both among each other and against the high-temperature baseline process [5]. Drain and source contacts of the lateral Si channel are created by opening the gate oxide and depositing Ni followed by an annealing step to drive NiSi contacts into the channel. Ti/Pt metal stacks are used as top contacts for the three independent gates which are placed on top of the Schottky junctions and the center of the channel as well as drain and source. Figure 1 a) shows a schematic cross-section and Figure 1 b) a top-view SEM image of the fabricated RFETs. Electrical characterization of the devices depicted in Figure 2 shows a high dielectric breakdown voltage of >8 V for SiO2 and 4.5 V for HfO2 and low leakage with off-currents lower than 2×10-11 A for both dielectrics. Figure 3 shows the schematic of a RFET channel illustrating the applied voltage for measuring transfer curves with a) p-program and b) n-program. The measured transfer characteristic programmed as p-FET (red) and n-FET (blue) of RFET with SiO2 and HfO2 dielectric are shown in Figure 3 c) and d), respectively. N-type (p-type) transfer curves are obtained by fixing the drain voltage at 1 V (−1 V) and keeping both gates at the Schottky barriers at 3 V (-3 V) while sweeping the center gate from 0 to 3 V (−3 V). The achieved on-current for 30 nm wide channel devices is on average 1×10-6 A for p-program while n-program yields lower overall on-currents especially in case of HfO2 dielectric. The average subthreshold swing extracted from the transfer curves is 160 mV/dec, with off-currents being lower than 1×10-11 A for both n- and p-type modes. This study demonstrates that BEOL integration of RFET is feasible and that low-temperature gate oxide processes do not degrade device performance. Although several material systems are compatible with this approach, further process optimization is necessary to enhance RFET characteristics.

ABSTRACT. Direct contact between indium-tin-oxide (ITO) and silicon is highly resistive. We introduced a TiW barrier between the ITO and silicon, achieving ohmic contacts with interconnect resistance 1.3 ± 0.5 kΩ in 1 μm transparent FDSOI CMOS technology. We demonstrated ITO as a multi-level interconnect.

ABSTRACT. This study explores the mitigation of contact punch-through failures in advanced FD-SOI nodes by introducing a thin Anti Punch-through layer. Among several materials, SiCO proved most effective. Integration of a 5nm SiCO layer beneath CESL demonstrated successful contact punch-through mitigation, relaxing contact placement constraints within the device active region. This approach offers a promising solution for advanced FD-SOI technologies

ABSTRACT. Electrostrictive materials and devices have been widely explored for information processing and storage devices. Electrostrictive FET is an emerging steep-slope device concept which could allow low-power logic operation, but practical insights into how an electrostrictive material can be best paired with an FET channel material are still missing. Here we propose to adopt 2D heterostructures as a backbone of the electrostrictive FET. Based on literature-benchmarked finite-element simulations, we show that the application of a minimal gate voltage to the electrostrictive 2D layer can induce stress as high as 10M pascal in the adjacent 2D channel layer. A scaling study is also conducted to ultimately guide experimental researchers through 2D electrostrictive FET device design and manufacturing.

ABSTRACT. This work compares four widely used threshold voltage (VTH) extraction methods in AlGaN/GaN High-mobility electron field-effect transistors (HEMTs) fabricated at imec. Here it is demonstrated that linear extrapolation provides the most robust VTH definition across different geometries and bias conditions. By normalizing ID–VG curves using VGT, it is shown that the apparent dependence on geometry discrepancies collapses, enabling a clearer interpretation of aspect ratio effects under varying drain bias. These results suggest that geometry-dependent trends reported in the literature may partially arise from inconsistencies in VTH extraction rather than intrinsic device physics

ABSTRACT. Reconfigurable Field-Effect Transistors (RFETs) enable polarity programmability by electrostatically modulating asymmetric Schottky barriers at the source and drain, allowing dynamic switching between n-type and p-type operation without structural modification. This makes them promising candidates for compact and energy-efficient logic circuits [1]. Existing Verilog-A compatible RFET models reported in the literature are predominantly based on look-up-table (LUT) or machine learning methodologies [2], which rely on interpolation within predefined bias spaces but are inherently limited in their ability to ensure physical consistency, device scalability. As a result, a physics-based and numerically efficient and stable compact model capable of supporting symmetric n-/p-type operation and robust circuit-level simulation is still lacking though urgently needed for application of these devices in circuit design. Following our basic work on analytical modelling of RFETs in [3], in this work we present a unified physics-based DC compact model for Dual- and Triple-Independent-Gate (DIG/TIG) RFETs implemented on a 22-nm FDSOI platform [4]. The corresponding device architectures are illustrated in Fig.1, highlighting the independent gate configurations and the source/drain Schottky contacts. The model reproduces ambipolar transport, Schottky-barrier injection, and multi-gate electrostatics robustly. The modelling framework explicitly separates carrier injection at the source contact from channel transport, enabling correct polarity selection and current contribution from both electron and hole branches for all bias conditions. Carrier injection at the source-side Schottky barrier is computed using a unified thermionic–tunnelling formulation that captures the maximum physically allowed injection current for both carrier types, ensuring physically consistent injection-limited behaviour in both n-/p-type modes. The channel current is described by MOSFET-like charge-control equations, applied independently to each active gate in DIG and TIG configurations, providing a flexible modulation of the channel charge along the source–drain path. Injection and channel currents are combined through a nonlinear blending function, which ensures a smooth transition between injection-limited and transport-limited regimes and avoids artificial discontinuities in the ID–VG and ID–VD characteristics. Second-order output behaviour such as S-shaped ID–VD curves are captured through an empirical drain-side transparency term. For all bias conditions, the model is fully symmetric regarding selection of left or right contact as injecting electrode. It has been implemented in Verilog-A and therefore can be linked to standard tools for circuit simulation. The proposed compact model shows excellent agreement with experimental measurements from [4] for both n-and p-type operation across transfer and output characteristics for DIG-RFETs (Fig. 2). For TIG-RFETs (Fig. 3), the results validate the model’s capability to accurately predict both low-Vt and high-Vt characteristics. The model demonstrates computational efficiency suitable for circuit-level simulation while keeping a close link to device structure and physics. Fig. 4 shows circuit simulation results for an RGATE [5] consisting of four TIG-RFETs demonstrating numerical stability and full flexibility regarding bias conditions, even during the reconfiguration event.

ABSTRACT. Conventional impurity doping of nanostructured Si-based transistor structures is subject to several obstacles, in particular: (i) deteriorated charge carrier mobility due to ionized impurity scattering causing both slower switching speeds and increased heat dissipation, (ii) random dopant fluctuations (RDF), (iii) nano-size effects impeding high doping efficiencies due to dielectric mismatch, quantum confinement, etc. Moreover, conventional impurity doping is not cryo-compatible because charge carriers freeze out – unless degenerate doping levels beyond Mott's semiconductor-metal transition are considered. Although it is inevitable to control the charge carrier type and density in Si for any device application, it is not mandatory to incorporate dopants into the semiconductor itself. Here, we present a method that allows to relocate acceptor dopants from substitutional sites in the Si or SiGe lattice into an adjacent SiO2 layer [1]. Modulation Acceptor Doping (MAD) uses unoccupied acceptor states generated by specific trivalent acceptor impurities incorporated in SiO2 with energy levels below the Si valence band edge. A direct and permanent ionization of these acceptor states is realized by electron-tunneling from the adjacent Si, which creates holes as majority charge carriers [2], as schematically shown in Fig. 1. This p-type doping method provides higher hole mobilities (cf. Fig. 2), self-adjusts via Coulomb blockade its ionization density to minimize RDF, is not significantly affected by nano-size effects, and cannot be frozen out by cryogenic temperatures (cf. Fig. 2). In this presentation, different modulation acceptor elements [3], as predicted by density functional theory (DFT), are compared, both by the oxide fixed charge (C-V measurements) and hole sheet density (Hall-effect). Moreover, the application of MAD to transistor test devices is demonstrated for back-gated junctionless Si nanowire transistors [4] as well as SiGe Schottky barrier field-effect transistors (SBFET, cf. Fig. 3) [5]. A specific emphasis is put on the performance of these devices at cryogenic temperatures.

References [1] D. König, D. Hiller S. Gutsch, M. Zacharias, S. Smith, Sci. Rep. 7 (2017) 46703. [2] S. Nagarajan, I. Ratschinski, S. Schmult, S. Wirth, D. König, T. Mikolajick, D. Hiller, J. Trommer, Adv. Funct. Mater. 35 (2025) 2415230. [3] D. König, D. Hiller, S. Smith, Phys. Rev. Appl. 10 (2018) 054034. [4] S. Nagarajan, D. König, I. Ratschinski, G. Galderisi, S. Shams, T. Mikolajick, D. Hiller, J. Trommer, „Junctionless Silicon Nanowire Transistors without the Use of Impurity Doping“, ACS Nano (2026), accepted. [5] A. Fuchsberger, K. Eysin, L. Wind, E. Prado Navarrete, J. Aberl, M. Brehm, I. Ratschinski, D. Hiller, M. Sistani, W. M. Weber, IEEE Electron Device Lett. 46 (2025) 1429-1432. [6] I. Ratschinski, S. Nagarajan, J. Trommer, A. Luferau, M. B. Khan, A. Erbe, Y. M. Georgiev, T. Mikolajick, S. C. Smith, D. König, D. Hiller, Phys. Status Solidi A 220 (2023) 2300068.

ABSTRACT. This research presents a simulation-based study of neuromorphic systems utilizing Resistive Random-Access Memory in a 1-Transistor-1-Resistor configuration. The study explores the critical role of Activation Functions in managing the non-linear processing requirements of RRAM-based networks, which are subject to inherent analog variability.The proposed framework utilizes a Multi-Layer Perceptron trained on the MNIST dataset, simulated within a Variable Neural Network environment. To account for realistic device behavior, Cycle-to-Cycle variability is incorporated using the Stanford Model. The methodology focuses on a qualitative mapping approach that aligns abstract Sigmoid and Tanh AFs with simulated MOSFET I-V characteristics. By varying the β parameter to adjust the slope of the AFs, the simulation seeks to identify the optimal hardware-equivalent parameters necessary to maintain network robustness and evaluate the Adjustment Rate under varying standard deviations of noise.

ABSTRACT. The rising demand for Complementary Metal–Oxide–Semiconductor (CMOS) integrated circuit (IC) technologies capable of delivering stable and predictable analog electrical performance in high-temperature (T) environments has become a critical challenge for modern electronics [1]. Fig. 1 illustrates the Half-Diamond MOS Field Effect Transistor (MOSFET), called HDM [(Fig. 1 (a)] and Rectangular MOSFET (RM) counterpart [(Fig. 1 (b)], both having the same gate area (AG) and channel width (W) [2]. The objective of this work is to experimentally compare their electrical performances under the same bias conditions over an extended temperature range (300 K - 573 K). This study evaluates the following electrical parameters as a function of T: threshold voltage VTH (Fig. 2), Subthreshold Swing SS (Fig. 3), drain current saturation [IDS_SAT/(W/L)] (Fig. 4), and maximum transconductance [gmmax/(W/L)] (Fig. 5). Besides, Fig. 6 shows IDS_SAT/(W/L) as a function of gate-to-source voltage (VGS) with a drain-to-source voltage (VDS) of 1 V, for different T. The devices were fabricated using a 180 nm Bulk CMOS IC process from TSMC. The Half-Diamond layout style, which defines the pentagonal hybrid gate shape, is the first element of the second-generation MOSFET layout styles. It was specially designed to further reduce the effective channel length (Leff) of the Diamond MOSFET, preserving 1) the Longitudinal Corner Effect (LCE), that enhances the longitudinal electric field in the channel region, 2) PArallel connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) that reduces the effective channel length, and 3) Deactivation Parasitic MOSFETs in the Birds’ Beak Regions Effect (DEPAMBBRE), which boost the ionizing radiation tolerance in relation to the RM counterpart [2]. Based on Fig. 2 and Fig. 3, one observes that the VTH and SS values of the devices remain practically identical across the entire high-temperature range. The IDS_SAT/(W/L) at an overdrive-gate voltage (VGT) of 0.5V (Fig. 4), as well as gmmax/(W/L) (Fig. 5), for both devices decrease as the temperature increases, due to the reduction of the mobility of the mobile charge carriers (μn) in the channel region [3]. The IDS_SAT/(W/L), gmmax/(W/L), and the normalized current at “Zero Temperature Coefficient “[IZTC/(W/L)] of HDM are 44%, 41% and 40%, respectively, higher than those observed in the RM counterpart, thanks to LCE and PAMDLE effects. Note also that VGS at the ZTC point (VZTC) of devices are practically the same. Therefore, these effects persist over the full temperature range, enabling superior electrical performance and positioning HDM as a robust, cost-effective hardness-by-design approach for high-temperature MOSFET operation in 180 nm Bulk planar CMOS IC technology.

ABSTRACT. Spin Qubits in industrial grade silicon structure hold promises for tremendous integration density compared to other platforms. Recent realizations have successfully demonstrated implementation of Quantum Dots (QD) in arrays of MOS-like structure, with increasing number of devices or terminal. Though, such scaling capabilities require control and readout means with comparable footprint. This work explores an FDSOI based circuit architecture to tackle qubit biasing challenges.

ABSTRACT. This work investigates the impact of TFET–FinFET co-integration in SOI-compatible technologies through the design of a hybrid low-dropout (LDO) regulator. Monolithic integration on the same wafer enables complementary use of the low leakage and output conductance of Tunnel FETs (TFETs) together with the high drive current and transconductance of FinFETs. Device behavior is modeled using experimentally calibrated look-up tables implemented in Verilog-A. Compared to single-technology implementations, the proposed hybrid LDO achieves a loop gain of 95.4 dB, a PSR of −82.2 dB, an efficiency of 91.6%, and a 2 MHz GBW, consistently outperforming both standalone TFET and FinFET counterparts. These results highlight the effectiveness of TFET–FinFET co-integration as a promising strategy for enhancing low-power analog performance.

ABSTRACT. This study used TCAD simulations to explore the statistical effects of variations on 2 nm gate-all-around nanosheet transistors (NSFETs), including work function variation (WFV) and interface dipole fluctuation-induced variation (DFV). We simulate the effects of these variability sources on single device performance with different workfunction metals and extend the analysis to assess the stability and yield of 6T-SRAM cells, focusing on read and write margins and determining the minimum operating voltage (Vmin) for reliable SRAM functionality.

ABSTRACT. Complementary FET (CFET) architectures are being intensively explored for sub-2 nm technology nodes to overcome the scaling limits of nanosheet FETs. However, the extreme vertical proximity of N/P tiers in monolithic CFETs introduces fundamental challenges, most notably strong vertical mechanical coupling that locks the channel stress profile. In this work, we investigate the physical mechanisms governing stress evolution in CFETs and demonstrate how structural decoupling enabled by sequential integration overcomes the mechanical coupling inherent to monolithic architectures. TCAD simulations were performed on CFET structures with a 30 nm nanosheet width, a 14 nm gate length, and a 45 nm contact poly pitch. In monolithic integration, shared process windows induce vertical stress compensation between N/P tiers, resulting in limited effective channel stress (σxx). Our analysis reveals that channel stress in CFETs is an integration-governed quantity, where identical stressors lead to fundamentally different stress outcomes depending on the integration scheme. Specifically, sequential integration significantly suppresses vertical stress compensation, enabling more than a twofold improvement in tensile stress retention in the NMOS tier (+0.31 GPa) compared to monolithic integration (+0.14 GPa). Exploiting the independent process windows of sequential integration, we further introduce tier-wise asymmetric SiGe stressor engineering. This approach transforms the stress profile from locked to engineerable, achieving a strong compressive stress of −1.26 GPa for PMOS and a tensile stress of +0.80 GPa for NMOS. Device-level validation confirms a 26.5% improvement in PMOS drive current (Ion) relative to the monolithic baseline, along with restored current symmetry as the N/P Ion ratio improves from 0.74 to 0.90. At a fixed off-state current (Ioff) of 1 nA, the optimized sequential CFET exhibits a 13.6% reduction in inverter propagation delay, decreasing from 3.961 ps to 3.423 ps. These results establish a critical physical guideline for maximizing carrier mobility through stress engineering in ultra-scaled CFET tiers.

ABSTRACT. Resistive memory exhibits stable resistance states, low-power operation, and nonlinear transport characteristics, making it a promising candidate for next-generation non-volatile resistive random-access memory (RRAM), neuromorphic synapses, and compute-in-memory architectures [1-2]. The Al/SnO2/ITO device shows volatile bipolar hysteresis with gradual LRS → HRS → LRS modulation, enabling intrinsic memristive soft-threshold neuron behavior. The continuous evolution of state-dependent resistance supports nonlinear spiking dynamics with inherent self-reset, eliminating the need for external capacitors or complex CMOS-based circuitry. This architecture provides a simplified pathway to compact, energy-efficient neuromorphic hardware.

ABSTRACT. Label-free detection of biomolecules is essential for rapid and accurate medical diagnostics. This work presents a T-Shaped Nanocavity Junctionless Field-Effect Transistor (T-JFET) biosensor that enhances biomolecule-channel interaction by extending the sensing cavity from the gate oxide into the N-type channel. The T-shaped geometry enables a dual-modulation mechanism, combining gate capacitance alteration and direct reshaping of the local electric field, resulting in stronger depletion-region perturbation and higher drain current modulation. Simulation results show that the device provides improved current sensitivity, enhanced biodevice sensitivity, and more effective biomolecule detection, making it a promising platform for high-sensitivity diagnostic applications.

ABSTRACT. Since the discovery of graphene in 2004, graphene field-effect transistors (GFETs) have progressed toward the edge of commercial applications [1]. In this context, accurate compact models are essential for circuit design and technology benchmarking, motivating significant efforts in recent years [2], [3]. However, the metal–graphene interface phenomena captured by a contact resistance (Rc) remain a major limiting factor that degrades the performance of GFET-based applications [4]. Recently, extracted values of Rc for GFETs have shown a dependence on the lateral electric field [5], i.e., drain (D)-source (S) voltage VDS. Therefore, physics-guided compact formulations that capture the bias dependence of Rc are essential for reliable GFET modeling. In this work, a scalable compact GFET model [2], [3] is extended by considering a VDS-dependent Rc, to describe the drain current ID of devices with various footprints at several bias conditions. The model is validated with trap-reduced experimental data of Graphene-on-Insulator FETs fabricated at the EU 2D experimental pilot line [1] (Fig. 1a). Rc is the sum of a constant metal–graphene resistance (Rmg) and a bias-dependent metal-coated and uncoated graphene resistance (Rgg) [6] at each channel end (eq. 1). Applying electrostatics in channel [2], [3] and at the metal-covered regions [6] yields the graphene chemical potentials Vcch and Vcm, respectively, vs. gate voltage VGS from low to high VDS (Fig. 1b). At S, both potentials are slightly VDS-dependent (not shown), while at D the VDS dependence is dominated by Vcm. Basic IV parameters were first derived for each GFET at low VDS=0.1 V [7] at p-type region, followed by their scaling parameters extraction [3], which accurately describe all GFETs in this regime. The expected Rc 1/Width (W) dependence is also captured at VDS=0.1 V; Rc is Length (L)-independent. To reproduce the 0.1 to 1 V VDS behavior, an exponential term, ~exp(−nVDS/UT), is added in the Rc model [3, eq. 4]; UT is the thermal voltage, n accounts for the VDS dependence and the exponential reflects a Schottky-like thermionic emission [8] (eq. 1). The resulting Rcp parameters are listed in Table 1, and the model accuracy (lines) versus extracted Rcp (markers) for all VDS and W is shown in Fig. 2. Excellent agreement between modeled (lines) and measured (markers) ID–VGS plots for all GFETs at every VDS is presented in Fig. 3; the n=0 case (dashed lines) is included for the 10/20 μm/μm GFET for comparison.

ABSTRACT. Pseudo-MOS(FET) method is one of the most promising methods to inspect the quality of layered wafers with its simple and conventional configuration of loading metal probes on it . In this study, a Hg probe was employed in the AC pseudo-MOS method to achieve damage- and pressure-free measurements of SOI wafers, eliminating mechanical contact from solid metal probes.

ABSTRACT. To meet the requirements of next-generation high-frequency communication systems, devices must operate reliably at higher frequencies. This requires shortening the electron conduction path to reduce parasitic impedance, including parasitic resistance and capacitance. In addition, improving device linearity is essential for enhancing signal integrity. Electric field engineering has been proven to effectively improve linearity by increasing transconductance (Gm) value, and flattening the Gm curve, thereby enhancing third-order intermodulation distortion power (IM3) and third-order output intercept point (OIP3) [1]. In this work, the extension metal is deposited inward from the edges of the source and drain to shorten the carrier transport distance. This structural modification moderately increases the drain current density (IDS) and maximum transconductance (Gm,max). Meanwhile, the extension metal soothes electric field near gate foot, reducing peak electric field (Epeak), and improving Gm flatness. To determine the optimal extension metal length (Lext), Synopsys Sentaurus TCAD simulations were performed on conventional AlGaN/GaN HEMTs (Lext = 0 nm) and devices with Lext = 200, 250, 300, and 350 nm. On top of that, to improve Gm, source-drain spacing (LSD), source-gate spacing (LSG), and gate length (LG) were set to be 2 μm, 700 nm, and 200 nm, respectively. Fig. 1 show the proposed device structure. Electric field and electron density distributions were analyzed under class A and class AB bias conditions (IDS = 0.5 and 0.25 * IDSS, respectively), with the drain voltage (VDS) fixed at 10 V. For electric field distribution, simulation results, as shown in Fig. 2 and Fig. 3, show that increasing Lext reduces Epeak at the gate foot for all bias conditions, as the extension metal modulating electric field. However, excessive extension (Lext ≧ 300 nm) introduces a high electric field near source side due to reduced LSG, leading to electric field coupling. For electron density distribution shown in Fig. 4 and Fig. 5, correspondingly, electron density near source remains unchanged for Lext up to 250 nm but decreases by 5-15% for Lext ≧ 300 nm, showing degraded carrier injection caused by electric field redistribution. To validate the simulations, devices with Lext = 0, 250, and 350 nm were fabricated and characterized under the same drain bias (10 V). Transfer characteristics and extracted Gm, as shown in Fig. 6, confirm that Lext = 250 nm exhibits the highest IDSS, Gm,max, and the best Gm flatness. Although Lext = 350 nm further reduces gate Epeak, it weakens carrier injection due to stronger electric field coupling near the Source edge, resulting in rapid Gm roll-off at higher gate bias. Combining simulation and experimental results, Lext = 250 nm is identified as the optimal design, achieving enhanced current performance and improved Gm without compromising carrier injection.

ABSTRACT. Triboelectricity can offer a promising mechanism for the internet of medical things (IoMT) due to self-activated transduction, which can change subtle physical behavior into a discretized electric signature. We developed a triboelectric haptic sensor (TEHS), featuring a high-precision response to bio-mechanical stimuli, utilizing a combination of graphene-modified PDMS and functionalized PVA layers. The TEHS devices were able to capture the time and pressure details of a finger touch by differentiating power signals as small as pW.

ABSTRACT. This work presents a TCAD-based geometrical optimization and performance analysis of a planar Back-Enhanced SOI Dual-Contact Reconfigurable Field-Effect Transistor (RFET). The device geometry is optimized to reduce the threshold voltages (in module) and to achieve balanced electron and hole conduction, addressing asymmetries observed in previous experimental generations. The optimized RFET exhibits nearly symmetric transfer characteristics in both n-type and p-type operation, enabling reliable reconfigurable digital logic. As a proof of concept, the device is applied in an eight-function dynamic logic gate, achieving a 62.5% reduction in transistor count compared to conventional SOI MOSFET implementations. These results confirm the potential of planar BE-SOI RFETs as low-cost, technology-compatible devices for high functional-density logic, while identifying power consumption and delay as remaining optimization challenges.

ABSTRACT. In this work, the impact of Random Dopant Fluctuation (RDF) in Drain-Extended Nanosheet FETs (De-NSFET) is investigated. This is achieved by evaluating Breakdown voltage (VBV), On-state Resistance (RON), Threshold Voltage (VTH), Switching Ratio (ION/IOFF), Figure of Merit (FOM), Cut-off Frequency (fT), at different channel stacks. The Standard Deviation (σ) of the performance matrices demonstrates the reliability of De-NSFET. Furthermore, statistical analyses are performed for the robustness of the stacked architectures for high-voltage applications.

ABSTRACT. The channel/sheets geometry plays a significant role in the performance dynamics of the vertically stacked Nanosheet FET (NSFET). In this paper, we propose a non-quasi-static (NQS) small-signal model of the NSFET, capturing the significant role of corner rounding in the effective admittance of the device. In our proposed small-signal model, to capture the impact of corner rounding, we included new capacitance terms (Crs/Crd) in series with the overlap capacitance, and a resistance term (Rgd/Rgs) in parallel with the gate-to-source/drain resistances. In comparison to rectangular corners, round corners have a lower electric field stress due to a uniform electric field distribution, resulting in a smoother potential distribution that minimizes leakage paths near the corners. The modified small-signal model is found to be in good agreement with TCAD results, i.e., the Y-parameter matrix is being calibrated.

ABSTRACT. This study develops a comprehensive axisymmetric electro-thermal model of an HfO2-based nanoscale memristive device to analyze resistive switching behavior, cycle-to-cycle (C2C) variability in the device switching voltages under consistent cyclic operation, the effect of voltage ramp rate VRR on the switching dynamics, and synaptic characteristics such as potentiation and depression. The overall objective of this work is to develop a realistic modelling framework that can accurately represent the coupled thermodynamic and electro-thermal processes that control memristor functioning and assess its applicability for neuromorphic and low-power memory applications.

ABSTRACT. The discovery of ferroelectricity in doped HfO2 thin films has revitalized semiconductor research due to their excellent CMOS compatibility and strong potential for next-generation memory and logic devices. Among various dopants, Zr plays a crucial role in stabilizing the ferroelectric orthorhombic phase of HfO2, significantly enhancing electrical performance. Consequently, Zr-doped hafnium oxide (Hf1-xZrxO2) has emerged as a highly promising material for advanced non-volatile memory applications. In parallel, the selection of a suitable metal gate electrode is critical for optimized device integration. Ru has attracted attention as a promising top electrode material owing to its favorable effective work function (~5 eV), thermal stability on high-κ dielectrics, and full compatibility with advanced CMOS processing. In this work, Hf1-xZrxO2 thin films were deposited using a novel pulsed-DC magnetron sputtering technique designed to emulate an ALD-like layer-by-layer growth process. Three sample configurations were investigated: HZ-4L and HZ-8L, containing four and eight ZrOx insertion layers, respectively, and HZ-8L(T), featuring similar HZ-8L structure with slightly thicker ZrOx layer. Structural analysis confirmed that homogeneous ZrOx diffusion within the HfOx matrix leads to the formation of a uniform ~36 nm Hf1-xZrxO2 film at room temperature, with an interfacial SiOx layer thickness of ~ 3.6 nm. In contrast, when individual ZrOx sublayers exceed ~2.5 nm in thickness, incomplete interdiffusion occurs, resulting in periodic HfOx/ZrOx stacking and a thicker interfacial SiOx layer (~4.9 nm). These findings indicate that complete intermixing is strongly dependent on ZrOx sublayer thickness. Electrical characterization of Ru/Hf1-xZrxO2/Si MOS structures revealed that HZ-8L exhibits the highest accumulation capacitance, while HZ-8L(T) shows reduced accumulation capacitance due to its thicker SiOₓ layer. The increased interfacial thickness in HZ-8L(T) lowers the extracted interface state density (Dit), resulting in reduced C-V hysteresis. I-V measurements indicate that leakage current increases with higher ZrOx incorporation, likely due to an increased density of trap centers that facilitate additional conduction pathways. However, HZ-8L(T) demonstrates reduced leakage current minima, consistent with its lower Dit. During reverse voltage sweeps, higher leakage minima are observed due to incomplete electron de-trapping under rapid voltage sweeping conditions. Overall, periodic layer-by-layer sputtering enables controlled incorporation of ultrathin ZrOx sublayers within HfOx, allowing the formation of tunable Hf1-xZrxO2 stacks at room temperature. The optimized structures exhibit reduced leakage current and suppressed C-V hysteresis, indicating improved dielectric quality. These results demonstrate the feasibility of sputtered Hf1-xZrxO2 ferroelectric films and confirm the compatibility of Ru top electrodes for next-generation non-volatile memory applications.

ABSTRACT. Neuromorphic computing has attracted significant attention in the last decade as conventional CMOS technology approaches its scaling and power-efficiency limits. Memristive devices have emerged as attractive alternatives due to their nonvolatile memory capability, reduced power consumption, and ability to emulate biological synaptic functions. In oxide-based memristors, resistive switching (RS) enables analog conductance tuning, scalability, and synaptic plasticity, making them suitable for neuromorphic applications. This work investigates the area-dependent RS behavior of Al/TiOx/TiN memristors. The TiOx layer was deposited by pulsed-DC reactive sputtering at room temperature, yielding a thickness of approximately 40 nm, while the TiN bottom electrode was 20 nm thick. Cross-sectional TEM image confirms the device structure. Current-voltage (I-V) measurements performed on devices with circular areas of π×(75)^2 µm2, π×(150)^2 µm2, and π×(300)^2 µm2 reveal clear current scaling with increasing device area. Both high-resistance state (HRS) and low-resistance state (LRS) values decrease as the device area increases, indicating predictable resistance scaling behavior. STEM- EDS elemental mapping analysis of the device structure in the LRS state shows an oxygen-deficient region in the TiOx layer adjacent to the TiN electrode. Correlating electrical data with HR-TEM observations suggests that the RS mechanism is dominated by interface-type switching rather than localized filament formation. The devices exhibit stable analog switching with DC endurance exceeding 500 cycles and retention times longer than 10^4 s. Gradual SET and RESET processes enable continuous conductance modulation. Furthermore, the memristors successfully emulate synaptic functions, including potentiation and depression under consecutive positive and negative pulses. Paired-pulse facilitation (PPF) behavior was evaluated using 3.7 V pulses with a 100 ms duration, where the PPF index was calculated as (I2/I1) × 100%. The observed facilitation confirms short-term plasticity characteristics.

Overall, the demonstrated area-dependent scaling, stable analog switching, and synaptic emulation highlight TiOx-based memristors as promising building blocks for high-performance neuromorphic systems.

ABSTRACT. Semiconductor devices at the nanometer scale require quantum-corrected transport models to accurately capture confinement and electrostatic effects. We extend our previously developed Mixed Finite Element Method (Mixed FEM) framework for the Poisson–Drift–Diffusion system by adding the Density Gradient (DG) model for quantum correction. The formulation treats electrostatic potential, carrier densities, and fluxes as independent variables, improving numerical stability, local conservation, and parallel efficiency. Implemented in MoFEM, the solver efficiently handles strongly coupled semiconductor simulations even on coarse meshes. Simulations of a three-gate silicon-on-insulator (SOI) device demonstrate accurate electrostatic potential and hole concentration distributions with strong agreement between coarse and refined meshes.

ABSTRACT. Bandgap engineering is a crucial and powerful technique in nanoelectronics. Recent advancements in creating a bandgap in graphene have inspired recent research studies into tuning the bandgap of the 2D semiconducting materials, e.g., MoS2 [1]. One effective method to induce a bandgap in graphene is by applying a perpendicular electric field to its bilayer (BL) structure [1]. This process works by breaking the inversion symmetry of BL graphene with an external electric field, leading to electrostatic screening between the two layers and splitting the π and π* bands that intersect at the Fermi level (Ef) [2]. PtTe2 has garnered significant interest as a member of the group-10 noble transition metal dichalcogenides (TMDs), MX2, in recent years. This is due to its unique physical and chemical properties, including high conductivity, dimensionality-mediated semimetal-to-semiconductor transition [3,4]. PtTe2 retains its semi-metallic properties for thicknesses down to BL but transits to a semiconductor when reduced to a monolayer due to the quantum confinement effect [5]. This characteristic underscores the importance of synthesizing ultrathin PtTe2 films to fully exploit their electronic properties for high-performance electronic devices. In this work, we demonstrate that a perpendicular gate electric field can dynamically tune the interlayer coupling in bilayer PtTe2 (Figures 1 and 2), driving a reversible transition from a metallic to a semiconducting state. Through density functional theory calculations combined with quantum transport simulations based on the non-equilibrium Green’s function formalism, we show that a critical electric field (2.5 MV/cm) increases the interlayer separation from the equilibrium metallic to the semiconducting behavior (Figure 3). The results demonstrate device performance compatible with the low-power requirements for ION and IOFF, as projected in the IRDS 2028 roadmap [6]. Acknowledgement: This research is supported by the Marie Skłodowska-Curie Actions (MSCA), grant agreement number 101109772. This work is also supported by Research Ireland through the Frontiers for the Future PI Award (24/FFP-A/13329) and the AMBER Research Centre (SFI-12/RC/2278_P2). SFI/HEA Irish Centre for High-End Computing (ICHEC) is acknowledged for the provision of computational facilities. References [1] Q. Liu, et al., The Journal of Physical Chemistry C 116 (40) (2012), 21556-21562. [2] E. V. Castro, et al., J. Phys.: Condens. Matter 22 (2010), 175503. [3] M. K. Lin, et al., Phys. Rev. Lett. 124 (2020), 036402. [4] K. Zhussupbekov, L. Ansari, J. B. McManus, et al., npj 2D Mater Appl 5 (2021), 14. [5] J. Li, et al., ACS Nano 15 (2021), 13249–13259. [6] L. Ansari, et al., 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 1-4.

ABSTRACT. This work investigates, for the first time, the influence of different nanosheet transistors inversion regimes — corresponding to transistor efficiencies (gm/IDS) ranging from 7 to 12 V⁻¹— when applied to the design of a two-stage operational transconductance amplifier (OTA) operating over a wide temperature range, from 125 °C down to -100 °C. The results show that higher transistor efficiency significantly improves the voltage gain (AV), reaching values around 80 dB at lower temperatures. In contrast, the gain-bandwidth product (GBW) achieves its maximum value (685 MHz) at lower efficiencies (higher IDS current) once it is proportional to the IDS, indicating the clear trade-off between voltage gain and GBW. Energy efficiency increases under lower bias currents (ISS), which occur at higher temperatures and higher gm/IDS values. Additionally, for a gm/IDS of 8 V⁻¹, the gain–bandwidth product (GBW) increases from 417 MHz to 657 MHz as the temperature decreases from 125 °C to −100 °C due to the mobility improvement. These findings highlight the relevance of nanosheet-based OTAs for applications requiring operation under extreme temperature conditions—such as cryogenic sensing, space electronics, and robust biomedical instrumentation—where high gain, tunable bandwidth, and low-power performance are essential.

ABSTRACT. This work investigates the impact of intrinsic vertical asymmetry in Vertical Nanowire FETs (VFETs) on the performance of two-stage Operational Transconductance Amplifiers (OTAs). Unlike planar devices, VFETs exhibit distinct electrical characteristics depending on the bias configuration, specifically whether the source is connected to the Top Electrode (TE) or to the Bottom Electrode (BE). While previous research has primarily focused on small-signal gain, this work analyzes critical figures of merit, including Common-Mode Rejection Ratio (CMRR), Power Supply Rejection Ratio (PSRR), and Slew Rate (SR). Experimental characterization of VFETs reveals a fundamental trade-off between static and dynamic performance. The BE configuration demonstrates superior signal integrity, achieving a CMRR of 61 dB and a PSRR- of 93 dB, driven by high Early Voltage, resulting in increased output impedance. Conversely, the TE configuration maximizes transient response, delivering a Slew Rate of 3.05 V/µs due to higher transconductance and reduced compensation capacitance requirements, also obtained a Gain-Bandwidth Product of 1 GHz. These results establish the VFET conduction direction as a critical design parameter for optimizing analog circuits, whether for high-precision instrumentation or high-frequency applications.

ABSTRACT. The origin of the ferroelectricity in ultrathin HfO₂ and ZrO₂ films remains controversial. We demonstrate that it is the strain-induced bond stretching that stabilizes the ferroelectric phase without depolarization effects, enabling CMOS-compatible nanoscale ferroelectric devices.

ABSTRACT. This work investigates the impact of time‑dependent hot‑carrier degradation (HCD) on statistical variability in nanosheet FETs (NSFETs) using process‑based TCAD device simulations combined with Monte Carlo variability analysis. We find that HCD increases the threshold voltage Vth and degrade key figures of merit such as drive current (Ion) and subthreshold swing (ss). In addition to the shifts in mean device characteristics, the variability of Vth broadens due to the generation and fluctuation of interface trap charges (ITC i.e Nit).

ABSTRACT. This work investigates, via TCAD simulations, the influence of gate dielectric selection and edge dielectric engineering on the electrostatics of 4H-SiC MOS capacitors. Al₂O₃, AlN, and HfO₂ gate dielectrics integrated with an ultrathin SiO₂ interfacial layer are analyzed under ideal and non-ideal interface conditions. Accumulation capacitance follows the geometrical oxide relation, with TCAD and analytical values agreeing within ±0.05% and varying by < 7% across stacks. High-κ TiO₂ edge termination reduces the peripheral peak electric field from 155 to 56 kV/cm (≈64% reduction) with only minor impact on quasi-static C–V characteristics. These results demonstrate a quasi-decoupled electrostatic behavior in SiC MOS capacitors, where vertical charge storage and lateral field crowding can be engineered independently, providing a design principle directly relevant to advanced SiC MOSFET edge-termination strategies.

ABSTRACT. We describe how the amorphous TeO2 network creates energetically deep, flexible polarons to avoid p-type doping.

ABSTRACT. The lattice structure and bandgaps of Sc1-xAlxN and Sc1-xGaxN alloys are calculated by a full hybrid function method with no adjustable parameters. The Al alloys show a transition at x~0.55 with continuously decreasing bandgap, whereas the Ga alloys have a transition at x~0.7 with a peak gap at x~0.6. The main near mid-gap defect level is due to the nitrogen vacancy.

ABSTRACT. InGaZn oxide (IGZO) is of great importance as a back end of line (BEOL) oxide due to its low temperature processing and ability to be deposited by atomic layer deposition. Experimentally it contains hydrogen, which controls its reliability at higher temperatures. This paper describes the first hybrid density functional calculation of the hydrogen states in IGZO as measured by IR spectroscopy. The most stable bonded hy-drogen state is that involving metal-H bridges, whereas O-H bonded states are found to be weaker experimentally. The effects of low In contents which increase the stability of IGZO are also studied.

ABSTRACT. The high n-type conductivity of back-end-of-line (BEOL) transistors requires an s-like conduction band minimum (CBM). In indium tungsten oxide (IWO), a torsional relaxation of the idealized bixbyite structure into the relaxed structure raises the W 5d states by nearly 2 eV, allowing the In 5s states to dominate the CBM and enable high conductivity. The stronger W-O bonding suppresses the oxygen vacancy and its simpler H bonding improves its stability compared to IGZO.

ABSTRACT. This paper analyzes the influence of temperature (T) on the low-frequency noise (LFN) of a single trap in junctionless nanowire transistors (JNTs) under different bias conditions. The study is based on three-dimensional (3D) simulations considering devices with channel lengths (L) of 30 nm and 100 nm, validated with experimental data at room temperature. Results show that the temperature increment modulates LFN, increasing current noise spectral density (SId) and shifting the corner frequency. These findings are relevant for predicting JNT reliability under different thermal conditions.

ABSTRACT. As transistor scaling approaches sub-5 nm technology nodes, conventional silicon field-effect transistors face increasing challenges including short-channel effects, increasing contact resistance, and power dissipation [1-2]. Two-dimensional (2D) materials have emerged as promising candidates for next-generation electronics due to their atomically thin channels and superior electrostatic control [3-5]. Among them, Pt-based transition metal dichalcogenides (TMDs) exhibit unique thickness-dependent electronic properties. In particular, PtTe2 demonstrates a transition from semiconducting to semimetallic behaviour depending on the number of layers, enabling the realization of novel device architectures without conventional doping [6]. This property enables monomaterial Schottky junction field-effect transistors (FETs), where semimetallic bilayer PtTe2 forms the source/drain contacts and semiconducting monolayer PtTe2 acts as the channel (Figure 1).

In this work, we investigate the performance of monomaterial PtTe2 Schottky FETs using first-principles electronic structure calculations combined with quantum transport simulations within the non-equilibrium Green’s function (NEGF) framework. The thickness-dependent band structure of PtTe2 is first analysed to confirm the transition from semiconducting monolayer to semimetallic multilayers, enabling efficient Schottky contacts within a single material platform (Figure 1). Device simulations are then performed for ultra-scaled transistor geometries with transport along two crystallographic orientations (Γ–M and Γ–K) in order to evaluate orientation-dependent carrier injection and electrostatic switching behaviour.

The simulated transfer characteristics demonstrate strong electrostatic control with subthreshold swings approaching ~75 mV/dec and suppressed OFF-state leakage currents depending on the transport orientation (Figure 2). Transport along the Γ–M direction shows improved ON-state current and switching performance compared with the Γ–K orientation. Analysis of the projected local density of states (PLDoS) and energy-resolved current spectra further reveals efficient Schottky barrier modulation and highlights the influence of orientation-dependent band dispersion on carrier transport.

The simulated output characteristics further confirm quasi-linear current behaviour at low drain bias and current saturation at higher voltages for both transport orientations (Figure 3). These results demonstrate that monomaterial PtTe2 Schottky FETs provide a promising dopant-free architecture for ultra-scaled nanoelectronic devices and highlight the potential of thickness-engineered 2D materials for beyond-CMOS logic technologies.

ABSTRACT. The Silicon-on-Insulator (SOI) substrate offers a unique opportunity to investigate 2D-confined systems, providing a versatile platform for advanced nanoelectronics applications, owing to its CMOS compatibility and complete tunability. While established in high-performance computing, SOI is emerging as the foundation for next-generation devices from ultra-low power to unconventional applications. Despite its potential, fundamental studies on dopant incorporation and ionization in ultrathin Si films remain limited, creating a knowledge gap in understanding the transition from bulk-like behavior to the quantum-confined regime. In our previous works we investigated ex-situ doping of ultrathin SOI across a wide range of thickness (HSOI) and P concentration (nD). Doping at the nanoscale was achieved via a mild bottom-up approach based on P-terminated polymers.[1,2] Full activation and optimal electrical properties were achieved on SOI substrates with HSOI ~ 30 nm, fully aligning with literature data for similarly doped bulk Si.[3] We observed significant deviations in transport properties reducing HSOI < 30 nm, in particular we demonstrated that interface engineering is critical for controlling dopant activation and ionization. Thermal oxidation (RTO) was employed to optimize carrier concentration (ne) and mobility at room T.[4] Interestingly, despite high nD, an unexpected semiconductor behaviour was observed at low T, driven by an increased P activation energy (Ea), resulting from the dielectric mismatch between Si and SiO2.[4] In this work we investigate the evolution of Ea with nD for ultrathin SOI (HSOI ~ 12 nm, Fig. 1a). Low T sheet resistance and Hall measurements (Fig. 1b) demonstrate that reducing nD, ne drops significantly due to charge trapping at non-passivated states at the (RTO)SiO2/Si interface. Non-passivated interface states significantly reduce the effective conductive thickness (Heff, Fig. 2a), leading to electrostatically induced quantum confinement. Under these conditions, Ea deepens significantly, reaching values 175 meV below the conduction band edge (Fig. 2b), nearly four times the bulk value of 45 meV.[3] By manipulating the SiO2/Si interface quality, specifically through capping with chemically grown SC2-SiO2 layers, we demonstrate that electrostatic confinement (Heff), and so Ea, can be precisely engineered (Fig. 2c). Ea values of 145 meV are achieved at high nD ~ 8 x 1018 cm-3. Subsequent forming gas anneal significantly improves the quality of the SC2-SiO2/Si interface, relaxes the electrostatic confinement and results in increase in ne by a factor of 10 and a reduction of Ea to 50 meV. These results provide fundamental insights into nanoscale doping, highlighting the differences between bulk Si and 2D-confined films. The ability to tune Ea and the metal-insulator transition through nD, HSOI and surface states, opens new possibilities for advanced tunable nanoelectronics devices, enabling precise control over carrier transport in the sub-15 nm regime.

References [1] M. Perego G. Seguini, E. Arduca, A. Nomellini, K. Sparnacci, D. Antonioli, V. Gianotti, and M. Laus, ACS Nano 12 (2018) 178–186. [2] A. Pulici S. Kuschlan, G. Seguini, F. Taglietti, M. Fanciulli, R. Chiarcos, M. Laus and M. Perego, Materials Science in Semiconductor Processing 163 (2023) 107548. [3] P.P. Altermatt A. Schenk, and G. Heiser, Journal of Applied Physics 100 (2006) 113714. [4] A. Pulici, G. Seguini, F. Taglietti, R. Gumeniuk, R. Chiarcos, M. Laus, J. Heitmann, M. Fanciulli, M. Perego, arXiv preprint arXiv:2601.09379 (2026).

ABSTRACT. Reconfigurable field-effect transistors (RFETs) offer new opportunities for adaptive and secure circuit design. In this work, the functionality of a Dual-Doped RFET (DDRFET) is experimentally emulated using discrete transistors to demonstrate its applicability in hardware security. The proposed configuration reproduces the dual N/P-type operation of the device and enables the implementation of polymorphic logic gates such as NAND/NOR, XOR/XNOR, and NOT/BUFFER. These gates are used to implement a logic-locking scheme based on the URSAT technique to protect the ISCAS’85 C17 benchmark circuit. Experimental measurements show that the correct circuit functionality is recovered only when the appropriate key is applied. These results demonstrate the feasibility of DDRFET-based polymorphic logic for secure hardware design.

ABSTRACT. The incorporation and activation of dopant impurities in Si have been extensively investigated, and the underlying physics is well-established and widely recognized [1]. The scenario becomes increasingly intricate and less obvious when considering doping of Si nanostructures due to the reduced dimensionality. Dielectric mismatch is expected to alter dopant ionization energies and carrier statistics, increasing ionization barriers and modifying local band bending near the Si/dielectric interface [2]. Interface passivation and engineering are crucial to suppress surface traps, tailor the local dielectric environment, and realize robust doping schemes of nanostructured semiconductors. In this work the role of interface states and dielectric mismatch is investigated in ultrathin P-doped silicon-on-insulator (SOI) films as a function of device layer thickness (HSOI) and dopant concentration (ND). An alternative gentle doping scheme based on polymers terminated with a P containing moiety [3] is used to tune the doping level from 1018 up to 1020 cm-3 in ultrathin SOI substrates with HSOI values varying from 30 to 8 nm. P concentration is assessed by Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS). Sample resistivity (ρ), carrier concentration (ne), and mobility (μe) are extracted via sheet resistance and Hall measurements in van der Pauw configuration. For samples with HSOI = 30 nm, transport measurements design a picture fully compatible with those of bulk Si with full dopant activation and almost complete ionization at room temperature [4]. Progressive 2D confinement by decreasing HSOI below 30 nm results in a reduction of ne (figure 1) and a concomitant degradation of μe (figure 2). These effects, which are significantly enhanced decreasing ND, are attributed to the presence of non-passivated interface states at the SiO2/Si interface. These states act as traps for electrons and contribute to the formation of a depleted region in the Si device layer that significantly narrows the effective conductive channel. This effect is significantly mitigated (Figure 3) by improving interface quality via high temperature rapid thermal oxidation (RTO). The SiO2/Si interface was investigated by electron-paramagnetic resonance (EPR) spectra and capacitance-voltage (CV) measurements and the experimental results well correlate with the observed electrical properties (Figure 3). Electrical characterization at room temperature of samples with 10 nm ≤ HSOI ≤ 20 nm and P concentration 6 x 1018 cm-3 highlighted a significant increase in ne and μe upon interface engineering. However, low-temperature transport measurements (figure 4) unequivocally demonstrate a transition from metallic to semiconductor behavior for samples with HSOI < 20 nm alongside with a significant increase of P ionization energy for HSOI ≤ 14.0 nm, tentatively attributed to dielectric mismatch effects. Acknowledgement. This work was financially supported by the Italian project DONORS (grant number 2022WBPHKF) within the Italian program for Research Projects of Relevant National Interest (PRIN) in the framework of the National Recovery and Resilience Plan (PNRR).

References [1] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, John Wiley & Sons, Inc., Hoboken, NJ, USA, 2006. [2] M. T. Björk, H. Schmid, J. Knoch, H. Riel and W. Riess, Nat. Nanotechnol., 4 (2009), 103–107. [3] M. Perego, G. Seguini, E. Arduca, A. Nomellini, K. Sparnacci, D. Antonioli, V. Gianotti and M. Laus, ACS Nano, 12 (2018), 178–186. [4] A. Pulici, S. Kuschlan, G. Seguini, M. D. Michielis, R. Chiarcos, M. Laus, M. Fanciulli and M. Perego, J.Mater. Chem. C, 12 (2024), 18772–18778.

ABSTRACT. The CFET configuration is a promising option for shrinking the area of circuits in the near future. Stack-in-Pillar (SiP) technology will enhance circuit integration (IC) by minimising the IC footprint through the stacking of multiple devices within the same pillar. The SiP proposal is technology-independent, as it can be implemented regardless of the pillar material or device configuration. We have simulated its use as a CMOS inverter to demonstrate its functionality. We have also analysed the impact of variability on circuit performance.

ABSTRACT. Memristors have emerged as a promising approach for meeting the growing global memory needs by enabling in-memory computing that alleviates the memory wall and the power wall limitations of traditional von Neumann architectures. Their nonlinear, input-dependent switching dynamics make memristors well-suited for neuromorphic computing, as they can closely replicate the synaptic plasticity and neuron-like behavior observed in biological neural systems. Perovskite memristors are among the most actively investigated resistive switching materials, offering reconfigurable volatile and nonvolatile analog switching, ultra-low energy consumption, high tunability, and low-cost solution-based fabrication. Physics-based compact models facilitate the integration of memristors into simulation-based circuit design. However, compact models tailored specifically to perovskite memristors are still scarce in the literature. In this work, we developed a physics-based compact model for halide perovskite memristors inspired by the Stanford ReRAM framework. We leverage its electric field and temperature-enhanced state equation and tunneling current formulations as a physically grounded foundation for perovskite device simulation. This adaptation preserves its mathematical structure while aligning the physical interpretation with perovskite ionic transport. Key modifications include reinterpretation and rescaling of device parameters as well as introducing new parameters consistent with perovskite memristor physics. The model was validated against experimental halide perovskite memristor I-V measurements and achieved good linear and log-scale agreement.

ABSTRACT. Resistance characterization of Back-End-Of-Line (BEOL) metallic layers down to cryogenic temperatures is required to model resistor values, inductance quality factors, DC voltage drops, current densities, or Joule heating under cryogenic operating conditions. The Residual Resistivity Ratio (RRR) is a key parameter in assessing metal quality and the evolution of layer resistivity with temperature. However, systematic RRR studies of microelectronic layers are not widely available, despite the growing importance of cryogenic microelectronics design. In this work, we report RRR measurements on copper and aluminum layers used in two standard process from STMicroelectronics, 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) and BiCMOS55X. A nearly linear increase in RRR with thickness is observed for copper layers. For qubit readout applications, the design and measurement of multilayer Cu/Al on-chip inductors for reflectometry measurements is considered.

ABSTRACT. Silicon Nanowire Field-Effect Transistors (NW FETs) are widely considered as a promising technology for next-generation biosensors due to their advantages of low-cost fabrication, rapid response time and label-free detection. However, they often encounter difficulties in preserving long-term stability and sensitivity when operating in complex biological fluids. In this work, diamond-like carbon (DLC) films with nanometer-scale thicknesses, ranging from 1 nm to 14 nm, were introduced to modify the surface characteristics of low-defect-density silicon dioxide (SiO₂) layers, aiming to enhance their long-term stability. The capacitance–voltage (C–V) characteristics and stability time-domain measurements of structures with various DLC thicknesses were systematically examined to estimate the evolution of the flat-band voltage (Vfb) during prolonged operation in different biological liquid environments. The experimental results indicate that incorporating a DLC layer enables the system to reach equilibrium more rapidly whilst improving electronic performance in liquid. Owing to its highly dense structure, DLC exhibits excellent chemical constancy over extended periods, which is essential for maintaining biosensor functionality in physiologically relevant solutions. Furter impedance spectroscopy measurements reveal that the improved stability of DLC-covered structures is determined by suppressed ion penetration and reduced diffusion transport through the high-quality diamond-like layer. As a result, the optimized structures demonstrate enhanced long-term performance, including shorter Vfb stabilization time, better stability compared with bare SiO₂-covered ones, and optimized sensitivity in various liquid environments. Experiments conducted in solutions with varying pH concentrations confirm that DLC-modified structures are well applicable for biological signal detection and monitoring.

To verify the functionality of DLC-covered structures for direct biosensing, silicon NW FETs with a DLC protective layer were fabricated using a complementary metal–oxide–semiconductor (CMOS)-compatible process and functionalized with C-reactive protein (CRP) aptamers. Biomedical studies of CRP solutions show that the DLC-protected NW FET devices achieve a sensitivity of approximately 100 mV per the decade concentration change, demonstrating their functionality as stable highly sensitive biosensors. This study provides valuable insight into the design of dielectric-layer-based structures and the surface modification of SiO₂ at liquid–solid interfaces in FET biosensing systems. Moreover, the results highlight the importance of DLC protective layer engineering for the development of highly stable SOI-based device structures, including reliable field-effect transistor (FET) biosensors.

ABSTRACT. Physical neural networks (PNNs) traditionally aim to emulate the architecture of Multilayer Perceptrons (MLPs), where training is confined to linear weights and hardware nonlinearities are treated as fixed constraints. We recently reported on a paradigm shift by implementing Physical Kolmogorov-Arnold Networks (KANs) on Silicon-on-Insulator (SOI) technology. Unlike MLPs, KANs place learnable nonlinear functions directly on the edges of the network. We experimentally demonstrated this with Synaptic Nonlinear Elements (SYNEs), Figure 1, novel microscale SOI devices that exhibit highly reconfigurable nonlinear I-V characteristics. The intricate physics, rooted in non-equilibrium carrier transport and complex electrostatic interactions within the multi-gate SOI structure, generate rich nonlinearities including negative differential resistance (NDR) and multi-stable states. Crucially, the SYNE's configuration is augmented by a floating back-gate effect, wherein charge trapping within the dielectric layer modulates the local potential, possibly enabling long-term plasticity and persistent storage of the learned "function shape" rather than just a linear weight. By leveraging the inherent "nonlinear heterogeneity" of SOI devices, we have shown that the variability of physical substrates can be a computational asset rather than a limitation. Our physical KANs operate at room temperature with microampere currents and 2 MHz speeds, consuming approximately 750 fJ per nonlinear operation. We validate this architecture across diverse tasks: i.e., nonlinear binary classification tasks and the prediction of Li-ion battery dynamics from noisy sensor data. Our results demonstrate that Physical KANs outperform equivalently-parameterized software MLPs and require up to two orders of magnitude fewer devices than conventional linear weight-based physical networks. This work establishes learned physical nonlinearity as a hardware-native computational primitive for efficient, compact, and high-performance neuromorphic SOI systems. The SYNE Device has been fabricated on a 30 nm SOI layer doped with molecular doping adopting four active contacts topology to modulate its internal electrostatic landscape. By tuning control voltages (VC), the device’s transfer function can morph between various nonlinear shapes, including negative differential resistance (NDR). To support our understanding of the device operation, we have performed 3D simulations, Figure 2, using Synopsys Sentaurus TCAD. In the model we have included the SOI layer, the buried oxide and a portion of the doped Si substrate. Interface states at the Si/SiO2 interfaces, revealed by electrically detected magnetic resonance (EDMR), with a Gaussian energy distribution have been considered to model presence of Pb0 centers. The simulated device characteristics qualitatively reproduce the experimental data, revealing the critical role of the floating back gate and of the interface defects, exploited to achieve the required non-linear expressivity. More work is necessary to completely understand all the mechanisms leading to the observed functionalities. We construct KAN synapses by summing the outputs of multiple SYNE devices in parallel. This creates a highly expressive, learnable edge that replaces the standard "weight \times input" operation. The hardware achieved 99.0% accuracy on the Yin-Yang classification task. Notably, the Physical KAN reached target accuracy with 100x fewer physical parameters than a standard linear PNN. This research demonstrates that the future of SOI-based neuromorphic hardware lies in embracing and training natural nonlinear complexities. Physical KANs provide a mathematically grounded framework to exploit these complexities, leading to AI hardware that is significantly more resource-efficient than current digital or analog-linear counterparts.

ABSTRACT. Transition metal dichalcogenides (TMDs) are a family of 2D materials with the chemical formula MX2 where M is a transition metal and X is a chalcogen. The transition metal forms a central plane in each layer of a TMD and is covalently “sandwiched” between 2 chalcogen layers. TMDs such as WSe2 are highly promising for use in the next generation of low-power electronics [1] due to their tuneable bandgap and their stability in monolayer form. WSe2 is the material of interest in this study due to its low effective mass for holes which leads to high mobility [2]. Importantly, WSe2 is an ambipolar TMD, making it a more viable candidate in CMOS electronics compared to other n-type TMDs such as MoS2 [3]. Understanding the carrier transport mechanisms of WSe2 is key for the optimisation of WSe2-based device performance. While carrier transport in WSe2 has been studied at around room temperatures, investigations at cryogenic temperatures are critical to isolating and understanding the transport bottlenecks arising from non-ideal metal-semiconductor contacts [4]. In this work we report on the fabrication and comprehensive electrical characterisation of a back-gated WSe2 field-effect transistor (FET) (Figure 1a). The device channel is a mechanically exfoliated, bulk WSe2 flake confirmed by Raman spectroscopy (Figure 1b) with Ni/Au source and drain contacts. We performed electrical measurements across a broad temperature range from room temperature down to cryogenic temperatures. Selected transfer characteristics of the device at Vd = 1V is presented in Figure 1c, exhibiting ambipolar behaviour. Our analysis reveals that the transport mechanisms are heavily temperature dependent and there are 3 distinct transport regimes: tunnelling at ultra-low temperatures (< 20 K), nearest neighbour hopping at low temperatures (20 K < T <60 K) (Figure 1d) and thermionic emission over the Schottky barrier at high temperature. To corroborate our experimental findings, density functional theory (DFT) simulations of the Ni/WSe2 interface were performed. The results are in strong agreement with device parameters extracted from experimental data.

ABSTRACT. This paper presents an analytical model for the input impedance and output voltage of RF– DC half-wave rectifiers for low-power energy harvesting. The model incorporates the diode dynamic resistance and junction capacitance to capture the rectifier nonlinear behavior. Closed-form expressions for the real and imaginary components of the input impedance are derived as functions of the input amplitude. The model is validated through SPICE simulations for different Schottky diodes, showing good agreement with the analytical results, and can be applied to FD-SOI MOS-connected transistors.

ABSTRACT. Methodologies to extract the access resistance (Raccess) dependence on the applied gate voltage (VGS) bias in ohmic operation regime are already available in the literature, but a dedicated Kelvin test structure is necessary [1]. A very strong impact on the estimated DC parameter extraction is pointed out in [2] if the Raccess dependence on the applied VGS is considered. However, the extracted parameters using (2) of [2] exhibit a strong dependency on the applied VGS range during the measurement [3]. In this work, the impact of assuming a constant Raccess rather than one dependent on VGS on the values of the extracted DC parameters is evaluated using methodology of [4]; the impact on the estimated 1/f noise parameters is also evidenced.

ABSTRACT. In this work, we comprehensively investigate the impact of spacer engineering of electrical performance on InGaAs Nanosheet FETs (NSFETs). The high-κ spacers significantly mitigating OFF Current (IOFF), as well as boosts the drive current of the target device. This is owing to the spacer induced fringing electric field at the source/channel and channel/drain junctions. This field also improves the electrostatic control at the channel and source/drain extension regions. We also observed, the intrinsic gain and unity gain bandwidth improves with the specific choice of spacers.

ABSTRACT. The strong downscaling and/or the typical substrate isolation of the new device architectures may change the impact of dielectric breakdown (BD) in the device and circuit performance. In this regard, recently, for FDSOI transistors, the authors reported the key role of the power dissipated after BD, leading to large detrimental effects that jeopardize not only the device functionality, but also the device and materials integrity. In this work the impact of BD in circuits, such as inverters or logic gates, fabricated with a 10nm high-k omega-gate FDSOI technology is analysed. Results show that the large variability of post-BD conductive states in FDSOI devices can lead to the malfunction of the circuit, being necessary to account for it in the early design stages to mitigate its impact on circuit reliability.

ABSTRACT. AlGaN/GaN High Electron Mobility Transistors (HEMTs) are the cornerstone of high-power RF electronics due to the two-dimensional electron gas induced by spontaneous piezoelectric polarization (2DEG) [1] and make it ideal for high-power, high-frequency PV applications, improving efficiency, power density, and reliability in next-generation PV systems. However, performance is often limited by the Self-Heating Effect (SHE) under high drain bias. Substrate selection is critical for thermal management; while Silicon Carbide (SiC) offers high thermal conductivity, alternative platforms such as Al2O3 (Sapphire) integrated with layered buried oxide (BOX) are being explored for enhanced carrier confinement [2]. In this work, a comparative TCAD simulation study is performed between a conventional GaN-on-SiC HEMT and a buried-channel GaN-on-Insulator (GaNOI) structure. The active stack for both devices remains identical: a 100 nm Si3N4 passivation layer, a 26 nm Al0.24Ga0.76N barrier, and a 1 nm AlN spacer on a 100 nm GaN channel. This study quantifies the trade-off between electrical confinement and thermal degradation when replacing the SiC substrate with an Al2O3/SiO2 platform.

ABSTRACT. We have performed a comprehensive study of the impact of different ground-plane (GP) doping types, buried-oxide thickness, and back-gate bias on 1/f noise in a pMOSFET using Sentaurus TCAD simulations calibrated to experimental data. The adopted pMOSFET is based on the 22 nm FDSOI technology with a gate length of 100 nm and a width of 170 nm. We show that a pMOSFET with an nGP has more noise compared to the pGP and noGP cases. From the hole density profile, we show that quantum confinement of holes at the front interface is responsible for this degradation. We also discuss the impact of back gate bias and box thickness on 1/f noise.

ABSTRACT. Resistive Random-Access Memory (RRAM) is regarded as one of the most promising technologies for artificial intelligence and neuromorphic computing, as it enables the emulation of synaptic plasticity and supports highly parallel architectures with low power consumption. Moreover, RRAM has the potential to overcome the limitations of conventional von Neumann architectures. The inherent randomness in the formation and rupture of conductive filaments requires effective control, which may be achieved by electrode optimization [1]. Deposition process parameters significantly influence surface roughness, and precise adjustment of this parameter is crucial for achieving properly functioning structures [2]. Moderate roughness enables guided filament formation through local electric field enhancement and increases the repeatability and stability of resistive switching cycles. However, this effect may lead to a higher device failure rate [1,3]. The optimization was carried out using the Taguchi L9(3⁴) orthogonal array (Tab. 1). The films were deposited on silicon substrates and characterized using atomic force microscopy (AFM), measuring the RMS surface roughness. For each experiment, two measurements were performed over scan areas of 1 × 1 µm and 10 × 10 µm. The surface roughness results are summarized in Tab. 1. Based on the obtained results, the trends in surface roughness were identified. For aluminum film, increasing the sputtering power, decreasing the chamber pressure, reducing the argon (Ar) flow rate, and lowering the substrate temperature led to a reduction in surface roughness. Consequently, two additional experiments were designed: one following the identified trends and one opposing them, to evaluate the surface with the lowest and highest roughness (Tab. 2). The configuration designed to achieve the lowest roughness yielded a surface roughness value lower than that observed for all previously tested conditions, whereas the configuration corresponding to the maximum roughness resulted in the highest measured roughness value. Furthermore, AFM images (Figs. 1 and 2) reveal significant differences in grain size and surface morphology, confirming the strong influence of process parameters on film roughness. Electrical characterization of AlOx-based RRAM structures demonstrates that the roughened electrode exhibits significantly lower dispersion of the set and reset voltages (Figs. 3 and 4). The device with the highest roughness (Fig. 5) also exhibits a clearer separation between the high-resistance state (HRS) and low-resistance state (LRS), resulting in a more clearly distinguishable memory window. Control of surface roughness enables more precise guidance of conductive filament formation, leading to improved regulation of RRAM device structures and more predictable electrical behavior.

Acknowledgment This research was carried out within the framework of the FAMES Pilot Line of the Chips JU, funded by Horizon Europe under grant agreement 101182279, Digital Europe under grant agreement 101182297, and Ministry of Science and Higer Education Republic of Poland under Grant Agreement No. MNiSW/2025/DIR/849, co-funded by the National Science Centre, Poland, under grant no. 2023/51/D/ST7/02706, and partially funded by the Warsaw University of Technology Excellence Initiative – Research University (IDUB) program, under agreement no. CPR-IDUB/306/Z07/2024.

References: [1] W. Ham, et al. Applied Surface Science 670 (2024) 160595. [2] S. K. Nandi, X. Liu, D. K. Venkatachalam, R. G. Elliman, Phys. Rev. Appl. 4 (2015) 064010. [3] Asgary, S., et al. Appl. Phys. A 127, 752 (2021).

ABSTRACT. The ongoing advancement in CMOS technology has driven the evolution of device architectures that maintain performance while increasing integration density. The complementary FET (CFET), in which nFETs are stacked on top of pFETs and vice versa, enables high device density at advanced technology nodes. The conventional CFET relies on junction-based source/drain regions, which increase fabrication complexity and parasitic capacitance. To address these challenges, a junctionless CFET (JL-CFET) architecture is proposed for the first time in this paper (Fig. 1a-b). In JL-CFET, the source, drain, and channel regions are uniformly doped [1], eliminating abrupt p–n junctions and enabling device operation through volume depletion of the channel. Sentaurus TCAD [2] is used to simulate and calibrate the IDS-VGS of the CFET (Fig.1c) against experimental data [3]. The transfer characteristics of JL-CFET exhibit lower ON current due to differences in carrier transport mechanisms, channel depletion, and series resistance (Fig. 2a). The energy band profile of JL-CFET exhibits smoother band variation with an extracted energy difference of about 0.07 eV, indicating reduced band bending due to the absence of abrupt p–n junctions (Fig.2b), resulting in a lower threshold voltage (VTH) of JL-CFET compared to CFET (Fig.2c). The JL-CFET shows significantly lower capacitance than CFET because the junctionless structure eliminates source–drain junction depletion capacitances and operates under full channel depletion (Fig.2d). As silicon thickness decreases, thermal conductivity decreases (Fig.3a). This relationship has been validated through experimental data pertaining to both doped and undoped silicon [4]-[5]. Fig.3b shows the temperature distribution at JL-CFET when nFET is ON and pFET is in OFF condition. Increasing LEXT reduces both temperature rise and dissipated power, as longer extension regions slightly decrease current flow and Joule heating (Fig.3c). As the channel width increases, the current and generated heat increase, resulting in higher mobility degradation and larger ION reduction (Fig.3d). Increasing channel thickness (TCH) improves gm due to a larger conduction path but degrades subthreshold slope (SS) because thicker channels weaken electrostatic gate control (Fig.4a), resulting improved figure of merit (FoM) with TCH, i.e. switching performance as the increase in ON-current dominates over the capacitance variation (Fig.4b). The high-frequency performance metric (gm/Cgg) of CFET over JL-CFET, this is due to its larger ON currents, although JL-CFET still demonstrates competitive RF performance (Fig.4c). Overall, the results demonstrate that the JL-CFET architecture provides lower capacitance, competitive electrical performance, and manageable self-heating, making it a promising candidate for future nanoscale logic technologies.

ABSTRACT. The demand for high-reliability Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits (ICs) in space, nuclear, medical, and military applications has driven the development of Radiation-Hardness-By-Design (RHBD) techniques to mitigate Total Ionizing Dose (TID) effects. While the Enclosed Layout Transistor (ELT) is a traditional alternative to the Rectangular MOSFET (RM) due to its ability to suppress leakage, it introduces significant modeling complexities and layout asymmetries. Consequently, the Diamond (hexagonal gate) MOSFET (DM) has emerged as a promising RHBD alternative, leveraging the Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) and the Longitudinal Corner Effect (LCE) and Parallel Connections of MOSFETs with different Channel Lengths Effect (PAMDLE) to enhance electrical performance and ionizing radiation tolerance. This study presents a statistical analysis of MOSFETs, channel (NMOSFETs) fabricated in a commercial 350 nm Bulk CMOS ICs process, comparing DM and RM layout styles with varying alpha angles (α) under cumulative gamma radiation up to 1.814 Mrad. The experimental procedure followed MIL-STD-883 and ESA-22900 standards, utilizing a 60Co gamma-ray source at a low dose rate of 1 krad/h. During irradiation, the devices were maintained in an analog-state (VGS = 2.5 V and VDS = 3.5 V: vertical and longitudinal electric fields applied in MOSFETs), on-state (VGS = 2.5 V and VDS = 0 V: vertical electric field applied in MOSFETs), and off-state (VGS = 0 V and VDS = 3.5 V: longitudinal electric field applied in MOSFETs). To quantify the robustness of these layouts, the Coefficient of Variation (CV = σ/µ) was used as the primary metric of parametric stability, with lower CV indicating greater structural resilience. Experimental results indicate that the Diamond layout with α = 90° achieves exceptional consistency, particularly regarding the threshold voltage (VTH) and leakage current (ILEAK). Specifically, the DM 90° structure exhibited a significantly lower VTH variation than its RM counterpart (Fig.1), attributed to the hexagonal geometry effectively limiting lateral parasitic paths. Under on-state conditions, the RM layout showed a leakage current increase of approximately 3.5 decades, whereas the DM 90° maintained a small variation of less than 0.5 decades (Fig.2). This superior performance is a direct result of the DEPAMBBRE effect, which prevents the activation of parasitic transistors in the bird’s beak regions. Furthermore, the study observed that DM layouts with angles less than 90° (e.g., 36.9° and 53.1°) are more susceptible to TID effects due to an increased resultant electric field resulting from the synergy between LCE and the PAMDLE. Statistical comparisons of the subthreshold slope (SS) further confirm the resilience of the Diamond geometry, as the DM 90° achieved the lowest variability among the tested sets (Fig.3 and Table I). While devices with α tend to 180° show a reduction in the DEPAMBBRE effect, increasing their sensitivity to radiation, the DM 90° remains the optimal balance between electrical performance (Fig.4 and Fig.5) and radiation hardness. The high consistency of these parameters even at Mrad dose levels positions the Diamond layout style as a highly effective, area-efficient, and predictable alternative for CMOS integrated circuits. In conclusion, this experimental study demonstrates that the Diamond layout style, particularly with a 90° alpha angle, provides superior statistical robustness and stability compared to conventional rectangular styles, making it a robust candidate for applications in extreme radiation environments. Quantitatively, at 1.814 Mrad, the DM 90° limits VTH shift to -70 mV and ION/IOFF loss to 1.0 decade, while the RM reaches -530 mV and 3.7 decades, respectively.

ABSTRACT. This work focuses on the design, fabrication, and characterization of the 1T1R (one transistor-one resistor) structure. The MIM stack (Cr/Al₂O₃/Al) was deposited by reactive magnetron sputtering. A crucial step was the final RTP annealing. This treatment partially reorganizes the initially amorphous Al2O3 layer and may promote localized γ-Al2O3 phase formation, improving switching stability. Impedance spectroscopy confirmed improved material quality, showing regularity and repeatability after annealing. Moreover, switching endurance increased significantly and stable operation was achieved. The obtained impedance spectra were modeled and analyzed to understand the device behaviour. The developed simple experimental platform can be utilized for further optimization of RRAM material stacks and device parameters, with potential applications in neuromorphic systems and in-memory computing architectures.

ABSTRACT. To mitigate the deleterious effects of ionizing radiation, Radiation-Hardness-By-Design (RHBD) techniques such as the Enclosed Layout Transistor (ELT) and the Diamond (hexagonal gate) MOSFET (DM) have been proposed as alternatives to the conventional Rectangular MOSFET (RM). While ELTs effectively eliminate Bird's Beak Regions (BBRs) to suppress leakage, they introduce inherent layout asymmetries and significant modeling complexities that often hinder standard analog design flows [1]. Conversely, the Diamond layout strategically leverages the Longitudinal Corner Effect (LCE) and Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) to enhance analog electrical performance (LCE AND PAMDLE) and ionizing radiation tolerance (DEPAMBRE), while preserving geometric symmetry. The devices under study, comprising RM, ELT, and DM structures, were fabricated using a commercial 180 nm Bulk CMOS integrated circuit (IC) process from TSMC. The Diamond layout was specifically engineered with an alpha angle (α) of 90° to optimize the DEPAMBBRE effect, which is critical for minimizing threshold voltage (VTH) variations (ΔVTH). High-dose irradiation tests were performed using a Co-60 gamma-ray source at the Ionizing Radiation Laboratory (LRI) of the Institute of Advanced Studies (IEAv), in accordance with MIL-STD-883 and ESA-22900 standards. During the cumulative irradiation procedure up to a Total Ionizing Dose (TID) of approximately 2 Mrad, the MOSFETs were maintained under worst-case analog-state bias conditions, VGS = VDS = 2.5 V and VS = 0 V. Regarding the Subthreshold Slope (SS), the Diamond layout (DM) demonstrated the highest structural resilience, achieving the lowest Coefficient of Variation (CV) of 0.172 (Table I), which signifies superior parameter stability under radiation compared to the RM counterpart (Fig.3 and Fig.5). This result is primarily attributed to synergy among the LCE, PAMDLE, and DEPAMBBRE, which collectively maintain a more consistent subthreshold electrical behavior despite the accumulation of trapped charges in the gate oxide and at the interface. In secondary comparative sets, the ELT presented a CV for SS of 0.207, whereas the DM maintained a significant improvement over the RM counterpart, which exhibited a much higher variability (CV of 0.326 vs. 0.411, respectively) (Table I, Fig.3 and Fig.4). For the VTH, the DM achieved the best performance with an exceptional CV of 0.017 (Table I). The high consistency of VTH in Diamond structures, even at Mrad dose levels, confirms that the hexagonal geometry effectively limits the impact of lateral parasitic paths that typically induce larger parametric shifts in rectangular devices (Fig.1 and Fig.2). This study experimentally demonstrates that the Diamond and ELT layouts provide enhanced radiation hardness compared to the conventional rectangular style. The Diamond layout stands out for its low SS variability and high VTH stability, making it a highly effective, area-efficient, and predictable RHBD alternative for space, nuclear, and medical CMOS IC applications.

ABSTRACT. This paper studies the effect of cryogenic temperatures on common source current mirror circuits based on Junctionless Nanowire Transistors (JNTs) with different channel lengths. At cryogenic temperatures, the current transfer ratio and conductance improve or degrade depending on the neutral impurities and the electron saturation velocity with respect to higher temperatures (200 K). However, the variations in conductance and current transfer ratio are small at cryogenic temperatures, which can be explored in Quantum Computing applications.