ABSTRACT. Doping normally serves to lower the semiconductor resistivity. We consider the opposite trend, that is increasing doping and resistivity concomitantly. The goal is to use the ground-planes of FD-SOI wafers for producing virtual RF substrate and co-integrating logic and RF circuits. The electron and hole concentrations are governed by the intrinsic carrier density and charge neutrality: n ∙ p = ni2 and n − p = ND − NA. In the extreme case of perfectly balanced donor and acceptor dopants (ND = NA), the carrier concentration reaches a minimum value (n = p = ni) and the resistivity is very high (1/ρ = qni (µn + µp)). Moreover, increasing the doping level above 1017 cm−3 will massively degrade the carrier mobility, leading to a paradox: resistivity does increase with doping (Figure 1). This counter-intuitive prediction is purely theoretical since a perfect doping balance is hard to achieve in silicon. With only 1% unbalance of 1017 cm−3 doping, the net resistivity is 10 Ωcm. Fig. 1 shows that the resistivity increase with doping would require an extremely good doping compensation; however, for 99.999% rate already demonstrated [1], the resistivity is as high as around 104 Ωcm. The strategy of doping compensation has already been implemented for extending the depletion region in solar cells, radiation sensors, photodiodes, etc. [1-3]. Our application is different, oriented to the reunification of RF-SOI and FD-SOI wafers. RF-SOI substrates feature high resistivity and multiple flavors of trap-rich layers underneath the BOX [4]. However, the trap-rich solution which is necessary to keep the high resistivity feature of the substrate beneath the BOX is incompatible with the implantation of back-gates in the case of FD-SOI. Indeed, because of the polysilicon grain boundaries of the trap-rich layer, the leakage current between the back-gate electrodes and the substrate will be too high [5]. Our aim is to co-integrate logic and RF devices in a single, revolutionary chip. Doping compensation stands as an alternative to trap-rich layers. The idea is to superpose the heavy N- and P-type doping of ground-planes for mimicking a high resistivity substrate right underneath the BOX. The two ground-planes will be located side-by-side underneath the logic section and superimposed in RF section, as illustrated in Figure 2. Simulations were conducted with Synopsys tools on a high-resistivity substrate featuring a nominal resistivity of 103 Ωcm. The implant dose and energy are fine-tuned to achieve maximum compensation between boron and phosphorous atoms before or after annealing. An example is shown in Figure 3. As annealing time increases, the diffusion of B and P dopants becomes similar (Fig. 3 (a)), thereby enabling a high compensation rate. Despite a high peak concentration of dopants (1018 cm−3) in the subsurface region, the electron and hole concentrations are orders of magnitude lower (< 1013 cm−3 in Fig. 3 (b)). The resulting resistivity underneath the BOX is remarkably high (104–106 Ωcm) over 300 nm depth, see Fig. 3 (c). Albeit the balance of B and P dopants is hard to maintain along the whole depth, the effective resistivity extracted by simulating S-parameters of coplanar waveguide transmission line is higher than 103 Ωcm, as shown in Fig. 3 (d). In summary, the creative approach of doping-compensation for logic+RF co-integration is surprising, challenging to implement, but not impossible.

ABSTRACT. This work presents the cryogenic RF characterisation of integrated inductors and MOS varactors in the 28-nm FD-SOI technology from STMicroelectronics, targeting VCO and PLL implementations for quantum computing control systems. Devices were measured down to 4.2 K using on-wafer RF probing to evaluate temperature-dependent variations in inductance, capacitance, series resistance, and frequency behaviour. While inductance values and self-resonance frequencies remain largely unchanged at cryogenic temperature, metal resistivity reduction improves inductor series resistance. Varactor performance exhibits device-geometry-dependent trends, with competing effects from reduced material resistivity and carrier freeze-out in the n-well impacting series resistance and depletion capacitance. These results quantify the evolution of passive component parameters from room temperature to 4.2 K, enabling adaptation of conventional RF design methodologies to cryogenic operation. Combined with future cryogenic characterisation of active devices, this work supports predictive retro-simulation of complete VCO architectures and advances the development of cryo-CMOS circuits for scalable quantum computing systems.

ABSTRACT. III–V semiconductors such as InGaAs are promising candidates for next-generation logic and RF applications due to their intrinsically high electron mobility [1]. In aggressively scaled devices, a self-aligned process is critical to minimize parasitic overlap capacitance (Cov) and enhance high-frequency performance. However, the elevated thermal budget typically associated with self-aligned fabrication can lead to a degradation of the semiconductor–oxide interface properties [2], which deteriorates DC and RF performance. This work compares Gate-First (GF) and Gate-Last (GL) InGaAs MOSFETs architectures, demonstrating that although GF devices exhibit degraded interface properties when compared with their GL counterpart, their lower Cov enables superior cut-off frequency (fT), indicating that geometric optimization can outweigh interface quality limitations in RF operation.

ABSTRACT. We experimentally demonstrate a novel interface passivation technique based on field-effect depletion regions (FEDRs) to mitigate parasitic surface conduction in high-resistivity silicon substrates. In this approach, alternating dielectric layers of SiO₂ and Al₂O₃ with opposite-polarity interface fixed charges are implemented at the silicon substrate surface. This structure induces periodic depletion regions at the high-resistivity silicon (HR-Si) surface through field effect, leading to enhanced surface silicon resistivity. On-wafer coplanar waveguide (CPW) small- and large-signal measurements demonstrate state-of-the-art RF performance comparable to the Trap-Rich technique.

ABSTRACT. As scaling of FDSOI transistors reaches its physical limits, new approaches are needed to improve performance at advanced technology nodes. One key strategy is to introduce mechanical stress into the channel to enhance carrier mobility, using tensile stress for nMOS and compressive stress for pMOS devices. In this study, we transferred approximately 1.1 GPa of compressive stress to the channel via the BOX Creep process for the pMOS performance. We examined the effect of various key process parameters, such as PadOx and thermal budget on the final stress. For nMOS mobility improvement, which requires tensile stress, we observed compressive strain in the channel. This strain resulted from the evolution of intrinsic stress in the PECVD SiN layer during thermal annealing.

ABSTRACT. Strain engineering is one of the major technological steps on the roadmap for future FDSOI devices. In this study, we report a unique way of inducing stress in a silicon (Si) thin film, at the 8-inch wafer scale and without the nucleation of defects in the crystalline lattice. The used method is the Surface Activated Hot Bonding (SAHB) of materials having coefficient of thermal expansion (CTE) mismatch.

ABSTRACT. This study demonstrates that while S/D implantation and spike annealing effectively reduce access resistance in 25nm FD-SOI NMOSFETs, the associated thermal budget triggers short-channel effects due to enhanced lateral dopant diffusion. Some electrical parameters are impacted by this effect. Transport analysis reveals a 50 % improvement in the first-order mobility attenuation coefficient through crystal lattice healing, which is counterbalanced by a degradation in the surface roughness coefficient. These results establish a critical trade-off between series resistance optimization and electrostatic control.

ABSTRACT. This work investigates self-heating (SH) and thermal coupling (TC) in fully depleted silicon-on-insulator (FD-SOI) transistors, focusing on their location within the silicon active area (SAA). The gate resistance thermometry technique [1] is used to extract thermal resistance, and the resulting temperature rise in operating MOSFET (“heater”) and nearby “sensors” at different distances from the “heater”. A temperature rise (ΔT) of ~45 °C above ambient is observed for the “heater” and rapidly decreases with distance. Moreover, the device located near the SAA edge exhibits a ~6 °C higher temperature rise than the centrally located device, with no significant impact on the electrical figures of merit (FoMs).

ABSTRACT. This work provides a deep assessment of RF technique for self-heating (SH) extraction in advanced FD-SOI MOSFETs focusing on the uncertainties introduced by the extraction procedure. Particularly, we investigate the impact of i) choice of thermal resistance, Rth formula and ii) extraction of drain current variation with temperature, gt = dID/dT. We show that the two valid output conductance gds-based formulations for thermal resistance, when applied to experimental data, exhibit discrepancies that increase at higher gate voltages and shorter gate lengths. Extracted uncertainty ranges from ~3% for 100 nm device to ~22% for the shortest lengths, underlining the importance of both consistent formulation and accurate gt extraction at aggressively scaled nodes.

ABSTRACT. Advanced patterning is one of the key enablers for scaled FD-SOI technologies. To meet aggressive logic density targets i.e. Lg = 20 nm and contact poly pitch (CPP) of 68 nm, self-aligned double patterning (SADP) is adopted for gate-level patterning.

A critical challenge lies in mandrel formation, which rely on organic or inorganic materials, with mandrel patterning and removal strongly impacting profile control, residue formation, and critical dimension (CD) stability. This work investigates mandrel integration in 10 nm FD-SOI, comparing spin-on carbon (SOC) and amorphous silicon (a-Si) mandrels. The focus on etches and removal optimization and their impact on SADP process integration has led to a first transfer demonstration.

ABSTRACT. Silicon-on-insulator (SOI) wafers underpin CMOS, MEMS, and RF technologies, yet conventional fabrication routes—such as SIMOX (separation by implanted oxygen), Smart Cut™, and wafer bonding—introduce implantation-induced defects, interfacial void risks, and costly multi-step processing, challenges that intensify for multilayer SOI where repeated implantation or bonding constrains scalability and reliability. Here, we present an implantation- and bonding-free fabrication strategy for multilayer SOI based on annealing-driven self-assembly and internal thermal oxidation. Lithographically defined silicon hole arrays evolve into membrane–cavity architectures during high-temperature annealing, after which oxygen is delivered through circumferential edge ports to form continuous buried oxide (BOX) layers beneath crystalline silicon membranes. A single oxidation cycle produces uniform BOX layers and enables reproducible fabrication of both single- and double-layer SOI substrates without ion implantation or wafer bonding. Cross-sectional electron microscopy and optical interferometry confirm uniform layer stacking and wafer-scale thickness control, while atomic force and scanning acoustic microscopy verify smooth membrane surfaces (<0.6 nm RMS) and void-free BOX interfaces (Figure 1). Notably, the use of high-aspect-ratio hole arrays enables double-layer SOI formation within a single thermal cycle, establishing a geometry-driven pathway extendable to scalable multilayer platforms for next-generation CMOS, MEMS, and optoelectronic integration.

ABSTRACT. There are several proposed platforms for realizing qubits, the basic units of quantum information processing, and to perform quantum computation. While there has been great scientific progress and proof-of-concept demonstrations on all these platforms, to address the challenge of scalability it makes sense to use all the machinery of traditional semiconductor. Charge or spin-qubits can be realised by using gate-defined quantum dots (QDs) in semiconductors in a similar fashion to the processes used in CMOS for conventional field-effect transistors (FETs) or state-of-the-art finFET technology. In the last few years, Ge has progressed immensely from a conceptually new material for qubits to demonstrations of two-qubit logic and most recently first demonstration of a four-qubit quantum processor. Furthermore, the GeSn alloy is a material platform that carries the promise of highly desirable extreme mobility, low effective mass and added optical control for the qubits operation. The ultimate realization of quantum circuits will require processes with high fidelity at ultimately small widths and spacings between the neighbouring structures to accommodate larger number of qubits. Herein, we report on the development of processing modes for realising GeSn quantum devices using the basic architecture of a nanowire/fin FET device and substrates with epi-grown Ge/GeSn/Ge on Si layers. The GeSn fabrication sequence is based on using the highest resolution electron beam lithography (EBL) resist, hydrogen silsesquioxane (HSQ), reactive ion etching (RIE), selective Ge-to-GeSn wet chemistry, and atomic layer deposition (ALD) of gate materials (gate oxide and TiN metal), and purposely developed dielectric-GeSn modifications for reduced interfacial traps. The structural and morphological properties were investigated at each step by correlating electron microscopy, AFM, Raman microscopy, XPS and carrier profiling. Intentionally designed test vehicle devices were fabricated to test the electrical performance, acquiring information about the quality of the dielectric-GeSn or metal – GeSn interfaces as well as quality of the TiN gates developed.

ABSTRACT. The studied devices are FDSOI MOSFETs from the 28 nm technology, fabricated by CEA-Leti, with a 25 nm-thick buried oxide (BOX). The gate stack consists of a thin SiO2 layer followed by HfO2, yielding an EOT of 1.05 nm. The metal gate is TiN covered by polycrystalline silicon. The channel width and length are identical (W=L=4.5\ \mu m). Samples with silicon thicknesses (\operatorname{t}_{Si}) of 5.5 nm and 7.5 nm were fabricated by the same process. Using drain current versus gate bias (Figure 1) and capacitance measurements, the Split-CV method [1] was applied to extract the carrier mobility versus carrier density (\operatorname{N}_{inv}) for both \operatorname{t}_{Si} values, as shown in Figure 2. It can be observed that for \operatorname{t}_{Si}=7.5\ nm, the mobility is higher than for \operatorname{t}_{Si}=5.5\ nm in the entire \operatorname{N}_{inv} range. This confirms that mobility is affected by silicon thickness, as reported by Uchida et al. [2]. The samples were cooled to cryogenic temperatures down to 4.2 K, and Figure 3 shows carrier mobility versus carrier density at each temperature. Figure 4 shows the maximum mobility versus temperature on the left axis, and the percentage difference in mobility, with tSi = 7.5 nm, as a reference. From Figure 4, is noticeable that as the temperature decreases, the trend reverses: at 100 K and 50 K, the thinner device achieves higher mobility than the thicker one, around 10% [3], [4]. However, in the deep cryogenic regime (below 20 K), the mobility of the thinner device is only slightly higher than that of the thicker one (around 5%), with some data overlapping between the samples. Using Matthiessen's rule [5], [6], a model was developed to decompose the mobility at 300 K and at 4.2 K into three main scattering mechanisms: Coulomb, phonon, and surface roughness. The results are shown in Figure 5. The analysis indicates that at room temperature, the two primary limiting mechanisms are phonon and Coulomb scattering. In the cryogenic regime, where phonon scattering is negligible, Coulomb scattering limits the carrier mobility of the thicker device more. To gain insight into the physical origin of the observed phenomena, the conduction centroid position perpendicular to the channel was estimated using a Poisson-Schrödinger solver [7]. Figure 6 shows that the variation in the centroid position is higher for tSi = 7.5 nm, making the carriers more exposed to Coulomb scattering [8] induced by the Si/oxide interface. In other words, while at room temperature the thicker device exhibits higher mobility due to a centroid positioned away from the interface—reducing surface roughness and Coulomb scattering—the thinner device demonstrates superior centroid stability, mitigating the interface-induced degradation observed in the thicker film at deep cryogenic temperatures.

ABSTRACT. This work extends the analysis of in-situ local annealing down to 4 K and demonstrates for the first time trap healing through in-situ heating at cryogenic temperature. Annealing is performed on a 30 nm long and 2 µm wide typical N-type MOSFET in 28 nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology with standard high k metal gate thin oxide from STMicroelectronics. Dedicated structure with splitted source and drain contact are used to apply a 1.5 V bias ramp between the two respective source and drain contacts at 4 K, leading to a temperature rise estimated above 450 K based on source thermometry measurements. The impact of active in-situ electro-thermal recovery is demonstrated through the electrical and low-frequency noise characteristics of the device measured at 4 K and 295 K, showing a 58 % noise power reduction and clear RTN mitigation at cryogenic temperature, while the typical 1/f power spectral density is preserved at 295 K.

ABSTRACT. This work presents a coupled DC and low-frequency-noise study of vertical gate-all-around silicon nanowire pMOSFET arrays from 300 K down to 4.2 K. The results show a monotonic threshold-voltage shift toward more negative values as temperature decreases, together with a reduction in transconductance and mobility, while the subthreshold swing improves and saturates at low temperature. The extracted access resistance exhibits a non-monotonic behavior, first decreasing down to about 160 K and then increasing again toward 4.2 K. Low-frequency-noise analysis shows that access-related noise is reduced at intermediate cryogenic temperatures, whereas channel-related fluctuations dominate at lower temperature. The marked increase in interface-trap-related noise indicators at 20 K points to stronger coupling between inversion charge and interface traps. Overall, the results indicate that cryogenic optimization of vertical GAA pMOSFET arrays requires both improved interface quality and reduced access-region fluctuations.

ABSTRACT. GaN High Electron Mobility Transistors (HEMTs) are primary contenders for applications in low-temperature electronics, low noise amplifiers and quantum computing. Recent studies show trapping effects and threshold voltage instability in GaN HEMTs at cryogenic temperatures. In this paper, we report a superior AlGaN/AlN/GaN HEMT structures with 25 nm AlGaN (25% Al) barrier layer, and passivated using SiN, that show nearly invariant threshold voltage under cryogenic temperatures down to 77 K. To explain the ultra-low threshold voltage shifts observed experimentally, a model that includes temperature dependence of Schottky barrier height, conduction band discontinuity, pinch-off voltage and polarization charge-dependent potential has been applied. The analysis based on the model shows a threshold voltage shift of -0.072 V, in close agreement to the experimentally obtained value of <0.1 V. The results show a promising HEMT device structure for applications in extreme environments.