ABSTRACT. This paper considers the interaction between a memristive device (MD) and a transistor and the further development of the Stanford model (SM) for MDs, so that the improved SM (ISM) gives more insight to device physics. This 1-transistor-1-resistor (1T1R) structure is needed to limit the current through the MD [1]. MDs are non-volatile memories that can change their state by altering a conductive filament (SET corresponds to the formation and RESET to the break) inside [2]. For investigation, the switching-cycle measurement of MD with compliance current limiting was used, to which the SM was fitted (Figure 1 (a)). This fitting was used to investigate the behavior of the 1T1R structure with a NMOS transistor (Figure 1 (a)-(b)). It is noticeable here that the current continues to rise with increasing voltage after the state changes at positive voltage (SET cycle). This effect is controlled by the current limitation by the transistor and is essential for a programming scheme via pulses [3]. In the SM, the current through the MD changes depending on the gap distance between the filament tip and the electrode. As the gap decreases, the current increases. It has been noticed that the gap in the SM can become negative (Figure 2). This does not make sense from a physical point of view, which is why the SM must be optimized for the calculation of the current. This optimization is necessary because performing the SET multiple times (Figure 2) leads to a further reduction of the gap value, meaning that it is not sufficient to set the minimum gap value. In order to describe the change in the filament geometry more physically, equations were developed for the ISM that first change the gap to a minimum value and then change the diameter of the filament and thus its area (Figure 3). To test the ISM, the SM and ISM were fitted in combination with an NMOS transistor model to 1T1R measurements [4] (repeated 65 times) (Figure 4). Both give the same results, but in case of ISM there is physically meaningful change in filament geometry. Changes in the filament are displayed in Figure 5. In SET cycle after reaching minimum gap distance the filament diameter increases, providing increased cross-section for current flow. Finally, the influence of parasitic effects was investigated (Figure 6). In summary, the influence of the transistor was investigated and the ISM was developed, which describes the physics of MDs more accurately and is helpful for further investigations.

ABSTRACT. Scaling silicon spin-qubit processors is limited by the wiring complexity and thermal load of cryogenic control electronics. Memristor-based cryogenic programmable-gain amplifiers can reduce DC wiring by generating gate voltages locally inside the cryostat. Here we demonstrate interface-engineered Pt/HfO₂/Ti/Pt memristors with ultra-low-noise multilevel operation at cryogenic temperatures. A nanometer-scale Pt interlayer suppresses resistance variability, yielding stable operation at 300 K and 4 K and reducing read noise to ~0.3% at 4 K, which enables sub-100 µV voltage resolution for scalable qubit biasing.

ABSTRACT. Al-rich AlN thin films were deposited by Molecular Beam Epitaxy on SiNx ReRAMs, in order to better control the resistance switching characteristics and to prove that the conductive filament isn't metallic. Different anneal environments, including nitrogen and forming gas, were tested as well. The addition of AlN on SiNx lead to lower SET voltages and forming gas annealing reduced the variability of both SET and RESET voltages. In addition, the breakdown characteristics were improved as well, especially for forming gas annealing.

ABSTRACT. Memristors using 2D materials are promising for artificial synapses due to their CMOS compatibility and lack of dangling bonds, which improve scalability unlike the ultrathin oxides [1],[2]. Mechanically exfoliated 2D materials, allow simpler fabrication of high-quality dangling-bond-free devices compared to chemical vapour deposited 2D materials [3]. For artificial synapses based on 2D memristors it is important to achieve a dynamic range of conductance (G) ratio (GMax/GMin) of at least 10 [4]. Most of the 2D-based devices exhibit a low GMax/GMin ratio [3]. In this study, an improvement of memristive characteristics of a Ti/MoS2/Pt stack [3] is achieved by initially adding a thin (2-3 layers) h-BN between the Pt and MoS2 layers. This device (device 1, inset Fig. 1.(a)) shows an increased memory window compared to our previous results without the h-BN interlayer [3] by up to a factor of 9.3. The current was extracted at +1.5 V and a +3.5 V programming voltage was used (Table 1). Its synaptic features are analyzed by applying the voltage amplitude where the highest memory window is achieved without compromising the device (Fig. 1(b)). The device exhibits potentiation with +3.5 V programming (device 1, inset 1, Fig.1 (b), potentiation side) and depression behavior with -3.5 V programming (inset 2, Fig.1 (b), depression side). Here, an improved GMax/GMin of 3 compared to devices employing only MoS2 as switching layer is achieved. It is also noted that the G in potentiation is saturating after applying 20 pulses. In a second step, the MoS2/h-BN switching layer was replaced by WS2 (inset Fig. 1(c)). This device (device 2) shows (Fig. 1(c)), an even higher memory window with a GMax/GMin ratio of ~30 (Table 1). This translates to an improved potentiation and depression behavior (Fig. 1(d)) and the absence of saturation of the G. Like device 1, the voltage amplitude where the highest memory window is achieved without compromising the device is applied where pulses of (inset 1, Fig.1 (d), potentiation side) -4 V for potentiation and +4 V for depression together with a readout at -1.5 V (inset 2, Fig.1 (d), depression side) are used.

ABSTRACT. We present a new FET architecture which allows maximizing the electrostatic control of the transistor, equivalent to 8 gates. The GAIA (Gate-All-Inside-and-Around) MOSFETs have enhanced flexibility, with significantly higher effective channel width for a given footprint or a footprint reduction for a given effective width, as well as better drive current and control of short channel effects compared with GAA (Gate-All-Around) with the same footprint. Additional parameters compared with GAA, due to the inner gate, also enable optimizing the electrical properties of GAIA MOSFETs for low power or high performance applications.

ABSTRACT. In the context of co-integration of multi-valued logic and spiking neuron circuits with CMOS, we investigate negative differential transconductance in ultra-thin-body Schottky barrier field-effect transistors. The proposed devices exhibit a hysteresis-free NDT, a tunable peak-to-valley ratio of up to 10^7 and ultra-low off-currents. Importantly, a 100-fold increase in NDT peak current was achieved by adding a 2 nm Ge layer atop the SOI.

ABSTRACT. The joint modeling of drain (Id) and gate (Ig) currents in FD-SOI transistors using a multilayer perceptron (MLP)-based architecture is investigated for accurate compact modeling. A unified asinh-based post-processing formulation is adopted to address both multi-range and negative current issues. A methodology to optimize the MLP parameter number and allocation is proposed and applied. The limitations of the final high-Performance split architecture are discussed.

ABSTRACT. Back-gate biasing is a unique feature of FD-SOI MOSFETs, enabling the dynamic tuning of the threshold voltage for performance and energy optimization. Recent measurements reveal a non-constant coupling rate explained by the shift in inversion-charge centroid controlled by the opposite gate bias. Also modulated are the carrier mobility, subthreshold swing, short-channel effects and series resistance. We adopt the back-biasing strategy for improving the performance of monolayer-thick double-gate MOSFETs integrated on 2D semiconductors.

ABSTRACT. Low frequency noise models for transistors based on 2D materials are prospective tools for assessing the impact of traps on device performance and reliability. However, until now scarce data are available mostly due to limited sample reproducibility. Furthermore, analysis is also limited to using compact analytical formulas since only recently TCAD tools have been extended to properly manage 2D materials. This work aims to expand physics-based noise modeling in the realm of devices featuring 2D material channels. It presents a model of trapping-detrapping noise (TDN) based on carrier number fluctuation (CNF) theory in single gate (SG) MOSFETs with graphene (Gr) or MoS2 as channel materials. The model is validated with results from a calibrated, technology computer-aided design (TCAD) tool and with available experiments.

ABSTRACT. We demonstrate a multifunctional W/NbOx/Pt memristive device that simultaneously exhibits volatile, non-volatile, and threshold switching behaviors, enabling unified implementation of reservoir computing, synaptic weight modulation, and leaky integrate-and-fire (LIF) neuron operation within a single element (Figure 1). Interface-controlled volatile switching provides gradual conductance dynamics and intrinsic short-term plasticity (Figure 2a), which are well suited for reservoir computing by offering nonlinear transformation and fading memory characteristics [1]. Using this volatile regime as a physical reservoir, the device achieves 98.4% recognition accuracy on the MNIST dataset, demonstrating effective temporal feature extraction and preprocessing capability. Filamentary non-volatile switching enables stable long-term potentiation and depression for synaptic weight storage (Figure 2b). Although the intrinsic potentiation and depression characteristics exhibit nonlinearity, they are significantly improved through an incremental step pulse with verify algorithm (ISPVA) [2], allowing reliable and symmetric multi-bit conductance tuning up to 6 bits. This precise weight programmability supports supervised learning with enhanced accuracy and reduced device-to-device variation. In addition, threshold switching originating from a localized NbOx insulator-to-metal transition is employed to realize LIF neuron functionality (Figure 2c), where voltage-controlled spike generation with tunable firing frequency emulates biologically inspired neuronal behavior. Structural and chemical analyses reveal the formation of an ultrathin interfacial WOx layer at the W/NbOx junction, which governs oxygen vacancy redistribution and switching-mode transition through compliance current control. This interface engineering enables deterministic access to volatile, non-volatile, and threshold switching within a single device stack. By integrating volatile reservoir dynamics, ISPVA-programmed readout synapses, and threshold-based neurons, we further demonstrate fully on-chip learning on the Fashion-MNIST dataset with an accuracy of 80.17%, validating the feasibility of a compact hardware learning framework without external processing.

ABSTRACT. We present the first spintronic device in which charge and spin-polarized currents are controlled solely by ferroelectricity, the Ferroelectric Spin–Orbit (FESO) device. It exploits the interaction between the polarization of a ferroelectric material and the chirality of the Rashba-split Fermi contours in an adjacent two-dimensional electron gas (2DEG) to control the sign of the spin to charge conversion (SCC), phenomenon known as the inverse Rashba Edelstein effect. Here, the spin momentum lock-in at the Fermi level, creates a spin (charge) current orthogonal to the charge (spin) current passing through the 2DEG. This solution simplifies the integration of FESO devices and improves the intrinsic delay of logic gates. The device (Fig 1) consists of a nanopillar made of, from top to bottom, a ferromagnet with fixed magnetization, a tunneling barrier, a 2DEG surface and a ferroelectric material. Four interconnects are arranged for the reading/writing process: one interconnect at the bottom of the ferroelectric layer, one on top of the ferromagnet, and two interfaced with two orthogonal sides of the 2DEG for the output and ground connections. To write the device, an input voltage (〖±V〗_in) is applied to the ferroelectric layer via the bottom metal, large enough to reverse the polarization (±P). For the reading, a charge current (Ic) is injected to the ferromagnet, which generates a spin current flowing through the 2DEG. This spin current in transduced to an orthogonal charge current by SCC, loading the output interconnect to an output voltage (∓V_out). This inversion of the signal sign shows that the device intrinsically behaves as a logic inverter. We developed an equivalent circuit to model the functionality of a FESO device (Fig 2). Fig 3 shows the simulation of the compact model, in which the inversion of the input signal at the output terminal can be observed. We implemented a three-input majority gate by connecting three FESO devices in parallel, i.e. sharing the output terminals (Fig 4, 5). The combination of these operations based on FESO devices enables a compact, non-volatile and energy-efficient implementation of any logic function. We benchmarked larger circuits, such as 32-bit adder circuits, showcasing the interest of FESO devices for next-generation low-power electronics [1]. Experimental results [2, 3] and design considerations highlight the potential of this technology to overcome the limitations of CMOS technology. Moreover, the dense implementation of arithmetic operations, combined with the low-energy and non-volatility of FESO place the device as an ideal candidate for in-memory computing.

ABSTRACT. The fabrication of CMOS technology has reached its physical limits in the present digital world. Artificial intelligence, the Internet of Things (IoT), and fast data processing demand lower power consumption, whereas in the von Neumann architecture, most of the energy is lost during data transfer between the memory and the processing unit [1-3]. Due to these factors, new computing paradigms such as neuromorphic computing are being developed. One of the most promising devices for emulating a biological synapse is Resistive Random-Access Memory (RRAM). RRAM can exhibit multi-level switching states, low power consumption, and high storage density, which makes it an ideal candidate for in memory computing [1-5]. However, not every RRAM device is suitable for such applications. For example, filamentary-switching-based resistive memory requires high voltage to form a conductive filament between the top and bottom electrodes. At the same time, the very high conductance in the low-resistance state (LRS) resulting from the forming process increases the system's overall power consumption [2]. For these reasons, analog-type, also called filament-free, RRAMs are preferred in neuromorphic computing [1-2,4]. In this work, we present filament free RRAM structures with Ru as the top electrode, 30 nm of TiOx as the insulating layer, and TiN as the bottom electrode. RRAM devices exhibited high stability of RLRS/RHRS, as shown in Figure 1, as well as a clear memory window even at a higher number of I-V DC sweep cycles (1000 cycles), as presented in Figure 2. After DC electrical characterization, the structures were tested using potentiation and depression pulses. The obtained current levels were below a few hundred nA, which makes them ideal candidates for ultra low power applications which is a highly demanded feature in neuromorphic computing [1-3,6]. With a fixed length of potentiation pulses, a linear increase in current was observed; however, during depression pulses, the current decreased exponentially. One of the most crucial requirements for devices that mimic biological synapses is the symmetry and linearity of resistance change as a function of applied pulses [6]. To achieve this, the lengths of the depression pulses were experimentally optimized. Current levels before and after optimization are shown in Figure 3. The behaviour of five resistance levels was measured across 100 cycles on a single structure, as shown in Figure 4. Statistical data of 1000 cycles is shown in Figure 5. It is also worth noting that the structures exhibited high retention (10⁴ s) of the LRS, as shown in Figure 6. which is crucial aspect that has not yet been fully explored in analog-switching RRAM devices [6]. In summary, the fabricated Ru/TiOx/TiN structures were characterized for application as artificial synapses. The structures exhibit stable switching behavior as a five state, ultra low power system. Experimentally optimized pulse lengths enabled high linearity and symmetry of resistance change as a function of the applied pulses.

Acknowledgment This research was carried out within the framework of the FAMES Pilot Line of the Chips JU, funded by Horizon Europe under grant agreement 101182279, Digital Europe under grant agreement 101182297, and Ministry of Science and Higer Education Republic of Poland under Grant Agreement No. MNiSW/2025/DIR/849, and partially by the Warsaw University of Technology Excellence Initiative – Research University (IDUB) program, under agreement no. CPR-IDUB/306/Z07/2024.

References [1] J. Park, A. Kumar, et al. Nat Commun 15, (2024) 3492. [2] A.K. Yadav, S. Vinayak, C. Prakash, A. Dixit. ACS Appl. Electron. Mater., doi: https://pubs.acs.org/action/showCitFormats?doi=10.1021/acsaelm.5c01702&ref=pdf. [3] B. Bakhit, et al. Commun Mater 6, (2025) 77. [4] U.I. Bature, H. Abbas, A. Alzahrani, A. Nisar, F. Bashir, F. Zahoor. Applied Materials Today 47 (2025) 102916. [5] Y.-F. Wang, Y.-C. Lin, I-T. Wang, T.-P. Ling, and T.-H. Hou, Sci Rep 5, (2015) 10150. [6] K. Moon, et al., Faraday Discuss., 213 (2019) 421.

ABSTRACT. This work investigates positive bias erase schemes for ferroelectric field effect transistors (FeFETs) and compares their switching behavior in FDSOI and bulk CMOS technologies (Fig. 1). Ferroelectric FETs are promising candidates for embedded non volatile memory due to their fast switching, CMOS compatibility, and scalability. However, conventional program and erase schemes typically rely on bipolar gate biasing, increasing voltage complexity and peripheral circuit constraints. In contrast to conventional negative gate erase, positive source/drain (S/D) erase enables polarization reversal using exclusively positive bias conditions, offering an attractive alternative toward simplified voltage schemes and unipolar operation [1],[2]. The positive bias erase behavior is evaluated for FeFETs implemented in FDSOI and bulk technologies, including long channel devices with dimensions up to 500 nm in FDSOI and 450 nm in bulk, as well as scaled bulk devices with channel lengths down to 72 nm. In FDSOI FeFETs, positive S/D erase pulses result in efficient low VT to high VT polarization switching that is comparable to the switching characteristics obtained with conventional negative gate erase, even for large device dimensions (Fig. 2). This efficient behavior is attributed to robust electrostatic control and high electric field across the ferroelectric layer in FDSOI. In contrast, bulk FeFETs show strongly reduced positive bias erase efficiency, particularly when the body remains floating and the positive bias is applied only to S/D. This limitation persists for both long channel devices (Fig. 3) and scaled channel lengths (Fig. 4) due to a lower electric field across the ferroelectric layer. When the positive bias is applied to S/D and Body, a gradual low VT to high VT transition is observed with increasing erase pulse amplitude. However, the switching onset is shifted to higher voltages compared to the standard erase scheme due to the increased parasitic capacitance. Further TCAD simulations support the experimental observations and reveal a substantially more favorable field distribution in FDSOI FeFETs compared to bulk devices. The results demonstrate that positive S/D erase is an effective and voltage efficient switching scheme for FeFETs in FDSOI technology, enabling unipolar program/erase operation with a reduced total voltage range and potential benefits for array level disturb immunity and inhibit functionality in unselected cells, while highlighting the dominant role of device architecture and electrostatics for advanced FeFET erase concepts.

ABSTRACT. This work focuses on the concept of a probabilistic bit (P-bit) that lies between the classical and quantum computing worlds. P-bit fluctuates between 0 and 1 and provides a binary output with a tunable probability, which can be exploited to implement various probabilistic computing schemes or hardware security mechanisms. In this work, we present a preliminary study of the properties of the Ag/SiOx/bottom-electrode threshold-switching (TS) memristor, which can be used to build a P-bit. We study the device's dynamic properties, observing spiking behavior under DC or pulse voltage stimuli. This effect can be used to apply probabilistic bits, as we presented. We propose a simple circuit to build a P-bit and present a Spice simulation of its output as a function of the input voltage.