NANOARCH 2023: 18TH ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES

This page contains an index consisting of author-provided keywords.

6
6G network	Concept paper on novel radio frequency resistive switches
A
Abundant-Data Workloads	The Future of Hardware Technologies for Computing
Adder optimization	Multiplexer Optimization for Adders in Stochastic Computing
AIMC	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study
Analog computing	On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing
Artificial Neural Network	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Artificial Neural Networks (ANNs)	Engineering memristors for memory, neuromorphic computing and beyond
B
beyond CMOS	Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?
Binary Decision Diagrams (BDDs)	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
bipolar switching	Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer Material
C
Carbon Nanotube Field Effect Transistor	Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology
Cellular Nonlinear Networks	Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Clifford+T	A T-depth two Toffoli gate for 2D square lattice architectures
CMOS Industry Adoption	Engineering memristors for memory, neuromorphic computing and beyond
computing	Electrical Properties of Proteinoids for Unconventional Computing Architectures
Computing-in-memory	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
configurable PUF	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
Content-Addressable Memory	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
Convolutional Neural Network (CNN)	VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
D
Deep Dopant	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
Deterministic sequences	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Device Design	Engineering memristors for memory, neuromorphic computing and beyond
DNN	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study
DNN mapping algorithm	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Donor	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
Dynamic Logic	Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology
E
electronic olfaction	Digital olfaction
Emerging computing	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Emerging Technology	Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds
Emulation	Non Volatile Operators Emulation Platform
Energy Efficiency	Memristive and CMOS Technologies for Advanced Cognitive Systems Memristor-based Network Switching Architecture for Energy Efficient Cognitive Computational Models
ex-situ training	Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights
experimental demonstrator	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
F
FeFET	Non Volatile Operators Emulation Platform
Ferroelectric FET (FeFET) Technology	In-Memory Computing using Ferroelectric Transistors: Lessons Learnt and Future Trends
ferroelectric field effect transistor (FeFET) emerging device modeling	Neural Network Modeling Bias for Hafnia-based FeFETs
Ferroelectric Tunneling Junction	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Field-coupled Nanocomputing	Post-Layout Optimization for Field-Coupled Nanotechnologies Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
FPGA	Non Volatile Operators Emulation Platform
FTJ	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
G
Gate Design	Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds
Gate Diffusion Input	Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology
H
hardware	Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?
Hardware Accelerator	VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
Hardware architecture	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Hardware Cognitive Systems	Memristive and CMOS Technologies for Advanced Cognitive Systems
hardware neural network	Neural Network Modeling Bias for Hafnia-based FeFETs
HDC	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
heterogeneous computing	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
HfO2-based memristive device	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
hybrid material	Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer Material
Hyper Dimensional Computing	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
I
Image processing	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
improved BER	A Robust Time-based Error-Proofing Readout Scheme for MRAM
In-Memory Computing	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing In-Memory Computing using Ferroelectric Transistors: Lessons Learnt and Future Trends
instruction set architecture	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
ISFET	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
L
limited precision	Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights
Logic in Memory	Non Volatile Operators Emulation Platform
logic in memory (LiM)	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
Lookup Table	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Low Power	Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology
M
machine learning	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing Digital olfaction
material computing	Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?
Materials Engineering	Engineering memristors for memory, neuromorphic computing and beyond
Memristive Circuits	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
Memristive Devices	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
Memristive Devices and Systems	Engineering memristors for memory, neuromorphic computing and beyond
Memristive Synapses	Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Memristive Technology	Memristive and CMOS Technologies for Advanced Cognitive Systems
Memristor	LUT-based RRAM Model for Neural Accelerator Circuit Simulation On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Memristor Cellular Nonlinear Network	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
memristor crossbar	Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights
Memristor Oscillatory Networks	Memristor-based Oscillatory Platforms for Pattern Recognition: from nano-device to bioinspired algorithms
Memristors	Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots Memristor-based Network Switching Architecture for Energy Efficient Cognitive Computational Models Concept paper on novel radio frequency resistive switches TBA
microspheres	Electrical Properties of Proteinoids for Unconventional Computing Architectures
Model Compression	VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
Modeling and Applications	TBA
Monolithic 3D	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Monolithic 3D Integration	In-Memory Computing using Ferroelectric Transistors: Lessons Learnt and Future Trends
MRAM	A Robust Time-based Error-Proofing Readout Scheme for MRAM
Multi-cycle processor	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
Multi-valued logic computing	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
multilevel state	Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer Material
Multiplexers	Multiplexer Optimization for Adders in Stochastic Computing
N
N3XT 3D MOSAIC	The Future of Hardware Technologies for Computing
Nano-devices	Impact of the switching mode on the read noise of ReRAM devices
nanosensors	Digital olfaction
Neural Accelerator	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
neural network	Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis? Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights
Neural network accelerator	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Neural networks	Multiplexer Optimization for Adders in Stochastic Computing
Neuromorphic	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?
Neuromorphic Computing	Memristive and CMOS Technologies for Advanced Cognitive Systems Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters Organic semiconductors: from displays to neuromorphic
neuromorphic hardware	Neural Network Modeling Bias for Hafnia-based FeFETs
NLP	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study
Noise	Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Nonlinear Dynamics	Memristor-based Oscillatory Platforms for Pattern Recognition: from nano-device to bioinspired algorithms
O
Online learning	On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing
Operational Domain	Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
optical memristor	Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer Material
Optimization	Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions Post-Layout Optimization for Field-Coupled Nanotechnologies
Organic Semiconductors	Organic semiconductors: from displays to neuromorphic
Organic Sensors	Organic semiconductors: from displays to neuromorphic
Oscillation-based Computing	Memristor-based Oscillatory Platforms for Pattern Recognition: from nano-device to bioinspired algorithms TBA
P
PCM	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study
phase detector	A Robust Time-based Error-Proofing Readout Scheme for MRAM
Physical Design	Post-Layout Optimization for Field-Coupled Nanotechnologies
physical unclonable function	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
Placement and Routing	Post-Layout Optimization for Field-Coupled Nanotechnologies
Polyethylene Oxide (PEO)	Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots
Polymer Electronics	Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots
Polymethacrylate (PMA)	Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots
Polynomial Formal Verification	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
Post-CMOS	Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds
post-CMOS technologies	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Post-Processing	Post-Layout Optimization for Field-Coupled Nanotechnologies
printed electronics	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
proteinoids	Electrical Properties of Proteinoids for Unconventional Computing Architectures
Pseudo-random sources	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
PUF	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
Pulse Programming	A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Pulsed Neural Networks	A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Q
quantum circuit	A T-depth two Toffoli gate for 2D square lattice architectures Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions
quantum gate	A T-depth two Toffoli gate for 2D square lattice architectures
Quasi-random number generators	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Qubit Operation	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
R
Read noise	Impact of the switching mode on the read noise of ReRAM devices
reconfiguration	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
recurrent neural network	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
reinforcement learning	Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing
ReRAM	Impact of the switching mode on the read noise of ReRAM devices A Behavioural Compact Model for Programmable Neuromorphic ReRAM
reservoir computing	Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?
Resistive RAM	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Resistive random access memory	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
reward function	Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions
RISC-V	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor Non Volatile Operators Emulation Platform
Room Temperature	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
RRAM	LUT-based RRAM Model for Neural Accelerator Circuit Simulation Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
S
Silicon architecture	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
Silicon Dangling Bonds	Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
Simulation	Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
Single Electron shuttling	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
sneak path current	Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights
SOT-MRAM	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
Spin Waves	Spin Wave Threshold Logic Gates
Spintronics	Spin Wave Threshold Logic Gates
Stochastic computing	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences Multiplexer Optimization for Adders in Stochastic Computing
Switches	Memristor-based Network Switching Architecture for Energy Efficient Cognitive Computational Models
System-Level Energy-Delay-Product Benefits	The Future of Hardware Technologies for Computing
T
temporal information processing	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
Threshold Logic	Spin Wave Threshold Logic Gates
time-based readout scheme	A Robust Time-based Error-Proofing Readout Scheme for MRAM
Toffoli gate	A T-depth two Toffoli gate for 2D square lattice architectures
U
uncoupled M-CNNs	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
V
VCM	Impact of the switching mode on the read noise of ReRAM devices
W
wireless communication	Concept paper on novel radio frequency resistive switches

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