NANOARCH 2023: 18TH ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES

A
Adam, Gina	Neural Network Modeling Bias for Hafnia-based FeFETs
Adamatzky, Andrew	Electrical Properties of Proteinoids for Unconventional Computing Architectures
Adawi, Ali	Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots
Adelmann, Christoph	Spin Wave Threshold Logic Gates
Al Beattie, Bakr	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Al Chawa, Mohamad Moner	A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Alam, Shahanur	On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing
Amrouch, Hussam	In-Memory Computing using Ferroelectric Transistors: Lessons Learnt and Future Trends
Anagnostou, Pantazis	Spin Wave Threshold Logic Gates
Ascoli, Alon	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Aussen, Stephan	Impact of the switching mode on the read noise of ReRAM devices
Aygun, Sercan	Multiplexer Optimization for Adders in Stochastic Computing Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
B
Beigl, Michael	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
Bengel, Christopher	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
C
Carta, Corrado	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Casa Branca, Nuno	Concept paper on novel radio frequency resistive switches
Chakraborty, Soumya	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
Chen, Jia	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
Chen, Ke	VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
Ciubotaru, Florin	Spin Wave Threshold Logic Gates
Corinto, Fernando	Memristor-based Oscillatory Platforms for Pattern Recognition: from nano-device to bioinspired algorithms
Cotofana, Sorin	Spin Wave Threshold Logic Gates
Covi, Erika	Memristive and CMOS Technologies for Advanced Cognitive Systems
Cui, Yijun	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
Cuniberti, Gianaurelio	Digital olfaction
Cüppers, Felix	Impact of the switching mode on the read noise of ReRAM devices Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
D
Datta, Kamalika	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
de Benito, Carol	A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Demirkol, Ahmet Samil	Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Dobbs, Evan	A T-depth two Toffoli gate for 2D square lattice architectures
Drechsler, Rolf	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
Drewniok, Jan	Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
F
Fey, Dietmar	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Friedman, Joseph S.	A T-depth two Toffoli gate for 2D square lattice architectures
G
Gao, Bin	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Gao, Hanran	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
Gater, Michael	Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots
Glasmann, Andreu	Neural Network Modeling Bias for Hafnia-based FeFETs
Gu, Chongyan	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
Gunes, Ece Olcay	Multiplexer Optimization for Adders in Stochastic Computing
H
Hamdioui, Said	Spin Wave Threshold Logic Gates
Hasan, Raqibul	Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision Weights
Hefenbrock, Michael	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
Hoffmann-Eifert, Susanne	Impact of the switching mode on the read noise of ReRAM devices Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
Hofmann, Simon	Post-Layout Optimization for Field-Coupled Nanotechnologies
Hosseinzadeh, Shima	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Hossen, Imtiaz	Neural Network Modeling Bias for Hafnia-based FeFETs
Hou, Zhengyi	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
J
Jaafar, Ayoub	Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer Material
K
Kahmen, Gerhard	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Kemp, Neil	Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer Material Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum Dots
Kenyon, Anthony	Engineering memristors for memory, neuromorphic computing and beyond
Kiazadeh, Asal	Concept paper on novel radio frequency resistive switches
Koldehofe, Boris	Memristor-based Network Switching Architecture for Energy Efficient Cognitive Computational Models
Kouhalvandi, Lida	Multiplexer Optimization for Adders in Stochastic Computing
L
Lancaster, Suzanne	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Leo, Karl	Organic semiconductors: from displays to neuromorphic
Leupers, Rainer	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Li, Jiaming	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Li, Jiang	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
Li, Pengbin	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
Li, Shixing	A Robust Time-based Error-Proofing Readout Scheme for MRAM
Li, Yi	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
Liu, Weiqiang	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
M
Manea, Paul-Philipp	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
Marchand, Cédric	Non Volatile Operators Emulation Platform
Matos, Sergio	Concept paper on novel radio frequency resistive switches
Menzel, Stephan	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Merchant, Farhad	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Messaris, Ioannis	Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Miao, Xiangshui	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
Mikolajick, Thomas	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Mitra, Subhasish	The Future of Hardware Technologies for Computing
Moflic, Ioana	Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions
Mougkogiannis, Panagiotis	Electrical Properties of Proteinoids for Unconventional Computing Architectures
Moussavi, Elmira	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
N
Najafi, M. Hassan	Multiplexer Optimization for Adders in Stochastic Computing Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Najmaei, Sina	Neural Network Modeling Bias for Hafnia-based FeFETs
Navarro, David	Non Volatile Operators Emulation Platform
Ng, Samuel Sze Hang	Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
Nicolas, Alban	Non Volatile Operators Emulation Platform
Ntinas, Vasileios	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
O
Ochs, Karlheinz	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Ostrovskyy, Philip	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Ou, Qianlei	A Robust Time-based Error-Proofing Readout Scheme for MRAM
P
Pachauri, Vivek	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Pal, Priyanjana	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
Paler, Alexandru	Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward Functions A T-depth two Toffoli gate for 2D square lattice architectures
Parvaresh, Amirhossein	Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study
Patkar, Sachin	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Pessoa, Luis Manuel	Concept paper on novel radio frequency resistive switches
Picos, Rodrigo	A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Prousalis, Dimitrios	Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Pérez, Eduardo	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Pérez-Bosch Quesada, Emilio	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Q
Qian, He	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
R
Ran, Shuo	VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
Rana, Vikas	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Rehal, Amandeep Singh	Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology
Ren, Shengguang	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
Reuben, John	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Riahi Alam, Mohsen	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Rizzi, Tommaso	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
S
Saleh, Saad	Memristor-based Network Switching Architecture for Energy Efficient Cognitive Computational Models
Samanta, Arup	Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room Temperature
Schmidt, Jonas I	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Schnieders, Kristoffer	Impact of the switching mode on the read noise of ReRAM devices Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
Shoushtari Moghadam, Mehran	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Singh, Simranjeet	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Sirakoulis, Georgios Ch.	TBA
Slesazeck, Stefan	Hyper Dimensional Computing with Ferroelectric Tunneling Junctions
Stavrinides, Stavros G.	A Behavioural Compact Model for Programmable Neuromorphic ReRAM
Strachan, John Paul	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
Sudarshan, Chirag	Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable Memories
T
Taha, Tarek	On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing
Taherinejad, Nima	Accurate and Energy-Efficient Stochastic Computing with Van Der Corput Sequences
Tahoori, Mehdi B.	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
Tang, Jianshi	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Tetzlaff, Ronald	A Behavioural Compact Model for Programmable Neuromorphic ReRAM Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noise
Teuscher, Christof	Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?
Tjortjis, Christos	A Behavioural Compact Model for Programmable Neuromorphic ReRAM
U
Uhlmann, Max	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
V
Van Zegbroeck, Arne	Spin Wave Threshold Logic Gates
W
Walter, Marcel	Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds Post-Layout Optimization for Field-Coupled Nanotechnologies Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
Walus, Konrad	Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
Wang, Bi	A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
Wang, Chao	A Robust Time-based Error-Proofing Readout Scheme for MRAM
Wang, Chenghua	An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode Operation
Wang, Yongmin	Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
Wang, Zhaohao	A Robust Time-based Error-Proofing Readout Scheme for MRAM A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAM
Waser, Rainer	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies
Weingarten, Lennart	PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
Wen, Jianan	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Wenger, Christian	LUT-based RRAM Model for Neural Accelerator Circuit Simulation
Wiefels, Stefan	Impact of the switching mode on the read noise of ReRAM devices Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection Task
Wille, Robert	Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds Post-Layout Optimization for Field-Coupled Nanotechnologies Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic
Wu, Bi	VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning
Wu, Huaqiang	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Y
Yakopcic, Chris	On-Chip Optimization and Deep Reinforcement Learning in Memristor Based Computing
Yao, Peng	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Yousuf, Osama	Neural Network Modeling Bias for Hafnia-based FeFETs
Yu, Ruihua	A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance Systems
Z
Zhang, He	A Robust Time-based Error-Proofing Readout Scheme for MRAM
Zhao, Haibin	Towards Temporal Information Processing – Printed Neuromorphic Circuits with Learnable Filters
Zhou, Houji	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing
Zhou, Zhiwei	Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory Computing

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